icssm_prueth.c

   1// SPDX-License-Identifier: GPL-2.0
   2
   3/* Texas Instruments ICSSM Ethernet Driver
   4 *
   5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
   6 *
   7 */
   8
   9#include <linux/etherdevice.h>
  10#include <linux/genalloc.h>
  11#include <linux/if_bridge.h>
  12#include <linux/if_hsr.h>
  13#include <linux/if_vlan.h>
  14#include <linux/interrupt.h>
  15#include <linux/kernel.h>
  16#include <linux/mfd/syscon.h>
  17#include <linux/module.h>
  18#include <linux/net_tstamp.h>
  19#include <linux/of.h>
  20#include <linux/of_irq.h>
  21#include <linux/of_mdio.h>
  22#include <linux/of_net.h>
  23#include <linux/platform_device.h>
  24#include <linux/phy.h>
  25#include <linux/remoteproc/pruss.h>
  26#include <linux/ptp_classify.h>
  27#include <linux/regmap.h>
  28#include <linux/remoteproc.h>
  29#include <net/pkt_cls.h>
  30
  31#include "icssm_prueth.h"
  32#include "../icssg/icssg_mii_rt.h"
  33#include "../icssg/icss_iep.h"
  34
  35#define OCMC_RAM_SIZE		(SZ_64K)
  36
  37#define TX_START_DELAY		0x40
  38#define TX_CLK_DELAY_100M	0x6
  39#define HR_TIMER_TX_DELAY_US	100
  40
  41static void icssm_prueth_write_reg(struct prueth *prueth,
  42				   enum prueth_mem region,
  43				   unsigned int reg, u32 val)
  44{
  45	writel_relaxed(val, prueth->mem[region].va + reg);
  46}
  47
  48/* Below macro is for 1528 Byte Frame support, to Allow even with
  49 * Redundancy tag
  50 */
  51#define PRUSS_MII_RT_RX_FRMS_MAX_SUPPORT_EMAC  (VLAN_ETH_FRAME_LEN + \
  52						ETH_FCS_LEN + \
  53						ICSSM_LRE_TAG_SIZE)
  54
  55/* ensure that order of PRUSS mem regions is same as enum prueth_mem */
  56static enum pruss_mem pruss_mem_ids[] = { PRUSS_MEM_DRAM0, PRUSS_MEM_DRAM1,
  57					  PRUSS_MEM_SHRD_RAM2 };
  58
  59static const struct prueth_queue_info queue_infos[][NUM_QUEUES] = {
  60	[PRUETH_PORT_QUEUE_HOST] = {
  61		[PRUETH_QUEUE1] = {
  62			P0_Q1_BUFFER_OFFSET,
  63			HOST_QUEUE_DESC_OFFSET,
  64			P0_Q1_BD_OFFSET,
  65			P0_Q1_BD_OFFSET + ((HOST_QUEUE_1_SIZE - 1) * BD_SIZE),
  66		},
  67		[PRUETH_QUEUE2] = {
  68			P0_Q2_BUFFER_OFFSET,
  69			HOST_QUEUE_DESC_OFFSET + 8,
  70			P0_Q2_BD_OFFSET,
  71			P0_Q2_BD_OFFSET + ((HOST_QUEUE_2_SIZE - 1) * BD_SIZE),
  72		},
  73		[PRUETH_QUEUE3] = {
  74			P0_Q3_BUFFER_OFFSET,
  75			HOST_QUEUE_DESC_OFFSET + 16,
  76			P0_Q3_BD_OFFSET,
  77			P0_Q3_BD_OFFSET + ((HOST_QUEUE_3_SIZE - 1) * BD_SIZE),
  78		},
  79		[PRUETH_QUEUE4] = {
  80			P0_Q4_BUFFER_OFFSET,
  81			HOST_QUEUE_DESC_OFFSET + 24,
  82			P0_Q4_BD_OFFSET,
  83			P0_Q4_BD_OFFSET + ((HOST_QUEUE_4_SIZE - 1) * BD_SIZE),
  84		},
  85	},
  86	[PRUETH_PORT_QUEUE_MII0] = {
  87		[PRUETH_QUEUE1] = {
  88			P1_Q1_BUFFER_OFFSET,
  89			P1_Q1_BUFFER_OFFSET + ((QUEUE_1_SIZE - 1) *
  90					ICSS_BLOCK_SIZE),
  91			P1_Q1_BD_OFFSET,
  92			P1_Q1_BD_OFFSET + ((QUEUE_1_SIZE - 1) * BD_SIZE),
  93		},
  94		[PRUETH_QUEUE2] = {
  95			P1_Q2_BUFFER_OFFSET,
  96			P1_Q2_BUFFER_OFFSET + ((QUEUE_2_SIZE - 1) *
  97					ICSS_BLOCK_SIZE),
  98			P1_Q2_BD_OFFSET,
  99			P1_Q2_BD_OFFSET + ((QUEUE_2_SIZE - 1) * BD_SIZE),
 100		},
 101		[PRUETH_QUEUE3] = {
 102			P1_Q3_BUFFER_OFFSET,
 103			P1_Q3_BUFFER_OFFSET + ((QUEUE_3_SIZE - 1) *
 104					ICSS_BLOCK_SIZE),
 105			P1_Q3_BD_OFFSET,
 106			P1_Q3_BD_OFFSET + ((QUEUE_3_SIZE - 1) * BD_SIZE),
 107		},
 108		[PRUETH_QUEUE4] = {
 109			P1_Q4_BUFFER_OFFSET,
 110			P1_Q4_BUFFER_OFFSET + ((QUEUE_4_SIZE - 1) *
 111					ICSS_BLOCK_SIZE),
 112			P1_Q4_BD_OFFSET,
 113			P1_Q4_BD_OFFSET + ((QUEUE_4_SIZE - 1) * BD_SIZE),
 114		},
 115	},
 116	[PRUETH_PORT_QUEUE_MII1] = {
 117		[PRUETH_QUEUE1] = {
 118			P2_Q1_BUFFER_OFFSET,
 119			P2_Q1_BUFFER_OFFSET + ((QUEUE_1_SIZE - 1) *
 120					ICSS_BLOCK_SIZE),
 121			P2_Q1_BD_OFFSET,
 122			P2_Q1_BD_OFFSET + ((QUEUE_1_SIZE - 1) * BD_SIZE),
 123		},
 124		[PRUETH_QUEUE2] = {
 125			P2_Q2_BUFFER_OFFSET,
 126			P2_Q2_BUFFER_OFFSET + ((QUEUE_2_SIZE - 1) *
 127					ICSS_BLOCK_SIZE),
 128			P2_Q2_BD_OFFSET,
 129			P2_Q2_BD_OFFSET + ((QUEUE_2_SIZE - 1) * BD_SIZE),
 130		},
 131		[PRUETH_QUEUE3] = {
 132			P2_Q3_BUFFER_OFFSET,
 133			P2_Q3_BUFFER_OFFSET + ((QUEUE_3_SIZE - 1) *
 134					ICSS_BLOCK_SIZE),
 135			P2_Q3_BD_OFFSET,
 136			P2_Q3_BD_OFFSET + ((QUEUE_3_SIZE - 1) * BD_SIZE),
 137		},
 138		[PRUETH_QUEUE4] = {
 139			P2_Q4_BUFFER_OFFSET,
 140			P2_Q4_BUFFER_OFFSET + ((QUEUE_4_SIZE - 1) *
 141					ICSS_BLOCK_SIZE),
 142			P2_Q4_BD_OFFSET,
 143			P2_Q4_BD_OFFSET + ((QUEUE_4_SIZE - 1) * BD_SIZE),
 144		},
 145	},
 146};
 147
 148static const struct prueth_queue_desc queue_descs[][NUM_QUEUES] = {
 149	[PRUETH_PORT_QUEUE_HOST] = {
 150		{ .rd_ptr = P0_Q1_BD_OFFSET, .wr_ptr = P0_Q1_BD_OFFSET, },
 151		{ .rd_ptr = P0_Q2_BD_OFFSET, .wr_ptr = P0_Q2_BD_OFFSET, },
 152		{ .rd_ptr = P0_Q3_BD_OFFSET, .wr_ptr = P0_Q3_BD_OFFSET, },
 153		{ .rd_ptr = P0_Q4_BD_OFFSET, .wr_ptr = P0_Q4_BD_OFFSET, },
 154	},
 155	[PRUETH_PORT_QUEUE_MII0] = {
 156		{ .rd_ptr = P1_Q1_BD_OFFSET, .wr_ptr = P1_Q1_BD_OFFSET, },
 157		{ .rd_ptr = P1_Q2_BD_OFFSET, .wr_ptr = P1_Q2_BD_OFFSET, },
 158		{ .rd_ptr = P1_Q3_BD_OFFSET, .wr_ptr = P1_Q3_BD_OFFSET, },
 159		{ .rd_ptr = P1_Q4_BD_OFFSET, .wr_ptr = P1_Q4_BD_OFFSET, },
 160	},
 161	[PRUETH_PORT_QUEUE_MII1] = {
 162		{ .rd_ptr = P2_Q1_BD_OFFSET, .wr_ptr = P2_Q1_BD_OFFSET, },
 163		{ .rd_ptr = P2_Q2_BD_OFFSET, .wr_ptr = P2_Q2_BD_OFFSET, },
 164		{ .rd_ptr = P2_Q3_BD_OFFSET, .wr_ptr = P2_Q3_BD_OFFSET, },
 165		{ .rd_ptr = P2_Q4_BD_OFFSET, .wr_ptr = P2_Q4_BD_OFFSET, },
 166	}
 167};
 168
 169static void icssm_prueth_hostconfig(struct prueth *prueth)
 170{
 171	void __iomem *sram_base = prueth->mem[PRUETH_MEM_SHARED_RAM].va;
 172	void __iomem *sram;
 173
 174	/* queue size lookup table */
 175	sram = sram_base + HOST_QUEUE_SIZE_ADDR;
 176	writew(HOST_QUEUE_1_SIZE, sram);
 177	writew(HOST_QUEUE_2_SIZE, sram + 2);
 178	writew(HOST_QUEUE_3_SIZE, sram + 4);
 179	writew(HOST_QUEUE_4_SIZE, sram + 6);
 180
 181	/* queue information table */
 182	sram = sram_base + HOST_Q1_RX_CONTEXT_OFFSET;
 183	memcpy_toio(sram, queue_infos[PRUETH_PORT_QUEUE_HOST],
 184		    sizeof(queue_infos[PRUETH_PORT_QUEUE_HOST]));
 185
 186	/* buffer offset table */
 187	sram = sram_base + HOST_QUEUE_OFFSET_ADDR;
 188	writew(P0_Q1_BUFFER_OFFSET, sram);
 189	writew(P0_Q2_BUFFER_OFFSET, sram + 2);
 190	writew(P0_Q3_BUFFER_OFFSET, sram + 4);
 191	writew(P0_Q4_BUFFER_OFFSET, sram + 6);
 192
 193	/* buffer descriptor offset table*/
 194	sram = sram_base + HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR;
 195	writew(P0_Q1_BD_OFFSET, sram);
 196	writew(P0_Q2_BD_OFFSET, sram + 2);
 197	writew(P0_Q3_BD_OFFSET, sram + 4);
 198	writew(P0_Q4_BD_OFFSET, sram + 6);
 199
 200	/* queue table */
 201	sram = sram_base + HOST_QUEUE_DESC_OFFSET;
 202	memcpy_toio(sram, queue_descs[PRUETH_PORT_QUEUE_HOST],
 203		    sizeof(queue_descs[PRUETH_PORT_QUEUE_HOST]));
 204}
 205
 206static void icssm_prueth_mii_init(struct prueth *prueth)
 207{
 208	struct regmap *mii_rt;
 209	u32 rxcfg_reg, rxcfg;
 210	u32 txcfg_reg, txcfg;
 211
 212	mii_rt = prueth->mii_rt;
 213
 214	rxcfg = PRUSS_MII_RT_RXCFG_RX_ENABLE |
 215		PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS |
 216		PRUSS_MII_RT_RXCFG_RX_L2_EN |
 217		PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE |
 218		PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS;
 219
 220	/* Configuration of Port 0 Rx */
 221	rxcfg_reg = PRUSS_MII_RT_RXCFG0;
 222
 223	regmap_write(mii_rt, rxcfg_reg, rxcfg);
 224
 225	/* Configuration of Port 1 Rx */
 226	rxcfg_reg = PRUSS_MII_RT_RXCFG1;
 227
 228	rxcfg |= PRUSS_MII_RT_RXCFG_RX_MUX_SEL;
 229
 230	regmap_write(mii_rt, rxcfg_reg, rxcfg);
 231
 232	txcfg = PRUSS_MII_RT_TXCFG_TX_ENABLE |
 233		PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE |
 234		PRUSS_MII_RT_TXCFG_TX_32_MODE_EN |
 235		(TX_START_DELAY << PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT) |
 236		(TX_CLK_DELAY_100M << PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT);
 237
 238	/* Configuration of Port 0 Tx */
 239	txcfg_reg = PRUSS_MII_RT_TXCFG0;
 240
 241	regmap_write(mii_rt, txcfg_reg, txcfg);
 242
 243	txcfg |= PRUSS_MII_RT_TXCFG_TX_MUX_SEL;
 244
 245	/* Configuration of Port 1 Tx */
 246	txcfg_reg = PRUSS_MII_RT_TXCFG1;
 247
 248	regmap_write(mii_rt, txcfg_reg, txcfg);
 249
 250	txcfg_reg = PRUSS_MII_RT_RX_FRMS0;
 251
 252	/* Min frame length should be set to 64 to allow receive of standard
 253	 * Ethernet frames such as PTP, LLDP that will not have the tag/rct.
 254	 * Actual size written to register is size - 1 per TRM. This also
 255	 * includes CRC/FCS.
 256	 */
 257	txcfg = FIELD_PREP(PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK,
 258			   (PRUSS_MII_RT_RX_FRMS_MIN_FRM - 1));
 259
 260	/* For EMAC, set Max frame size to 1528 i.e size with VLAN.
 261	 * Actual size written to register is size - 1 as per TRM.
 262	 * Since driver support run time change of protocol, driver
 263	 * must overwrite the values based on Ethernet type.
 264	 */
 265	txcfg |= FIELD_PREP(PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK,
 266			    (PRUSS_MII_RT_RX_FRMS_MAX_SUPPORT_EMAC - 1));
 267
 268	regmap_write(mii_rt, txcfg_reg, txcfg);
 269
 270	txcfg_reg = PRUSS_MII_RT_RX_FRMS1;
 271
 272	regmap_write(mii_rt, txcfg_reg, txcfg);
 273}
 274
 275static void icssm_prueth_clearmem(struct prueth *prueth, enum prueth_mem region)
 276{
 277	memset_io(prueth->mem[region].va, 0, prueth->mem[region].size);
 278}
 279
 280static void icssm_prueth_hostinit(struct prueth *prueth)
 281{
 282	/* Clear shared RAM */
 283	icssm_prueth_clearmem(prueth, PRUETH_MEM_SHARED_RAM);
 284
 285	/* Clear OCMC RAM */
 286	icssm_prueth_clearmem(prueth, PRUETH_MEM_OCMC);
 287
 288	/* Clear data RAMs */
 289	if (prueth->eth_node[PRUETH_MAC0])
 290		icssm_prueth_clearmem(prueth, PRUETH_MEM_DRAM0);
 291	if (prueth->eth_node[PRUETH_MAC1])
 292		icssm_prueth_clearmem(prueth, PRUETH_MEM_DRAM1);
 293
 294	/* Initialize host queues in shared RAM */
 295	icssm_prueth_hostconfig(prueth);
 296
 297	/* Configure MII_RT */
 298	icssm_prueth_mii_init(prueth);
 299}
 300
 301/* This function initialize the driver in EMAC mode
 302 * based on eth_type
 303 */
 304static void icssm_prueth_init_ethernet_mode(struct prueth *prueth)
 305{
 306	icssm_prueth_hostinit(prueth);
 307}
 308
 309static void icssm_prueth_port_enable(struct prueth_emac *emac, bool enable)
 310{
 311	struct prueth *prueth = emac->prueth;
 312	void __iomem *port_ctrl;
 313	void __iomem *ram;
 314
 315	ram = prueth->mem[emac->dram].va;
 316	port_ctrl = ram + PORT_CONTROL_ADDR;
 317	writeb(!!enable, port_ctrl);
 318}
 319
 320static int icssm_prueth_emac_config(struct prueth_emac *emac)
 321{
 322	struct prueth *prueth = emac->prueth;
 323	u32 sharedramaddr, ocmcaddr;
 324	void __iomem *dram_base;
 325	void __iomem *mac_addr;
 326	void __iomem *dram;
 327	void __iomem *sram;
 328
 329	/* PRU needs local shared RAM address for C28 */
 330	sharedramaddr = ICSS_LOCAL_SHARED_RAM;
 331	/* PRU needs real global OCMC address for C30*/
 332	ocmcaddr = (u32)prueth->mem[PRUETH_MEM_OCMC].pa;
 333	sram = prueth->mem[PRUETH_MEM_SHARED_RAM].va;
 334
 335	/* Clear data RAM */
 336	icssm_prueth_clearmem(prueth, emac->dram);
 337
 338	dram_base = prueth->mem[emac->dram].va;
 339
 340	/* setup mac address */
 341	mac_addr = dram_base + PORT_MAC_ADDR;
 342	memcpy_toio(mac_addr, emac->mac_addr, 6);
 343
 344	/* queue information table */
 345	dram = dram_base + TX_CONTEXT_Q1_OFFSET_ADDR;
 346	memcpy_toio(dram, queue_infos[emac->port_id],
 347		    sizeof(queue_infos[emac->port_id]));
 348
 349	/* queue table */
 350	dram = dram_base + PORT_QUEUE_DESC_OFFSET;
 351	memcpy_toio(dram, queue_descs[emac->port_id],
 352		    sizeof(queue_descs[emac->port_id]));
 353
 354	emac->rx_queue_descs = sram + HOST_QUEUE_DESC_OFFSET;
 355	emac->tx_queue_descs = dram;
 356
 357	/* Set in constant table C28 of PRU0 to ICSS Shared memory */
 358	pru_rproc_set_ctable(emac->pru, PRU_C28, sharedramaddr);
 359
 360	/* Set in constant table C30 of PRU0 to OCMC memory */
 361	pru_rproc_set_ctable(emac->pru, PRU_C30, ocmcaddr);
 362
 363	return 0;
 364}
 365
 366/* called back by PHY layer if there is change in link state of hw port*/
 367static void icssm_emac_adjust_link(struct net_device *ndev)
 368{
 369	struct prueth_emac *emac = netdev_priv(ndev);
 370	struct phy_device *phydev = emac->phydev;
 371	struct prueth *prueth = emac->prueth;
 372	bool new_state = false;
 373	enum prueth_mem region;
 374	unsigned long flags;
 375	u32 port_status = 0;
 376	u32 txcfg, mask;
 377	u32 delay;
 378
 379	spin_lock_irqsave(&emac->lock, flags);
 380
 381	if (phydev->link) {
 382		/* check the mode of operation */
 383		if (phydev->duplex != emac->duplex) {
 384			new_state = true;
 385			emac->duplex = phydev->duplex;
 386		}
 387		if (phydev->speed != emac->speed) {
 388			new_state = true;
 389			emac->speed = phydev->speed;
 390		}
 391		if (!emac->link) {
 392			new_state = true;
 393			emac->link = 1;
 394		}
 395	} else if (emac->link) {
 396		new_state = true;
 397		emac->link = 0;
 398	}
 399
 400	if (new_state) {
 401		phy_print_status(phydev);
 402		region = emac->dram;
 403
 404		/* update phy/port status information based on PHY values*/
 405		if (emac->link) {
 406			port_status |= PORT_LINK_MASK;
 407
 408			icssm_prueth_write_reg(prueth, region, PHY_SPEED_OFFSET,
 409					       emac->speed);
 410
 411			delay = TX_CLK_DELAY_100M;
 412			delay = delay << PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT;
 413			mask = PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK;
 414
 415			if (emac->port_id)
 416				txcfg = PRUSS_MII_RT_TXCFG1;
 417			else
 418				txcfg = PRUSS_MII_RT_TXCFG0;
 419
 420			regmap_update_bits(prueth->mii_rt, txcfg, mask, delay);
 421		}
 422
 423		writeb(port_status, prueth->mem[region].va +
 424		       PORT_STATUS_OFFSET);
 425	}
 426
 427	if (emac->link) {
 428	       /* reactivate the transmit queue if it is stopped */
 429		if (netif_running(ndev) && netif_queue_stopped(ndev))
 430			netif_wake_queue(ndev);
 431	} else {
 432		if (!netif_queue_stopped(ndev))
 433			netif_stop_queue(ndev);
 434	}
 435
 436	spin_unlock_irqrestore(&emac->lock, flags);
 437}
 438
 439static unsigned int
 440icssm_get_buff_desc_count(const struct prueth_queue_info *queue)
 441{
 442	unsigned int buffer_desc_count;
 443
 444	buffer_desc_count = queue->buffer_desc_end -
 445			    queue->buffer_desc_offset;
 446	buffer_desc_count /= BD_SIZE;
 447	buffer_desc_count++;
 448
 449	return buffer_desc_count;
 450}
 451
 452static void icssm_get_block(struct prueth_queue_desc __iomem *queue_desc,
 453			    const struct prueth_queue_info *queue,
 454			    int *write_block, int *read_block)
 455{
 456	*write_block = (readw(&queue_desc->wr_ptr) -
 457			queue->buffer_desc_offset) / BD_SIZE;
 458	*read_block = (readw(&queue_desc->rd_ptr) -
 459		       queue->buffer_desc_offset) / BD_SIZE;
 460}
 461
 462/**
 463 * icssm_emac_rx_irq - EMAC Rx interrupt handler
 464 * @irq: interrupt number
 465 * @dev_id: pointer to net_device
 466 *
 467 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
 468 * here.
 469 *
 470 * Return: IRQ_HANDLED if the interrupt handled
 471 */
 472static irqreturn_t icssm_emac_rx_irq(int irq, void *dev_id)
 473{
 474	struct net_device *ndev = (struct net_device *)dev_id;
 475	struct prueth_emac *emac = netdev_priv(ndev);
 476
 477	if (likely(netif_running(ndev))) {
 478		/* disable Rx system event */
 479		disable_irq_nosync(emac->rx_irq);
 480		napi_schedule(&emac->napi);
 481	}
 482
 483	return IRQ_HANDLED;
 484}
 485
 486/**
 487 * icssm_prueth_tx_enqueue - queue a packet to firmware for transmission
 488 *
 489 * @emac: EMAC data structure
 490 * @skb: packet data buffer
 491 * @queue_id: priority queue id
 492 *
 493 * Return: 0 (Success)
 494 */
 495static int icssm_prueth_tx_enqueue(struct prueth_emac *emac,
 496				   struct sk_buff *skb,
 497				   enum prueth_queue_id queue_id)
 498{
 499	struct prueth_queue_desc __iomem *queue_desc;
 500	const struct prueth_queue_info *txqueue;
 501	struct net_device *ndev = emac->ndev;
 502	unsigned int buffer_desc_count;
 503	int free_blocks, update_block;
 504	bool buffer_wrapped = false;
 505	int write_block, read_block;
 506	void *src_addr, *dst_addr;
 507	int pkt_block_size;
 508	void __iomem *dram;
 509	int txport, pktlen;
 510	u16 update_wr_ptr;
 511	u32 wr_buf_desc;
 512	void *ocmc_ram;
 513
 514	dram = emac->prueth->mem[emac->dram].va;
 515	if (eth_skb_pad(skb)) {
 516		if (netif_msg_tx_err(emac) && net_ratelimit())
 517			netdev_err(ndev, "packet pad failed\n");
 518		return -ENOMEM;
 519	}
 520
 521	/* which port to tx: MII0 or MII1 */
 522	txport = emac->tx_port_queue;
 523	src_addr = skb->data;
 524	pktlen = skb->len;
 525	/* Get the tx queue */
 526	queue_desc = emac->tx_queue_descs + queue_id;
 527	txqueue = &queue_infos[txport][queue_id];
 528
 529	buffer_desc_count = icssm_get_buff_desc_count(txqueue);
 530
 531	/* the PRU firmware deals mostly in pointers already
 532	 * offset into ram, we would like to deal in indexes
 533	 * within the queue we are working with for code
 534	 * simplicity, calculate this here
 535	 */
 536	icssm_get_block(queue_desc, txqueue, &write_block, &read_block);
 537
 538	if (write_block > read_block) {
 539		free_blocks = buffer_desc_count - write_block;
 540		free_blocks += read_block;
 541	} else if (write_block < read_block) {
 542		free_blocks = read_block - write_block;
 543	} else { /* they are all free */
 544		free_blocks = buffer_desc_count;
 545	}
 546
 547	pkt_block_size = DIV_ROUND_UP(pktlen, ICSS_BLOCK_SIZE);
 548	if (pkt_block_size > free_blocks) /* out of queue space */
 549		return -ENOBUFS;
 550
 551	/* calculate end BD address post write */
 552	update_block = write_block + pkt_block_size;
 553
 554	/* Check for wrap around */
 555	if (update_block >= buffer_desc_count) {
 556		update_block %= buffer_desc_count;
 557		buffer_wrapped = true;
 558	}
 559
 560	/* OCMC RAM is not cached and write order is not important */
 561	ocmc_ram = (__force void *)emac->prueth->mem[PRUETH_MEM_OCMC].va;
 562	dst_addr = ocmc_ram + txqueue->buffer_offset +
 563		   (write_block * ICSS_BLOCK_SIZE);
 564
 565	/* Copy the data from socket buffer(DRAM) to PRU buffers(OCMC) */
 566	if (buffer_wrapped) { /* wrapped around buffer */
 567		int bytes = (buffer_desc_count - write_block) * ICSS_BLOCK_SIZE;
 568		int remaining;
 569
 570		/* bytes is integral multiple of ICSS_BLOCK_SIZE but
 571		 * entire packet may have fit within the last BD
 572		 * if pkt_info.length is not integral multiple of
 573		 * ICSS_BLOCK_SIZE
 574		 */
 575		if (pktlen < bytes)
 576			bytes = pktlen;
 577
 578		/* copy non-wrapped part */
 579		memcpy(dst_addr, src_addr, bytes);
 580
 581		/* copy wrapped part */
 582		src_addr += bytes;
 583		remaining = pktlen - bytes;
 584		dst_addr = ocmc_ram + txqueue->buffer_offset;
 585		memcpy(dst_addr, src_addr, remaining);
 586	} else {
 587		memcpy(dst_addr, src_addr, pktlen);
 588	}
 589
 590       /* update first buffer descriptor */
 591	wr_buf_desc = (pktlen << PRUETH_BD_LENGTH_SHIFT) &
 592		       PRUETH_BD_LENGTH_MASK;
 593	writel(wr_buf_desc, dram + readw(&queue_desc->wr_ptr));
 594
 595	/* update the write pointer in this queue descriptor, the firmware
 596	 * polls for this change so this will signal the start of transmission
 597	 */
 598	update_wr_ptr = txqueue->buffer_desc_offset + (update_block * BD_SIZE);
 599	writew(update_wr_ptr, &queue_desc->wr_ptr);
 600
 601	return 0;
 602}
 603
 604void icssm_parse_packet_info(struct prueth *prueth, u32 buffer_descriptor,
 605			     struct prueth_packet_info *pkt_info)
 606{
 607	pkt_info->shadow = !!(buffer_descriptor & PRUETH_BD_SHADOW_MASK);
 608	pkt_info->port = (buffer_descriptor & PRUETH_BD_PORT_MASK) >>
 609			 PRUETH_BD_PORT_SHIFT;
 610	pkt_info->length = (buffer_descriptor & PRUETH_BD_LENGTH_MASK) >>
 611			   PRUETH_BD_LENGTH_SHIFT;
 612	pkt_info->broadcast = !!(buffer_descriptor & PRUETH_BD_BROADCAST_MASK);
 613	pkt_info->error = !!(buffer_descriptor & PRUETH_BD_ERROR_MASK);
 614	pkt_info->lookup_success = !!(buffer_descriptor &
 615				      PRUETH_BD_LOOKUP_SUCCESS_MASK);
 616	pkt_info->flood = !!(buffer_descriptor & PRUETH_BD_SW_FLOOD_MASK);
 617	pkt_info->timestamp = !!(buffer_descriptor & PRUETH_BD_TIMESTAMP_MASK);
 618}
 619
 620/**
 621 * icssm_emac_rx_packet - EMAC Receive function
 622 *
 623 * @emac: EMAC data structure
 624 * @bd_rd_ptr: Buffer descriptor read pointer
 625 * @pkt_info: packet information structure
 626 * @rxqueue: Receive queue information structure
 627 *
 628 * Get a packet from receive queue
 629 *
 630 * Return: 0 (Success)
 631 */
 632int icssm_emac_rx_packet(struct prueth_emac *emac, u16 *bd_rd_ptr,
 633			 struct prueth_packet_info *pkt_info,
 634			 const struct prueth_queue_info *rxqueue)
 635{
 636	struct net_device *ndev = emac->ndev;
 637	unsigned int buffer_desc_count;
 638	int read_block, update_block;
 639	unsigned int actual_pkt_len;
 640	bool buffer_wrapped = false;
 641	void *src_addr, *dst_addr;
 642	struct sk_buff *skb;
 643	int pkt_block_size;
 644	void *ocmc_ram;
 645
 646	/* the PRU firmware deals mostly in pointers already
 647	 * offset into ram, we would like to deal in indexes
 648	 * within the queue we are working with for code
 649	 * simplicity, calculate this here
 650	 */
 651	buffer_desc_count = icssm_get_buff_desc_count(rxqueue);
 652	read_block = (*bd_rd_ptr - rxqueue->buffer_desc_offset) / BD_SIZE;
 653	pkt_block_size = DIV_ROUND_UP(pkt_info->length, ICSS_BLOCK_SIZE);
 654
 655	/* calculate end BD address post read */
 656	update_block = read_block + pkt_block_size;
 657
 658	/* Check for wrap around */
 659	if (update_block >= buffer_desc_count) {
 660		update_block %= buffer_desc_count;
 661		if (update_block)
 662			buffer_wrapped = true;
 663	}
 664
 665	/* calculate new pointer in ram */
 666	*bd_rd_ptr = rxqueue->buffer_desc_offset + (update_block * BD_SIZE);
 667
 668	actual_pkt_len = pkt_info->length;
 669
 670	/* Allocate a socket buffer for this packet */
 671	skb = netdev_alloc_skb_ip_align(ndev, actual_pkt_len);
 672	if (!skb) {
 673		if (netif_msg_rx_err(emac) && net_ratelimit())
 674			netdev_err(ndev, "failed rx buffer alloc\n");
 675		return -ENOMEM;
 676	}
 677
 678	dst_addr = skb->data;
 679
 680	/* OCMC RAM is not cached and read order is not important */
 681	ocmc_ram = (__force void *)emac->prueth->mem[PRUETH_MEM_OCMC].va;
 682
 683	/* Get the start address of the first buffer from
 684	 * the read buffer description
 685	 */
 686	src_addr = ocmc_ram + rxqueue->buffer_offset +
 687		   (read_block * ICSS_BLOCK_SIZE);
 688
 689	/* Copy the data from PRU buffers(OCMC) to socket buffer(DRAM) */
 690	if (buffer_wrapped) { /* wrapped around buffer */
 691		int bytes = (buffer_desc_count - read_block) * ICSS_BLOCK_SIZE;
 692		int remaining;
 693		/* bytes is integral multiple of ICSS_BLOCK_SIZE but
 694		 * entire packet may have fit within the last BD
 695		 * if pkt_info.length is not integral multiple of
 696		 * ICSS_BLOCK_SIZE
 697		 */
 698		if (pkt_info->length < bytes)
 699			bytes = pkt_info->length;
 700
 701		/* copy non-wrapped part */
 702		memcpy(dst_addr, src_addr, bytes);
 703
 704		/* copy wrapped part */
 705		dst_addr += bytes;
 706		remaining = actual_pkt_len - bytes;
 707
 708		src_addr = ocmc_ram + rxqueue->buffer_offset;
 709		memcpy(dst_addr, src_addr, remaining);
 710		src_addr += remaining;
 711	} else {
 712		memcpy(dst_addr, src_addr, actual_pkt_len);
 713		src_addr += actual_pkt_len;
 714	}
 715
 716	skb_put(skb, actual_pkt_len);
 717
 718	/* send packet up the stack */
 719	skb->protocol = eth_type_trans(skb, ndev);
 720	netif_receive_skb(skb);
 721
 722	/* update stats */
 723	emac->stats.rx_bytes += actual_pkt_len;
 724	emac->stats.rx_packets++;
 725
 726	return 0;
 727}
 728
 729static int icssm_emac_rx_packets(struct prueth_emac *emac, int budget)
 730{
 731	struct prueth_queue_desc __iomem *queue_desc;
 732	const struct prueth_queue_info *rxqueue;
 733	struct prueth *prueth = emac->prueth;
 734	struct prueth_packet_info pkt_info;
 735	int start_queue, end_queue;
 736	void __iomem *shared_ram;
 737	u16 bd_rd_ptr, bd_wr_ptr;
 738	u16 update_rd_ptr;
 739	u8 overflow_cnt;
 740	u32 rd_buf_desc;
 741	int used = 0;
 742	int i, ret;
 743
 744	shared_ram = emac->prueth->mem[PRUETH_MEM_SHARED_RAM].va;
 745
 746	start_queue = emac->rx_queue_start;
 747	end_queue = emac->rx_queue_end;
 748
 749	/* skip Rx if budget is 0 */
 750	if (!budget)
 751		return 0;
 752
 753	/* search host queues for packets */
 754	for (i = start_queue; i <= end_queue; i++) {
 755		queue_desc = emac->rx_queue_descs + i;
 756		rxqueue = &queue_infos[PRUETH_PORT_HOST][i];
 757
 758		overflow_cnt = readb(&queue_desc->overflow_cnt);
 759		if (overflow_cnt > 0) {
 760			emac->stats.rx_over_errors += overflow_cnt;
 761			/* reset to zero */
 762			writeb(0, &queue_desc->overflow_cnt);
 763		}
 764
 765		bd_rd_ptr = readw(&queue_desc->rd_ptr);
 766		bd_wr_ptr = readw(&queue_desc->wr_ptr);
 767
 768		/* while packets are available in this queue */
 769		while (bd_rd_ptr != bd_wr_ptr) {
 770			/* get packet info from the read buffer descriptor */
 771			rd_buf_desc = readl(shared_ram + bd_rd_ptr);
 772			icssm_parse_packet_info(prueth, rd_buf_desc, &pkt_info);
 773
 774			if (pkt_info.length <= 0) {
 775				/* a packet length of zero will cause us to
 776				 * never move the read pointer ahead, locking
 777				 * the driver, so we manually have to move it
 778				 * to the write pointer, discarding all
 779				 * remaining packets in this queue. This should
 780				 * never happen.
 781				 */
 782				update_rd_ptr = bd_wr_ptr;
 783				emac->stats.rx_length_errors++;
 784			} else if (pkt_info.length > EMAC_MAX_FRM_SUPPORT) {
 785				/* if the packet is too large we skip it but we
 786				 * still need to move the read pointer ahead
 787				 * and assume something is wrong with the read
 788				 * pointer as the firmware should be filtering
 789				 * these packets
 790				 */
 791				update_rd_ptr = bd_wr_ptr;
 792				emac->stats.rx_length_errors++;
 793			} else {
 794				update_rd_ptr = bd_rd_ptr;
 795				ret = icssm_emac_rx_packet(emac, &update_rd_ptr,
 796							   &pkt_info, rxqueue);
 797				if (ret)
 798					return used;
 799				used++;
 800			}
 801
 802			/* after reading the buffer descriptor we clear it
 803			 * to prevent improperly moved read pointer errors
 804			 * from simply looking like old packets.
 805			 */
 806			writel(0, shared_ram + bd_rd_ptr);
 807
 808			/* update read pointer in queue descriptor */
 809			writew(update_rd_ptr, &queue_desc->rd_ptr);
 810			bd_rd_ptr = update_rd_ptr;
 811
 812			/* all we have room for? */
 813			if (used >= budget)
 814				return used;
 815		}
 816	}
 817
 818	return used;
 819}
 820
 821static int icssm_emac_napi_poll(struct napi_struct *napi, int budget)
 822{
 823	struct prueth_emac *emac = container_of(napi, struct prueth_emac, napi);
 824	int num_rx;
 825
 826	num_rx = icssm_emac_rx_packets(emac, budget);
 827
 828	if (num_rx < budget && napi_complete_done(napi, num_rx))
 829		enable_irq(emac->rx_irq);
 830
 831	return num_rx;
 832}
 833
 834static int icssm_emac_set_boot_pru(struct prueth_emac *emac,
 835				   struct net_device *ndev)
 836{
 837	const struct prueth_firmware *pru_firmwares;
 838	struct prueth *prueth = emac->prueth;
 839	const char *fw_name;
 840	int ret;
 841
 842	pru_firmwares = &prueth->fw_data->fw_pru[emac->port_id - 1];
 843	fw_name = pru_firmwares->fw_name[prueth->eth_type];
 844	if (!fw_name) {
 845		netdev_err(ndev, "eth_type %d not supported\n",
 846			   prueth->eth_type);
 847		return -ENODEV;
 848	}
 849
 850	ret = rproc_set_firmware(emac->pru, fw_name);
 851	if (ret) {
 852		netdev_err(ndev, "failed to set %s firmware: %d\n",
 853			   fw_name, ret);
 854		return ret;
 855	}
 856
 857	ret = rproc_boot(emac->pru);
 858	if (ret) {
 859		netdev_err(ndev, "failed to boot %s firmware: %d\n",
 860			   fw_name, ret);
 861		return ret;
 862	}
 863	return ret;
 864}
 865
 866static int icssm_emac_request_irqs(struct prueth_emac *emac)
 867{
 868	struct net_device *ndev = emac->ndev;
 869	int ret;
 870
 871	ret = request_irq(emac->rx_irq, icssm_emac_rx_irq,
 872			  IRQF_TRIGGER_HIGH,
 873			  ndev->name, ndev);
 874	if (ret) {
 875		netdev_err(ndev, "unable to request RX IRQ\n");
 876		return ret;
 877	}
 878
 879	return ret;
 880}
 881
 882static void icssm_ptp_dram_init(struct prueth_emac *emac)
 883{
 884	void __iomem *sram = emac->prueth->mem[PRUETH_MEM_SHARED_RAM].va;
 885	u64 temp64;
 886
 887	writew(0, sram + MII_RX_CORRECTION_OFFSET);
 888	writew(0, sram + MII_TX_CORRECTION_OFFSET);
 889
 890	/* Initialize RCF to 1 (Linux N/A) */
 891	writel(1 * 1024, sram + TIMESYNC_TC_RCF_OFFSET);
 892
 893	/* This flag will be set and cleared by firmware */
 894	/* Write Sync0 period for sync signal generation in PTP
 895	 * memory in shared RAM
 896	 */
 897	writel(200000000 / 50, sram + TIMESYNC_SYNC0_WIDTH_OFFSET);
 898
 899	/* Write CMP1 period for sync signal generation in PTP
 900	 * memory in shared RAM
 901	 */
 902	temp64 = 1000000;
 903	memcpy_toio(sram + TIMESYNC_CMP1_CMP_OFFSET, &temp64, sizeof(temp64));
 904
 905	/* Write Sync0 period for sync signal generation in PTP
 906	 * memory in shared RAM
 907	 */
 908	writel(1000000, sram + TIMESYNC_CMP1_PERIOD_OFFSET);
 909
 910	/* Configures domainNumber list. Firmware supports 2 domains */
 911	writeb(0, sram + TIMESYNC_DOMAIN_NUMBER_LIST);
 912	writeb(0, sram + TIMESYNC_DOMAIN_NUMBER_LIST + 1);
 913
 914	/* Configure 1-step/2-step */
 915	writeb(1, sram + DISABLE_SWITCH_SYNC_RELAY_OFFSET);
 916
 917	/* Configures the setting to Link local frame without HSR tag */
 918	writeb(0, sram + LINK_LOCAL_FRAME_HAS_HSR_TAG);
 919
 920	/* Enable E2E/UDP PTP message timestamping */
 921	writeb(1, sram + PTP_IPV4_UDP_E2E_ENABLE);
 922}
 923
 924/**
 925 * icssm_emac_ndo_open - EMAC device open
 926 * @ndev: network adapter device
 927 *
 928 * Called when system wants to start the interface.
 929 *
 930 * Return: 0 for a successful open, or appropriate error code
 931 */
 932static int icssm_emac_ndo_open(struct net_device *ndev)
 933{
 934	struct prueth_emac *emac = netdev_priv(ndev);
 935	struct prueth *prueth = emac->prueth;
 936	int ret;
 937
 938	/* set h/w MAC as user might have re-configured */
 939	ether_addr_copy(emac->mac_addr, ndev->dev_addr);
 940
 941	if (!prueth->emac_configured)
 942		icssm_prueth_init_ethernet_mode(prueth);
 943
 944	icssm_prueth_emac_config(emac);
 945
 946	if (!prueth->emac_configured) {
 947		icssm_ptp_dram_init(emac);
 948		ret = icss_iep_init(prueth->iep, NULL, NULL, 0);
 949		if (ret) {
 950			netdev_err(ndev, "Failed to initialize iep: %d\n", ret);
 951			goto iep_exit;
 952		}
 953	}
 954
 955	ret = icssm_emac_set_boot_pru(emac, ndev);
 956	if (ret)
 957		goto iep_exit;
 958
 959	ret = icssm_emac_request_irqs(emac);
 960	if (ret)
 961		goto rproc_shutdown;
 962
 963	napi_enable(&emac->napi);
 964
 965	/* start PHY */
 966	phy_start(emac->phydev);
 967
 968	/* enable the port and vlan */
 969	icssm_prueth_port_enable(emac, true);
 970
 971	prueth->emac_configured |= BIT(emac->port_id);
 972
 973	if (netif_msg_drv(emac))
 974		dev_notice(&ndev->dev, "started\n");
 975
 976	return 0;
 977
 978rproc_shutdown:
 979	rproc_shutdown(emac->pru);
 980
 981iep_exit:
 982	if (!prueth->emac_configured)
 983		icss_iep_exit(prueth->iep);
 984
 985	return ret;
 986}
 987
 988/**
 989 * icssm_emac_ndo_stop - EMAC device stop
 990 * @ndev: network adapter device
 991 *
 992 * Called when system wants to stop or down the interface.
 993 *
 994 * Return: Always 0 (Success)
 995 */
 996static int icssm_emac_ndo_stop(struct net_device *ndev)
 997{
 998	struct prueth_emac *emac = netdev_priv(ndev);
 999	struct prueth *prueth = emac->prueth;
1000
1001	prueth->emac_configured &= ~BIT(emac->port_id);
1002
1003	/* disable the mac port */
1004	icssm_prueth_port_enable(emac, false);
1005
1006	/* stop PHY */
1007	phy_stop(emac->phydev);
1008
1009	napi_disable(&emac->napi);
1010	hrtimer_cancel(&emac->tx_hrtimer);
1011
1012	/* stop the PRU */
1013	rproc_shutdown(emac->pru);
1014
1015	/* free rx interrupts */
1016	free_irq(emac->rx_irq, ndev);
1017
1018	if (netif_msg_drv(emac))
1019		dev_notice(&ndev->dev, "stopped\n");
1020
1021	return 0;
1022}
1023
1024/* VLAN-tag PCP to priority queue map for EMAC/Switch/HSR/PRP used by driver
1025 * Index is PCP val / 2.
1026 *   low  - pcp 0..3 maps to Q4 for Host
1027 *   high - pcp 4..7 maps to Q3 for Host
1028 *   low  - pcp 0..3 maps to Q2 (FWD Queue) for PRU-x
1029 *   where x = 1 for PRUETH_PORT_MII0
1030 *             0 for PRUETH_PORT_MII1
1031 *   high - pcp 4..7 maps to Q1 (FWD Queue) for PRU-x
1032 */
1033static const unsigned short emac_pcp_tx_priority_queue_map[] = {
1034	PRUETH_QUEUE4, PRUETH_QUEUE4,
1035	PRUETH_QUEUE3, PRUETH_QUEUE3,
1036	PRUETH_QUEUE2, PRUETH_QUEUE2,
1037	PRUETH_QUEUE1, PRUETH_QUEUE1,
1038};
1039
1040static u16 icssm_prueth_get_tx_queue_id(struct prueth *prueth,
1041					struct sk_buff *skb)
1042{
1043	u16 vlan_tci, pcp;
1044	int err;
1045
1046	err = vlan_get_tag(skb, &vlan_tci);
1047	if (likely(err))
1048		pcp = 0;
1049	else
1050		pcp = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1051
1052	/* Below code (pcp >>= 1) is made common for all
1053	 * protocols (i.e., EMAC, RSTP, HSR and PRP)*
1054	 * pcp value 0,1 will be updated to 0 mapped to QUEUE4
1055	 * pcp value 2,3 will be updated to 1 mapped to QUEUE4
1056	 * pcp value 4,5 will be updated to 2 mapped to QUEUE3
1057	 * pcp value 6,7 will be updated to 3 mapped to QUEUE3
1058	 */
1059	pcp >>= 1;
1060
1061	return emac_pcp_tx_priority_queue_map[pcp];
1062}
1063
1064/**
1065 * icssm_emac_ndo_start_xmit - EMAC Transmit function
1066 * @skb: SKB pointer
1067 * @ndev: EMAC network adapter
1068 *
1069 * Called by the system to transmit a packet - we queue the packet in
1070 * EMAC hardware transmit queue
1071 *
1072 * Return: enum netdev_tx
1073 */
1074static enum netdev_tx icssm_emac_ndo_start_xmit(struct sk_buff *skb,
1075						struct net_device *ndev)
1076{
1077	struct prueth_emac *emac = netdev_priv(ndev);
1078	int ret;
1079	u16 qid;
1080
1081	qid = icssm_prueth_get_tx_queue_id(emac->prueth, skb);
1082	ret = icssm_prueth_tx_enqueue(emac, skb, qid);
1083	if (ret) {
1084		if (ret != -ENOBUFS && netif_msg_tx_err(emac) &&
1085		    net_ratelimit())
1086			netdev_err(ndev, "packet queue failed: %d\n", ret);
1087		goto fail_tx;
1088	}
1089
1090	emac->stats.tx_packets++;
1091	emac->stats.tx_bytes += skb->len;
1092	dev_kfree_skb_any(skb);
1093
1094	return NETDEV_TX_OK;
1095
1096fail_tx:
1097	if (ret == -ENOBUFS) {
1098		netif_stop_queue(ndev);
1099		hrtimer_start(&emac->tx_hrtimer,
1100			      us_to_ktime(HR_TIMER_TX_DELAY_US),
1101			      HRTIMER_MODE_REL_PINNED);
1102		ret = NETDEV_TX_BUSY;
1103	} else {
1104		/* error */
1105		emac->stats.tx_dropped++;
1106		ret = NET_XMIT_DROP;
1107	}
1108
1109	return ret;
1110}
1111
1112/**
1113 * icssm_emac_ndo_get_stats64 - EMAC get statistics function
1114 * @ndev: The EMAC network adapter
1115 * @stats: rtnl_link_stats structure
1116 *
1117 * Called when system wants to get statistics from the device.
1118 *
1119 */
1120static void icssm_emac_ndo_get_stats64(struct net_device *ndev,
1121				       struct rtnl_link_stats64 *stats)
1122{
1123	struct prueth_emac *emac = netdev_priv(ndev);
1124
1125	stats->rx_packets = emac->stats.rx_packets;
1126	stats->rx_bytes = emac->stats.rx_bytes;
1127	stats->tx_packets = emac->stats.tx_packets;
1128	stats->tx_bytes = emac->stats.tx_bytes;
1129	stats->tx_dropped = emac->stats.tx_dropped;
1130	stats->rx_over_errors = emac->stats.rx_over_errors;
1131	stats->rx_length_errors = emac->stats.rx_length_errors;
1132}
1133
1134static const struct net_device_ops emac_netdev_ops = {
1135	.ndo_open = icssm_emac_ndo_open,
1136	.ndo_stop = icssm_emac_ndo_stop,
1137	.ndo_start_xmit = icssm_emac_ndo_start_xmit,
1138	.ndo_get_stats64 = icssm_emac_ndo_get_stats64,
1139};
1140
1141/* get emac_port corresponding to eth_node name */
1142static int icssm_prueth_node_port(struct device_node *eth_node)
1143{
1144	u32 port_id;
1145	int ret;
1146
1147	ret = of_property_read_u32(eth_node, "reg", &port_id);
1148	if (ret)
1149		return ret;
1150
1151	if (port_id == 0)
1152		return PRUETH_PORT_MII0;
1153	else if (port_id == 1)
1154		return PRUETH_PORT_MII1;
1155	else
1156		return PRUETH_PORT_INVALID;
1157}
1158
1159/* get MAC instance corresponding to eth_node name */
1160static int icssm_prueth_node_mac(struct device_node *eth_node)
1161{
1162	u32 port_id;
1163	int ret;
1164
1165	ret = of_property_read_u32(eth_node, "reg", &port_id);
1166	if (ret)
1167		return ret;
1168
1169	if (port_id == 0)
1170		return PRUETH_MAC0;
1171	else if (port_id == 1)
1172		return PRUETH_MAC1;
1173	else
1174		return PRUETH_MAC_INVALID;
1175}
1176
1177static enum hrtimer_restart icssm_emac_tx_timer_callback(struct hrtimer *timer)
1178{
1179	struct prueth_emac *emac =
1180			container_of(timer, struct prueth_emac, tx_hrtimer);
1181
1182	if (netif_queue_stopped(emac->ndev))
1183		netif_wake_queue(emac->ndev);
1184
1185	return HRTIMER_NORESTART;
1186}
1187
1188static int icssm_prueth_netdev_init(struct prueth *prueth,
1189				    struct device_node *eth_node)
1190{
1191	struct prueth_emac *emac;
1192	struct net_device *ndev;
1193	enum prueth_port port;
1194	enum prueth_mac mac;
1195	int ret;
1196
1197	port = icssm_prueth_node_port(eth_node);
1198	if (port == PRUETH_PORT_INVALID)
1199		return -EINVAL;
1200
1201	mac = icssm_prueth_node_mac(eth_node);
1202	if (mac == PRUETH_MAC_INVALID)
1203		return -EINVAL;
1204
1205	ndev = devm_alloc_etherdev(prueth->dev, sizeof(*emac));
1206	if (!ndev)
1207		return -ENOMEM;
1208
1209	SET_NETDEV_DEV(ndev, prueth->dev);
1210	emac = netdev_priv(ndev);
1211	prueth->emac[mac] = emac;
1212	emac->prueth = prueth;
1213	emac->ndev = ndev;
1214	emac->port_id = port;
1215
1216	/* by default eth_type is EMAC */
1217	switch (port) {
1218	case PRUETH_PORT_MII0:
1219		emac->tx_port_queue = PRUETH_PORT_QUEUE_MII0;
1220
1221		/* packets from MII0 are on queues 1 through 2 */
1222		emac->rx_queue_start = PRUETH_QUEUE1;
1223		emac->rx_queue_end = PRUETH_QUEUE2;
1224
1225		emac->dram = PRUETH_MEM_DRAM0;
1226		emac->pru = prueth->pru0;
1227		break;
1228	case PRUETH_PORT_MII1:
1229		emac->tx_port_queue = PRUETH_PORT_QUEUE_MII1;
1230
1231		/* packets from MII1 are on queues 3 through 4 */
1232		emac->rx_queue_start = PRUETH_QUEUE3;
1233		emac->rx_queue_end = PRUETH_QUEUE4;
1234
1235		emac->dram = PRUETH_MEM_DRAM1;
1236		emac->pru = prueth->pru1;
1237		break;
1238	default:
1239		return -EINVAL;
1240	}
1241
1242	emac->rx_irq = of_irq_get_byname(eth_node, "rx");
1243	if (emac->rx_irq < 0) {
1244		ret = emac->rx_irq;
1245		if (ret != -EPROBE_DEFER)
1246			dev_err(prueth->dev, "could not get rx irq\n");
1247		goto free;
1248	}
1249
1250	/* get mac address from DT and set private and netdev addr */
1251	ret = of_get_ethdev_address(eth_node, ndev);
1252	if (!is_valid_ether_addr(ndev->dev_addr)) {
1253		eth_hw_addr_random(ndev);
1254		dev_warn(prueth->dev, "port %d: using random MAC addr: %pM\n",
1255			 port, ndev->dev_addr);
1256	}
1257	ether_addr_copy(emac->mac_addr, ndev->dev_addr);
1258
1259	/* connect PHY */
1260	emac->phydev = of_phy_get_and_connect(ndev, eth_node,
1261					      icssm_emac_adjust_link);
1262	if (!emac->phydev) {
1263		dev_dbg(prueth->dev, "PHY connection failed\n");
1264		ret = -ENODEV;
1265		goto free;
1266	}
1267
1268	/* remove unsupported modes */
1269	phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1270
1271	phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1272	phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1273
1274	phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1275	phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1276
1277	ndev->dev.of_node = eth_node;
1278	ndev->netdev_ops = &emac_netdev_ops;
1279
1280	netif_napi_add(ndev, &emac->napi, icssm_emac_napi_poll);
1281
1282	hrtimer_setup(&emac->tx_hrtimer, &icssm_emac_tx_timer_callback,
1283		      CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED);
1284
1285	return 0;
1286free:
1287	emac->ndev = NULL;
1288	prueth->emac[mac] = NULL;
1289
1290	return ret;
1291}
1292
1293static void icssm_prueth_netdev_exit(struct prueth *prueth,
1294				     struct device_node *eth_node)
1295{
1296	struct prueth_emac *emac;
1297	enum prueth_mac mac;
1298
1299	mac = icssm_prueth_node_mac(eth_node);
1300	if (mac == PRUETH_MAC_INVALID)
1301		return;
1302
1303	emac = prueth->emac[mac];
1304	if (!emac)
1305		return;
1306
1307	phy_disconnect(emac->phydev);
1308
1309	netif_napi_del(&emac->napi);
1310	prueth->emac[mac] = NULL;
1311}
1312
1313static int icssm_prueth_probe(struct platform_device *pdev)
1314{
1315	struct device_node *eth0_node = NULL, *eth1_node = NULL;
1316	struct device_node *eth_node, *eth_ports_node;
1317	enum pruss_pru_id pruss_id0, pruss_id1;
1318	struct device *dev = &pdev->dev;
1319	struct device_node *np;
1320	struct prueth *prueth;
1321	struct pruss *pruss;
1322	int i, ret;
1323
1324	np = dev->of_node;
1325	if (!np)
1326		return -ENODEV; /* we don't support non DT */
1327
1328	prueth = devm_kzalloc(dev, sizeof(*prueth), GFP_KERNEL);
1329	if (!prueth)
1330		return -ENOMEM;
1331
1332	platform_set_drvdata(pdev, prueth);
1333	prueth->dev = dev;
1334	prueth->fw_data = device_get_match_data(dev);
1335
1336	eth_ports_node = of_get_child_by_name(np, "ethernet-ports");
1337	if (!eth_ports_node)
1338		return -ENOENT;
1339
1340	for_each_child_of_node(eth_ports_node, eth_node) {
1341		u32 reg;
1342
1343		if (strcmp(eth_node->name, "ethernet-port"))
1344			continue;
1345		ret = of_property_read_u32(eth_node, "reg", &reg);
1346		if (ret < 0) {
1347			dev_err(dev, "%pOF error reading port_id %d\n",
1348				eth_node, ret);
1349			of_node_put(eth_node);
1350			return ret;
1351		}
1352
1353		of_node_get(eth_node);
1354
1355		if (reg == 0 && !eth0_node) {
1356			eth0_node = eth_node;
1357			if (!of_device_is_available(eth0_node)) {
1358				of_node_put(eth0_node);
1359				eth0_node = NULL;
1360			}
1361		} else if (reg == 1 && !eth1_node) {
1362			eth1_node = eth_node;
1363			if (!of_device_is_available(eth1_node)) {
1364				of_node_put(eth1_node);
1365				eth1_node = NULL;
1366			}
1367		} else {
1368			if (reg == 0 || reg == 1)
1369				dev_err(dev, "duplicate port reg value: %d\n",
1370					reg);
1371			else
1372				dev_err(dev, "invalid port reg value: %d\n",
1373					reg);
1374
1375			of_node_put(eth_node);
1376		}
1377	}
1378
1379	of_node_put(eth_ports_node);
1380
1381	/* At least one node must be present and available else we fail */
1382	if (!eth0_node && !eth1_node) {
1383		dev_err(dev, "neither port0 nor port1 node available\n");
1384		return -ENODEV;
1385	}
1386
1387	prueth->eth_node[PRUETH_MAC0] = eth0_node;
1388	prueth->eth_node[PRUETH_MAC1] = eth1_node;
1389
1390	prueth->mii_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-rt");
1391	if (IS_ERR(prueth->mii_rt)) {
1392		dev_err(dev, "couldn't get mii-rt syscon regmap\n");
1393		ret = PTR_ERR(prueth->mii_rt);
1394		goto put_eth;
1395	}
1396
1397	if (eth0_node) {
1398		prueth->pru0 = pru_rproc_get(np, 0, &pruss_id0);
1399		if (IS_ERR(prueth->pru0)) {
1400			ret = PTR_ERR(prueth->pru0);
1401			dev_err_probe(dev, ret, "unable to get PRU0");
1402			goto put_eth;
1403		}
1404	}
1405
1406	if (eth1_node) {
1407		prueth->pru1 = pru_rproc_get(np, 1, &pruss_id1);
1408		if (IS_ERR(prueth->pru1)) {
1409			ret = PTR_ERR(prueth->pru1);
1410			dev_err_probe(dev, ret, "unable to get PRU1");
1411			goto put_pru0;
1412		}
1413	}
1414
1415	pruss = pruss_get(prueth->pru0 ? prueth->pru0 : prueth->pru1);
1416	if (IS_ERR(pruss)) {
1417		ret = PTR_ERR(pruss);
1418		dev_err(dev, "unable to get pruss handle\n");
1419		goto put_pru1;
1420	}
1421	prueth->pruss = pruss;
1422
1423	/* Configure PRUSS */
1424	if (eth0_node)
1425		pruss_cfg_gpimode(pruss, pruss_id0, PRUSS_GPI_MODE_MII);
1426	if (eth1_node)
1427		pruss_cfg_gpimode(pruss, pruss_id1, PRUSS_GPI_MODE_MII);
1428	pruss_cfg_miirt_enable(pruss, true);
1429	pruss_cfg_xfr_enable(pruss, PRU_TYPE_PRU, true);
1430
1431	/* Get PRUSS mem resources */
1432	/* OCMC is system resource which we get separately */
1433	for (i = 0; i < ARRAY_SIZE(pruss_mem_ids); i++) {
1434		/* skip appropriate DRAM if not required */
1435		if (!eth0_node && i == PRUETH_MEM_DRAM0)
1436			continue;
1437
1438		if (!eth1_node && i == PRUETH_MEM_DRAM1)
1439			continue;
1440
1441		ret = pruss_request_mem_region(pruss, pruss_mem_ids[i],
1442					       &prueth->mem[i]);
1443		if (ret) {
1444			dev_err(dev, "unable to get PRUSS resource %d: %d\n",
1445				i, ret);
1446			goto put_mem;
1447		}
1448	}
1449
1450	prueth->sram_pool = of_gen_pool_get(np, "sram", 0);
1451	if (!prueth->sram_pool) {
1452		dev_err(dev, "unable to get SRAM pool\n");
1453		ret = -ENODEV;
1454		goto put_mem;
1455	}
1456
1457	prueth->ocmc_ram_size = OCMC_RAM_SIZE;
1458	/* Decreased by 8KB to address the reserved region for AM33x */
1459	if (prueth->fw_data->driver_data == PRUSS_AM33XX)
1460		prueth->ocmc_ram_size = (SZ_64K - SZ_8K);
1461
1462	prueth->mem[PRUETH_MEM_OCMC].va =
1463			(void __iomem *)gen_pool_alloc(prueth->sram_pool,
1464						       prueth->ocmc_ram_size);
1465	if (!prueth->mem[PRUETH_MEM_OCMC].va) {
1466		dev_err(dev, "unable to allocate OCMC resource\n");
1467		ret = -ENOMEM;
1468		goto put_mem;
1469	}
1470	prueth->mem[PRUETH_MEM_OCMC].pa = gen_pool_virt_to_phys
1471		(prueth->sram_pool, (unsigned long)
1472		 prueth->mem[PRUETH_MEM_OCMC].va);
1473	prueth->mem[PRUETH_MEM_OCMC].size = prueth->ocmc_ram_size;
1474	dev_dbg(dev, "ocmc: pa %pa va %p size %#zx\n",
1475		&prueth->mem[PRUETH_MEM_OCMC].pa,
1476		prueth->mem[PRUETH_MEM_OCMC].va,
1477		prueth->mem[PRUETH_MEM_OCMC].size);
1478
1479	/* setup netdev interfaces */
1480	if (eth0_node) {
1481		ret = icssm_prueth_netdev_init(prueth, eth0_node);
1482		if (ret) {
1483			if (ret != -EPROBE_DEFER) {
1484				dev_err(dev, "netdev init %s failed: %d\n",
1485					eth0_node->name, ret);
1486			}
1487			goto free_pool;
1488		}
1489	}
1490
1491	if (eth1_node) {
1492		ret = icssm_prueth_netdev_init(prueth, eth1_node);
1493		if (ret) {
1494			if (ret != -EPROBE_DEFER) {
1495				dev_err(dev, "netdev init %s failed: %d\n",
1496					eth1_node->name, ret);
1497			}
1498			goto netdev_exit;
1499		}
1500	}
1501
1502	prueth->iep = icss_iep_get(np);
1503	if (IS_ERR(prueth->iep)) {
1504		ret = PTR_ERR(prueth->iep);
1505		dev_err(dev, "unable to get IEP\n");
1506		goto netdev_exit;
1507	}
1508
1509	/* register the network devices */
1510	if (eth0_node) {
1511		ret = register_netdev(prueth->emac[PRUETH_MAC0]->ndev);
1512		if (ret) {
1513			dev_err(dev, "can't register netdev for port MII0");
1514			goto iep_put;
1515		}
1516
1517		prueth->registered_netdevs[PRUETH_MAC0] =
1518			prueth->emac[PRUETH_MAC0]->ndev;
1519	}
1520
1521	if (eth1_node) {
1522		ret = register_netdev(prueth->emac[PRUETH_MAC1]->ndev);
1523		if (ret) {
1524			dev_err(dev, "can't register netdev for port MII1");
1525			goto netdev_unregister;
1526		}
1527
1528		prueth->registered_netdevs[PRUETH_MAC1] =
1529			prueth->emac[PRUETH_MAC1]->ndev;
1530	}
1531
1532	dev_info(dev, "TI PRU ethernet driver initialized: %s EMAC mode\n",
1533		 (!eth0_node || !eth1_node) ? "single" : "dual");
1534
1535	if (eth1_node)
1536		of_node_put(eth1_node);
1537	if (eth0_node)
1538		of_node_put(eth0_node);
1539	return 0;
1540
1541netdev_unregister:
1542	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1543		if (!prueth->registered_netdevs[i])
1544			continue;
1545		unregister_netdev(prueth->registered_netdevs[i]);
1546	}
1547
1548iep_put:
1549	icss_iep_put(prueth->iep);
1550	prueth->iep = NULL;
1551
1552netdev_exit:
1553	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1554		eth_node = prueth->eth_node[i];
1555		if (!eth_node)
1556			continue;
1557
1558		icssm_prueth_netdev_exit(prueth, eth_node);
1559	}
1560
1561free_pool:
1562	gen_pool_free(prueth->sram_pool,
1563		      (unsigned long)prueth->mem[PRUETH_MEM_OCMC].va,
1564		      prueth->ocmc_ram_size);
1565
1566put_mem:
1567	for (i = PRUETH_MEM_DRAM0; i < PRUETH_MEM_OCMC; i++) {
1568		if (prueth->mem[i].va)
1569			pruss_release_mem_region(pruss, &prueth->mem[i]);
1570	}
1571	pruss_put(prueth->pruss);
1572
1573put_pru1:
1574	if (eth1_node)
1575		pru_rproc_put(prueth->pru1);
1576put_pru0:
1577	if (eth0_node)
1578		pru_rproc_put(prueth->pru0);
1579put_eth:
1580	of_node_put(eth1_node);
1581	of_node_put(eth0_node);
1582
1583	return ret;
1584}
1585
1586static void icssm_prueth_remove(struct platform_device *pdev)
1587{
1588	struct prueth *prueth = platform_get_drvdata(pdev);
1589	struct device_node *eth_node;
1590	int i;
1591
1592	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1593		if (!prueth->registered_netdevs[i])
1594			continue;
1595		unregister_netdev(prueth->registered_netdevs[i]);
1596	}
1597
1598	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1599		eth_node = prueth->eth_node[i];
1600		if (!eth_node)
1601			continue;
1602
1603		icssm_prueth_netdev_exit(prueth, eth_node);
1604		of_node_put(eth_node);
1605	}
1606
1607	gen_pool_free(prueth->sram_pool,
1608		      (unsigned long)prueth->mem[PRUETH_MEM_OCMC].va,
1609		      prueth->ocmc_ram_size);
1610
1611	for (i = PRUETH_MEM_DRAM0; i < PRUETH_MEM_OCMC; i++) {
1612		if (prueth->mem[i].va)
1613			pruss_release_mem_region(prueth->pruss,
1614						 &prueth->mem[i]);
1615	}
1616
1617	icss_iep_put(prueth->iep);
1618	prueth->iep = NULL;
1619
1620	pruss_put(prueth->pruss);
1621
1622	if (prueth->eth_node[PRUETH_MAC0])
1623		pru_rproc_put(prueth->pru0);
1624	if (prueth->eth_node[PRUETH_MAC1])
1625		pru_rproc_put(prueth->pru1);
1626}
1627
1628#ifdef CONFIG_PM_SLEEP
1629static int icssm_prueth_suspend(struct device *dev)
1630{
1631	struct prueth *prueth = dev_get_drvdata(dev);
1632	struct net_device *ndev;
1633	int i, ret;
1634
1635	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1636		ndev = prueth->registered_netdevs[i];
1637
1638		if (!ndev)
1639			continue;
1640
1641		if (netif_running(ndev)) {
1642			netif_device_detach(ndev);
1643			ret = icssm_emac_ndo_stop(ndev);
1644			if (ret < 0) {
1645				netdev_err(ndev, "failed to stop: %d", ret);
1646				return ret;
1647			}
1648		}
1649	}
1650
1651	return 0;
1652}
1653
1654static int icssm_prueth_resume(struct device *dev)
1655{
1656	struct prueth *prueth = dev_get_drvdata(dev);
1657	struct net_device *ndev;
1658	int i, ret;
1659
1660	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1661		ndev = prueth->registered_netdevs[i];
1662
1663		if (!ndev)
1664			continue;
1665
1666		if (netif_running(ndev)) {
1667			ret = icssm_emac_ndo_open(ndev);
1668			if (ret < 0) {
1669				netdev_err(ndev, "failed to start: %d", ret);
1670				return ret;
1671			}
1672			netif_device_attach(ndev);
1673		}
1674	}
1675
1676	return 0;
1677}
1678
1679#endif /* CONFIG_PM_SLEEP */
1680
1681static const struct dev_pm_ops prueth_dev_pm_ops = {
1682	SET_SYSTEM_SLEEP_PM_OPS(icssm_prueth_suspend, icssm_prueth_resume)
1683};
1684
1685/* AM335x SoC-specific firmware data */
1686static struct prueth_private_data am335x_prueth_pdata = {
1687	.driver_data = PRUSS_AM33XX,
1688	.fw_pru[PRUSS_PRU0] = {
1689		.fw_name[PRUSS_ETHTYPE_EMAC] =
1690			"ti-pruss/am335x-pru0-prueth-fw.elf",
1691	},
1692	.fw_pru[PRUSS_PRU1] = {
1693		.fw_name[PRUSS_ETHTYPE_EMAC] =
1694			"ti-pruss/am335x-pru1-prueth-fw.elf",
1695	},
1696};
1697
1698/* AM437x SoC-specific firmware data */
1699static struct prueth_private_data am437x_prueth_pdata = {
1700	.driver_data = PRUSS_AM43XX,
1701	.fw_pru[PRUSS_PRU0] = {
1702		.fw_name[PRUSS_ETHTYPE_EMAC] =
1703			"ti-pruss/am437x-pru0-prueth-fw.elf",
1704	},
1705	.fw_pru[PRUSS_PRU1] = {
1706		.fw_name[PRUSS_ETHTYPE_EMAC] =
1707			"ti-pruss/am437x-pru1-prueth-fw.elf",
1708	},
1709};
1710
1711/* AM57xx SoC-specific firmware data */
1712static struct prueth_private_data am57xx_prueth_pdata = {
1713	.driver_data = PRUSS_AM57XX,
1714	.fw_pru[PRUSS_PRU0] = {
1715		.fw_name[PRUSS_ETHTYPE_EMAC] =
1716			"ti-pruss/am57xx-pru0-prueth-fw.elf",
1717	},
1718	.fw_pru[PRUSS_PRU1] = {
1719		.fw_name[PRUSS_ETHTYPE_EMAC] =
1720			"ti-pruss/am57xx-pru1-prueth-fw.elf",
1721	},
1722};
1723
1724static const struct of_device_id prueth_dt_match[] = {
1725	{ .compatible = "ti,am57-prueth", .data = &am57xx_prueth_pdata, },
1726	{ .compatible = "ti,am4376-prueth", .data = &am437x_prueth_pdata, },
1727	{ .compatible = "ti,am3359-prueth", .data = &am335x_prueth_pdata, },
1728	{ /* sentinel */ }
1729};
1730MODULE_DEVICE_TABLE(of, prueth_dt_match);
1731
1732static struct platform_driver prueth_driver = {
1733	.probe = icssm_prueth_probe,
1734	.remove = icssm_prueth_remove,
1735	.driver = {
1736		.name = "prueth",
1737		.of_match_table = prueth_dt_match,
1738		.pm = &prueth_dev_pm_ops,
1739	},
1740};
1741module_platform_driver(prueth_driver);
1742
1743MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
1744MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
1745MODULE_DESCRIPTION("PRUSS ICSSM Ethernet Driver");
1746MODULE_LICENSE("GPL");