icssg_mii_cfg.c

  1// SPDX-License-Identifier: GPL-2.0
  2/* Texas Instruments ICSSG Ethernet Driver
  3 *
  4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
  5 *
  6 */
  7
  8#include <linux/etherdevice.h>
  9#include <linux/regmap.h>
 10#include <linux/types.h>
 11
 12#include "icssg_mii_rt.h"
 13#include "icssg_prueth.h"
 14
 15void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg)
 16{
 17	u32 val;
 18
 19	if (mii == ICSS_MII0) {
 20		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, ipg);
 21	} else {
 22		regmap_read(mii_rt, PRUSS_MII_RT_TX_IPG0, &val);
 23		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG1, ipg);
 24		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, val);
 25	}
 26}
 27
 28void icssg_mii_update_mtu(struct regmap *mii_rt, int mii, int mtu)
 29{
 30	mtu += (ETH_HLEN + ETH_FCS_LEN);
 31	if (mii == ICSS_MII0) {
 32		regmap_update_bits(mii_rt,
 33				   PRUSS_MII_RT_RX_FRMS0,
 34				   PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK,
 35				   (mtu - 1) << PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT);
 36	} else {
 37		regmap_update_bits(mii_rt,
 38				   PRUSS_MII_RT_RX_FRMS1,
 39				   PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK,
 40				   (mtu - 1) << PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT);
 41	}
 42}
 43EXPORT_SYMBOL_GPL(icssg_mii_update_mtu);
 44
 45void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac)
 46{
 47	u32 gig_en_mask, gig_val = 0, full_duplex_mask, full_duplex_val = 0;
 48	int slice = prueth_emac_slice(emac);
 49	u32 inband_en_mask, inband_val = 0;
 50
 51	gig_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 :
 52					RGMII_CFG_GIG_EN_MII1;
 53	if (emac->speed == SPEED_1000)
 54		gig_val = gig_en_mask;
 55	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val);
 56
 57	inband_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 :
 58					RGMII_CFG_INBAND_EN_MII1;
 59	if (emac->speed == SPEED_10 && phy_interface_mode_is_rgmii(emac->phy_if))
 60		inband_val = inband_en_mask;
 61	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val);
 62
 63	full_duplex_mask = (slice == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 :
 64					   RGMII_CFG_FULL_DUPLEX_MII1;
 65	if (emac->duplex == DUPLEX_FULL)
 66		full_duplex_val = full_duplex_mask;
 67	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask,
 68			   full_duplex_val);
 69}
 70EXPORT_SYMBOL_GPL(icssg_update_rgmii_cfg);
 71
 72void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if)
 73{
 74	u32 val, mask, shift;
 75
 76	mask = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE : ICSSG_CFG_MII1_MODE;
 77	shift =  mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE_SHIFT : ICSSG_CFG_MII1_MODE_SHIFT;
 78
 79	val = MII_MODE_RGMII;
 80	if (phy_if == PHY_INTERFACE_MODE_MII)
 81		val = MII_MODE_MII;
 82
 83	val <<= shift;
 84	regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val);
 85	regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val);
 86}
 87
 88u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift)
 89{
 90	u32 val;
 91
 92	regmap_read(miig_rt, RGMII_CFG_OFFSET, &val);
 93	val &= mask;
 94	val >>= shift;
 95
 96	return val;
 97}
 98
 99u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii)
100{
101	u32 shift = RGMII_CFG_SPEED_MII0_SHIFT, mask = RGMII_CFG_SPEED_MII0;
102
103	if (mii == ICSS_MII1) {
104		shift = RGMII_CFG_SPEED_MII1_SHIFT;
105		mask = RGMII_CFG_SPEED_MII1;
106	}
107
108	return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift);
109}
110EXPORT_SYMBOL_GPL(icssg_rgmii_get_speed);
111
112u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii)
113{
114	u32 shift = RGMII_CFG_FULLDUPLEX_MII0_SHIFT;
115	u32 mask = RGMII_CFG_FULLDUPLEX_MII0;
116
117	if (mii == ICSS_MII1) {
118		shift = RGMII_CFG_FULLDUPLEX_MII1_SHIFT;
119		mask = RGMII_CFG_FULLDUPLEX_MII1;
120	}
121
122	return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift);
123}
124EXPORT_SYMBOL_GPL(icssg_rgmii_get_fullduplex);