stmmac_pcs.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * stmmac_pcs.h: Physical Coding Sublayer Header File
  4 *
  5 * Copyright (C) 2016 STMicroelectronics (R&D) Limited
  6 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  7 */
  8
  9#ifndef __STMMAC_PCS_H__
 10#define __STMMAC_PCS_H__
 11
 12#include <linux/phylink.h>
 13#include <linux/slab.h>
 14#include <linux/io.h>
 15#include "common.h"
 16
 17/* PCS registers (AN/TBI/SGMII/RGMII) offsets */
 18#define GMAC_AN_CTRL(x)		(x)		/* AN control */
 19#define GMAC_AN_STATUS(x)	(x + 0x4)	/* AN status */
 20
 21/* ADV, LPA and EXP are only available for the TBI and RTBI interfaces */
 22#define GMAC_ANE_ADV(x)		(x + 0x8)	/* ANE Advertisement */
 23#define GMAC_ANE_LPA(x)		(x + 0xc)	/* ANE link partener ability */
 24#define GMAC_ANE_EXP(x)		(x + 0x10)	/* ANE expansion */
 25#define GMAC_TBI(x)		(x + 0x14)	/* TBI extend status */
 26
 27/* AN Configuration defines */
 28#define GMAC_AN_CTRL_RAN	BIT(9)	/* Restart Auto-Negotiation */
 29#define GMAC_AN_CTRL_ANE	BIT(12)	/* Auto-Negotiation Enable */
 30#define GMAC_AN_CTRL_ELE	BIT(14)	/* External Loopback Enable */
 31#define GMAC_AN_CTRL_ECD	BIT(16)	/* Enable Comma Detect */
 32#define GMAC_AN_CTRL_LR		BIT(17)	/* Lock to Reference */
 33#define GMAC_AN_CTRL_SGMRAL	BIT(18)	/* SGMII RAL Control */
 34
 35/* AN Status defines */
 36#define GMAC_AN_STATUS_LS	BIT(2)	/* Link Status 0:down 1:up */
 37#define GMAC_AN_STATUS_ANA	BIT(3)	/* Auto-Negotiation Ability */
 38#define GMAC_AN_STATUS_ANC	BIT(5)	/* Auto-Negotiation Complete */
 39#define GMAC_AN_STATUS_ES	BIT(8)	/* Extended Status */
 40
 41/* ADV and LPA defines */
 42#define GMAC_ANE_FD		BIT(5)
 43#define GMAC_ANE_HD		BIT(6)
 44#define GMAC_ANE_PSE		GENMASK(8, 7)
 45#define GMAC_ANE_PSE_SHIFT	7
 46#define GMAC_ANE_RFE		GENMASK(13, 12)
 47#define GMAC_ANE_RFE_SHIFT	12
 48#define GMAC_ANE_ACK		BIT(14)
 49
 50struct stmmac_priv;
 51
 52struct stmmac_pcs {
 53	struct stmmac_priv *priv;
 54	void __iomem *base;
 55	u32 int_mask;
 56	struct phylink_pcs pcs;
 57};
 58
 59static inline struct stmmac_pcs *
 60phylink_pcs_to_stmmac_pcs(struct phylink_pcs *pcs)
 61{
 62	return container_of(pcs, struct stmmac_pcs, pcs);
 63}
 64
 65int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
 66			       u32 int_mask);
 67
 68/**
 69 * dwmac_pcs_isr - TBI, RTBI, or SGMII PHY ISR
 70 * @ioaddr: IO registers pointer
 71 * @reg: Base address of the AN Control Register.
 72 * @intr_status: GMAC core interrupt status
 73 * @x: pointer to log these events as stats
 74 * Description: it is the ISR for PCS events: Auto-Negotiation Completed and
 75 * Link status.
 76 */
 77static inline void dwmac_pcs_isr(void __iomem *ioaddr, u32 reg,
 78				 unsigned int intr_status,
 79				 struct stmmac_extra_stats *x)
 80{
 81	u32 val = readl(ioaddr + GMAC_AN_STATUS(reg));
 82
 83	if (intr_status & PCS_ANE_IRQ) {
 84		x->irq_pcs_ane_n++;
 85		if (val & GMAC_AN_STATUS_ANC)
 86			pr_info("stmmac_pcs: ANE process completed\n");
 87	}
 88
 89	if (intr_status & PCS_LINK_IRQ) {
 90		x->irq_pcs_link_n++;
 91		if (val & GMAC_AN_STATUS_LS)
 92			pr_info("stmmac_pcs: Link Up\n");
 93		else
 94			pr_info("stmmac_pcs: Link Down\n");
 95	}
 96}
 97
 98/**
 99 * dwmac_ctrl_ane - To program the AN Control Register.
100 * @ioaddr: IO registers pointer
101 * @reg: Base address of the AN Control Register.
102 * @ane: to enable the auto-negotiation
103 * @srgmi_ral: to manage MAC-2-MAC SGMII connections.
104 * Description: this is the main function to configure the AN control register
105 * and init the ANE, select loopback (usually for debugging purpose) and
106 * configure SGMII RAL.
107 */
108static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,
109				  bool srgmi_ral)
110{
111	u32 value = readl(ioaddr + GMAC_AN_CTRL(reg));
112
113	/* Enable and restart the Auto-Negotiation */
114	if (ane)
115		value |= GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_RAN;
116	else
117		value &= ~GMAC_AN_CTRL_ANE;
118
119	/* In case of MAC-2-MAC connection, block is configured to operate
120	 * according to MAC conf register.
121	 */
122	if (srgmi_ral)
123		value |= GMAC_AN_CTRL_SGMRAL;
124
125	writel(value, ioaddr + GMAC_AN_CTRL(reg));
126}
127#endif /* __STMMAC_PCS_H__ */