stmmac_mdio.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*******************************************************************************
  3  STMMAC Ethernet Driver -- MDIO bus implementation
  4  Provides Bus interface for MII registers
  5
  6  Copyright (C) 2007-2009  STMicroelectronics Ltd
  7
  8
  9  Author: Carl Shaw <carl.shaw@st.com>
 10  Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 11*******************************************************************************/
 12
 13#include <linux/gpio/consumer.h>
 14#include <linux/io.h>
 15#include <linux/iopoll.h>
 16#include <linux/mii.h>
 17#include <linux/of_mdio.h>
 18#include <linux/pm_runtime.h>
 19#include <linux/phy.h>
 20#include <linux/property.h>
 21#include <linux/slab.h>
 22
 23#include "dwxgmac2.h"
 24#include "stmmac.h"
 25
 26#define MII_ADDR_GBUSY			BIT(0)
 27#define MII_ADDR_GWRITE			BIT(1)
 28#define MII_DATA_GD_MASK		GENMASK(15, 0)
 29
 30/* GMAC4 defines */
 31#define MII_GMAC4_GOC_SHIFT		2
 32#define MII_GMAC4_REG_ADDR_SHIFT	16
 33#define MII_GMAC4_WRITE			(1 << MII_GMAC4_GOC_SHIFT)
 34#define MII_GMAC4_READ			(3 << MII_GMAC4_GOC_SHIFT)
 35#define MII_GMAC4_C45E			BIT(1)
 36
 37/* XGMAC defines */
 38#define MII_XGMAC_SADDR			BIT(18)
 39#define MII_XGMAC_CMD_SHIFT		16
 40#define MII_XGMAC_WRITE			(1 << MII_XGMAC_CMD_SHIFT)
 41#define MII_XGMAC_READ			(3 << MII_XGMAC_CMD_SHIFT)
 42#define MII_XGMAC_BUSY			BIT(22)
 43#define MII_XGMAC_MAX_C22ADDR		3
 44#define MII_XGMAC_C22P_MASK		GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
 45#define MII_XGMAC_PA_SHIFT		16
 46#define MII_XGMAC_DA_SHIFT		21
 47
 48static int stmmac_mdio_wait(void __iomem *reg, u32 mask)
 49{
 50	u32 v;
 51
 52	if (readl_poll_timeout(reg, v, !(v & mask), 100, 10000))
 53		return -EBUSY;
 54
 55	return 0;
 56}
 57
 58static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
 59				     int devad, int phyreg, u32 *hw_addr)
 60{
 61	u32 tmp;
 62
 63	/* Set port as Clause 45 */
 64	tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
 65	tmp &= ~BIT(phyaddr);
 66	writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
 67
 68	*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff);
 69	*hw_addr |= devad << MII_XGMAC_DA_SHIFT;
 70}
 71
 72static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
 73				     int phyreg, u32 *hw_addr)
 74{
 75	u32 tmp = 0;
 76
 77	if (priv->synopsys_id < DWXGMAC_CORE_2_20) {
 78		/* Until ver 2.20 XGMAC does not support C22 addr >= 4. Those
 79		 * bits above bit 3 of XGMAC_MDIO_C22P register are reserved.
 80		 */
 81		tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
 82		tmp &= ~MII_XGMAC_C22P_MASK;
 83	}
 84	/* Set port as Clause 22 */
 85	tmp |= BIT(phyaddr);
 86	writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
 87
 88	*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f);
 89}
 90
 91static int stmmac_xgmac2_mdio_read(struct stmmac_priv *priv, u32 addr,
 92				   u32 value)
 93{
 94	unsigned int mii_address = priv->hw->mii.addr;
 95	unsigned int mii_data = priv->hw->mii.data;
 96	int ret;
 97
 98	ret = pm_runtime_resume_and_get(priv->device);
 99	if (ret < 0)
100		return ret;
101
102	/* Wait until any existing MII operation is complete */
103	ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
104	if (ret)
105		goto err_disable_clks;
106
107	value |= priv->gmii_address_bus_config | MII_XGMAC_READ;
108
109	/* Wait until any existing MII operation is complete */
110	ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
111	if (ret)
112		goto err_disable_clks;
113
114	/* Set the MII address register to read */
115	writel(addr, priv->ioaddr + mii_address);
116	writel(value, priv->ioaddr + mii_data);
117
118	/* Wait until any existing MII operation is complete */
119	ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
120	if (ret)
121		goto err_disable_clks;
122
123	/* Read the data from the MII data register */
124	ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
125
126err_disable_clks:
127	pm_runtime_put(priv->device);
128
129	return ret;
130}
131
132static int stmmac_xgmac2_mdio_read_c22(struct mii_bus *bus, int phyaddr,
133				       int phyreg)
134{
135	struct stmmac_priv *priv = netdev_priv(bus->priv);
136	u32 addr;
137
138	/* Until ver 2.20 XGMAC does not support C22 addr >= 4 */
139	if (priv->synopsys_id < DWXGMAC_CORE_2_20 &&
140	    phyaddr > MII_XGMAC_MAX_C22ADDR)
141		return -ENODEV;
142
143	stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
144
145	return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
146}
147
148static int stmmac_xgmac2_mdio_read_c45(struct mii_bus *bus, int phyaddr,
149				       int devad, int phyreg)
150{
151	struct stmmac_priv *priv = netdev_priv(bus->priv);
152	u32 addr;
153
154	stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
155
156	return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
157}
158
159static int stmmac_xgmac2_mdio_write(struct stmmac_priv *priv, u32 addr,
160				    u32 value, u16 phydata)
161{
162	unsigned int mii_address = priv->hw->mii.addr;
163	unsigned int mii_data = priv->hw->mii.data;
164	int ret;
165
166	ret = pm_runtime_resume_and_get(priv->device);
167	if (ret < 0)
168		return ret;
169
170	/* Wait until any existing MII operation is complete */
171	ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
172	if (ret)
173		goto err_disable_clks;
174
175	value |= priv->gmii_address_bus_config | phydata | MII_XGMAC_WRITE;
176
177	/* Wait until any existing MII operation is complete */
178	ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
179	if (ret)
180		goto err_disable_clks;
181
182	/* Set the MII address register to write */
183	writel(addr, priv->ioaddr + mii_address);
184	writel(value, priv->ioaddr + mii_data);
185
186	/* Wait until any existing MII operation is complete */
187	ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
188
189err_disable_clks:
190	pm_runtime_put(priv->device);
191
192	return ret;
193}
194
195static int stmmac_xgmac2_mdio_write_c22(struct mii_bus *bus, int phyaddr,
196					int phyreg, u16 phydata)
197{
198	struct stmmac_priv *priv = netdev_priv(bus->priv);
199	u32 addr;
200
201	/* Until ver 2.20 XGMAC does not support C22 addr >= 4 */
202	if (priv->synopsys_id < DWXGMAC_CORE_2_20 &&
203	    phyaddr > MII_XGMAC_MAX_C22ADDR)
204		return -ENODEV;
205
206	stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
207
208	return stmmac_xgmac2_mdio_write(priv, addr,
209					MII_XGMAC_BUSY | MII_XGMAC_SADDR, phydata);
210}
211
212static int stmmac_xgmac2_mdio_write_c45(struct mii_bus *bus, int phyaddr,
213					int devad, int phyreg, u16 phydata)
214{
215	struct stmmac_priv *priv = netdev_priv(bus->priv);
216	u32 addr;
217
218	stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
219
220	return stmmac_xgmac2_mdio_write(priv, addr, MII_XGMAC_BUSY,
221					phydata);
222}
223
224/**
225 * stmmac_mdio_format_addr() - format the address register
226 * @priv: struct stmmac_priv pointer
227 * @pa: 5-bit MDIO package address
228 * @gr: 5-bit MDIO register address (C22) or MDIO device address (C45)
229 *
230 * Return: formatted address register
231 */
232static u32 stmmac_mdio_format_addr(struct stmmac_priv *priv,
233				   unsigned int pa, unsigned int gr)
234{
235	const struct mii_regs *mii_regs = &priv->hw->mii;
236
237	return ((pa << mii_regs->addr_shift) & mii_regs->addr_mask) |
238	       ((gr << mii_regs->reg_shift) & mii_regs->reg_mask) |
239	       priv->gmii_address_bus_config |
240	       MII_ADDR_GBUSY;
241}
242
243static int stmmac_mdio_access(struct stmmac_priv *priv, unsigned int pa,
244			      unsigned int gr, u32 cmd, u32 data, bool read)
245{
246	void __iomem *mii_address = priv->ioaddr + priv->hw->mii.addr;
247	void __iomem *mii_data = priv->ioaddr + priv->hw->mii.data;
248	u32 addr;
249	int ret;
250
251	ret = pm_runtime_resume_and_get(priv->device);
252	if (ret < 0)
253		return ret;
254
255	ret = stmmac_mdio_wait(mii_address, MII_ADDR_GBUSY);
256	if (ret)
257		goto out;
258
259	addr = stmmac_mdio_format_addr(priv, pa, gr) | cmd;
260
261	writel(data, mii_data);
262	writel(addr, mii_address);
263
264	ret = stmmac_mdio_wait(mii_address, MII_ADDR_GBUSY);
265	if (ret)
266		goto out;
267
268	/* Read the data from the MII data register if in read mode */
269	ret = read ? readl(mii_data) & MII_DATA_GD_MASK : 0;
270
271out:
272	pm_runtime_put(priv->device);
273
274	return ret;
275}
276
277static int stmmac_mdio_read(struct stmmac_priv *priv, unsigned int pa,
278			    unsigned int gr, u32 cmd, int data)
279{
280	return stmmac_mdio_access(priv, pa, gr, cmd, data, true);
281}
282
283static int stmmac_mdio_write(struct stmmac_priv *priv, unsigned int pa,
284			     unsigned int gr, u32 cmd, int data)
285{
286	return stmmac_mdio_access(priv, pa, gr, cmd, data, false);
287}
288
289/**
290 * stmmac_mdio_read_c22
291 * @bus: points to the mii_bus structure
292 * @phyaddr: MII addr
293 * @phyreg: MII reg
294 * Description: it reads data from the MII register from within the phy device.
295 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
296 * accessing the PHY registers.
297 * Fortunately, it seems this has no drawback for the 7109 MAC.
298 */
299static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg)
300{
301	struct stmmac_priv *priv = netdev_priv(bus->priv);
302	u32 cmd;
303
304	if (priv->plat->core_type == DWMAC_CORE_GMAC4)
305		cmd = MII_GMAC4_READ;
306	else
307		cmd = 0;
308
309	return stmmac_mdio_read(priv, phyaddr, phyreg, cmd, 0);
310}
311
312/**
313 * stmmac_mdio_read_c45
314 * @bus: points to the mii_bus structure
315 * @phyaddr: MII addr
316 * @devad: device address to read
317 * @phyreg: MII reg
318 * Description: it reads data from the MII register from within the phy device.
319 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
320 * accessing the PHY registers.
321 * Fortunately, it seems this has no drawback for the 7109 MAC.
322 */
323static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad,
324				int phyreg)
325{
326	struct stmmac_priv *priv = netdev_priv(bus->priv);
327	int data = phyreg << MII_GMAC4_REG_ADDR_SHIFT;
328	u32 cmd = MII_GMAC4_READ | MII_GMAC4_C45E;
329
330	return stmmac_mdio_read(priv, phyaddr, devad, cmd, data);
331}
332
333/**
334 * stmmac_mdio_write_c22
335 * @bus: points to the mii_bus structure
336 * @phyaddr: MII addr
337 * @phyreg: MII reg
338 * @phydata: phy data
339 * Description: it writes the data into the MII register from within the device.
340 */
341static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg,
342				 u16 phydata)
343{
344	struct stmmac_priv *priv = netdev_priv(bus->priv);
345	u32 cmd;
346
347	if (priv->plat->core_type == DWMAC_CORE_GMAC4)
348		cmd = MII_GMAC4_WRITE;
349	else
350		cmd = MII_ADDR_GWRITE;
351
352	return stmmac_mdio_write(priv, phyaddr, phyreg, cmd, phydata);
353}
354
355/**
356 * stmmac_mdio_write_c45
357 * @bus: points to the mii_bus structure
358 * @phyaddr: MII addr
359 * @phyreg: MII reg
360 * @devad: device address to read
361 * @phydata: phy data
362 * Description: it writes the data into the MII register from within the device.
363 */
364static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr,
365				 int devad, int phyreg, u16 phydata)
366{
367	struct stmmac_priv *priv = netdev_priv(bus->priv);
368	u32 cmd = MII_GMAC4_WRITE | MII_GMAC4_C45E;
369	int data = phydata;
370
371	data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
372
373	return stmmac_mdio_write(priv, phyaddr, devad, cmd, data);
374}
375
376/**
377 * stmmac_mdio_reset
378 * @bus: points to the mii_bus structure
379 * Description: reset the MII bus
380 */
381int stmmac_mdio_reset(struct mii_bus *bus)
382{
383#if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
384	struct stmmac_priv *priv = netdev_priv(bus->priv);
385	unsigned int mii_address = priv->hw->mii.addr;
386
387#ifdef CONFIG_OF
388	if (priv->device->of_node) {
389		struct gpio_desc *reset_gpio;
390		u32 delays[3] = { 0, 0, 0 };
391
392		reset_gpio = devm_gpiod_get_optional(priv->device,
393						     "snps,reset",
394						     GPIOD_OUT_LOW);
395		if (IS_ERR(reset_gpio))
396			return PTR_ERR(reset_gpio);
397
398		device_property_read_u32_array(priv->device,
399					       "snps,reset-delays-us",
400					       delays, ARRAY_SIZE(delays));
401
402		if (delays[0])
403			msleep(DIV_ROUND_UP(delays[0], 1000));
404
405		gpiod_set_value_cansleep(reset_gpio, 1);
406		if (delays[1])
407			msleep(DIV_ROUND_UP(delays[1], 1000));
408
409		gpiod_set_value_cansleep(reset_gpio, 0);
410		if (delays[2])
411			msleep(DIV_ROUND_UP(delays[2], 1000));
412	}
413#endif
414
415	/* This is a workaround for problems with the STE101P PHY.
416	 * It doesn't complete its reset until at least one clock cycle
417	 * on MDC, so perform a dummy mdio read. To be updated for GMAC4
418	 * if needed.
419	 */
420	if (priv->plat->core_type != DWMAC_CORE_GMAC4)
421		writel(0, priv->ioaddr + mii_address);
422#endif
423	return 0;
424}
425
426int stmmac_pcs_setup(struct net_device *ndev)
427{
428	struct stmmac_priv *priv = netdev_priv(ndev);
429	struct fwnode_handle *devnode, *pcsnode;
430	struct dw_xpcs *xpcs = NULL;
431	int addr, ret;
432
433	devnode = priv->plat->port_node;
434
435	if (priv->plat->pcs_init) {
436		ret = priv->plat->pcs_init(priv);
437	} else if (fwnode_property_present(devnode, "pcs-handle")) {
438		pcsnode = fwnode_find_reference(devnode, "pcs-handle", 0);
439		xpcs = xpcs_create_fwnode(pcsnode);
440		fwnode_handle_put(pcsnode);
441		ret = PTR_ERR_OR_ZERO(xpcs);
442	} else if (priv->plat->mdio_bus_data &&
443		   priv->plat->mdio_bus_data->pcs_mask) {
444		addr = ffs(priv->plat->mdio_bus_data->pcs_mask) - 1;
445		xpcs = xpcs_create_mdiodev(priv->mii, addr);
446		ret = PTR_ERR_OR_ZERO(xpcs);
447	} else {
448		return 0;
449	}
450
451	if (ret)
452		return dev_err_probe(priv->device, ret, "No xPCS found\n");
453
454	if (xpcs)
455		xpcs_config_eee_mult_fact(xpcs, priv->plat->mult_fact_100ns);
456
457	priv->hw->xpcs = xpcs;
458
459	return 0;
460}
461
462void stmmac_pcs_clean(struct net_device *ndev)
463{
464	struct stmmac_priv *priv = netdev_priv(ndev);
465
466	if (priv->plat->pcs_exit)
467		priv->plat->pcs_exit(priv);
468
469	if (!priv->hw->xpcs)
470		return;
471
472	xpcs_destroy(priv->hw->xpcs);
473	priv->hw->xpcs = NULL;
474}
475
476/**
477 * stmmac_clk_csr_set - dynamically set the MDC clock
478 * @priv: driver private structure
479 * Description: this is to dynamically set the MDC clock according to the csr
480 * clock input.
481 * Return: MII register CR field value
482 * Note:
483 *	If a specific clk_csr value is passed from the platform
484 *	this means that the CSR Clock Range selection cannot be
485 *	changed at run-time and it is fixed (as reported in the driver
486 *	documentation). Viceversa the driver will try to set the MDC
487 *	clock dynamically according to the actual clock input.
488 */
489static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)
490{
491	unsigned long clk_rate;
492	u32 value = ~0;
493
494	clk_rate = clk_get_rate(priv->plat->stmmac_clk);
495
496	/* Platform provided default clk_csr would be assumed valid
497	 * for all other cases except for the below mentioned ones.
498	 * For values higher than the IEEE 802.3 specified frequency
499	 * we can not estimate the proper divider as it is not known
500	 * the frequency of clk_csr_i. So we do not change the default
501	 * divider.
502	 */
503	if (clk_rate < CSR_F_35M)
504		value = STMMAC_CSR_20_35M;
505	else if (clk_rate < CSR_F_60M)
506		value = STMMAC_CSR_35_60M;
507	else if (clk_rate < CSR_F_100M)
508		value = STMMAC_CSR_60_100M;
509	else if (clk_rate < CSR_F_150M)
510		value = STMMAC_CSR_100_150M;
511	else if (clk_rate < CSR_F_250M)
512		value = STMMAC_CSR_150_250M;
513	else if (clk_rate <= CSR_F_300M)
514		value = STMMAC_CSR_250_300M;
515	else if (clk_rate < CSR_F_500M)
516		value = STMMAC_CSR_300_500M;
517	else if (clk_rate < CSR_F_800M)
518		value = STMMAC_CSR_500_800M;
519
520	if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
521		if (clk_rate > 160000000)
522			value = 0x03;
523		else if (clk_rate > 80000000)
524			value = 0x02;
525		else if (clk_rate > 40000000)
526			value = 0x01;
527		else
528			value = 0;
529	}
530
531	if (priv->plat->core_type == DWMAC_CORE_XGMAC) {
532		if (clk_rate > 400000000)
533			value = 0x5;
534		else if (clk_rate > 350000000)
535			value = 0x4;
536		else if (clk_rate > 300000000)
537			value = 0x3;
538		else if (clk_rate > 250000000)
539			value = 0x2;
540		else if (clk_rate > 150000000)
541			value = 0x1;
542		else
543			value = 0x0;
544	}
545
546	return value;
547}
548
549static void stmmac_mdio_bus_config(struct stmmac_priv *priv)
550{
551	u32 value;
552
553	/* If a specific clk_csr value is passed from the platform, this means
554	 * that the CSR Clock Range value should not be computed from the CSR
555	 * clock.
556	 */
557	if (priv->plat->clk_csr >= 0)
558		value = priv->plat->clk_csr;
559	else
560		value = stmmac_clk_csr_set(priv);
561
562	value <<= priv->hw->mii.clk_csr_shift;
563
564	if (value & ~priv->hw->mii.clk_csr_mask)
565		dev_warn(priv->device,
566			 "clk_csr value out of range (0x%08x exceeds mask 0x%08x), truncating\n",
567			 value, priv->hw->mii.clk_csr_mask);
568
569	priv->gmii_address_bus_config = value & priv->hw->mii.clk_csr_mask;
570}
571
572/**
573 * stmmac_mdio_register
574 * @ndev: net device structure
575 * Description: it registers the MII bus
576 */
577int stmmac_mdio_register(struct net_device *ndev)
578{
579	int err = 0;
580	struct mii_bus *new_bus;
581	struct stmmac_priv *priv = netdev_priv(ndev);
582	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
583	struct device_node *mdio_node = priv->plat->mdio_node;
584	struct device *dev = ndev->dev.parent;
585	struct fwnode_handle *fixed_node;
586	int max_addr = PHY_MAX_ADDR - 1;
587	struct fwnode_handle *fwnode;
588	struct phy_device *phydev;
589
590	if (!mdio_bus_data)
591		return 0;
592
593	stmmac_mdio_bus_config(priv);
594
595	new_bus = mdiobus_alloc();
596	if (!new_bus)
597		return -ENOMEM;
598
599	if (mdio_bus_data->irqs)
600		memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
601
602	new_bus->name = "stmmac";
603
604	if (priv->plat->core_type == DWMAC_CORE_XGMAC) {
605		new_bus->read = &stmmac_xgmac2_mdio_read_c22;
606		new_bus->write = &stmmac_xgmac2_mdio_write_c22;
607		new_bus->read_c45 = &stmmac_xgmac2_mdio_read_c45;
608		new_bus->write_c45 = &stmmac_xgmac2_mdio_write_c45;
609
610		if (priv->synopsys_id < DWXGMAC_CORE_2_20) {
611			/* Right now only C22 phys are supported */
612			max_addr = MII_XGMAC_MAX_C22ADDR;
613
614			/* Check if DT specified an unsupported phy addr */
615			if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
616				dev_err(dev, "Unsupported phy_addr (max=%d)\n",
617					MII_XGMAC_MAX_C22ADDR);
618		}
619	} else {
620		new_bus->read = &stmmac_mdio_read_c22;
621		new_bus->write = &stmmac_mdio_write_c22;
622		if (priv->plat->core_type == DWMAC_CORE_GMAC4) {
623			new_bus->read_c45 = &stmmac_mdio_read_c45;
624			new_bus->write_c45 = &stmmac_mdio_write_c45;
625		}
626	}
627
628	if (mdio_bus_data->needs_reset)
629		new_bus->reset = &stmmac_mdio_reset;
630
631	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
632		 new_bus->name, priv->plat->bus_id);
633	new_bus->priv = ndev;
634	new_bus->phy_mask = mdio_bus_data->phy_mask | mdio_bus_data->pcs_mask;
635	new_bus->parent = priv->device;
636
637	err = of_mdiobus_register(new_bus, mdio_node);
638	if (err == -ENODEV) {
639		err = 0;
640		dev_info(dev, "MDIO bus is disabled\n");
641		goto bus_register_fail;
642	} else if (err) {
643		dev_err_probe(dev, err, "Cannot register the MDIO bus\n");
644		goto bus_register_fail;
645	}
646
647	/* Looks like we need a dummy read for XGMAC only and C45 PHYs */
648	if (priv->plat->core_type == DWMAC_CORE_XGMAC)
649		stmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);
650
651	/* If fixed-link is set, skip PHY scanning */
652	fwnode = priv->plat->port_node;
653	if (!fwnode)
654		fwnode = dev_fwnode(priv->device);
655
656	if (fwnode) {
657		fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
658		if (fixed_node) {
659			fwnode_handle_put(fixed_node);
660			goto bus_register_done;
661		}
662	}
663
664	if (priv->plat->phy_node || mdio_node)
665		goto bus_register_done;
666
667	phydev = phy_find_first(new_bus);
668	if (!phydev || phydev->mdio.addr > max_addr) {
669		dev_warn(dev, "No PHY found\n");
670		err = -ENODEV;
671		goto no_phy_found;
672	}
673
674	/*
675	 * If an IRQ was provided to be assigned after
676	 * the bus probe, do it here.
677	 */
678	if (!mdio_bus_data->irqs && mdio_bus_data->probed_phy_irq > 0) {
679		new_bus->irq[phydev->mdio.addr] = mdio_bus_data->probed_phy_irq;
680		phydev->irq = mdio_bus_data->probed_phy_irq;
681	}
682
683	/*
684	 * If we're going to bind the MAC to this PHY bus, and no PHY number
685	 * was provided to the MAC, use the one probed here.
686	 */
687	if (priv->plat->phy_addr == -1)
688		priv->plat->phy_addr = phydev->mdio.addr;
689
690	phy_attached_info(phydev);
691
692bus_register_done:
693	priv->mii = new_bus;
694
695	return 0;
696
697no_phy_found:
698	mdiobus_unregister(new_bus);
699bus_register_fail:
700	mdiobus_free(new_bus);
701	return err;
702}
703
704/**
705 * stmmac_mdio_unregister
706 * @ndev: net device structure
707 * Description: it unregisters the MII bus
708 */
709int stmmac_mdio_unregister(struct net_device *ndev)
710{
711	struct stmmac_priv *priv = netdev_priv(ndev);
712
713	if (!priv->mii)
714		return 0;
715
716	mdiobus_unregister(priv->mii);
717	priv->mii->priv = NULL;
718	mdiobus_free(priv->mii);
719	priv->mii = NULL;
720
721	return 0;
722}
723
724void stmmac_mdio_lock(struct stmmac_priv *priv)
725{
726	if (priv->mii)
727		mutex_lock(&priv->mii->mdio_lock);
728}
729EXPORT_SYMBOL_GPL(stmmac_mdio_lock);
730
731void stmmac_mdio_unlock(struct stmmac_priv *priv)
732{
733	if (priv->mii)
734		mutex_unlock(&priv->mii->mdio_lock);
735}
736EXPORT_SYMBOL_GPL(stmmac_mdio_unlock);