stmmac_hwtstamp.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*******************************************************************************
  3  Copyright (C) 2013  Vayavya Labs Pvt Ltd
  4
  5  This implements all the API for managing HW timestamp & PTP.
  6
  7
  8  Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
  9  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 10*******************************************************************************/
 11
 12#include <linux/io.h>
 13#include <linux/iopoll.h>
 14#include <linux/delay.h>
 15#include <linux/ptp_clock_kernel.h>
 16#include "common.h"
 17#include "stmmac_ptp.h"
 18#include "dwmac4.h"
 19#include "stmmac.h"
 20
 21#define STMMAC_HWTS_CFG_MASK	(PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
 22				 PTP_TCR_TSINIT | PTP_TCR_TSUPDT | \
 23				 PTP_TCR_TSCTRLSSR | PTP_TCR_SNAPTYPSEL_1 | \
 24				 PTP_TCR_TSIPV4ENA | PTP_TCR_TSIPV6ENA | \
 25				 PTP_TCR_TSEVNTENA | PTP_TCR_TSMSTRENA | \
 26				 PTP_TCR_TSVER2ENA | PTP_TCR_TSIPENA | \
 27				 PTP_TCR_TSTRIG | PTP_TCR_TSENALL)
 28
 29static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
 30{
 31	u32 regval = readl(ioaddr + PTP_TCR);
 32
 33	regval &= ~STMMAC_HWTS_CFG_MASK;
 34	regval |= data;
 35
 36	writel(regval, ioaddr + PTP_TCR);
 37}
 38
 39static void config_sub_second_increment(void __iomem *ioaddr,
 40		u32 ptp_clock, int gmac4, u32 *ssinc)
 41{
 42	u32 value = readl(ioaddr + PTP_TCR);
 43	unsigned long data;
 44	u32 reg_value;
 45
 46	/* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
 47	 * increment to twice the number of nanoseconds of a clock cycle.
 48	 * The calculation of the default_addend value by the caller will set it
 49	 * to mid-range = 2^31 when the remainder of this division is zero,
 50	 * which will make the accumulator overflow once every 2 ptp_clock
 51	 * cycles, adding twice the number of nanoseconds of a clock cycle :
 52	 * 2000000000ULL / ptp_clock.
 53	 */
 54	if (value & PTP_TCR_TSCFUPDT)
 55		data = (2000000000ULL / ptp_clock);
 56	else
 57		data = (1000000000ULL / ptp_clock);
 58
 59	/* 0.465ns accuracy */
 60	if (!(value & PTP_TCR_TSCTRLSSR))
 61		data = (data * 1000) / 465;
 62
 63	if (data > PTP_SSIR_SSINC_MAX)
 64		data = PTP_SSIR_SSINC_MAX;
 65
 66	reg_value = data;
 67	if (gmac4)
 68		reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
 69
 70	writel(reg_value, ioaddr + PTP_SSIR);
 71
 72	if (ssinc)
 73		*ssinc = data;
 74}
 75
 76static void hwtstamp_correct_latency(struct stmmac_priv *priv)
 77{
 78	void __iomem *ioaddr = priv->ptpaddr;
 79	u32 reg_tsic, reg_tsicsns;
 80	u32 reg_tsec, reg_tsecsns;
 81	u64 scaled_ns;
 82	u32 val;
 83
 84	/* MAC-internal ingress latency */
 85	scaled_ns = readl(ioaddr + PTP_TS_INGR_LAT);
 86
 87	/* See section 11.7.2.5.3.1 "Ingress Correction" on page 4001 of
 88	 * i.MX8MP Applications Processor Reference Manual Rev. 1, 06/2021
 89	 */
 90	val = readl(ioaddr + PTP_TCR);
 91	if (val & PTP_TCR_TSCTRLSSR)
 92		/* nanoseconds field is in decimal format with granularity of 1ns/bit */
 93		scaled_ns = ((u64)NSEC_PER_SEC << 16) - scaled_ns;
 94	else
 95		/* nanoseconds field is in binary format with granularity of ~0.466ns/bit */
 96		scaled_ns = ((1ULL << 31) << 16) -
 97			DIV_U64_ROUND_CLOSEST(scaled_ns * PSEC_PER_NSEC, 466U);
 98
 99	reg_tsic = scaled_ns >> 16;
100	reg_tsicsns = scaled_ns & 0xff00;
101
102	/* set bit 31 for 2's compliment */
103	reg_tsic |= BIT(31);
104
105	writel(reg_tsic, ioaddr + PTP_TS_INGR_CORR_NS);
106	writel(reg_tsicsns, ioaddr + PTP_TS_INGR_CORR_SNS);
107
108	/* MAC-internal egress latency */
109	scaled_ns = readl(ioaddr + PTP_TS_EGR_LAT);
110
111	reg_tsec = scaled_ns >> 16;
112	reg_tsecsns = scaled_ns & 0xff00;
113
114	writel(reg_tsec, ioaddr + PTP_TS_EGR_CORR_NS);
115	writel(reg_tsecsns, ioaddr + PTP_TS_EGR_CORR_SNS);
116}
117
118static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
119{
120	u32 value;
121
122	writel(sec, ioaddr + PTP_STSUR);
123	writel(nsec, ioaddr + PTP_STNSUR);
124	/* issue command to initialize the system time value */
125	value = readl(ioaddr + PTP_TCR);
126	value |= PTP_TCR_TSINIT;
127	writel(value, ioaddr + PTP_TCR);
128
129	/* wait for present system time initialize to complete */
130	return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
131				 !(value & PTP_TCR_TSINIT),
132				 10, 100000);
133}
134
135static int config_addend(void __iomem *ioaddr, u32 addend)
136{
137	u32 value;
138
139	writel(addend, ioaddr + PTP_TAR);
140	/* issue command to update the addend value */
141	value = readl(ioaddr + PTP_TCR);
142	value |= PTP_TCR_TSADDREG;
143	writel(value, ioaddr + PTP_TCR);
144
145	/* wait for present addend update to complete */
146	return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
147					 !(value & PTP_TCR_TSADDREG),
148					 10, 100000);
149}
150
151static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
152		int add_sub, int gmac4)
153{
154	u32 value;
155
156	if (add_sub) {
157		/* If the new sec value needs to be subtracted with
158		 * the system time, then MAC_STSUR reg should be
159		 * programmed with (2^32 – <new_sec_value>)
160		 */
161		if (gmac4)
162			sec = -sec;
163
164		value = readl(ioaddr + PTP_TCR);
165		if (value & PTP_TCR_TSCTRLSSR)
166			nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
167		else
168			nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
169	}
170
171	writel(sec, ioaddr + PTP_STSUR);
172	value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
173	writel(value, ioaddr + PTP_STNSUR);
174
175	/* issue command to initialize the system time value */
176	value = readl(ioaddr + PTP_TCR);
177	value |= PTP_TCR_TSUPDT;
178	writel(value, ioaddr + PTP_TCR);
179
180	/* wait for present system time adjust/update to complete */
181	return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
182					 !(value & PTP_TCR_TSUPDT),
183					 10, 100000);
184}
185
186static void get_systime(void __iomem *ioaddr, u64 *systime)
187{
188	u64 ns, sec0, sec1;
189
190	/* Get the TSS value */
191	sec1 = readl_relaxed(ioaddr + PTP_STSR);
192	do {
193		sec0 = sec1;
194		/* Get the TSSS value */
195		ns = readl_relaxed(ioaddr + PTP_STNSR);
196		/* Get the TSS value */
197		sec1 = readl_relaxed(ioaddr + PTP_STSR);
198	} while (sec0 != sec1);
199
200	if (systime)
201		*systime = ns + (sec1 * 1000000000ULL);
202}
203
204static void get_ptptime(void __iomem *ptpaddr, u64 *ptp_time)
205{
206	u64 ns;
207
208	ns = readl(ptpaddr + PTP_ATNR);
209	ns += (u64)readl(ptpaddr + PTP_ATSR) * NSEC_PER_SEC;
210
211	*ptp_time = ns;
212}
213
214static void timestamp_interrupt(struct stmmac_priv *priv)
215{
216	u32 num_snapshot, ts_status, tsync_int;
217	struct ptp_clock_event event;
218	u32 acr_value, channel;
219	unsigned long flags;
220	u64 ptp_time;
221	int i;
222
223	if (priv->plat->flags & STMMAC_FLAG_INT_SNAPSHOT_EN) {
224		wake_up(&priv->tstamp_busy_wait);
225		return;
226	}
227
228	tsync_int = readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE;
229
230	if (!tsync_int)
231		return;
232
233	/* Read timestamp status to clear interrupt from either external
234	 * timestamp or start/end of PPS.
235	 */
236	ts_status = readl(priv->ioaddr + GMAC_TIMESTAMP_STATUS);
237
238	if (!(priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN))
239		return;
240
241	num_snapshot = (ts_status & GMAC_TIMESTAMP_ATSNS_MASK) >>
242		       GMAC_TIMESTAMP_ATSNS_SHIFT;
243
244	acr_value = readl(priv->ptpaddr + PTP_ACR);
245	channel = ilog2(FIELD_GET(PTP_ACR_MASK, acr_value));
246
247	for (i = 0; i < num_snapshot; i++) {
248		read_lock_irqsave(&priv->ptp_lock, flags);
249		get_ptptime(priv->ptpaddr, &ptp_time);
250		read_unlock_irqrestore(&priv->ptp_lock, flags);
251		event.type = PTP_CLOCK_EXTTS;
252		event.index = channel;
253		event.timestamp = ptp_time;
254		ptp_clock_event(priv->ptp_clock, &event);
255	}
256}
257
258const struct stmmac_hwtimestamp stmmac_ptp = {
259	.config_hw_tstamping = config_hw_tstamping,
260	.init_systime = init_systime,
261	.config_sub_second_increment = config_sub_second_increment,
262	.config_addend = config_addend,
263	.adjust_systime = adjust_systime,
264	.get_systime = get_systime,
265	.get_ptptime = get_ptptime,
266	.timestamp_interrupt = timestamp_interrupt,
267	.hwtstamp_correct_latency = hwtstamp_correct_latency,
268};
269
270const struct stmmac_hwtimestamp dwmac1000_ptp = {
271	.config_hw_tstamping = config_hw_tstamping,
272	.init_systime = init_systime,
273	.config_sub_second_increment = config_sub_second_increment,
274	.config_addend = config_addend,
275	.adjust_systime = adjust_systime,
276	.get_systime = get_systime,
277	.get_ptptime = dwmac1000_get_ptptime,
278	.timestamp_interrupt = dwmac1000_timestamp_interrupt,
279};