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stmmac_ethtool.c
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linux-6.19.14/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
1// SPDX-License-Identifier: GPL-2.0-only 2/******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9*******************************************************************************/ 10 11#include <linux/etherdevice.h> 12#include <linux/ethtool.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/mii.h> 16#include <linux/phylink.h> 17#include <linux/net_tstamp.h> 18 19#include "stmmac.h" 20#include "stmmac_fpe.h" 21#include "dwmac_dma.h" 22#include "dwxgmac2.h" 23 24#define REG_SPACE_SIZE 0x1060 25#define GMAC4_REG_SPACE_SIZE 0x116C 26#define MAC100_ETHTOOL_NAME "st_mac100" 27#define GMAC_ETHTOOL_NAME "st_gmac" 28#define XGMAC_ETHTOOL_NAME "st_xgmac" 29 30/* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 31 * 32 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 33 * same time due to the conflicting macro names. 34 */ 35#define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 36 37#define ETHTOOL_DMA_OFFSET 55 38 39struct stmmac_stats { 40 char stat_string[ETH_GSTRING_LEN] __nonstring; 41 int sizeof_stat; 42 int stat_offset; 43}; 44 45#define STMMAC_STAT(m) \ 46 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 47 offsetof(struct stmmac_priv, xstats.m)} 48 49static const struct stmmac_stats stmmac_gstrings_stats[] = { 50 /* Transmit errors */ 51 STMMAC_STAT(tx_underflow), 52 STMMAC_STAT(tx_carrier), 53 STMMAC_STAT(tx_losscarrier), 54 STMMAC_STAT(vlan_tag), 55 STMMAC_STAT(tx_deferred), 56 STMMAC_STAT(tx_vlan), 57 STMMAC_STAT(tx_jabber), 58 STMMAC_STAT(tx_frame_flushed), 59 STMMAC_STAT(tx_payload_error), 60 STMMAC_STAT(tx_ip_header_error), 61 /* Receive errors */ 62 STMMAC_STAT(rx_desc), 63 STMMAC_STAT(sa_filter_fail), 64 STMMAC_STAT(overflow_error), 65 STMMAC_STAT(ipc_csum_error), 66 STMMAC_STAT(rx_collision), 67 STMMAC_STAT(rx_crc_errors), 68 STMMAC_STAT(dribbling_bit), 69 STMMAC_STAT(rx_length), 70 STMMAC_STAT(rx_mii), 71 STMMAC_STAT(rx_multicast), 72 STMMAC_STAT(rx_gmac_overflow), 73 STMMAC_STAT(rx_watchdog), 74 STMMAC_STAT(da_rx_filter_fail), 75 STMMAC_STAT(sa_rx_filter_fail), 76 STMMAC_STAT(rx_missed_cntr), 77 STMMAC_STAT(rx_overflow_cntr), 78 STMMAC_STAT(rx_vlan), 79 STMMAC_STAT(rx_split_hdr_pkt_n), 80 /* Tx/Rx IRQ error info */ 81 STMMAC_STAT(tx_undeflow_irq), 82 STMMAC_STAT(tx_process_stopped_irq), 83 STMMAC_STAT(tx_jabber_irq), 84 STMMAC_STAT(rx_overflow_irq), 85 STMMAC_STAT(rx_buf_unav_irq), 86 STMMAC_STAT(rx_process_stopped_irq), 87 STMMAC_STAT(rx_watchdog_irq), 88 STMMAC_STAT(tx_early_irq), 89 STMMAC_STAT(fatal_bus_error_irq), 90 /* Tx/Rx IRQ Events */ 91 STMMAC_STAT(rx_early_irq), 92 STMMAC_STAT(threshold), 93 STMMAC_STAT(irq_receive_pmt_irq_n), 94 /* MMC info */ 95 STMMAC_STAT(mmc_tx_irq_n), 96 STMMAC_STAT(mmc_rx_irq_n), 97 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 98 /* EEE */ 99 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 100 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 102 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 103 STMMAC_STAT(phy_eee_wakeup_error_n), 104 /* Extended RDES status */ 105 STMMAC_STAT(ip_hdr_err), 106 STMMAC_STAT(ip_payload_err), 107 STMMAC_STAT(ip_csum_bypassed), 108 STMMAC_STAT(ipv4_pkt_rcvd), 109 STMMAC_STAT(ipv6_pkt_rcvd), 110 STMMAC_STAT(no_ptp_rx_msg_type_ext), 111 STMMAC_STAT(ptp_rx_msg_type_sync), 112 STMMAC_STAT(ptp_rx_msg_type_follow_up), 113 STMMAC_STAT(ptp_rx_msg_type_delay_req), 114 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 117 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 118 STMMAC_STAT(ptp_rx_msg_type_announce), 119 STMMAC_STAT(ptp_rx_msg_type_management), 120 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 121 STMMAC_STAT(ptp_frame_type), 122 STMMAC_STAT(ptp_ver), 123 STMMAC_STAT(timestamp_dropped), 124 STMMAC_STAT(av_pkt_rcvd), 125 STMMAC_STAT(av_tagged_pkt_rcvd), 126 STMMAC_STAT(vlan_tag_priority_val), 127 STMMAC_STAT(l3_filter_match), 128 STMMAC_STAT(l4_filter_match), 129 STMMAC_STAT(l3_l4_filter_no_match), 130 /* PCS */ 131 STMMAC_STAT(irq_pcs_ane_n), 132 STMMAC_STAT(irq_pcs_link_n), 133 STMMAC_STAT(irq_rgmii_n), 134 /* DEBUG */ 135 STMMAC_STAT(mtl_tx_status_fifo_full), 136 STMMAC_STAT(mtl_tx_fifo_not_empty), 137 STMMAC_STAT(mmtl_fifo_ctrl), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 141 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 142 STMMAC_STAT(mac_tx_in_pause), 143 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 144 STMMAC_STAT(mac_tx_frame_ctrl_idle), 145 STMMAC_STAT(mac_tx_frame_ctrl_wait), 146 STMMAC_STAT(mac_tx_frame_ctrl_pause), 147 STMMAC_STAT(mac_gmii_tx_proto_engine), 148 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 149 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 151 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 155 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 156 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 157 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 158 STMMAC_STAT(mac_gmii_rx_proto_engine), 159 /* EST */ 160 STMMAC_STAT(mtl_est_cgce), 161 STMMAC_STAT(mtl_est_hlbs), 162 STMMAC_STAT(mtl_est_hlbf), 163 STMMAC_STAT(mtl_est_btre), 164 STMMAC_STAT(mtl_est_btrlm), 165}; 166#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 167 168/* statistics collected in queue which will be summed up for all TX or RX 169 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n). 170 */ 171static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = { 172 "rx_pkt_n", 173 "rx_normal_irq_n", 174 "tx_pkt_n", 175 "tx_normal_irq_n", 176 "tx_clean", 177 "tx_set_ic_bit", 178 "tx_tso_frames", 179 "tx_tso_nfrags", 180 "normal_irq_n", 181 "napi_poll", 182}; 183#define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string) 184 185/* HW MAC Management counters (if supported) */ 186#define STMMAC_MMC_STAT(m) \ 187 { #m, sizeof_field(struct stmmac_counters, m), \ 188 offsetof(struct stmmac_priv, mmc.m)} 189 190static const struct stmmac_stats stmmac_mmc[] = { 191 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 192 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 193 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 194 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 195 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 196 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 197 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 198 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 199 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 200 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 201 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 202 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 203 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 204 STMMAC_MMC_STAT(mmc_tx_underflow_error), 205 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 206 STMMAC_MMC_STAT(mmc_tx_multicol_g), 207 STMMAC_MMC_STAT(mmc_tx_deferred), 208 STMMAC_MMC_STAT(mmc_tx_latecol), 209 STMMAC_MMC_STAT(mmc_tx_exesscol), 210 STMMAC_MMC_STAT(mmc_tx_carrier_error), 211 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 212 STMMAC_MMC_STAT(mmc_tx_framecount_g), 213 STMMAC_MMC_STAT(mmc_tx_excessdef), 214 STMMAC_MMC_STAT(mmc_tx_pause_frame), 215 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 216 STMMAC_MMC_STAT(mmc_tx_oversize_g), 217 STMMAC_MMC_STAT(mmc_tx_lpi_usec), 218 STMMAC_MMC_STAT(mmc_tx_lpi_tran), 219 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 220 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 221 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 222 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 223 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 224 STMMAC_MMC_STAT(mmc_rx_crc_error), 225 STMMAC_MMC_STAT(mmc_rx_align_error), 226 STMMAC_MMC_STAT(mmc_rx_run_error), 227 STMMAC_MMC_STAT(mmc_rx_jabber_error), 228 STMMAC_MMC_STAT(mmc_rx_undersize_g), 229 STMMAC_MMC_STAT(mmc_rx_oversize_g), 230 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 231 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 232 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 233 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 234 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 235 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 236 STMMAC_MMC_STAT(mmc_rx_unicast_g), 237 STMMAC_MMC_STAT(mmc_rx_length_error), 238 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 239 STMMAC_MMC_STAT(mmc_rx_pause_frames), 240 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 241 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 242 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 243 STMMAC_MMC_STAT(mmc_rx_error), 244 STMMAC_MMC_STAT(mmc_rx_lpi_usec), 245 STMMAC_MMC_STAT(mmc_rx_lpi_tran), 246 STMMAC_MMC_STAT(mmc_rx_discard_frames_gb), 247 STMMAC_MMC_STAT(mmc_rx_discard_octets_gb), 248 STMMAC_MMC_STAT(mmc_rx_align_err_frames), 249 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 250 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 251 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 252 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 253 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 254 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 255 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 256 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 257 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 258 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 259 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 260 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 261 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 262 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 263 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 264 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 265 STMMAC_MMC_STAT(mmc_rx_udp_gd), 266 STMMAC_MMC_STAT(mmc_rx_udp_err), 267 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 268 STMMAC_MMC_STAT(mmc_rx_tcp_err), 269 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 270 STMMAC_MMC_STAT(mmc_rx_icmp_err), 271 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 272 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 273 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 274 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 275 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 276 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 277 STMMAC_MMC_STAT(mmc_sgf_pass_fragment_cntr), 278 STMMAC_MMC_STAT(mmc_sgf_fail_fragment_cntr), 279 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 280 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 281 STMMAC_MMC_STAT(mmc_tx_gate_overrun_cntr), 282 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 283 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 284 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 285 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 286}; 287#define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 288 289static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 290 "tx_pkt_n", 291 "tx_irq_n", 292#define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 293}; 294 295static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 296 "rx_pkt_n", 297 "rx_irq_n", 298#define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 299}; 300 301static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 302 struct ethtool_drvinfo *info) 303{ 304 struct stmmac_priv *priv = netdev_priv(dev); 305 306 if (priv->plat->core_type == DWMAC_CORE_GMAC || 307 priv->plat->core_type == DWMAC_CORE_GMAC4) 308 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 309 else if (priv->plat->core_type == DWMAC_CORE_XGMAC) 310 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 311 else 312 strscpy(info->driver, MAC100_ETHTOOL_NAME, 313 sizeof(info->driver)); 314 315 if (priv->plat->pdev) { 316 strscpy(info->bus_info, pci_name(priv->plat->pdev), 317 sizeof(info->bus_info)); 318 } 319} 320 321static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 322 struct ethtool_link_ksettings *cmd) 323{ 324 struct stmmac_priv *priv = netdev_priv(dev); 325 326 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 327} 328 329static int 330stmmac_ethtool_set_link_ksettings(struct net_device *dev, 331 const struct ethtool_link_ksettings *cmd) 332{ 333 struct stmmac_priv *priv = netdev_priv(dev); 334 335 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 336} 337 338static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 339{ 340 struct stmmac_priv *priv = netdev_priv(dev); 341 return priv->msg_enable; 342} 343 344static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 345{ 346 struct stmmac_priv *priv = netdev_priv(dev); 347 priv->msg_enable = level; 348 349} 350 351static int stmmac_ethtool_get_regs_len(struct net_device *dev) 352{ 353 struct stmmac_priv *priv = netdev_priv(dev); 354 355 if (priv->plat->core_type == DWMAC_CORE_XGMAC) 356 return XGMAC_REGSIZE * 4; 357 else if (priv->plat->core_type == DWMAC_CORE_GMAC4) 358 return GMAC4_REG_SPACE_SIZE; 359 return REG_SPACE_SIZE; 360} 361 362static void stmmac_ethtool_gregs(struct net_device *dev, 363 struct ethtool_regs *regs, void *space) 364{ 365 struct stmmac_priv *priv = netdev_priv(dev); 366 u32 *reg_space = (u32 *) space; 367 368 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 369 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 370 371 /* Copy DMA registers to where ethtool expects them */ 372 if (priv->plat->core_type == DWMAC_CORE_GMAC4) { 373 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 374 memcpy(®_space[ETHTOOL_DMA_OFFSET], 375 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 376 NUM_DWMAC4_DMA_REGS * 4); 377 } else if (priv->plat->core_type != DWMAC_CORE_XGMAC) { 378 memcpy(®_space[ETHTOOL_DMA_OFFSET], 379 ®_space[DMA_BUS_MODE / 4], 380 NUM_DWMAC1000_DMA_REGS * 4); 381 } 382} 383 384static int stmmac_nway_reset(struct net_device *dev) 385{ 386 struct stmmac_priv *priv = netdev_priv(dev); 387 388 return phylink_ethtool_nway_reset(priv->phylink); 389} 390 391static void stmmac_get_ringparam(struct net_device *netdev, 392 struct ethtool_ringparam *ring, 393 struct kernel_ethtool_ringparam *kernel_ring, 394 struct netlink_ext_ack *extack) 395{ 396 struct stmmac_priv *priv = netdev_priv(netdev); 397 398 ring->rx_max_pending = DMA_MAX_RX_SIZE; 399 ring->tx_max_pending = DMA_MAX_TX_SIZE; 400 ring->rx_pending = priv->dma_conf.dma_rx_size; 401 ring->tx_pending = priv->dma_conf.dma_tx_size; 402} 403 404static int stmmac_set_ringparam(struct net_device *netdev, 405 struct ethtool_ringparam *ring, 406 struct kernel_ethtool_ringparam *kernel_ring, 407 struct netlink_ext_ack *extack) 408{ 409 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 410 ring->rx_pending < DMA_MIN_RX_SIZE || 411 ring->rx_pending > DMA_MAX_RX_SIZE || 412 !is_power_of_2(ring->rx_pending) || 413 ring->tx_pending < DMA_MIN_TX_SIZE || 414 ring->tx_pending > DMA_MAX_TX_SIZE || 415 !is_power_of_2(ring->tx_pending)) 416 return -EINVAL; 417 418 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 419 ring->tx_pending); 420} 421 422static void 423stmmac_get_pauseparam(struct net_device *netdev, 424 struct ethtool_pauseparam *pause) 425{ 426 struct stmmac_priv *priv = netdev_priv(netdev); 427 428 phylink_ethtool_get_pauseparam(priv->phylink, pause); 429} 430 431static int 432stmmac_set_pauseparam(struct net_device *netdev, 433 struct ethtool_pauseparam *pause) 434{ 435 struct stmmac_priv *priv = netdev_priv(netdev); 436 437 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 438} 439 440static u64 stmmac_get_rx_normal_irq_n(struct stmmac_priv *priv, int q) 441{ 442 u64 total; 443 int cpu; 444 445 total = 0; 446 for_each_possible_cpu(cpu) { 447 struct stmmac_pcpu_stats *pcpu; 448 unsigned int start; 449 u64 irq_n; 450 451 pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu); 452 do { 453 start = u64_stats_fetch_begin(&pcpu->syncp); 454 irq_n = u64_stats_read(&pcpu->rx_normal_irq_n[q]); 455 } while (u64_stats_fetch_retry(&pcpu->syncp, start)); 456 total += irq_n; 457 } 458 return total; 459} 460 461static u64 stmmac_get_tx_normal_irq_n(struct stmmac_priv *priv, int q) 462{ 463 u64 total; 464 int cpu; 465 466 total = 0; 467 for_each_possible_cpu(cpu) { 468 struct stmmac_pcpu_stats *pcpu; 469 unsigned int start; 470 u64 irq_n; 471 472 pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu); 473 do { 474 start = u64_stats_fetch_begin(&pcpu->syncp); 475 irq_n = u64_stats_read(&pcpu->tx_normal_irq_n[q]); 476 } while (u64_stats_fetch_retry(&pcpu->syncp, start)); 477 total += irq_n; 478 } 479 return total; 480} 481 482static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 483{ 484 u32 tx_cnt = priv->plat->tx_queues_to_use; 485 u32 rx_cnt = priv->plat->rx_queues_to_use; 486 unsigned int start; 487 int q; 488 489 for (q = 0; q < tx_cnt; q++) { 490 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q]; 491 u64 pkt_n; 492 493 do { 494 start = u64_stats_fetch_begin(&txq_stats->napi_syncp); 495 pkt_n = u64_stats_read(&txq_stats->napi.tx_pkt_n); 496 } while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start)); 497 498 *data++ = pkt_n; 499 *data++ = stmmac_get_tx_normal_irq_n(priv, q); 500 } 501 502 for (q = 0; q < rx_cnt; q++) { 503 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q]; 504 u64 pkt_n; 505 506 do { 507 start = u64_stats_fetch_begin(&rxq_stats->napi_syncp); 508 pkt_n = u64_stats_read(&rxq_stats->napi.rx_pkt_n); 509 } while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start)); 510 511 *data++ = pkt_n; 512 *data++ = stmmac_get_rx_normal_irq_n(priv, q); 513 } 514} 515 516static void stmmac_get_ethtool_stats(struct net_device *dev, 517 struct ethtool_stats *dummy, u64 *data) 518{ 519 struct stmmac_priv *priv = netdev_priv(dev); 520 u32 rx_queues_count = priv->plat->rx_queues_to_use; 521 u32 tx_queues_count = priv->plat->tx_queues_to_use; 522 u64 napi_poll = 0, normal_irq_n = 0; 523 int i, j = 0, pos, ret; 524 unsigned long count; 525 unsigned int start; 526 527 if (priv->dma_cap.asp) { 528 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 529 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 530 &count, NULL)) 531 data[j++] = count; 532 } 533 } 534 535 /* Update the DMA HW counters for dwmac10/100 */ 536 ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr); 537 if (ret) { 538 /* If supported, for new GMAC chips expose the MMC counters */ 539 if (priv->dma_cap.rmon) { 540 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 541 542 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 543 char *p; 544 p = (char *)priv + stmmac_mmc[i].stat_offset; 545 546 data[j++] = (stmmac_mmc[i].sizeof_stat == 547 sizeof(u64)) ? (*(u64 *)p) : 548 (*(u32 *)p); 549 } 550 } 551 if (priv->dma_cap.eee) { 552 int val = phylink_get_eee_err(priv->phylink); 553 if (val) 554 priv->xstats.phy_eee_wakeup_error_n = val; 555 } 556 557 if (priv->synopsys_id >= DWMAC_CORE_3_50) 558 stmmac_mac_debug(priv, priv->ioaddr, 559 (void *)&priv->xstats, 560 rx_queues_count, tx_queues_count); 561 } 562 for (i = 0; i < STMMAC_STATS_LEN; i++) { 563 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 564 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 565 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 566 } 567 568 pos = j; 569 for (i = 0; i < rx_queues_count; i++) { 570 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i]; 571 struct stmmac_napi_rx_stats snapshot; 572 u64 n_irq; 573 574 j = pos; 575 do { 576 start = u64_stats_fetch_begin(&rxq_stats->napi_syncp); 577 snapshot = rxq_stats->napi; 578 } while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start)); 579 580 data[j++] += u64_stats_read(&snapshot.rx_pkt_n); 581 n_irq = stmmac_get_rx_normal_irq_n(priv, i); 582 data[j++] += n_irq; 583 normal_irq_n += n_irq; 584 napi_poll += u64_stats_read(&snapshot.poll); 585 } 586 587 pos = j; 588 for (i = 0; i < tx_queues_count; i++) { 589 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i]; 590 struct stmmac_napi_tx_stats napi_snapshot; 591 struct stmmac_q_tx_stats q_snapshot; 592 u64 n_irq; 593 594 j = pos; 595 do { 596 start = u64_stats_fetch_begin(&txq_stats->q_syncp); 597 q_snapshot = txq_stats->q; 598 } while (u64_stats_fetch_retry(&txq_stats->q_syncp, start)); 599 do { 600 start = u64_stats_fetch_begin(&txq_stats->napi_syncp); 601 napi_snapshot = txq_stats->napi; 602 } while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start)); 603 604 data[j++] += u64_stats_read(&napi_snapshot.tx_pkt_n); 605 n_irq = stmmac_get_tx_normal_irq_n(priv, i); 606 data[j++] += n_irq; 607 normal_irq_n += n_irq; 608 data[j++] += u64_stats_read(&napi_snapshot.tx_clean); 609 data[j++] += u64_stats_read(&q_snapshot.tx_set_ic_bit) + 610 u64_stats_read(&napi_snapshot.tx_set_ic_bit); 611 data[j++] += u64_stats_read(&q_snapshot.tx_tso_frames); 612 data[j++] += u64_stats_read(&q_snapshot.tx_tso_nfrags); 613 napi_poll += u64_stats_read(&napi_snapshot.poll); 614 } 615 normal_irq_n += priv->xstats.rx_early_irq; 616 data[j++] = normal_irq_n; 617 data[j++] = napi_poll; 618 619 stmmac_get_per_qstats(priv, &data[j]); 620} 621 622static int stmmac_get_sset_count(struct net_device *netdev, int sset) 623{ 624 struct stmmac_priv *priv = netdev_priv(netdev); 625 u32 tx_cnt = priv->plat->tx_queues_to_use; 626 u32 rx_cnt = priv->plat->rx_queues_to_use; 627 int i, len, safety_len = 0; 628 629 switch (sset) { 630 case ETH_SS_STATS: 631 len = STMMAC_STATS_LEN + STMMAC_QSTATS + 632 STMMAC_TXQ_STATS * tx_cnt + 633 STMMAC_RXQ_STATS * rx_cnt; 634 635 if (priv->dma_cap.rmon) 636 len += STMMAC_MMC_STATS_LEN; 637 if (priv->dma_cap.asp) { 638 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 639 if (!stmmac_safety_feat_dump(priv, 640 &priv->sstats, i, 641 NULL, NULL)) 642 safety_len++; 643 } 644 645 len += safety_len; 646 } 647 648 return len; 649 case ETH_SS_TEST: 650 return stmmac_selftest_get_count(priv); 651 default: 652 return -EOPNOTSUPP; 653 } 654} 655 656static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 657{ 658 u32 tx_cnt = priv->plat->tx_queues_to_use; 659 u32 rx_cnt = priv->plat->rx_queues_to_use; 660 int q, stat; 661 662 for (q = 0; q < tx_cnt; q++) { 663 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 664 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 665 stmmac_qstats_tx_string[stat]); 666 data += ETH_GSTRING_LEN; 667 } 668 } 669 for (q = 0; q < rx_cnt; q++) { 670 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 671 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 672 stmmac_qstats_rx_string[stat]); 673 data += ETH_GSTRING_LEN; 674 } 675 } 676} 677 678static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 679{ 680 int i; 681 u8 *p = data; 682 struct stmmac_priv *priv = netdev_priv(dev); 683 684 switch (stringset) { 685 case ETH_SS_STATS: 686 if (priv->dma_cap.asp) { 687 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 688 const char *desc; 689 if (!stmmac_safety_feat_dump(priv, 690 &priv->sstats, i, 691 NULL, &desc)) { 692 memcpy(p, desc, ETH_GSTRING_LEN); 693 p += ETH_GSTRING_LEN; 694 } 695 } 696 } 697 if (priv->dma_cap.rmon) 698 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 699 memcpy(p, stmmac_mmc[i].stat_string, 700 ETH_GSTRING_LEN); 701 p += ETH_GSTRING_LEN; 702 } 703 for (i = 0; i < STMMAC_STATS_LEN; i++) { 704 memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN); 705 p += ETH_GSTRING_LEN; 706 } 707 for (i = 0; i < STMMAC_QSTATS; i++) { 708 memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN); 709 p += ETH_GSTRING_LEN; 710 } 711 stmmac_get_qstats_string(priv, p); 712 break; 713 case ETH_SS_TEST: 714 stmmac_selftest_get_strings(priv, p); 715 break; 716 default: 717 WARN_ON(1); 718 break; 719 } 720} 721 722/* Currently only support WOL through Magic packet. */ 723static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 724{ 725 struct stmmac_priv *priv = netdev_priv(dev); 726 727 return phylink_ethtool_get_wol(priv->phylink, wol); 728} 729 730static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 731{ 732 struct stmmac_priv *priv = netdev_priv(dev); 733 734 return phylink_ethtool_set_wol(priv->phylink, wol); 735} 736 737static int stmmac_ethtool_op_get_eee(struct net_device *dev, 738 struct ethtool_keee *edata) 739{ 740 struct stmmac_priv *priv = netdev_priv(dev); 741 742 return phylink_ethtool_get_eee(priv->phylink, edata); 743} 744 745static int stmmac_ethtool_op_set_eee(struct net_device *dev, 746 struct ethtool_keee *edata) 747{ 748 struct stmmac_priv *priv = netdev_priv(dev); 749 750 return phylink_ethtool_set_eee(priv->phylink, edata); 751} 752 753static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 754{ 755 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 756 757 if (!clk) { 758 clk = priv->plat->clk_ref_rate; 759 if (!clk) 760 return 0; 761 } 762 763 return (usec * (clk / 1000000)) / 256; 764} 765 766static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 767{ 768 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 769 770 if (!clk) { 771 clk = priv->plat->clk_ref_rate; 772 if (!clk) 773 return 0; 774 } 775 776 return (riwt * 256) / (clk / 1000000); 777} 778 779static int __stmmac_get_coalesce(struct net_device *dev, 780 struct ethtool_coalesce *ec, 781 int queue) 782{ 783 struct stmmac_priv *priv = netdev_priv(dev); 784 u32 max_cnt; 785 u32 rx_cnt; 786 u32 tx_cnt; 787 788 rx_cnt = priv->plat->rx_queues_to_use; 789 tx_cnt = priv->plat->tx_queues_to_use; 790 max_cnt = max(rx_cnt, tx_cnt); 791 792 if (queue < 0) 793 queue = 0; 794 else if (queue >= max_cnt) 795 return -EINVAL; 796 797 if (queue < tx_cnt) { 798 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 799 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 800 } else { 801 ec->tx_coalesce_usecs = 0; 802 ec->tx_max_coalesced_frames = 0; 803 } 804 805 if (priv->use_riwt && queue < rx_cnt) { 806 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 807 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 808 priv); 809 } else { 810 ec->rx_max_coalesced_frames = 0; 811 ec->rx_coalesce_usecs = 0; 812 } 813 814 return 0; 815} 816 817static int stmmac_get_coalesce(struct net_device *dev, 818 struct ethtool_coalesce *ec, 819 struct kernel_ethtool_coalesce *kernel_coal, 820 struct netlink_ext_ack *extack) 821{ 822 return __stmmac_get_coalesce(dev, ec, -1); 823} 824 825static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 826 struct ethtool_coalesce *ec) 827{ 828 return __stmmac_get_coalesce(dev, ec, queue); 829} 830 831static int __stmmac_set_coalesce(struct net_device *dev, 832 struct ethtool_coalesce *ec, 833 int queue) 834{ 835 struct stmmac_priv *priv = netdev_priv(dev); 836 bool all_queues = false; 837 unsigned int rx_riwt; 838 u32 max_cnt; 839 u32 rx_cnt; 840 u32 tx_cnt; 841 842 rx_cnt = priv->plat->rx_queues_to_use; 843 tx_cnt = priv->plat->tx_queues_to_use; 844 max_cnt = max(rx_cnt, tx_cnt); 845 846 if (queue < 0) 847 all_queues = true; 848 else if (queue >= max_cnt) 849 return -EINVAL; 850 851 if (priv->use_riwt) { 852 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 853 854 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 855 return -EINVAL; 856 857 if (all_queues) { 858 int i; 859 860 for (i = 0; i < rx_cnt; i++) { 861 priv->rx_riwt[i] = rx_riwt; 862 stmmac_rx_watchdog(priv, priv->ioaddr, 863 rx_riwt, i); 864 priv->rx_coal_frames[i] = 865 ec->rx_max_coalesced_frames; 866 } 867 } else if (queue < rx_cnt) { 868 priv->rx_riwt[queue] = rx_riwt; 869 stmmac_rx_watchdog(priv, priv->ioaddr, 870 rx_riwt, queue); 871 priv->rx_coal_frames[queue] = 872 ec->rx_max_coalesced_frames; 873 } 874 } 875 876 if ((ec->tx_coalesce_usecs == 0) && 877 (ec->tx_max_coalesced_frames == 0)) 878 return -EINVAL; 879 880 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 881 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 882 return -EINVAL; 883 884 if (all_queues) { 885 int i; 886 887 for (i = 0; i < tx_cnt; i++) { 888 priv->tx_coal_frames[i] = 889 ec->tx_max_coalesced_frames; 890 priv->tx_coal_timer[i] = 891 ec->tx_coalesce_usecs; 892 } 893 } else if (queue < tx_cnt) { 894 priv->tx_coal_frames[queue] = 895 ec->tx_max_coalesced_frames; 896 priv->tx_coal_timer[queue] = 897 ec->tx_coalesce_usecs; 898 } 899 900 return 0; 901} 902 903static int stmmac_set_coalesce(struct net_device *dev, 904 struct ethtool_coalesce *ec, 905 struct kernel_ethtool_coalesce *kernel_coal, 906 struct netlink_ext_ack *extack) 907{ 908 return __stmmac_set_coalesce(dev, ec, -1); 909} 910 911static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 912 struct ethtool_coalesce *ec) 913{ 914 return __stmmac_set_coalesce(dev, ec, queue); 915} 916 917static int stmmac_get_rxnfc(struct net_device *dev, 918 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 919{ 920 struct stmmac_priv *priv = netdev_priv(dev); 921 922 switch (rxnfc->cmd) { 923 case ETHTOOL_GRXRINGS: 924 rxnfc->data = priv->plat->rx_queues_to_use; 925 break; 926 default: 927 return -EOPNOTSUPP; 928 } 929 930 return 0; 931} 932 933static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 934{ 935 struct stmmac_priv *priv = netdev_priv(dev); 936 937 return sizeof(priv->rss.key); 938} 939 940static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 941{ 942 struct stmmac_priv *priv = netdev_priv(dev); 943 944 return ARRAY_SIZE(priv->rss.table); 945} 946 947static int stmmac_get_rxfh(struct net_device *dev, 948 struct ethtool_rxfh_param *rxfh) 949{ 950 struct stmmac_priv *priv = netdev_priv(dev); 951 int i; 952 953 if (rxfh->indir) { 954 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 955 rxfh->indir[i] = priv->rss.table[i]; 956 } 957 958 if (rxfh->key) 959 memcpy(rxfh->key, priv->rss.key, sizeof(priv->rss.key)); 960 rxfh->hfunc = ETH_RSS_HASH_TOP; 961 962 return 0; 963} 964 965static int stmmac_set_rxfh(struct net_device *dev, 966 struct ethtool_rxfh_param *rxfh, 967 struct netlink_ext_ack *extack) 968{ 969 struct stmmac_priv *priv = netdev_priv(dev); 970 int i; 971 972 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 973 rxfh->hfunc != ETH_RSS_HASH_TOP) 974 return -EOPNOTSUPP; 975 976 if (rxfh->indir) { 977 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 978 priv->rss.table[i] = rxfh->indir[i]; 979 } 980 981 if (rxfh->key) 982 memcpy(priv->rss.key, rxfh->key, sizeof(priv->rss.key)); 983 984 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 985 priv->plat->rx_queues_to_use); 986} 987 988static void stmmac_get_channels(struct net_device *dev, 989 struct ethtool_channels *chan) 990{ 991 struct stmmac_priv *priv = netdev_priv(dev); 992 993 chan->rx_count = priv->plat->rx_queues_to_use; 994 chan->tx_count = priv->plat->tx_queues_to_use; 995 chan->max_rx = priv->dma_cap.number_rx_queues; 996 chan->max_tx = priv->dma_cap.number_tx_queues; 997} 998 999static int stmmac_set_channels(struct net_device *dev, 1000 struct ethtool_channels *chan) 1001{ 1002 struct stmmac_priv *priv = netdev_priv(dev); 1003 1004 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1005 chan->tx_count > priv->dma_cap.number_tx_queues || 1006 !chan->rx_count || !chan->tx_count) 1007 return -EINVAL; 1008 1009 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1010} 1011 1012static int stmmac_get_ts_info(struct net_device *dev, 1013 struct kernel_ethtool_ts_info *info) 1014{ 1015 struct stmmac_priv *priv = netdev_priv(dev); 1016 1017 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1018 1019 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1020 SOF_TIMESTAMPING_TX_HARDWARE | 1021 SOF_TIMESTAMPING_RX_HARDWARE | 1022 SOF_TIMESTAMPING_RAW_HARDWARE; 1023 1024 if (priv->ptp_clock) 1025 info->phc_index = ptp_clock_index(priv->ptp_clock); 1026 else 1027 info->phc_index = 0; 1028 1029 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1030 1031 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1032 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1033 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1034 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1035 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1036 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1037 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1038 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1039 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1040 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1041 (1 << HWTSTAMP_FILTER_ALL)); 1042 return 0; 1043 } else 1044 return ethtool_op_get_ts_info(dev, info); 1045} 1046 1047static int stmmac_get_mm(struct net_device *ndev, 1048 struct ethtool_mm_state *state) 1049{ 1050 struct stmmac_priv *priv = netdev_priv(ndev); 1051 u32 frag_size; 1052 1053 if (!stmmac_fpe_supported(priv)) 1054 return -EOPNOTSUPP; 1055 1056 state->rx_min_frag_size = ETH_ZLEN; 1057 frag_size = stmmac_fpe_get_add_frag_size(priv); 1058 state->tx_min_frag_size = ethtool_mm_frag_size_add_to_min(frag_size); 1059 1060 ethtool_mmsv_get_mm(&priv->fpe_cfg.mmsv, state); 1061 1062 return 0; 1063} 1064 1065static int stmmac_set_mm(struct net_device *ndev, struct ethtool_mm_cfg *cfg, 1066 struct netlink_ext_ack *extack) 1067{ 1068 struct stmmac_priv *priv = netdev_priv(ndev); 1069 u32 frag_size; 1070 int err; 1071 1072 err = ethtool_mm_frag_size_min_to_add(cfg->tx_min_frag_size, 1073 &frag_size, extack); 1074 if (err) 1075 return err; 1076 1077 stmmac_fpe_set_add_frag_size(priv, frag_size); 1078 ethtool_mmsv_set_mm(&priv->fpe_cfg.mmsv, cfg); 1079 1080 return 0; 1081} 1082 1083static void stmmac_get_mm_stats(struct net_device *ndev, 1084 struct ethtool_mm_stats *s) 1085{ 1086 struct stmmac_priv *priv = netdev_priv(ndev); 1087 struct stmmac_counters *mmc = &priv->mmc; 1088 1089 if (!priv->dma_cap.rmon) 1090 return; 1091 1092 stmmac_mmc_read(priv, priv->mmcaddr, mmc); 1093 1094 s->MACMergeFrameAssErrorCount = mmc->mmc_rx_packet_assembly_err_cntr; 1095 s->MACMergeFrameAssOkCount = mmc->mmc_rx_packet_assembly_ok_cntr; 1096 s->MACMergeFrameSmdErrorCount = mmc->mmc_rx_packet_smd_err_cntr; 1097 s->MACMergeFragCountRx = mmc->mmc_rx_fpe_fragment_cntr; 1098 s->MACMergeFragCountTx = mmc->mmc_tx_fpe_fragment_cntr; 1099 s->MACMergeHoldCount = mmc->mmc_tx_hold_req_cntr; 1100} 1101 1102static const struct ethtool_ops stmmac_ethtool_ops = { 1103 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1104 ETHTOOL_COALESCE_MAX_FRAMES, 1105 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1106 .get_msglevel = stmmac_ethtool_getmsglevel, 1107 .set_msglevel = stmmac_ethtool_setmsglevel, 1108 .get_regs = stmmac_ethtool_gregs, 1109 .get_regs_len = stmmac_ethtool_get_regs_len, 1110 .get_link = ethtool_op_get_link, 1111 .nway_reset = stmmac_nway_reset, 1112 .get_ringparam = stmmac_get_ringparam, 1113 .set_ringparam = stmmac_set_ringparam, 1114 .get_pauseparam = stmmac_get_pauseparam, 1115 .set_pauseparam = stmmac_set_pauseparam, 1116 .self_test = stmmac_selftest_run, 1117 .get_ethtool_stats = stmmac_get_ethtool_stats, 1118 .get_strings = stmmac_get_strings, 1119 .get_wol = stmmac_get_wol, 1120 .set_wol = stmmac_set_wol, 1121 .get_eee = stmmac_ethtool_op_get_eee, 1122 .set_eee = stmmac_ethtool_op_set_eee, 1123 .get_sset_count = stmmac_get_sset_count, 1124 .get_rxnfc = stmmac_get_rxnfc, 1125 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1126 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1127 .get_rxfh = stmmac_get_rxfh, 1128 .set_rxfh = stmmac_set_rxfh, 1129 .get_ts_info = stmmac_get_ts_info, 1130 .get_coalesce = stmmac_get_coalesce, 1131 .set_coalesce = stmmac_set_coalesce, 1132 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1133 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1134 .get_channels = stmmac_get_channels, 1135 .set_channels = stmmac_set_channels, 1136 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1137 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1138 .get_mm = stmmac_get_mm, 1139 .set_mm = stmmac_set_mm, 1140 .get_mm_stats = stmmac_get_mm_stats, 1141}; 1142 1143void stmmac_set_ethtool_ops(struct net_device *netdev) 1144{ 1145 netdev->ethtool_ops = &stmmac_ethtool_ops; 1146}
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