stmmac.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*******************************************************************************
  3  Copyright (C) 2007-2009  STMicroelectronics Ltd
  4
  5
  6  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  7*******************************************************************************/
  8
  9#ifndef __STMMAC_H__
 10#define __STMMAC_H__
 11
 12#define STMMAC_RESOURCE_NAME   "stmmaceth"
 13
 14#include <linux/clk.h>
 15#include <linux/hrtimer.h>
 16#include <linux/if_vlan.h>
 17#include <linux/stmmac.h>
 18#include <linux/phylink.h>
 19#include <linux/pci.h>
 20#include "common.h"
 21#include <linux/ptp_clock_kernel.h>
 22#include <linux/net_tstamp.h>
 23#include <linux/reset.h>
 24#include <net/page_pool/types.h>
 25#include <net/xdp.h>
 26#include <uapi/linux/bpf.h>
 27
 28struct stmmac_pcs;
 29
 30struct stmmac_resources {
 31	void __iomem *addr;
 32	u8 mac[ETH_ALEN];
 33	int wol_irq;
 34	int irq;
 35	int sfty_irq;
 36	int sfty_ce_irq;
 37	int sfty_ue_irq;
 38	int rx_irq[MTL_MAX_RX_QUEUES];
 39	int tx_irq[MTL_MAX_TX_QUEUES];
 40};
 41
 42enum stmmac_txbuf_type {
 43	STMMAC_TXBUF_T_SKB,
 44	STMMAC_TXBUF_T_XDP_TX,
 45	STMMAC_TXBUF_T_XDP_NDO,
 46	STMMAC_TXBUF_T_XSK_TX,
 47};
 48
 49struct stmmac_tx_info {
 50	dma_addr_t buf;
 51	bool map_as_page;
 52	unsigned len;
 53	bool last_segment;
 54	bool is_jumbo;
 55	enum stmmac_txbuf_type buf_type;
 56	struct xsk_tx_metadata_compl xsk_meta;
 57};
 58
 59#define STMMAC_TBS_AVAIL	BIT(0)
 60#define STMMAC_TBS_EN		BIT(1)
 61
 62/* Frequently used values are kept adjacent for cache effect */
 63struct stmmac_tx_queue {
 64	u32 tx_count_frames;
 65	int tbs;
 66	struct hrtimer txtimer;
 67	u32 queue_index;
 68	struct stmmac_priv *priv_data;
 69	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
 70	struct dma_edesc *dma_entx;
 71	struct dma_desc *dma_tx;
 72	union {
 73		struct sk_buff **tx_skbuff;
 74		struct xdp_frame **xdpf;
 75	};
 76	struct stmmac_tx_info *tx_skbuff_dma;
 77	struct xsk_buff_pool *xsk_pool;
 78	u32 xsk_frames_done;
 79	unsigned int cur_tx;
 80	unsigned int dirty_tx;
 81	dma_addr_t dma_tx_phy;
 82	dma_addr_t tx_tail_addr;
 83	u32 mss;
 84};
 85
 86struct stmmac_rx_buffer {
 87	union {
 88		struct {
 89			struct page *page;
 90			dma_addr_t addr;
 91			__u32 page_offset;
 92		};
 93		struct xdp_buff *xdp;
 94	};
 95	struct page *sec_page;
 96	dma_addr_t sec_addr;
 97};
 98
 99struct stmmac_xdp_buff {
100	struct xdp_buff xdp;
101	struct stmmac_priv *priv;
102	struct dma_desc *desc;
103	struct dma_desc *ndesc;
104};
105
106struct stmmac_metadata_request {
107	struct stmmac_priv *priv;
108	struct dma_desc *tx_desc;
109	bool *set_ic;
110	struct dma_edesc *edesc;
111	int tbs;
112};
113
114struct stmmac_xsk_tx_complete {
115	struct stmmac_priv *priv;
116	struct dma_desc *desc;
117};
118
119struct stmmac_rx_queue {
120	u32 rx_count_frames;
121	u32 queue_index;
122	struct xdp_rxq_info xdp_rxq;
123	struct xsk_buff_pool *xsk_pool;
124	struct page_pool *page_pool;
125	struct stmmac_rx_buffer *buf_pool;
126	struct stmmac_priv *priv_data;
127	struct dma_extended_desc *dma_erx;
128	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
129	unsigned int cur_rx;
130	unsigned int dirty_rx;
131	unsigned int buf_alloc_num;
132	unsigned int napi_skb_frag_size;
133	dma_addr_t dma_rx_phy;
134	u32 rx_tail_addr;
135	unsigned int state_saved;
136	struct {
137		struct sk_buff *skb;
138		unsigned int len;
139		unsigned int error;
140	} state;
141};
142
143struct stmmac_channel {
144	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
145	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
146	struct napi_struct rxtx_napi ____cacheline_aligned_in_smp;
147	struct stmmac_priv *priv_data;
148	spinlock_t lock;
149	u32 index;
150};
151
152struct stmmac_fpe_cfg {
153	struct ethtool_mmsv mmsv;
154	const struct stmmac_fpe_reg *reg;
155	u32 fpe_csr;	/* MAC_FPE_CTRL_STS reg cache */
156};
157
158struct stmmac_tc_entry {
159	bool in_use;
160	bool in_hw;
161	bool is_last;
162	bool is_frag;
163	void *frag_ptr;
164	unsigned int table_pos;
165	u32 handle;
166	u32 prio;
167	struct {
168		u32 match_data;
169		u32 match_en;
170		u8 af:1;
171		u8 rf:1;
172		u8 im:1;
173		u8 nc:1;
174		u8 res1:4;
175		u8 frame_offset;
176		u8 ok_index;
177		u8 dma_ch_no;
178		u32 res2;
179	} __packed val;
180};
181
182#define STMMAC_PPS_MAX		4
183struct stmmac_pps_cfg {
184	bool available;
185	struct timespec64 start;
186	struct timespec64 period;
187};
188
189struct stmmac_rss {
190	int enable;
191	u8 key[STMMAC_RSS_HASH_KEY_SIZE];
192	u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
193};
194
195#define STMMAC_FLOW_ACTION_DROP		BIT(0)
196struct stmmac_flow_entry {
197	unsigned long cookie;
198	unsigned long action;
199	u8 ip_proto;
200	int in_use;
201	int idx;
202	int is_l4;
203};
204
205/* Rx Frame Steering */
206enum stmmac_rfs_type {
207	STMMAC_RFS_T_VLAN,
208	STMMAC_RFS_T_LLDP,
209	STMMAC_RFS_T_1588,
210	STMMAC_RFS_T_MAX,
211};
212
213struct stmmac_rfs_entry {
214	unsigned long cookie;
215	u16 etype;
216	int in_use;
217	int type;
218	int tc;
219};
220
221struct stmmac_dma_conf {
222	unsigned int dma_buf_sz;
223
224	/* RX Queue */
225	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
226	unsigned int dma_rx_size;
227
228	/* TX Queue */
229	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
230	unsigned int dma_tx_size;
231};
232
233#define EST_GCL         1024
234struct stmmac_est {
235	int enable;
236	u32 btr_reserve[2];
237	u32 btr_offset[2];
238	u32 btr[2];
239	u32 ctr[2];
240	u32 ter;
241	u32 gcl_unaligned[EST_GCL];
242	u32 gcl[EST_GCL];
243	u32 gcl_size;
244	u32 max_sdu[MTL_MAX_TX_QUEUES];
245};
246
247struct stmmac_priv {
248	/* Frequently used values are kept adjacent for cache effect */
249	u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
250	u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
251	u32 rx_coal_frames[MTL_MAX_RX_QUEUES];
252
253	int hwts_tx_en;
254	bool tx_path_in_lpi_mode;
255	bool tso;
256	bool sph_active;
257	bool sph_capable;
258	u32 sarc_type;
259	u32 rx_riwt[MTL_MAX_RX_QUEUES];
260	int hwts_rx_en;
261	bool tsfupdt_coarse;
262
263	void __iomem *ioaddr;
264	struct net_device *dev;
265	struct device *device;
266	struct mac_device_info *hw;
267	int (*hwif_quirks)(struct stmmac_priv *priv);
268	struct mutex lock;
269
270	struct stmmac_dma_conf dma_conf;
271
272	/* Generic channel for NAPI */
273	struct stmmac_channel channel[STMMAC_CH_MAX];
274
275	unsigned int pause_time;
276	struct mii_bus *mii;
277
278	struct stmmac_pcs *integrated_pcs;
279
280	struct phylink_config phylink_config;
281	struct phylink *phylink;
282
283	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
284	struct stmmac_safety_stats sstats;
285	struct plat_stmmacenet_data *plat;
286	/* Protect est parameters */
287	struct mutex est_lock;
288	struct stmmac_est *est;
289	struct dma_features dma_cap;
290	struct stmmac_counters mmc;
291	int hw_cap_support;
292	int synopsys_id;
293	u32 msg_enable;
294	/* Our MAC Wake-on-Lan options */
295	int wolopts;
296	int wol_irq;
297	u32 gmii_address_bus_config;
298	struct timer_list eee_ctrl_timer;
299	u32 tx_lpi_timer;
300	bool tx_lpi_clk_stop;
301	bool eee_enabled;
302	bool eee_active;
303	bool eee_sw_timer_en;
304	unsigned int mode;
305	unsigned int chain_mode;
306	int extend_desc;
307	struct kernel_hwtstamp_config tstamp_config;
308	struct ptp_clock *ptp_clock;
309	struct ptp_clock_info ptp_clock_ops;
310	unsigned int default_addend;
311	u32 sub_second_inc;
312	u32 systime_flags;
313	u32 adv_ts;
314	int use_riwt;
315	int irq_wake;
316	rwlock_t ptp_lock;
317	/* Protects auxiliary snapshot registers from concurrent access. */
318	struct mutex aux_ts_lock;
319	wait_queue_head_t tstamp_busy_wait;
320
321	void __iomem *mmcaddr;
322	void __iomem *ptpaddr;
323	void __iomem *estaddr;
324	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
325	unsigned int num_double_vlans;
326	int sfty_irq;
327	int sfty_ce_irq;
328	int sfty_ue_irq;
329	int rx_irq[MTL_MAX_RX_QUEUES];
330	int tx_irq[MTL_MAX_TX_QUEUES];
331	/*irq name */
332	char int_name_mac[IFNAMSIZ + 9];
333	char int_name_wol[IFNAMSIZ + 9];
334	char int_name_lpi[IFNAMSIZ + 9];
335	char int_name_sfty[IFNAMSIZ + 10];
336	char int_name_sfty_ce[IFNAMSIZ + 10];
337	char int_name_sfty_ue[IFNAMSIZ + 10];
338	char int_name_rx_irq[MTL_MAX_RX_QUEUES][IFNAMSIZ + 14];
339	char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];
340
341#ifdef CONFIG_DEBUG_FS
342	struct dentry *dbgfs_dir;
343#endif
344
345	unsigned long state;
346	struct workqueue_struct *wq;
347	struct work_struct service_task;
348
349	/* Frame Preemption feature (FPE) */
350	struct stmmac_fpe_cfg fpe_cfg;
351
352	/* TC Handling */
353	unsigned int tc_entries_max;
354	unsigned int tc_off_max;
355	struct stmmac_tc_entry *tc_entries;
356	unsigned int flow_entries_max;
357	struct stmmac_flow_entry *flow_entries;
358	unsigned int rfs_entries_max[STMMAC_RFS_T_MAX];
359	unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX];
360	unsigned int rfs_entries_total;
361	struct stmmac_rfs_entry *rfs_entries;
362
363	/* Pulse Per Second output */
364	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
365
366	/* Receive Side Scaling */
367	struct stmmac_rss rss;
368
369	/* XDP BPF Program */
370	unsigned long *af_xdp_zc_qps;
371	struct bpf_prog *xdp_prog;
372
373	struct devlink *devlink;
374};
375
376enum stmmac_state {
377	STMMAC_DOWN,
378	STMMAC_RESET_REQUESTED,
379	STMMAC_RESETING,
380	STMMAC_SERVICE_SCHED,
381};
382
383extern const struct dev_pm_ops stmmac_simple_pm_ops;
384
385int stmmac_mdio_unregister(struct net_device *ndev);
386int stmmac_mdio_register(struct net_device *ndev);
387int stmmac_mdio_reset(struct mii_bus *mii);
388void stmmac_mdio_lock(struct stmmac_priv *priv);
389void stmmac_mdio_unlock(struct stmmac_priv *priv);
390int stmmac_pcs_setup(struct net_device *ndev);
391void stmmac_pcs_clean(struct net_device *ndev);
392void stmmac_set_ethtool_ops(struct net_device *netdev);
393
394void stmmac_ptp_register(struct stmmac_priv *priv);
395void stmmac_ptp_unregister(struct stmmac_priv *priv);
396int stmmac_xdp_open(struct net_device *dev);
397void stmmac_xdp_release(struct net_device *dev);
398int stmmac_get_phy_intf_sel(phy_interface_t interface);
399int stmmac_resume(struct device *dev);
400int stmmac_suspend(struct device *dev);
401void stmmac_dvr_remove(struct device *dev);
402int stmmac_dvr_probe(struct device *device,
403		     struct plat_stmmacenet_data *plat_dat,
404		     struct stmmac_resources *res);
405int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
406int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
407int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
408			   phy_interface_t interface, int speed);
409
410struct plat_stmmacenet_data *stmmac_plat_dat_alloc(struct device *dev);
411
412static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
413{
414	return !!priv->xdp_prog;
415}
416
417void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue);
418void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue);
419void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue);
420void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue);
421int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags);
422struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
423					   ktime_t current_time,
424					   u64 cycle_time);
425
426#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
427void stmmac_selftest_run(struct net_device *dev,
428			 struct ethtool_test *etest, u64 *buf);
429void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
430int stmmac_selftest_get_count(struct stmmac_priv *priv);
431#else
432static inline void stmmac_selftest_run(struct net_device *dev,
433				       struct ethtool_test *etest, u64 *buf)
434{
435	/* Not enabled */
436}
437static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
438					       u8 *data)
439{
440	/* Not enabled */
441}
442static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
443{
444	return -EOPNOTSUPP;
445}
446#endif /* CONFIG_STMMAC_SELFTESTS */
447
448#endif /* __STMMAC_H__ */