dwmac4_descs.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * This contains the functions to handle the descriptors for DesignWare databook
  4 * 4.xx.
  5 *
  6 * Copyright (C) 2015  STMicroelectronics Ltd
  7 *
  8 * Author: Alexandre Torgue <alexandre.torgue@st.com>
  9 */
 10
 11#include <linux/stmmac.h>
 12#include "common.h"
 13#include "dwmac4.h"
 14#include "dwmac4_descs.h"
 15
 16static int dwmac4_wrback_get_tx_status(struct stmmac_extra_stats *x,
 17				       struct dma_desc *p,
 18				       void __iomem *ioaddr)
 19{
 20	unsigned int tdes3;
 21	int ret = tx_done;
 22
 23	tdes3 = le32_to_cpu(p->des3);
 24
 25	/* Get tx owner first */
 26	if (unlikely(tdes3 & TDES3_OWN))
 27		return tx_dma_own;
 28
 29	/* Verify tx error by looking at the last segment. */
 30	if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
 31		return tx_not_ls;
 32
 33	if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
 34		ret = tx_err;
 35
 36		if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
 37			x->tx_jabber++;
 38		if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
 39			x->tx_frame_flushed++;
 40		if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
 41			x->tx_losscarrier++;
 42		}
 43		if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
 44			x->tx_carrier++;
 45		}
 46		if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
 47			     (tdes3 & TDES3_EXCESSIVE_COLLISION)))
 48			x->tx_collision +=
 49			    (tdes3 & TDES3_COLLISION_COUNT_MASK)
 50			    >> TDES3_COLLISION_COUNT_SHIFT;
 51
 52		if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
 53			x->tx_deferred++;
 54
 55		if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) {
 56			x->tx_underflow++;
 57			ret |= tx_err_bump_tc;
 58		}
 59
 60		if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
 61			x->tx_ip_header_error++;
 62
 63		if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
 64			x->tx_payload_error++;
 65	}
 66
 67	if (unlikely(tdes3 & TDES3_DEFERRED))
 68		x->tx_deferred++;
 69
 70	return ret;
 71}
 72
 73static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
 74				       struct dma_desc *p)
 75{
 76	unsigned int rdes1 = le32_to_cpu(p->des1);
 77	unsigned int rdes2 = le32_to_cpu(p->des2);
 78	unsigned int rdes3 = le32_to_cpu(p->des3);
 79	int message_type;
 80	int ret = good_frame;
 81
 82	if (unlikely(rdes3 & RDES3_OWN))
 83		return dma_own;
 84
 85	if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
 86		return discard_frame;
 87	if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
 88		return rx_not_ls;
 89
 90	if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
 91		if (unlikely(rdes3 & RDES3_GIANT_PACKET))
 92			x->rx_length++;
 93		if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
 94			x->rx_gmac_overflow++;
 95
 96		if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
 97			x->rx_watchdog++;
 98
 99		if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
100			x->rx_mii++;
101
102		if (unlikely(rdes3 & RDES3_CRC_ERROR))
103			x->rx_crc_errors++;
104
105		if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
106			x->dribbling_bit++;
107
108		ret = discard_frame;
109	}
110
111	message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
112
113	if (rdes1 & RDES1_IP_HDR_ERROR) {
114		x->ip_hdr_err++;
115		ret |= csum_none;
116	}
117	if (rdes1 & RDES1_IP_CSUM_BYPASSED)
118		x->ip_csum_bypassed++;
119	if (rdes1 & RDES1_IPV4_HEADER)
120		x->ipv4_pkt_rcvd++;
121	if (rdes1 & RDES1_IPV6_HEADER)
122		x->ipv6_pkt_rcvd++;
123	if (rdes1 & RDES1_IP_PAYLOAD_ERROR) {
124		x->ip_payload_err++;
125		ret |= csum_none;
126	}
127
128	if (message_type == RDES_EXT_NO_PTP)
129		x->no_ptp_rx_msg_type_ext++;
130	else if (message_type == RDES_EXT_SYNC)
131		x->ptp_rx_msg_type_sync++;
132	else if (message_type == RDES_EXT_FOLLOW_UP)
133		x->ptp_rx_msg_type_follow_up++;
134	else if (message_type == RDES_EXT_DELAY_REQ)
135		x->ptp_rx_msg_type_delay_req++;
136	else if (message_type == RDES_EXT_DELAY_RESP)
137		x->ptp_rx_msg_type_delay_resp++;
138	else if (message_type == RDES_EXT_PDELAY_REQ)
139		x->ptp_rx_msg_type_pdelay_req++;
140	else if (message_type == RDES_EXT_PDELAY_RESP)
141		x->ptp_rx_msg_type_pdelay_resp++;
142	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
143		x->ptp_rx_msg_type_pdelay_follow_up++;
144	else if (message_type == RDES_PTP_ANNOUNCE)
145		x->ptp_rx_msg_type_announce++;
146	else if (message_type == RDES_PTP_MANAGEMENT)
147		x->ptp_rx_msg_type_management++;
148	else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
149		x->ptp_rx_msg_pkt_reserved_type++;
150
151	if (rdes1 & RDES1_PTP_PACKET_TYPE)
152		x->ptp_frame_type++;
153	if (rdes1 & RDES1_PTP_VER)
154		x->ptp_ver++;
155	if (rdes1 & RDES1_TIMESTAMP_DROPPED)
156		x->timestamp_dropped++;
157
158	if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
159		x->sa_rx_filter_fail++;
160		ret = discard_frame;
161	}
162	if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
163		x->da_rx_filter_fail++;
164		ret = discard_frame;
165	}
166
167	if (rdes2 & RDES2_L3_FILTER_MATCH)
168		x->l3_filter_match++;
169	if (rdes2 & RDES2_L4_FILTER_MATCH)
170		x->l4_filter_match++;
171	if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
172	    >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
173		x->l3_l4_filter_no_match++;
174
175	return ret;
176}
177
178static int dwmac4_rd_get_tx_len(struct dma_desc *p)
179{
180	return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
181}
182
183static int dwmac4_get_tx_owner(struct dma_desc *p)
184{
185	return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
186}
187
188static void dwmac4_set_tx_owner(struct dma_desc *p)
189{
190	p->des3 |= cpu_to_le32(TDES3_OWN);
191}
192
193static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
194{
195	u32 flags = (RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
196
197	if (!disable_rx_ic)
198		flags |= RDES3_INT_ON_COMPLETION_EN;
199
200	p->des3 |= cpu_to_le32(flags);
201}
202
203static int dwmac4_get_tx_ls(struct dma_desc *p)
204{
205	return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
206		>> TDES3_LAST_DESCRIPTOR_SHIFT;
207}
208
209static u16 dwmac4_wrback_get_rx_vlan_tci(struct dma_desc *p)
210{
211	return (le32_to_cpu(p->des0) & RDES0_VLAN_TAG_MASK);
212}
213
214static bool dwmac4_wrback_get_rx_vlan_valid(struct dma_desc *p)
215{
216	return ((le32_to_cpu(p->des3) & RDES3_LAST_DESCRIPTOR) &&
217		(le32_to_cpu(p->des3) & RDES3_RDES0_VALID));
218}
219
220static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
221{
222	return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
223}
224
225static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
226{
227	p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
228}
229
230static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
231{
232	/* Context type from W/B descriptor must be zero */
233	if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
234		return 0;
235
236	/* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
237	if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
238		return 1;
239
240	return 0;
241}
242
243static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
244{
245	struct dma_desc *p = (struct dma_desc *)desc;
246	u64 ns;
247
248	ns = le32_to_cpu(p->des0);
249	/* convert high/sec time stamp value to nanosecond */
250	ns += le32_to_cpu(p->des1) * 1000000000ULL;
251
252	*ts = ns;
253}
254
255static int dwmac4_rx_check_timestamp(void *desc)
256{
257	struct dma_desc *p = (struct dma_desc *)desc;
258	unsigned int rdes0 = le32_to_cpu(p->des0);
259	unsigned int rdes1 = le32_to_cpu(p->des1);
260	unsigned int rdes3 = le32_to_cpu(p->des3);
261	u32 own, ctxt;
262	int ret = 1;
263
264	own = rdes3 & RDES3_OWN;
265	ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
266		>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
267
268	if (likely(!own && ctxt)) {
269		if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
270			/* Corrupted value */
271			ret = -EINVAL;
272		else
273			/* A valid Timestamp is ready to be read */
274			ret = 0;
275	}
276
277	/* Timestamp not ready */
278	return ret;
279}
280
281static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
282						 u32 ats)
283{
284	struct dma_desc *p = (struct dma_desc *)desc;
285	int ret = -EINVAL;
286
287	/* Get the status from normal w/b descriptor */
288	if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
289		if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
290			int i = 0;
291
292			/* Check if timestamp is OK from context descriptor */
293			do {
294				ret = dwmac4_rx_check_timestamp(next_desc);
295				if (ret < 0)
296					goto exit;
297				i++;
298
299			} while ((ret == 1) && (i < 10));
300
301			if (i == 10)
302				ret = -EBUSY;
303		}
304	}
305exit:
306	if (likely(ret == 0))
307		return 1;
308
309	return 0;
310}
311
312static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
313				   int mode, int end, int bfsize)
314{
315	dwmac4_set_rx_owner(p, disable_rx_ic);
316}
317
318static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
319{
320	p->des0 = 0;
321	p->des1 = 0;
322	p->des2 = 0;
323	p->des3 = 0;
324}
325
326static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
327				      bool csum_flag, int mode, bool tx_own,
328				      bool ls, unsigned int tot_pkt_len)
329{
330	unsigned int tdes3 = le32_to_cpu(p->des3);
331
332	p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
333
334	tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
335	if (is_fs)
336		tdes3 |= TDES3_FIRST_DESCRIPTOR;
337	else
338		tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
339
340	if (likely(csum_flag))
341		tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
342	else
343		tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
344
345	if (ls)
346		tdes3 |= TDES3_LAST_DESCRIPTOR;
347	else
348		tdes3 &= ~TDES3_LAST_DESCRIPTOR;
349
350	/* Finally set the OWN bit. Later the DMA will start! */
351	if (tx_own)
352		tdes3 |= TDES3_OWN;
353
354	if (is_fs && tx_own)
355		/* When the own bit, for the first frame, has to be set, all
356		 * descriptors for the same frame has to be set before, to
357		 * avoid race condition.
358		 */
359		dma_wmb();
360
361	p->des3 = cpu_to_le32(tdes3);
362}
363
364static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
365					  int len1, int len2, bool tx_own,
366					  bool ls, unsigned int tcphdrlen,
367					  unsigned int tcppayloadlen)
368{
369	unsigned int tdes3 = le32_to_cpu(p->des3);
370
371	if (len1)
372		p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
373
374	if (len2)
375		p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
376			    & TDES2_BUFFER2_SIZE_MASK);
377
378	if (is_fs) {
379		tdes3 |= TDES3_FIRST_DESCRIPTOR |
380			 TDES3_TCP_SEGMENTATION_ENABLE |
381			 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
382			  TDES3_SLOT_NUMBER_MASK) |
383			 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
384	} else {
385		tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
386	}
387
388	if (ls)
389		tdes3 |= TDES3_LAST_DESCRIPTOR;
390	else
391		tdes3 &= ~TDES3_LAST_DESCRIPTOR;
392
393	/* Finally set the OWN bit. Later the DMA will start! */
394	if (tx_own)
395		tdes3 |= TDES3_OWN;
396
397	if (is_fs && tx_own)
398		/* When the own bit, for the first frame, has to be set, all
399		 * descriptors for the same frame has to be set before, to
400		 * avoid race condition.
401		 */
402		dma_wmb();
403
404	p->des3 = cpu_to_le32(tdes3);
405}
406
407static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
408{
409	p->des0 = 0;
410	p->des1 = 0;
411	p->des2 = 0;
412	p->des3 = 0;
413}
414
415static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
416{
417	p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
418}
419
420static void dwmac4_display_ring(void *head, unsigned int size, bool rx,
421				dma_addr_t dma_rx_phy, unsigned int desc_size)
422{
423	dma_addr_t dma_addr;
424	int i;
425
426	pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
427
428	if (desc_size == sizeof(struct dma_desc)) {
429		struct dma_desc *p = (struct dma_desc *)head;
430
431		for (i = 0; i < size; i++) {
432			dma_addr = dma_rx_phy + i * sizeof(*p);
433			pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
434				i, &dma_addr,
435				le32_to_cpu(p->des0), le32_to_cpu(p->des1),
436				le32_to_cpu(p->des2), le32_to_cpu(p->des3));
437			p++;
438		}
439	} else if (desc_size == sizeof(struct dma_extended_desc)) {
440		struct dma_extended_desc *extp = (struct dma_extended_desc *)head;
441
442		for (i = 0; i < size; i++) {
443			dma_addr = dma_rx_phy + i * sizeof(*extp);
444			pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
445				i, &dma_addr,
446				le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),
447				le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),
448				le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),
449				le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));
450			extp++;
451		}
452	} else if (desc_size == sizeof(struct dma_edesc)) {
453		struct dma_edesc *ep = (struct dma_edesc *)head;
454
455		for (i = 0; i < size; i++) {
456			dma_addr = dma_rx_phy + i * sizeof(*ep);
457			pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
458				i, &dma_addr,
459				le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),
460				le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),
461				le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),
462				le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));
463			ep++;
464		}
465	} else {
466		pr_err("unsupported descriptor!");
467	}
468}
469
470static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
471{
472	p->des0 = 0;
473	p->des1 = 0;
474	p->des2 = cpu_to_le32(mss);
475	p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
476}
477
478static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
479{
480	p->des0 = cpu_to_le32(lower_32_bits(addr));
481	p->des1 = cpu_to_le32(upper_32_bits(addr));
482}
483
484static void dwmac4_clear(struct dma_desc *p)
485{
486	p->des0 = 0;
487	p->des1 = 0;
488	p->des2 = 0;
489	p->des3 = 0;
490}
491
492static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
493{
494	sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
495
496	p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
497}
498
499static int set_16kib_bfsize(int mtu)
500{
501	int ret = 0;
502
503	if (unlikely(mtu >= BUF_SIZE_8KiB))
504		ret = BUF_SIZE_16KiB;
505	return ret;
506}
507
508static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
509				u32 inner_type)
510{
511	p->des0 = 0;
512	p->des1 = 0;
513	p->des2 = 0;
514	p->des3 = 0;
515
516	/* Inner VLAN */
517	if (inner_type) {
518		u32 des = inner_tag << TDES2_IVT_SHIFT;
519
520		des &= TDES2_IVT_MASK;
521		p->des2 = cpu_to_le32(des);
522
523		des = inner_type << TDES3_IVTIR_SHIFT;
524		des &= TDES3_IVTIR_MASK;
525		p->des3 = cpu_to_le32(des | TDES3_IVLTV);
526	}
527
528	/* Outer VLAN */
529	p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
530	p->des3 |= cpu_to_le32(TDES3_VLTV);
531
532	p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
533}
534
535static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
536{
537	type <<= TDES2_VLAN_TAG_SHIFT;
538	p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
539}
540
541static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
542{
543	*len = le32_to_cpu(p->des2) & RDES2_HL;
544}
545
546static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)
547{
548	p->des2 = cpu_to_le32(lower_32_bits(addr));
549	p->des3 = cpu_to_le32(upper_32_bits(addr));
550
551	if (buf2_valid)
552		p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);
553	else
554		p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);
555}
556
557static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
558{
559	p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
560	p->des5 = cpu_to_le32(nsec & TDES5_LT);
561	p->des6 = 0;
562	p->des7 = 0;
563}
564
565const struct stmmac_desc_ops dwmac4_desc_ops = {
566	.tx_status = dwmac4_wrback_get_tx_status,
567	.rx_status = dwmac4_wrback_get_rx_status,
568	.get_tx_len = dwmac4_rd_get_tx_len,
569	.get_tx_owner = dwmac4_get_tx_owner,
570	.set_tx_owner = dwmac4_set_tx_owner,
571	.set_rx_owner = dwmac4_set_rx_owner,
572	.get_tx_ls = dwmac4_get_tx_ls,
573	.get_rx_vlan_tci = dwmac4_wrback_get_rx_vlan_tci,
574	.get_rx_vlan_valid = dwmac4_wrback_get_rx_vlan_valid,
575	.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
576	.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
577	.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
578	.get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
579	.get_timestamp = dwmac4_get_timestamp,
580	.set_tx_ic = dwmac4_rd_set_tx_ic,
581	.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
582	.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
583	.release_tx_desc = dwmac4_release_tx_desc,
584	.init_rx_desc = dwmac4_rd_init_rx_desc,
585	.init_tx_desc = dwmac4_rd_init_tx_desc,
586	.display_ring = dwmac4_display_ring,
587	.set_mss = dwmac4_set_mss_ctxt,
588	.set_addr = dwmac4_set_addr,
589	.clear = dwmac4_clear,
590	.set_sarc = dwmac4_set_sarc,
591	.set_vlan_tag = dwmac4_set_vlan_tag,
592	.set_vlan = dwmac4_set_vlan,
593	.get_rx_header_len = dwmac4_get_rx_header_len,
594	.set_sec_addr = dwmac4_set_sec_addr,
595	.set_tbs = dwmac4_set_tbs,
596};
597
598const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
599	.set_16kib_bfsize = set_16kib_bfsize,
600};