dwmac4.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * DWMAC4 Header file.
  4 *
  5 * Copyright (C) 2015  STMicroelectronics Ltd
  6 *
  7 * Author: Alexandre Torgue <alexandre.torgue@st.com>
  8 */
  9
 10#ifndef __DWMAC4_H__
 11#define __DWMAC4_H__
 12
 13#include "common.h"
 14
 15/*  MAC registers */
 16#define GMAC_CONFIG			0x00000000
 17#define GMAC_EXT_CONFIG			0x00000004
 18#define GMAC_PACKET_FILTER		0x00000008
 19#define GMAC_HASH_TAB(x)		(0x10 + (x) * 4)
 20#define GMAC_RX_FLOW_CTRL		0x00000090
 21#define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
 22#define GMAC_TXQ_PRTY_MAP0		0x98
 23#define GMAC_TXQ_PRTY_MAP1		0x9C
 24#define GMAC_RXQ_CTRL0			0x000000a0
 25#define GMAC_RXQ_CTRL1			0x000000a4
 26#define GMAC_RXQ_CTRL2			0x000000a8
 27#define GMAC_RXQ_CTRL3			0x000000ac
 28#define GMAC_INT_STATUS			0x000000b0
 29#define GMAC_INT_EN			0x000000b4
 30#define GMAC_PCS_BASE			0x000000e0
 31#define GMAC_PHYIF_CONTROL_STATUS	0x000000f8
 32#define GMAC_PMT			0x000000c0
 33#define GMAC_DEBUG			0x00000114
 34#define GMAC_HW_FEATURE0		0x0000011c
 35#define GMAC_HW_FEATURE1		0x00000120
 36#define GMAC_HW_FEATURE2		0x00000124
 37#define GMAC_HW_FEATURE3		0x00000128
 38#define GMAC_MDIO_ADDR			0x00000200
 39#define GMAC_MDIO_DATA			0x00000204
 40#define GMAC_GPIO_STATUS		0x0000020C
 41#define GMAC_ARP_ADDR			0x00000210
 42#define GMAC_EXT_CFG1			0x00000238
 43#define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
 44#define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
 45#define GMAC_L3L4_CTRL(reg)		(0x900 + (reg) * 0x30)
 46#define GMAC_L4_ADDR(reg)		(0x904 + (reg) * 0x30)
 47#define GMAC_L3_ADDR0(reg)		(0x910 + (reg) * 0x30)
 48#define GMAC_L3_ADDR1(reg)		(0x914 + (reg) * 0x30)
 49#define GMAC_TIMESTAMP_STATUS		0x00000b20
 50
 51/* RX Queues Routing */
 52#define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
 53#define GMAC_RXQCTRL_AVCPQ_SHIFT	0
 54#define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
 55#define GMAC_RXQCTRL_PTPQ_SHIFT		4
 56#define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
 57#define GMAC_RXQCTRL_DCBCPQ_SHIFT	8
 58#define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
 59#define GMAC_RXQCTRL_UPQ_SHIFT		12
 60#define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
 61#define GMAC_RXQCTRL_MCBCQ_SHIFT	16
 62#define GMAC_RXQCTRL_MCBCQEN		BIT(20)
 63#define GMAC_RXQCTRL_MCBCQEN_SHIFT	20
 64#define GMAC_RXQCTRL_TACPQE		BIT(21)
 65#define GMAC_RXQCTRL_TACPQE_SHIFT	21
 66#define GMAC_RXQCTRL_FPRQ		GENMASK(26, 24)
 67
 68/* MAC Packet Filtering */
 69#define GMAC_PACKET_FILTER_PR		BIT(0)
 70#define GMAC_PACKET_FILTER_HMC		BIT(2)
 71#define GMAC_PACKET_FILTER_PM		BIT(4)
 72#define GMAC_PACKET_FILTER_PCF		BIT(7)
 73#define GMAC_PACKET_FILTER_HPF		BIT(10)
 74#define GMAC_PACKET_FILTER_VTFE		BIT(16)
 75#define GMAC_PACKET_FILTER_IPFE		BIT(20)
 76#define GMAC_PACKET_FILTER_RA		BIT(31)
 77
 78#define GMAC_MAX_PERFECT_ADDRESSES	128
 79
 80/* MAC RX Queue Enable */
 81#define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
 82#define GMAC_RX_AV_QUEUE_ENABLE(queue)	BIT((queue) * 2)
 83#define GMAC_RX_DCB_QUEUE_ENABLE(queue)	BIT(((queue) * 2) + 1)
 84
 85/* MAC Flow Control RX */
 86#define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
 87
 88/* RX Queues Priorities */
 89#define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
 90#define GMAC_RXQCTRL_PSRQX_SHIFT(x)	((x) * 8)
 91
 92/* TX Queues Priorities */
 93#define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
 94#define GMAC_TXQCTRL_PSTQX_SHIFT(x)	((x) * 8)
 95
 96/* MAC Flow Control TX */
 97#define GMAC_TX_FLOW_CTRL_TFE		BIT(1)
 98#define GMAC_TX_FLOW_CTRL_PT_SHIFT	16
 99
100/*  MAC Interrupt bitmap*/
101#define GMAC_INT_RGSMIIS		BIT(0)
102#define GMAC_INT_PCS_LINK		BIT(1)
103#define GMAC_INT_PCS_ANE		BIT(2)
104#define GMAC_INT_PCS_PHYIS		BIT(3)
105#define GMAC_INT_PMT_EN			BIT(4)
106#define GMAC_INT_LPI_EN			BIT(5)
107#define GMAC_INT_TSIE			BIT(12)
108
109#define	GMAC_INT_DEFAULT_ENABLE	(GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \
110				 GMAC_INT_TSIE)
111
112enum dwmac4_irq_status {
113	time_stamp_irq = 0x00001000,
114	mmc_rx_csum_offload_irq = 0x00000800,
115	mmc_tx_irq = 0x00000400,
116	mmc_rx_irq = 0x00000200,
117	mmc_irq = 0x00000100,
118	lpi_irq = 0x00000020,
119	pmt_irq = 0x00000010,
120};
121
122/* MAC PMT bitmap */
123enum power_event {
124	pointer_reset =	0x80000000,
125	global_unicast = 0x00000200,
126	wake_up_rx_frame = 0x00000040,
127	magic_frame = 0x00000020,
128	wake_up_frame_en = 0x00000004,
129	magic_pkt_en = 0x00000002,
130	power_down = 0x00000001,
131};
132
133/* Energy Efficient Ethernet (EEE) for GMAC4
134 *
135 * LPI status, timer and control register offset
136 * For LPI control and status bit definitions, see common.h.
137 */
138#define GMAC4_LPI_CTRL_STATUS	0xd0
139#define GMAC4_LPI_TIMER_CTRL	0xd4
140#define GMAC4_LPI_ENTRY_TIMER	0xd8
141#define GMAC4_MAC_ONEUS_TIC_COUNTER	0xdc
142
143/* MAC Debug bitmap */
144#define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
145#define GMAC_DEBUG_TFCSTS_SHIFT		17
146#define GMAC_DEBUG_TFCSTS_IDLE		0
147#define GMAC_DEBUG_TFCSTS_WAIT		1
148#define GMAC_DEBUG_TFCSTS_GEN_PAUSE	2
149#define GMAC_DEBUG_TFCSTS_XFER		3
150#define GMAC_DEBUG_TPESTS		BIT(16)
151#define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
152#define GMAC_DEBUG_RFCFCSTS_SHIFT	1
153#define GMAC_DEBUG_RPESTS		BIT(0)
154
155/* MAC config */
156#define GMAC_CONFIG_ARPEN		BIT(31)
157#define GMAC_CONFIG_SARC		GENMASK(30, 28)
158#define GMAC_CONFIG_SARC_SHIFT		28
159#define GMAC_CONFIG_IPC			BIT(27)
160#define GMAC_CONFIG_IPG			GENMASK(26, 24)
161#define GMAC_CONFIG_IPG_SHIFT		24
162#define GMAC_CONFIG_2K			BIT(22)
163#define GMAC_CONFIG_ACS			BIT(20)
164#define GMAC_CONFIG_BE			BIT(18)
165#define GMAC_CONFIG_JD			BIT(17)
166#define GMAC_CONFIG_JE			BIT(16)
167#define GMAC_CONFIG_PS			BIT(15)
168#define GMAC_CONFIG_FES			BIT(14)
169#define GMAC_CONFIG_FES_SHIFT		14
170#define GMAC_CONFIG_DM			BIT(13)
171#define GMAC_CONFIG_LM			BIT(12)
172#define GMAC_CONFIG_DCRS		BIT(9)
173#define GMAC_CONFIG_TE			BIT(1)
174#define GMAC_CONFIG_RE			BIT(0)
175
176/* MAC extended config */
177#define GMAC_CONFIG_EIPG		GENMASK(29, 25)
178#define GMAC_CONFIG_EIPG_SHIFT		25
179#define GMAC_CONFIG_EIPG_EN		BIT(24)
180#define GMAC_CONFIG_HDSMS		GENMASK(22, 20)
181#define GMAC_CONFIG_HDSMS_SHIFT		20
182#define GMAC_CONFIG_HDSMS_256		(0x2 << GMAC_CONFIG_HDSMS_SHIFT)
183
184/* MAC HW features0 bitmap */
185#define GMAC_HW_FEAT_SAVLANINS		BIT(27)
186#define GMAC_HW_FEAT_ADDMAC		BIT(18)
187#define GMAC_HW_FEAT_RXCOESEL		BIT(16)
188#define GMAC_HW_FEAT_TXCOSEL		BIT(14)
189#define GMAC_HW_FEAT_EEESEL		BIT(13)
190#define GMAC_HW_FEAT_TSSEL		BIT(12)
191#define GMAC_HW_FEAT_ARPOFFSEL		BIT(9)
192#define GMAC_HW_FEAT_MMCSEL		BIT(8)
193#define GMAC_HW_FEAT_MGKSEL		BIT(7)
194#define GMAC_HW_FEAT_RWKSEL		BIT(6)
195#define GMAC_HW_FEAT_SMASEL		BIT(5)
196#define GMAC_HW_FEAT_VLHASH		BIT(4)
197#define GMAC_HW_FEAT_PCSSEL		BIT(3)
198#define GMAC_HW_FEAT_HDSEL		BIT(2)
199#define GMAC_HW_FEAT_GMIISEL		BIT(1)
200#define GMAC_HW_FEAT_MIISEL		BIT(0)
201
202/* MAC HW features1 bitmap */
203#define GMAC_HW_FEAT_L3L4FNUM		GENMASK(30, 27)
204#define GMAC_HW_HASH_TB_SZ		GENMASK(25, 24)
205#define GMAC_HW_FEAT_AVSEL		BIT(20)
206#define GMAC_HW_TSOEN			BIT(18)
207#define GMAC_HW_FEAT_SPHEN		BIT(17)
208#define GMAC_HW_ADDR64			GENMASK(15, 14)
209#define GMAC_HW_TXFIFOSIZE		GENMASK(10, 6)
210#define GMAC_HW_RXFIFOSIZE		GENMASK(4, 0)
211
212/* MAC HW features2 bitmap */
213#define GMAC_HW_FEAT_AUXSNAPNUM		GENMASK(30, 28)
214#define GMAC_HW_FEAT_PPSOUTNUM		GENMASK(26, 24)
215#define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
216#define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
217#define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
218#define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
219
220/* MAC HW features3 bitmap */
221#define GMAC_HW_FEAT_ASP		GENMASK(29, 28)
222#define GMAC_HW_FEAT_TBSSEL		BIT(27)
223#define GMAC_HW_FEAT_FPESEL		BIT(26)
224#define GMAC_HW_FEAT_ESTWID		GENMASK(21, 20)
225#define GMAC_HW_FEAT_ESTDEP		GENMASK(19, 17)
226#define GMAC_HW_FEAT_ESTSEL		BIT(16)
227#define GMAC_HW_FEAT_FRPES		GENMASK(14, 13)
228#define GMAC_HW_FEAT_FRPBS		GENMASK(12, 11)
229#define GMAC_HW_FEAT_FRPSEL		BIT(10)
230#define GMAC_HW_FEAT_DVLAN		BIT(5)
231#define GMAC_HW_FEAT_NRVF		GENMASK(2, 0)
232
233/* MAC extended config 1 */
234#define GMAC_CONFIG1_SAVE_EN		BIT(24)
235#define GMAC_CONFIG1_SPLM(v)		FIELD_PREP(GENMASK(9, 8), v)
236
237/* GMAC GPIO Status reg */
238#define GMAC_GPO0			BIT(16)
239#define GMAC_GPO1			BIT(17)
240#define GMAC_GPO2			BIT(18)
241#define GMAC_GPO3			BIT(19)
242
243/* MAC HW ADDR regs */
244#define GMAC_HI_DCS			GENMASK(18, 16)
245#define GMAC_HI_DCS_SHIFT		16
246#define GMAC_HI_REG_AE			BIT(31)
247
248/* L3/L4 Filters regs */
249#define GMAC_L4DPIM0			BIT(21)
250#define GMAC_L4DPM0			BIT(20)
251#define GMAC_L4SPIM0			BIT(19)
252#define GMAC_L4SPM0			BIT(18)
253#define GMAC_L4PEN0			BIT(16)
254#define GMAC_L3DAIM0			BIT(5)
255#define GMAC_L3DAM0			BIT(4)
256#define GMAC_L3SAIM0			BIT(3)
257#define GMAC_L3SAM0			BIT(2)
258#define GMAC_L3PEN0			BIT(0)
259#define GMAC_L4DP0			GENMASK(31, 16)
260#define GMAC_L4DP0_SHIFT		16
261#define GMAC_L4SP0			GENMASK(15, 0)
262
263/* MAC Timestamp Status */
264#define GMAC_TIMESTAMP_AUXTSTRIG	BIT(2)
265#define GMAC_TIMESTAMP_ATSNS_MASK	GENMASK(29, 25)
266#define GMAC_TIMESTAMP_ATSNS_SHIFT	25
267
268/*  MTL registers */
269#define MTL_OPERATION_MODE		0x00000c00
270#define MTL_FRPE			BIT(15)
271#define MTL_OPERATION_SCHALG_MASK	GENMASK(6, 5)
272#define MTL_OPERATION_SCHALG_WRR	(0x0 << 5)
273#define MTL_OPERATION_SCHALG_WFQ	(0x1 << 5)
274#define MTL_OPERATION_SCHALG_DWRR	(0x2 << 5)
275#define MTL_OPERATION_SCHALG_SP		(0x3 << 5)
276#define MTL_OPERATION_RAA		BIT(2)
277#define MTL_OPERATION_RAA_SP		(0x0 << 2)
278#define MTL_OPERATION_RAA_WSP		(0x1 << 2)
279
280#define MTL_INT_STATUS			0x00000c20
281#define MTL_INT_QX(x)			BIT(x)
282
283#define MTL_RXQ_DMA_MAP0		0x00000c30 /* queue 0 to 3 */
284#define MTL_RXQ_DMA_MAP1		0x00000c34 /* queue 4 to 7 */
285#define MTL_RXQ_DMA_QXMDMACH_MASK(x)	(0xf << 8 * (x))
286#define MTL_RXQ_DMA_QXMDMACH(chan, q)	((chan) << (8 * (q)))
287
288#define MTL_CHAN_BASE_ADDR		0x00000d00
289#define MTL_CHAN_BASE_OFFSET		0x40
290
291static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs,
292				      const u32 x)
293{
294	u32 addr;
295
296	if (addrs)
297		addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset);
298	else
299		addr = MTL_CHAN_BASE_ADDR + (x * MTL_CHAN_BASE_OFFSET);
300
301	return addr;
302}
303
304#define MTL_CHAN_TX_OP_MODE(addrs, x)	mtl_chanx_base_addr(addrs, x)
305#define MTL_CHAN_TX_DEBUG(addrs, x)	(mtl_chanx_base_addr(addrs, x) + 0x8)
306#define MTL_CHAN_INT_CTRL(addrs, x)	(mtl_chanx_base_addr(addrs, x) + 0x2c)
307#define MTL_CHAN_RX_OP_MODE(addrs, x)	(mtl_chanx_base_addr(addrs, x) + 0x30)
308#define MTL_CHAN_RX_DEBUG(addrs, x)	(mtl_chanx_base_addr(addrs, x) + 0x38)
309
310#define MTL_OP_MODE_RSF			BIT(5)
311#define MTL_OP_MODE_TXQEN_MASK		GENMASK(3, 2)
312#define MTL_OP_MODE_TXQEN_AV		BIT(2)
313#define MTL_OP_MODE_TXQEN		BIT(3)
314#define MTL_OP_MODE_TSF			BIT(1)
315
316#define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
317#define MTL_OP_MODE_TQS_SHIFT		16
318
319#define MTL_OP_MODE_TTC_MASK		0x70
320#define MTL_OP_MODE_TTC_SHIFT		4
321
322#define MTL_OP_MODE_TTC_32		0
323#define MTL_OP_MODE_TTC_64		(1 << MTL_OP_MODE_TTC_SHIFT)
324#define MTL_OP_MODE_TTC_96		(2 << MTL_OP_MODE_TTC_SHIFT)
325#define MTL_OP_MODE_TTC_128		(3 << MTL_OP_MODE_TTC_SHIFT)
326#define MTL_OP_MODE_TTC_192		(4 << MTL_OP_MODE_TTC_SHIFT)
327#define MTL_OP_MODE_TTC_256		(5 << MTL_OP_MODE_TTC_SHIFT)
328#define MTL_OP_MODE_TTC_384		(6 << MTL_OP_MODE_TTC_SHIFT)
329#define MTL_OP_MODE_TTC_512		(7 << MTL_OP_MODE_TTC_SHIFT)
330
331#define MTL_OP_MODE_RQS_MASK		GENMASK(29, 20)
332#define MTL_OP_MODE_RQS_SHIFT		20
333
334#define MTL_OP_MODE_RFD_MASK		GENMASK(19, 14)
335#define MTL_OP_MODE_RFD_SHIFT		14
336
337#define MTL_OP_MODE_RFA_MASK		GENMASK(13, 8)
338#define MTL_OP_MODE_RFA_SHIFT		8
339
340#define MTL_OP_MODE_EHFC		BIT(7)
341#define MTL_OP_MODE_DIS_TCP_EF		BIT(6)
342
343#define MTL_OP_MODE_RTC_MASK		GENMASK(1, 0)
344#define MTL_OP_MODE_RTC_SHIFT		0
345
346#define MTL_OP_MODE_RTC_32		(1 << MTL_OP_MODE_RTC_SHIFT)
347#define MTL_OP_MODE_RTC_64		0
348#define MTL_OP_MODE_RTC_96		(2 << MTL_OP_MODE_RTC_SHIFT)
349#define MTL_OP_MODE_RTC_128		(3 << MTL_OP_MODE_RTC_SHIFT)
350
351/* MTL ETS Control register */
352#define MTL_ETS_CTRL_BASE_ADDR		0x00000d10
353#define MTL_ETS_CTRL_BASE_OFFSET	0x40
354
355static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs,
356					  const u32 x)
357{
358	u32 addr;
359
360	if (addrs)
361		addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset);
362	else
363		addr = MTL_ETS_CTRL_BASE_ADDR + (x * MTL_ETS_CTRL_BASE_OFFSET);
364
365	return addr;
366}
367
368#define MTL_ETS_CTRL_CC			BIT(3)
369#define MTL_ETS_CTRL_AVALG		BIT(2)
370
371/* MTL Queue Quantum Weight */
372#define MTL_TXQ_WEIGHT_BASE_ADDR	0x00000d18
373#define MTL_TXQ_WEIGHT_BASE_OFFSET	0x40
374
375static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs,
376					    const u32 x)
377{
378	u32 addr;
379
380	if (addrs)
381		addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset);
382	else
383		addr = MTL_TXQ_WEIGHT_BASE_ADDR + (x * MTL_TXQ_WEIGHT_BASE_OFFSET);
384
385	return addr;
386}
387
388#define MTL_TXQ_WEIGHT_ISCQW_MASK	GENMASK(20, 0)
389
390/* MTL sendSlopeCredit register */
391#define MTL_SEND_SLP_CRED_BASE_ADDR	0x00000d1c
392#define MTL_SEND_SLP_CRED_OFFSET	0x40
393
394static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs,
395					       const u32 x)
396{
397	u32 addr;
398
399	if (addrs)
400		addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset);
401	else
402		addr = MTL_SEND_SLP_CRED_BASE_ADDR + (x * MTL_SEND_SLP_CRED_OFFSET);
403
404	return addr;
405}
406
407#define MTL_SEND_SLP_CRED_SSC_MASK	GENMASK(13, 0)
408
409/* MTL hiCredit register */
410#define MTL_HIGH_CRED_BASE_ADDR		0x00000d20
411#define MTL_HIGH_CRED_OFFSET		0x40
412
413static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs,
414					   const u32 x)
415{
416	u32 addr;
417
418	if (addrs)
419		addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset);
420	else
421		addr = MTL_HIGH_CRED_BASE_ADDR + (x * MTL_HIGH_CRED_OFFSET);
422
423	return addr;
424}
425
426#define MTL_HIGH_CRED_HC_MASK		GENMASK(28, 0)
427
428/* MTL loCredit register */
429#define MTL_LOW_CRED_BASE_ADDR		0x00000d24
430#define MTL_LOW_CRED_OFFSET		0x40
431
432static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
433					  const u32 x)
434{
435	u32 addr;
436
437	if (addrs)
438		addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset);
439	else
440		addr = MTL_LOW_CRED_BASE_ADDR + (x * MTL_LOW_CRED_OFFSET);
441
442	return addr;
443}
444
445#define MTL_HIGH_CRED_LC_MASK		GENMASK(28, 0)
446
447/*  MTL debug */
448#define MTL_DEBUG_TXSTSFSTS		BIT(5)
449#define MTL_DEBUG_TXFSTS		BIT(4)
450#define MTL_DEBUG_TWCSTS		BIT(3)
451
452/* MTL debug: Tx FIFO Read Controller Status */
453#define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
454#define MTL_DEBUG_TRCSTS_SHIFT		1
455#define MTL_DEBUG_TRCSTS_IDLE		0
456#define MTL_DEBUG_TRCSTS_READ		1
457#define MTL_DEBUG_TRCSTS_TXW		2
458#define MTL_DEBUG_TRCSTS_WRITE		3
459#define MTL_DEBUG_TXPAUSED		BIT(0)
460
461/* MAC debug: GMII or MII Transmit Protocol Engine Status */
462#define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
463#define MTL_DEBUG_RXFSTS_SHIFT		4
464#define MTL_DEBUG_RXFSTS_EMPTY		0
465#define MTL_DEBUG_RXFSTS_BT		1
466#define MTL_DEBUG_RXFSTS_AT		2
467#define MTL_DEBUG_RXFSTS_FULL		3
468#define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
469#define MTL_DEBUG_RRCSTS_SHIFT		1
470#define MTL_DEBUG_RRCSTS_IDLE		0
471#define MTL_DEBUG_RRCSTS_RDATA		1
472#define MTL_DEBUG_RRCSTS_RSTAT		2
473#define MTL_DEBUG_RRCSTS_FLUSH		3
474#define MTL_DEBUG_RWCSTS		BIT(0)
475
476/*  MTL interrupt */
477#define MTL_RX_OVERFLOW_INT_EN		BIT(24)
478#define MTL_RX_OVERFLOW_INT		BIT(16)
479
480/* Default operating mode of the MAC */
481#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
482			GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
483			GMAC_CONFIG_JE)
484
485/* To dump the core regs excluding  the Address Registers */
486#define	GMAC_REG_NUM	132
487
488/*  MTL debug */
489#define MTL_DEBUG_TXSTSFSTS		BIT(5)
490#define MTL_DEBUG_TXFSTS		BIT(4)
491#define MTL_DEBUG_TWCSTS		BIT(3)
492
493/* MTL debug: Tx FIFO Read Controller Status */
494#define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
495#define MTL_DEBUG_TRCSTS_SHIFT		1
496#define MTL_DEBUG_TRCSTS_IDLE		0
497#define MTL_DEBUG_TRCSTS_READ		1
498#define MTL_DEBUG_TRCSTS_TXW		2
499#define MTL_DEBUG_TRCSTS_WRITE		3
500#define MTL_DEBUG_TXPAUSED		BIT(0)
501
502/* MAC debug: GMII or MII Transmit Protocol Engine Status */
503#define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
504#define MTL_DEBUG_RXFSTS_SHIFT		4
505#define MTL_DEBUG_RXFSTS_EMPTY		0
506#define MTL_DEBUG_RXFSTS_BT		1
507#define MTL_DEBUG_RXFSTS_AT		2
508#define MTL_DEBUG_RXFSTS_FULL		3
509#define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
510#define MTL_DEBUG_RRCSTS_SHIFT		1
511#define MTL_DEBUG_RRCSTS_IDLE		0
512#define MTL_DEBUG_RRCSTS_RDATA		1
513#define MTL_DEBUG_RRCSTS_RSTAT		2
514#define MTL_DEBUG_RRCSTS_FLUSH		3
515#define MTL_DEBUG_RWCSTS		BIT(0)
516
517/* SGMII/RGMII status register */
518#define GMAC_PHYIF_CTRLSTATUS_TC		BIT(0)
519#define GMAC_PHYIF_CTRLSTATUS_LUD		BIT(1)
520#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS		BIT(4)
521#define GMAC_PHYIF_CTRLSTATUS_LNKMOD		BIT(16)
522#define GMAC_PHYIF_CTRLSTATUS_SPEED		GENMASK(18, 17)
523#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT	17
524#define GMAC_PHYIF_CTRLSTATUS_LNKSTS		BIT(19)
525#define GMAC_PHYIF_CTRLSTATUS_JABTO		BIT(20)
526#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET	BIT(21)
527/* LNKSPEED */
528#define GMAC_PHYIF_CTRLSTATUS_SPEED_125		0x2
529#define GMAC_PHYIF_CTRLSTATUS_SPEED_25		0x1
530#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5		0x0
531
532extern const struct stmmac_dma_ops dwmac4_dma_ops;
533extern const struct stmmac_dma_ops dwmac410_dma_ops;
534#endif /* __DWMAC4_H__ */