dwmac-sun8i.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
   4 *
   5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/io.h>
  10#include <linux/iopoll.h>
  11#include <linux/mdio-mux.h>
  12#include <linux/mfd/syscon.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/of_mdio.h>
  16#include <linux/of_net.h>
  17#include <linux/of_platform.h>
  18#include <linux/phy.h>
  19#include <linux/platform_device.h>
  20#include <linux/pm_runtime.h>
  21#include <linux/regulator/consumer.h>
  22#include <linux/regmap.h>
  23#include <linux/stmmac.h>
  24
  25#include "stmmac.h"
  26#include "stmmac_platform.h"
  27
  28/* General notes on dwmac-sun8i:
  29 * Locking: no locking is necessary in this file because all necessary locking
  30 *		is done in the "stmmac files"
  31 */
  32
  33/* struct emac_variant - Describe dwmac-sun8i hardware variant
  34 * @syscon_field		reg_field for the syscon's gmac register
  35 * @soc_has_internal_phy:	Does the MAC embed an internal PHY
  36 * @support_mii:		Does the MAC handle MII
  37 * @support_rmii:		Does the MAC handle RMII
  38 * @support_rgmii:		Does the MAC handle RGMII
  39 *
  40 * @rx_delay_max:		Maximum raw value for RX delay chain
  41 * @tx_delay_max:		Maximum raw value for TX delay chain
  42 *				These two also indicate the bitmask for
  43 *				the RX and TX delay chain registers. A
  44 *				value of zero indicates this is not supported.
  45 */
  46struct emac_variant {
  47	const struct reg_field *syscon_field;
  48	bool soc_has_internal_phy;
  49	bool support_mii;
  50	bool support_rmii;
  51	bool support_rgmii;
  52	u8 rx_delay_max;
  53	u8 tx_delay_max;
  54};
  55
  56/* struct sunxi_priv_data - hold all sunxi private data
  57 * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
  58 * @regulator:	reference to the optional regulator
  59 * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
  60 * @variant:	reference to the current board variant
  61 * @regmap:	regmap for using the syscon
  62 * @internal_phy_powered: Does the internal PHY is enabled
  63 * @use_internal_phy: Is the internal PHY selected for use
  64 * @mux_handle:	Internal pointer used by mdio-mux lib
  65 */
  66struct sunxi_priv_data {
  67	struct clk *ephy_clk;
  68	struct regulator *regulator;
  69	struct reset_control *rst_ephy;
  70	const struct emac_variant *variant;
  71	struct regmap_field *regmap_field;
  72	bool internal_phy_powered;
  73	bool use_internal_phy;
  74	void *mux_handle;
  75};
  76
  77/* EMAC clock register @ 0x30 in the "system control" address range */
  78static const struct reg_field sun8i_syscon_reg_field = {
  79	.reg = 0x30,
  80	.lsb = 0,
  81	.msb = 31,
  82};
  83
  84/* EMAC clock register @ 0x164 in the CCU address range */
  85static const struct reg_field sun8i_ccu_reg_field = {
  86	.reg = 0x164,
  87	.lsb = 0,
  88	.msb = 31,
  89};
  90
  91static const struct emac_variant emac_variant_h3 = {
  92	.syscon_field = &sun8i_syscon_reg_field,
  93	.soc_has_internal_phy = true,
  94	.support_mii = true,
  95	.support_rmii = true,
  96	.support_rgmii = true,
  97	.rx_delay_max = 31,
  98	.tx_delay_max = 7,
  99};
 100
 101static const struct emac_variant emac_variant_v3s = {
 102	.syscon_field = &sun8i_syscon_reg_field,
 103	.soc_has_internal_phy = true,
 104	.support_mii = true
 105};
 106
 107static const struct emac_variant emac_variant_a83t = {
 108	.syscon_field = &sun8i_syscon_reg_field,
 109	.soc_has_internal_phy = false,
 110	.support_mii = true,
 111	.support_rgmii = true,
 112	.rx_delay_max = 31,
 113	.tx_delay_max = 7,
 114};
 115
 116static const struct emac_variant emac_variant_r40 = {
 117	.syscon_field = &sun8i_ccu_reg_field,
 118	.support_mii = true,
 119	.support_rgmii = true,
 120	.rx_delay_max = 7,
 121};
 122
 123static const struct emac_variant emac_variant_a64 = {
 124	.syscon_field = &sun8i_syscon_reg_field,
 125	.soc_has_internal_phy = false,
 126	.support_mii = true,
 127	.support_rmii = true,
 128	.support_rgmii = true,
 129	.rx_delay_max = 31,
 130	.tx_delay_max = 7,
 131};
 132
 133static const struct emac_variant emac_variant_h6 = {
 134	.syscon_field = &sun8i_syscon_reg_field,
 135	/* The "Internal PHY" of H6 is not on the die. It's on the
 136	 * co-packaged AC200 chip instead.
 137	 */
 138	.soc_has_internal_phy = false,
 139	.support_mii = true,
 140	.support_rmii = true,
 141	.support_rgmii = true,
 142	.rx_delay_max = 31,
 143	.tx_delay_max = 7,
 144};
 145
 146#define EMAC_BASIC_CTL0 0x00
 147#define EMAC_BASIC_CTL1 0x04
 148#define EMAC_INT_STA    0x08
 149#define EMAC_INT_EN     0x0C
 150#define EMAC_TX_CTL0    0x10
 151#define EMAC_TX_CTL1    0x14
 152#define EMAC_TX_FLOW_CTL        0x1C
 153#define EMAC_TX_DESC_LIST 0x20
 154#define EMAC_RX_CTL0    0x24
 155#define EMAC_RX_CTL1    0x28
 156#define EMAC_RX_DESC_LIST 0x34
 157#define EMAC_RX_FRM_FLT 0x38
 158#define EMAC_MDIO_CMD   0x48
 159#define EMAC_MDIO_DATA  0x4C
 160#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
 161#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
 162#define EMAC_TX_DMA_STA 0xB0
 163#define EMAC_TX_CUR_DESC        0xB4
 164#define EMAC_TX_CUR_BUF 0xB8
 165#define EMAC_RX_DMA_STA 0xC0
 166#define EMAC_RX_CUR_DESC        0xC4
 167#define EMAC_RX_CUR_BUF 0xC8
 168
 169/* Use in EMAC_BASIC_CTL0 */
 170#define EMAC_DUPLEX_FULL	BIT(0)
 171#define EMAC_LOOPBACK		BIT(1)
 172#define EMAC_SPEED_1000 0
 173#define EMAC_SPEED_100 (0x03 << 2)
 174#define EMAC_SPEED_10 (0x02 << 2)
 175
 176/* Use in EMAC_BASIC_CTL1 */
 177#define EMAC_BURSTLEN_SHIFT		24
 178
 179/* Used in EMAC_RX_FRM_FLT */
 180#define EMAC_FRM_FLT_RXALL              BIT(0)
 181#define EMAC_FRM_FLT_CTL                BIT(13)
 182#define EMAC_FRM_FLT_MULTICAST          BIT(16)
 183
 184/* Used in RX_CTL1*/
 185#define EMAC_RX_MD              BIT(1)
 186#define EMAC_RX_TH_MASK		GENMASK(5, 4)
 187#define EMAC_RX_TH_32		0
 188#define EMAC_RX_TH_64		(0x1 << 4)
 189#define EMAC_RX_TH_96		(0x2 << 4)
 190#define EMAC_RX_TH_128		(0x3 << 4)
 191#define EMAC_RX_DMA_EN  BIT(30)
 192#define EMAC_RX_DMA_START       BIT(31)
 193
 194/* Used in TX_CTL1*/
 195#define EMAC_TX_MD              BIT(1)
 196#define EMAC_TX_NEXT_FRM        BIT(2)
 197#define EMAC_TX_TH_MASK		GENMASK(10, 8)
 198#define EMAC_TX_TH_64		0
 199#define EMAC_TX_TH_128		(0x1 << 8)
 200#define EMAC_TX_TH_192		(0x2 << 8)
 201#define EMAC_TX_TH_256		(0x3 << 8)
 202#define EMAC_TX_DMA_EN  BIT(30)
 203#define EMAC_TX_DMA_START       BIT(31)
 204
 205/* Used in RX_CTL0 */
 206#define EMAC_RX_RECEIVER_EN             BIT(31)
 207#define EMAC_RX_DO_CRC BIT(27)
 208#define EMAC_RX_FLOW_CTL_EN             BIT(16)
 209
 210/* Used in TX_CTL0 */
 211#define EMAC_TX_TRANSMITTER_EN  BIT(31)
 212
 213/* Used in EMAC_TX_FLOW_CTL */
 214#define EMAC_TX_FLOW_CTL_EN             BIT(0)
 215
 216/* Used in EMAC_INT_STA */
 217#define EMAC_TX_INT             BIT(0)
 218#define EMAC_TX_DMA_STOP_INT    BIT(1)
 219#define EMAC_TX_BUF_UA_INT      BIT(2)
 220#define EMAC_TX_TIMEOUT_INT     BIT(3)
 221#define EMAC_TX_UNDERFLOW_INT   BIT(4)
 222#define EMAC_TX_EARLY_INT       BIT(5)
 223#define EMAC_RX_INT             BIT(8)
 224#define EMAC_RX_BUF_UA_INT      BIT(9)
 225#define EMAC_RX_DMA_STOP_INT    BIT(10)
 226#define EMAC_RX_TIMEOUT_INT     BIT(11)
 227#define EMAC_RX_OVERFLOW_INT    BIT(12)
 228#define EMAC_RX_EARLY_INT       BIT(13)
 229#define EMAC_RGMII_STA_INT      BIT(16)
 230
 231#define EMAC_INT_MSK_COMMON	EMAC_RGMII_STA_INT
 232#define EMAC_INT_MSK_TX		(EMAC_TX_INT | \
 233				 EMAC_TX_DMA_STOP_INT | \
 234				 EMAC_TX_BUF_UA_INT | \
 235				 EMAC_TX_TIMEOUT_INT | \
 236				 EMAC_TX_UNDERFLOW_INT | \
 237				 EMAC_TX_EARLY_INT |\
 238				 EMAC_INT_MSK_COMMON)
 239#define EMAC_INT_MSK_RX		(EMAC_RX_INT | \
 240				 EMAC_RX_BUF_UA_INT | \
 241				 EMAC_RX_DMA_STOP_INT | \
 242				 EMAC_RX_TIMEOUT_INT | \
 243				 EMAC_RX_OVERFLOW_INT | \
 244				 EMAC_RX_EARLY_INT | \
 245				 EMAC_INT_MSK_COMMON)
 246
 247#define MAC_ADDR_TYPE_DST BIT(31)
 248
 249/* H3 specific bits for EPHY */
 250#define H3_EPHY_ADDR_SHIFT	20
 251#define H3_EPHY_CLK_SEL		BIT(18) /* 1: 24MHz, 0: 25MHz */
 252#define H3_EPHY_LED_POL		BIT(17) /* 1: active low, 0: active high */
 253#define H3_EPHY_SHUTDOWN	BIT(16) /* 1: shutdown, 0: power up */
 254#define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
 255#define H3_EPHY_MUX_MASK	(H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
 256#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID	1
 257#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID	2
 258
 259/* H3/A64 specific bits */
 260#define SYSCON_RMII_EN		BIT(13) /* 1: enable RMII (overrides EPIT) */
 261
 262/* Generic system control EMAC_CLK bits */
 263#define SYSCON_ETXDC_SHIFT		10
 264#define SYSCON_ERXDC_SHIFT		5
 265/* EMAC PHY Interface Type */
 266#define SYSCON_EPIT			BIT(2) /* 1: RGMII, 0: MII */
 267#define SYSCON_ETCS_MASK		GENMASK(1, 0)
 268#define SYSCON_ETCS_MII		0x0
 269#define SYSCON_ETCS_EXT_GMII	0x1
 270#define SYSCON_ETCS_INT_GMII	0x2
 271
 272/* sun8i_dwmac_dma_reset() - reset the EMAC
 273 * Called from stmmac via stmmac_dma_ops->reset
 274 */
 275static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
 276{
 277	writel(0, ioaddr + EMAC_RX_CTL1);
 278	writel(0, ioaddr + EMAC_TX_CTL1);
 279	writel(0, ioaddr + EMAC_RX_FRM_FLT);
 280	writel(0, ioaddr + EMAC_RX_DESC_LIST);
 281	writel(0, ioaddr + EMAC_TX_DESC_LIST);
 282	writel(0, ioaddr + EMAC_INT_EN);
 283	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
 284	return 0;
 285}
 286
 287/* sun8i_dwmac_dma_init() - initialize the EMAC
 288 * Called from stmmac via stmmac_dma_ops->init
 289 */
 290static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
 291				 struct stmmac_dma_cfg *dma_cfg)
 292{
 293	writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
 294	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
 295}
 296
 297static void sun8i_dwmac_dma_init_rx(struct stmmac_priv *priv,
 298				    void __iomem *ioaddr,
 299				    struct stmmac_dma_cfg *dma_cfg,
 300				    dma_addr_t dma_rx_phy, u32 chan)
 301{
 302	/* Write RX descriptors address */
 303	writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);
 304}
 305
 306static void sun8i_dwmac_dma_init_tx(struct stmmac_priv *priv,
 307				    void __iomem *ioaddr,
 308				    struct stmmac_dma_cfg *dma_cfg,
 309				    dma_addr_t dma_tx_phy, u32 chan)
 310{
 311	/* Write TX descriptors address */
 312	writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);
 313}
 314
 315/* sun8i_dwmac_dump_regs() - Dump EMAC address space
 316 * Called from stmmac_dma_ops->dump_regs
 317 * Used for ethtool
 318 */
 319static void sun8i_dwmac_dump_regs(struct stmmac_priv *priv,
 320				  void __iomem *ioaddr, u32 *reg_space)
 321{
 322	int i;
 323
 324	for (i = 0; i < 0xC8; i += 4) {
 325		if (i == 0x32 || i == 0x3C)
 326			continue;
 327		reg_space[i / 4] = readl(ioaddr + i);
 328	}
 329}
 330
 331/* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
 332 * Called from stmmac_ops->dump_regs
 333 * Used for ethtool
 334 */
 335static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
 336				      u32 *reg_space)
 337{
 338	int i;
 339	void __iomem *ioaddr = hw->pcsr;
 340
 341	for (i = 0; i < 0xC8; i += 4) {
 342		if (i == 0x32 || i == 0x3C)
 343			continue;
 344		reg_space[i / 4] = readl(ioaddr + i);
 345	}
 346}
 347
 348static void sun8i_dwmac_enable_dma_irq(struct stmmac_priv *priv,
 349				       void __iomem *ioaddr, u32 chan,
 350				       bool rx, bool tx)
 351{
 352	u32 value = readl(ioaddr + EMAC_INT_EN);
 353
 354	if (rx)
 355		value |= EMAC_RX_INT;
 356	if (tx)
 357		value |= EMAC_TX_INT;
 358
 359	writel(value, ioaddr + EMAC_INT_EN);
 360}
 361
 362static void sun8i_dwmac_disable_dma_irq(struct stmmac_priv *priv,
 363					void __iomem *ioaddr, u32 chan,
 364					bool rx, bool tx)
 365{
 366	u32 value = readl(ioaddr + EMAC_INT_EN);
 367
 368	if (rx)
 369		value &= ~EMAC_RX_INT;
 370	if (tx)
 371		value &= ~EMAC_TX_INT;
 372
 373	writel(value, ioaddr + EMAC_INT_EN);
 374}
 375
 376static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
 377				     void __iomem *ioaddr, u32 chan)
 378{
 379	u32 v;
 380
 381	v = readl(ioaddr + EMAC_TX_CTL1);
 382	v |= EMAC_TX_DMA_START;
 383	v |= EMAC_TX_DMA_EN;
 384	writel(v, ioaddr + EMAC_TX_CTL1);
 385}
 386
 387static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan)
 388{
 389	u32 v;
 390
 391	v = readl(ioaddr + EMAC_TX_CTL1);
 392	v |= EMAC_TX_DMA_START;
 393	v |= EMAC_TX_DMA_EN;
 394	writel(v, ioaddr + EMAC_TX_CTL1);
 395}
 396
 397static void sun8i_dwmac_dma_stop_tx(struct stmmac_priv *priv,
 398				    void __iomem *ioaddr, u32 chan)
 399{
 400	u32 v;
 401
 402	v = readl(ioaddr + EMAC_TX_CTL1);
 403	v &= ~EMAC_TX_DMA_EN;
 404	writel(v, ioaddr + EMAC_TX_CTL1);
 405}
 406
 407static void sun8i_dwmac_dma_start_rx(struct stmmac_priv *priv,
 408				     void __iomem *ioaddr, u32 chan)
 409{
 410	u32 v;
 411
 412	v = readl(ioaddr + EMAC_RX_CTL1);
 413	v |= EMAC_RX_DMA_START;
 414	v |= EMAC_RX_DMA_EN;
 415	writel(v, ioaddr + EMAC_RX_CTL1);
 416}
 417
 418static void sun8i_dwmac_dma_stop_rx(struct stmmac_priv *priv,
 419				    void __iomem *ioaddr, u32 chan)
 420{
 421	u32 v;
 422
 423	v = readl(ioaddr + EMAC_RX_CTL1);
 424	v &= ~EMAC_RX_DMA_EN;
 425	writel(v, ioaddr + EMAC_RX_CTL1);
 426}
 427
 428static int sun8i_dwmac_dma_interrupt(struct stmmac_priv *priv,
 429				     void __iomem *ioaddr,
 430				     struct stmmac_extra_stats *x, u32 chan,
 431				     u32 dir)
 432{
 433	struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats);
 434	int ret = 0;
 435	u32 v;
 436
 437	v = readl(ioaddr + EMAC_INT_STA);
 438
 439	if (dir == DMA_DIR_RX)
 440		v &= EMAC_INT_MSK_RX;
 441	else if (dir == DMA_DIR_TX)
 442		v &= EMAC_INT_MSK_TX;
 443
 444	if (v & EMAC_TX_INT) {
 445		ret |= handle_tx;
 446		u64_stats_update_begin(&stats->syncp);
 447		u64_stats_inc(&stats->tx_normal_irq_n[chan]);
 448		u64_stats_update_end(&stats->syncp);
 449	}
 450
 451	if (v & EMAC_TX_DMA_STOP_INT)
 452		x->tx_process_stopped_irq++;
 453
 454	if (v & EMAC_TX_BUF_UA_INT)
 455		x->tx_process_stopped_irq++;
 456
 457	if (v & EMAC_TX_TIMEOUT_INT)
 458		ret |= tx_hard_error;
 459
 460	if (v & EMAC_TX_UNDERFLOW_INT) {
 461		ret |= tx_hard_error;
 462		x->tx_undeflow_irq++;
 463	}
 464
 465	if (v & EMAC_TX_EARLY_INT)
 466		x->tx_early_irq++;
 467
 468	if (v & EMAC_RX_INT) {
 469		ret |= handle_rx;
 470		u64_stats_update_begin(&stats->syncp);
 471		u64_stats_inc(&stats->rx_normal_irq_n[chan]);
 472		u64_stats_update_end(&stats->syncp);
 473	}
 474
 475	if (v & EMAC_RX_BUF_UA_INT)
 476		x->rx_buf_unav_irq++;
 477
 478	if (v & EMAC_RX_DMA_STOP_INT)
 479		x->rx_process_stopped_irq++;
 480
 481	if (v & EMAC_RX_TIMEOUT_INT)
 482		ret |= tx_hard_error;
 483
 484	if (v & EMAC_RX_OVERFLOW_INT) {
 485		ret |= tx_hard_error;
 486		x->rx_overflow_irq++;
 487	}
 488
 489	if (v & EMAC_RX_EARLY_INT)
 490		x->rx_early_irq++;
 491
 492	if (v & EMAC_RGMII_STA_INT)
 493		x->irq_rgmii_n++;
 494
 495	writel(v, ioaddr + EMAC_INT_STA);
 496
 497	return ret;
 498}
 499
 500static void sun8i_dwmac_dma_operation_mode_rx(struct stmmac_priv *priv,
 501					      void __iomem *ioaddr, int mode,
 502					      u32 channel, int fifosz, u8 qmode)
 503{
 504	u32 v;
 505
 506	v = readl(ioaddr + EMAC_RX_CTL1);
 507	if (mode == SF_DMA_MODE) {
 508		v |= EMAC_RX_MD;
 509	} else {
 510		v &= ~EMAC_RX_MD;
 511		v &= ~EMAC_RX_TH_MASK;
 512		if (mode < 32)
 513			v |= EMAC_RX_TH_32;
 514		else if (mode < 64)
 515			v |= EMAC_RX_TH_64;
 516		else if (mode < 96)
 517			v |= EMAC_RX_TH_96;
 518		else if (mode < 128)
 519			v |= EMAC_RX_TH_128;
 520	}
 521	writel(v, ioaddr + EMAC_RX_CTL1);
 522}
 523
 524static void sun8i_dwmac_dma_operation_mode_tx(struct stmmac_priv *priv,
 525					      void __iomem *ioaddr, int mode,
 526					      u32 channel, int fifosz, u8 qmode)
 527{
 528	u32 v;
 529
 530	v = readl(ioaddr + EMAC_TX_CTL1);
 531	if (mode == SF_DMA_MODE) {
 532		v |= EMAC_TX_MD;
 533		/* Undocumented bit (called TX_NEXT_FRM in BSP), the original
 534		 * comment is
 535		 * "Operating on second frame increase the performance
 536		 * especially when transmit store-and-forward is used."
 537		 */
 538		v |= EMAC_TX_NEXT_FRM;
 539	} else {
 540		v &= ~EMAC_TX_MD;
 541		v &= ~EMAC_TX_TH_MASK;
 542		if (mode < 64)
 543			v |= EMAC_TX_TH_64;
 544		else if (mode < 128)
 545			v |= EMAC_TX_TH_128;
 546		else if (mode < 192)
 547			v |= EMAC_TX_TH_192;
 548		else if (mode < 256)
 549			v |= EMAC_TX_TH_256;
 550	}
 551	writel(v, ioaddr + EMAC_TX_CTL1);
 552}
 553
 554static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
 555	.reset = sun8i_dwmac_dma_reset,
 556	.init = sun8i_dwmac_dma_init,
 557	.init_rx_chan = sun8i_dwmac_dma_init_rx,
 558	.init_tx_chan = sun8i_dwmac_dma_init_tx,
 559	.dump_regs = sun8i_dwmac_dump_regs,
 560	.dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx,
 561	.dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx,
 562	.enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
 563	.enable_dma_irq = sun8i_dwmac_enable_dma_irq,
 564	.disable_dma_irq = sun8i_dwmac_disable_dma_irq,
 565	.start_tx = sun8i_dwmac_dma_start_tx,
 566	.stop_tx = sun8i_dwmac_dma_stop_tx,
 567	.start_rx = sun8i_dwmac_dma_start_rx,
 568	.stop_rx = sun8i_dwmac_dma_stop_rx,
 569	.dma_interrupt = sun8i_dwmac_dma_interrupt,
 570};
 571
 572static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv);
 573
 574static int sun8i_dwmac_init(struct device *dev, void *priv)
 575{
 576	struct net_device *ndev = dev_get_drvdata(dev);
 577	struct sunxi_priv_data *gmac = priv;
 578	int ret;
 579
 580	if (gmac->regulator) {
 581		ret = regulator_enable(gmac->regulator);
 582		if (ret) {
 583			dev_err(dev, "Fail to enable regulator\n");
 584			return ret;
 585		}
 586	}
 587
 588	if (gmac->use_internal_phy) {
 589		ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev));
 590		if (ret)
 591			goto err_disable_regulator;
 592	}
 593
 594	return 0;
 595
 596err_disable_regulator:
 597	if (gmac->regulator)
 598		regulator_disable(gmac->regulator);
 599
 600	return ret;
 601}
 602
 603static void sun8i_dwmac_core_init(struct mac_device_info *hw,
 604				  struct net_device *dev)
 605{
 606	void __iomem *ioaddr = hw->pcsr;
 607	u32 v;
 608
 609	v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
 610	writel(v, ioaddr + EMAC_BASIC_CTL1);
 611}
 612
 613static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
 614{
 615	u32 t, r;
 616
 617	t = readl(ioaddr + EMAC_TX_CTL0);
 618	r = readl(ioaddr + EMAC_RX_CTL0);
 619	if (enable) {
 620		t |= EMAC_TX_TRANSMITTER_EN;
 621		r |= EMAC_RX_RECEIVER_EN;
 622	} else {
 623		t &= ~EMAC_TX_TRANSMITTER_EN;
 624		r &= ~EMAC_RX_RECEIVER_EN;
 625	}
 626	writel(t, ioaddr + EMAC_TX_CTL0);
 627	writel(r, ioaddr + EMAC_RX_CTL0);
 628}
 629
 630/* Set MAC address at slot reg_n
 631 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
 632 * If addr is NULL, clear the slot
 633 */
 634static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
 635				      const unsigned char *addr,
 636				      unsigned int reg_n)
 637{
 638	void __iomem *ioaddr = hw->pcsr;
 639	u32 v;
 640
 641	if (!addr) {
 642		writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
 643		return;
 644	}
 645
 646	stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
 647			    EMAC_MACADDR_LO(reg_n));
 648	if (reg_n > 0) {
 649		v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
 650		v |= MAC_ADDR_TYPE_DST;
 651		writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
 652	}
 653}
 654
 655static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
 656				      unsigned char *addr,
 657				      unsigned int reg_n)
 658{
 659	void __iomem *ioaddr = hw->pcsr;
 660
 661	stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
 662			    EMAC_MACADDR_LO(reg_n));
 663}
 664
 665/* caution this function must return non 0 to work */
 666static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
 667{
 668	void __iomem *ioaddr = hw->pcsr;
 669	u32 v;
 670
 671	v = readl(ioaddr + EMAC_RX_CTL0);
 672	v |= EMAC_RX_DO_CRC;
 673	writel(v, ioaddr + EMAC_RX_CTL0);
 674
 675	return 1;
 676}
 677
 678static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
 679				   struct net_device *dev)
 680{
 681	void __iomem *ioaddr = hw->pcsr;
 682	u32 v;
 683	int i = 1;
 684	struct netdev_hw_addr *ha;
 685	int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
 686
 687	v = EMAC_FRM_FLT_CTL;
 688
 689	if (dev->flags & IFF_PROMISC) {
 690		v = EMAC_FRM_FLT_RXALL;
 691	} else if (dev->flags & IFF_ALLMULTI) {
 692		v |= EMAC_FRM_FLT_MULTICAST;
 693	} else if (macaddrs <= hw->unicast_filter_entries) {
 694		if (!netdev_mc_empty(dev)) {
 695			netdev_for_each_mc_addr(ha, dev) {
 696				sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
 697				i++;
 698			}
 699		}
 700		if (!netdev_uc_empty(dev)) {
 701			netdev_for_each_uc_addr(ha, dev) {
 702				sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
 703				i++;
 704			}
 705		}
 706	} else {
 707		if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL))
 708			netdev_info(dev, "Too many address, switching to promiscuous\n");
 709		v = EMAC_FRM_FLT_RXALL;
 710	}
 711
 712	/* Disable unused address filter slots */
 713	while (i < hw->unicast_filter_entries)
 714		sun8i_dwmac_set_umac_addr(hw, NULL, i++);
 715
 716	writel(v, ioaddr + EMAC_RX_FRM_FLT);
 717}
 718
 719static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
 720				  unsigned int duplex, unsigned int fc,
 721				  unsigned int pause_time, u32 tx_cnt)
 722{
 723	void __iomem *ioaddr = hw->pcsr;
 724	u32 v;
 725
 726	v = readl(ioaddr + EMAC_RX_CTL0);
 727	if (fc == FLOW_AUTO)
 728		v |= EMAC_RX_FLOW_CTL_EN;
 729	else
 730		v &= ~EMAC_RX_FLOW_CTL_EN;
 731	writel(v, ioaddr + EMAC_RX_CTL0);
 732
 733	v = readl(ioaddr + EMAC_TX_FLOW_CTL);
 734	if (fc == FLOW_AUTO)
 735		v |= EMAC_TX_FLOW_CTL_EN;
 736	else
 737		v &= ~EMAC_TX_FLOW_CTL_EN;
 738	writel(v, ioaddr + EMAC_TX_FLOW_CTL);
 739}
 740
 741static int sun8i_dwmac_reset(struct stmmac_priv *priv)
 742{
 743	u32 v;
 744	int err;
 745
 746	v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
 747	writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
 748
 749	/* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
 750	 * need more if no cable plugged. 100ms seems OK
 751	 */
 752	err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
 753				 !(v & 0x01), 100, 100000);
 754
 755	if (err) {
 756		dev_err(priv->device, "EMAC reset timeout\n");
 757		return err;
 758	}
 759	return 0;
 760}
 761
 762/* Search in mdio-mux node for internal PHY node and get its clk/reset */
 763static int get_ephy_nodes(struct stmmac_priv *priv)
 764{
 765	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 766	struct device_node *mdio_internal;
 767	struct device_node *mdio_mux;
 768	int ret;
 769
 770	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
 771	if (!mdio_mux) {
 772		dev_err(priv->device, "Cannot get mdio-mux node\n");
 773		return -ENODEV;
 774	}
 775
 776	mdio_internal = of_get_compatible_child(mdio_mux,
 777						"allwinner,sun8i-h3-mdio-internal");
 778	of_node_put(mdio_mux);
 779	if (!mdio_internal) {
 780		dev_err(priv->device, "Cannot get internal_mdio node\n");
 781		return -ENODEV;
 782	}
 783
 784	/* Seek for internal PHY */
 785	for_each_child_of_node_scoped(mdio_internal, iphynode) {
 786		gmac->ephy_clk = of_clk_get(iphynode, 0);
 787		if (IS_ERR(gmac->ephy_clk))
 788			continue;
 789		gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
 790		if (IS_ERR(gmac->rst_ephy)) {
 791			ret = PTR_ERR(gmac->rst_ephy);
 792			if (ret == -EPROBE_DEFER) {
 793				of_node_put(mdio_internal);
 794				return ret;
 795			}
 796			continue;
 797		}
 798		dev_info(priv->device, "Found internal PHY node\n");
 799		of_node_put(mdio_internal);
 800		return 0;
 801	}
 802
 803	of_node_put(mdio_internal);
 804	return -ENODEV;
 805}
 806
 807static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
 808{
 809	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 810	int ret;
 811
 812	if (gmac->internal_phy_powered) {
 813		dev_warn(priv->device, "Internal PHY already powered\n");
 814		return 0;
 815	}
 816
 817	dev_info(priv->device, "Powering internal PHY\n");
 818	ret = clk_prepare_enable(gmac->ephy_clk);
 819	if (ret) {
 820		dev_err(priv->device, "Cannot enable internal PHY\n");
 821		return ret;
 822	}
 823
 824	/* Make sure the EPHY is properly reseted, as U-Boot may leave
 825	 * it at deasserted state, and thus it may fail to reset EMAC.
 826	 *
 827	 * This assumes the driver has exclusive access to the EPHY reset.
 828	 */
 829	ret = reset_control_reset(gmac->rst_ephy);
 830	if (ret) {
 831		dev_err(priv->device, "Cannot reset internal PHY\n");
 832		clk_disable_unprepare(gmac->ephy_clk);
 833		return ret;
 834	}
 835
 836	gmac->internal_phy_powered = true;
 837
 838	return 0;
 839}
 840
 841static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
 842{
 843	if (!gmac->internal_phy_powered)
 844		return;
 845
 846	clk_disable_unprepare(gmac->ephy_clk);
 847	reset_control_assert(gmac->rst_ephy);
 848	gmac->internal_phy_powered = false;
 849}
 850
 851/* MDIO multiplexing switch function
 852 * This function is called by the mdio-mux layer when it thinks the mdio bus
 853 * multiplexer needs to switch.
 854 * 'current_child' is the current value of the mux register
 855 * 'desired_child' is the value of the 'reg' property of the target child MDIO
 856 * node.
 857 * The first time this function is called, current_child == -1.
 858 * If current_child == desired_child, then the mux is already set to the
 859 * correct bus.
 860 */
 861static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
 862				     void *data)
 863{
 864	struct stmmac_priv *priv = data;
 865	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 866	u32 reg, val;
 867	int ret = 0;
 868
 869	if (current_child ^ desired_child) {
 870		regmap_field_read(gmac->regmap_field, &reg);
 871		switch (desired_child) {
 872		case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
 873			dev_info(priv->device, "Switch mux to internal PHY");
 874			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
 875			gmac->use_internal_phy = true;
 876			break;
 877		case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
 878			dev_info(priv->device, "Switch mux to external PHY");
 879			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
 880			gmac->use_internal_phy = false;
 881			break;
 882		default:
 883			dev_err(priv->device, "Invalid child ID %x\n",
 884				desired_child);
 885			return -EINVAL;
 886		}
 887		regmap_field_write(gmac->regmap_field, val);
 888		if (gmac->use_internal_phy) {
 889			ret = sun8i_dwmac_power_internal_phy(priv);
 890			if (ret)
 891				return ret;
 892		} else {
 893			sun8i_dwmac_unpower_internal_phy(gmac);
 894		}
 895		/* After changing syscon value, the MAC need reset or it will
 896		 * use the last value (and so the last PHY set).
 897		 */
 898		ret = sun8i_dwmac_reset(priv);
 899	}
 900	return ret;
 901}
 902
 903static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
 904{
 905	int ret;
 906	struct device_node *mdio_mux;
 907	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
 908
 909	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
 910	if (!mdio_mux)
 911		return -ENODEV;
 912
 913	ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
 914			    &gmac->mux_handle, priv, priv->mii);
 915	of_node_put(mdio_mux);
 916	return ret;
 917}
 918
 919static int sun8i_dwmac_set_syscon(struct device *dev,
 920				  struct plat_stmmacenet_data *plat)
 921{
 922	struct sunxi_priv_data *gmac = plat->bsp_priv;
 923	struct device_node *node = dev->of_node;
 924	int ret;
 925	u32 reg = 0, val;
 926
 927	if (gmac->variant->soc_has_internal_phy) {
 928		if (of_property_read_bool(node, "allwinner,leds-active-low"))
 929			reg |= H3_EPHY_LED_POL;
 930
 931		/* Force EPHY xtal frequency to 24MHz. */
 932		reg |= H3_EPHY_CLK_SEL;
 933
 934		ret = of_mdio_parse_addr(dev, plat->phy_node);
 935		if (ret < 0) {
 936			dev_err(dev, "Could not parse MDIO addr\n");
 937			return ret;
 938		}
 939		/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
 940		 * address. No need to mask it again.
 941		 */
 942		reg |= ret << H3_EPHY_ADDR_SHIFT;
 943	}
 944
 945	if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
 946		if (val % 100) {
 947			dev_err(dev, "tx-delay must be a multiple of 100\n");
 948			return -EINVAL;
 949		}
 950		val /= 100;
 951		dev_dbg(dev, "set tx-delay to %x\n", val);
 952		if (val <= gmac->variant->tx_delay_max) {
 953			reg |= (val << SYSCON_ETXDC_SHIFT);
 954		} else {
 955			dev_err(dev, "Invalid TX clock delay: %d\n",
 956				val);
 957			return -EINVAL;
 958		}
 959	}
 960
 961	if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
 962		if (val % 100) {
 963			dev_err(dev, "rx-delay must be a multiple of 100\n");
 964			return -EINVAL;
 965		}
 966		val /= 100;
 967		dev_dbg(dev, "set rx-delay to %x\n", val);
 968		if (val <= gmac->variant->rx_delay_max) {
 969			reg |= (val << SYSCON_ERXDC_SHIFT);
 970		} else {
 971			dev_err(dev, "Invalid RX clock delay: %d\n",
 972				val);
 973			return -EINVAL;
 974		}
 975	}
 976
 977	switch (plat->phy_interface) {
 978	case PHY_INTERFACE_MODE_MII:
 979		/* default */
 980		break;
 981	case PHY_INTERFACE_MODE_RGMII:
 982	case PHY_INTERFACE_MODE_RGMII_ID:
 983	case PHY_INTERFACE_MODE_RGMII_RXID:
 984	case PHY_INTERFACE_MODE_RGMII_TXID:
 985		reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
 986		break;
 987	case PHY_INTERFACE_MODE_RMII:
 988		reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
 989		break;
 990	default:
 991		dev_err(dev, "Unsupported interface mode: %s",
 992			phy_modes(plat->phy_interface));
 993		return -EINVAL;
 994	}
 995
 996	regmap_field_write(gmac->regmap_field, reg);
 997
 998	return 0;
 999}
1000
1001static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
1002{
1003	if (gmac->variant->soc_has_internal_phy)
1004		regmap_field_write(gmac->regmap_field,
1005				   (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT));
1006}
1007
1008static void sun8i_dwmac_exit(struct device *dev, void *priv)
1009{
1010	struct sunxi_priv_data *gmac = priv;
1011
1012	if (gmac->variant->soc_has_internal_phy)
1013		sun8i_dwmac_unpower_internal_phy(gmac);
1014
1015	if (gmac->regulator)
1016		regulator_disable(gmac->regulator);
1017}
1018
1019static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
1020{
1021	u32 value = readl(ioaddr + EMAC_BASIC_CTL0);
1022
1023	if (enable)
1024		value |= EMAC_LOOPBACK;
1025	else
1026		value &= ~EMAC_LOOPBACK;
1027
1028	writel(value, ioaddr + EMAC_BASIC_CTL0);
1029}
1030
1031static const struct stmmac_ops sun8i_dwmac_ops = {
1032	.core_init = sun8i_dwmac_core_init,
1033	.set_mac = sun8i_dwmac_set_mac,
1034	.dump_regs = sun8i_dwmac_dump_mac_regs,
1035	.rx_ipc = sun8i_dwmac_rx_ipc_enable,
1036	.set_filter = sun8i_dwmac_set_filter,
1037	.flow_ctrl = sun8i_dwmac_flow_ctrl,
1038	.set_umac_addr = sun8i_dwmac_set_umac_addr,
1039	.get_umac_addr = sun8i_dwmac_get_umac_addr,
1040	.set_mac_loopback = sun8i_dwmac_set_mac_loopback,
1041};
1042
1043static int sun8i_dwmac_setup(void *ppriv, struct mac_device_info *mac)
1044{
1045	struct stmmac_priv *priv = ppriv;
1046
1047	mac->pcsr = priv->ioaddr;
1048	mac->mac = &sun8i_dwmac_ops;
1049	mac->dma = &sun8i_dwmac_dma_ops;
1050
1051	priv->dev->priv_flags |= IFF_UNICAST_FLT;
1052
1053	mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1054			 MAC_10 | MAC_100 | MAC_1000;
1055	/* The loopback bit seems to be re-set when link change
1056	 * Simply mask it each time
1057	 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
1058	 */
1059	mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
1060	mac->link.speed10 = EMAC_SPEED_10;
1061	mac->link.speed100 = EMAC_SPEED_100;
1062	mac->link.speed1000 = EMAC_SPEED_1000;
1063	mac->link.duplex = EMAC_DUPLEX_FULL;
1064	mac->mii.addr = EMAC_MDIO_CMD;
1065	mac->mii.data = EMAC_MDIO_DATA;
1066	mac->mii.reg_shift = 4;
1067	mac->mii.reg_mask = GENMASK(8, 4);
1068	mac->mii.addr_shift = 12;
1069	mac->mii.addr_mask = GENMASK(16, 12);
1070	mac->mii.clk_csr_shift = 20;
1071	mac->mii.clk_csr_mask = GENMASK(22, 20);
1072	mac->unicast_filter_entries = 8;
1073
1074	/* Synopsys Id is not available */
1075	priv->synopsys_id = 0;
1076
1077	return 0;
1078}
1079
1080static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node)
1081{
1082	struct device_node *syscon_node;
1083	struct platform_device *syscon_pdev;
1084	struct regmap *regmap = NULL;
1085
1086	syscon_node = of_parse_phandle(node, "syscon", 0);
1087	if (!syscon_node)
1088		return ERR_PTR(-ENODEV);
1089
1090	syscon_pdev = of_find_device_by_node(syscon_node);
1091	if (!syscon_pdev) {
1092		/* platform device might not be probed yet */
1093		regmap = ERR_PTR(-EPROBE_DEFER);
1094		goto out_put_node;
1095	}
1096
1097	/* If no regmap is found then the other device driver is at fault */
1098	regmap = dev_get_regmap(&syscon_pdev->dev, NULL);
1099	if (!regmap)
1100		regmap = ERR_PTR(-EINVAL);
1101
1102	platform_device_put(syscon_pdev);
1103out_put_node:
1104	of_node_put(syscon_node);
1105	return regmap;
1106}
1107
1108static int sun8i_dwmac_probe(struct platform_device *pdev)
1109{
1110	struct plat_stmmacenet_data *plat_dat;
1111	struct stmmac_resources stmmac_res;
1112	struct sunxi_priv_data *gmac;
1113	struct device *dev = &pdev->dev;
1114	struct stmmac_priv *priv;
1115	struct net_device *ndev;
1116	struct regmap *regmap;
1117	int ret;
1118
1119	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1120	if (ret)
1121		return ret;
1122
1123	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
1124	if (!gmac)
1125		return -ENOMEM;
1126
1127	gmac->variant = of_device_get_match_data(&pdev->dev);
1128	if (!gmac->variant) {
1129		dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
1130		return -EINVAL;
1131	}
1132
1133	/* Optional regulator for PHY */
1134	gmac->regulator = devm_regulator_get_optional(dev, "phy");
1135	if (IS_ERR(gmac->regulator)) {
1136		if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
1137			return -EPROBE_DEFER;
1138		dev_info(dev, "No regulator found\n");
1139		gmac->regulator = NULL;
1140	}
1141
1142	/* The "GMAC clock control" register might be located in the
1143	 * CCU address range (on the R40), or the system control address
1144	 * range (on most other sun8i and later SoCs).
1145	 *
1146	 * The former controls most if not all clocks in the SoC. The
1147	 * latter has an SoC identification register, and on some SoCs,
1148	 * controls to map device specific SRAM to either the intended
1149	 * peripheral, or the CPU address space.
1150	 *
1151	 * In either case, there should be a coordinated and restricted
1152	 * method of accessing the register needed here. This is done by
1153	 * having the device export a custom regmap, instead of a generic
1154	 * syscon, which grants all access to all registers.
1155	 *
1156	 * To support old device trees, we fall back to using the syscon
1157	 * interface if possible.
1158	 */
1159	regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node);
1160	if (IS_ERR(regmap))
1161		regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1162							 "syscon");
1163	if (IS_ERR(regmap)) {
1164		ret = PTR_ERR(regmap);
1165		dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
1166		return ret;
1167	}
1168
1169	gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
1170						     *gmac->variant->syscon_field);
1171	if (IS_ERR(gmac->regmap_field)) {
1172		ret = PTR_ERR(gmac->regmap_field);
1173		dev_err(dev, "Unable to map syscon register: %d\n", ret);
1174		return ret;
1175	}
1176
1177	plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1178	if (IS_ERR(plat_dat))
1179		return PTR_ERR(plat_dat);
1180
1181	/* platform data specifying hardware features and callbacks.
1182	 * hardware features were copied from Allwinner drivers.
1183	 */
1184	plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1185	plat_dat->tx_coe = 1;
1186	plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I;
1187	plat_dat->bsp_priv = gmac;
1188	plat_dat->init = sun8i_dwmac_init;
1189	plat_dat->exit = sun8i_dwmac_exit;
1190	plat_dat->mac_setup = sun8i_dwmac_setup;
1191	plat_dat->tx_fifo_size = 4096;
1192	plat_dat->rx_fifo_size = 16384;
1193
1194	ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat);
1195	if (ret)
1196		return ret;
1197
1198	ret = stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
1199	if (ret)
1200		goto dwmac_syscon;
1201
1202	ndev = dev_get_drvdata(&pdev->dev);
1203	priv = netdev_priv(ndev);
1204
1205	/* the MAC is runtime suspended after stmmac_dvr_probe(), so we
1206	 * need to ensure the MAC resume back before other operations such
1207	 * as reset.
1208	 */
1209	pm_runtime_get_sync(&pdev->dev);
1210
1211	/* The mux must be registered after parent MDIO
1212	 * so after stmmac_dvr_probe()
1213	 */
1214	if (gmac->variant->soc_has_internal_phy) {
1215		ret = get_ephy_nodes(priv);
1216		if (ret)
1217			goto dwmac_remove;
1218		ret = sun8i_dwmac_register_mdio_mux(priv);
1219		if (ret) {
1220			dev_err(&pdev->dev, "Failed to register mux\n");
1221			goto dwmac_mux;
1222		}
1223	} else {
1224		ret = sun8i_dwmac_reset(priv);
1225		if (ret)
1226			goto dwmac_remove;
1227	}
1228
1229	pm_runtime_put(&pdev->dev);
1230
1231	return 0;
1232
1233dwmac_mux:
1234	reset_control_put(gmac->rst_ephy);
1235	clk_put(gmac->ephy_clk);
1236dwmac_remove:
1237	pm_runtime_put_noidle(&pdev->dev);
1238	stmmac_pltfr_remove(pdev);
1239dwmac_syscon:
1240	sun8i_dwmac_unset_syscon(gmac);
1241
1242	return ret;
1243}
1244
1245static void sun8i_dwmac_remove(struct platform_device *pdev)
1246{
1247	struct net_device *ndev = platform_get_drvdata(pdev);
1248	struct stmmac_priv *priv = netdev_priv(ndev);
1249	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
1250
1251	if (gmac->variant->soc_has_internal_phy) {
1252		mdio_mux_uninit(gmac->mux_handle);
1253		sun8i_dwmac_unpower_internal_phy(gmac);
1254		reset_control_put(gmac->rst_ephy);
1255		clk_put(gmac->ephy_clk);
1256	}
1257
1258	stmmac_pltfr_remove(pdev);
1259	sun8i_dwmac_unset_syscon(gmac);
1260}
1261
1262static void sun8i_dwmac_shutdown(struct platform_device *pdev)
1263{
1264	struct net_device *ndev = platform_get_drvdata(pdev);
1265	struct stmmac_priv *priv = netdev_priv(ndev);
1266	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
1267
1268	sun8i_dwmac_exit(&pdev->dev, gmac);
1269}
1270
1271static const struct of_device_id sun8i_dwmac_match[] = {
1272	{ .compatible = "allwinner,sun8i-h3-emac",
1273		.data = &emac_variant_h3 },
1274	{ .compatible = "allwinner,sun8i-v3s-emac",
1275		.data = &emac_variant_v3s },
1276	{ .compatible = "allwinner,sun8i-a83t-emac",
1277		.data = &emac_variant_a83t },
1278	{ .compatible = "allwinner,sun8i-r40-gmac",
1279		.data = &emac_variant_r40 },
1280	{ .compatible = "allwinner,sun50i-a64-emac",
1281		.data = &emac_variant_a64 },
1282	{ .compatible = "allwinner,sun50i-h6-emac",
1283		.data = &emac_variant_h6 },
1284	{ }
1285};
1286MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1287
1288static struct platform_driver sun8i_dwmac_driver = {
1289	.probe  = sun8i_dwmac_probe,
1290	.remove = sun8i_dwmac_remove,
1291	.shutdown = sun8i_dwmac_shutdown,
1292	.driver = {
1293		.name           = "dwmac-sun8i",
1294		.pm		= &stmmac_pltfr_pm_ops,
1295		.of_match_table = sun8i_dwmac_match,
1296	},
1297};
1298module_platform_driver(sun8i_dwmac_driver);
1299
1300MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1301MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1302MODULE_LICENSE("GPL");