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dwmac-qcom-ethqos.c
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linux-6.19.14/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2018-19, Linaro Limited 3 4#include <linux/module.h> 5#include <linux/of.h> 6#include <linux/of_net.h> 7#include <linux/platform_device.h> 8#include <linux/phy.h> 9#include <linux/phy/phy.h> 10 11#include "stmmac.h" 12#include "stmmac_platform.h" 13 14#define RGMII_IO_MACRO_CONFIG 0x0 15#define SDCC_HC_REG_DLL_CONFIG 0x4 16#define SDCC_TEST_CTL 0x8 17#define SDCC_HC_REG_DDR_CONFIG 0xC 18#define SDCC_HC_REG_DLL_CONFIG2 0x10 19#define SDC4_STATUS 0x14 20#define SDCC_USR_CTL 0x18 21#define RGMII_IO_MACRO_CONFIG2 0x1C 22#define RGMII_IO_MACRO_DEBUG1 0x20 23#define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 24#define EMAC_WRAPPER_SGMII_PHY_CNTRL1 0xf4 25 26/* RGMII_IO_MACRO_CONFIG fields */ 27#define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 28#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 29#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 30#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 31#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 32#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 33#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 34#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 35#define RGMII_CONFIG_LOOPBACK_EN BIT(2) 36#define RGMII_CONFIG_PROG_SWAP BIT(1) 37#define RGMII_CONFIG_DDR_MODE BIT(0) 38#define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10) 39 40/* SDCC_HC_REG_DLL_CONFIG fields */ 41#define SDCC_DLL_CONFIG_DLL_RST BIT(30) 42#define SDCC_DLL_CONFIG_PDN BIT(29) 43#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 44#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 45#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 46#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 47#define SDCC_DLL_CONFIG_CDR_EN BIT(17) 48#define SDCC_DLL_CONFIG_DLL_EN BIT(16) 49#define SDCC_DLL_MCLK_GATING_EN BIT(5) 50#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 51 52/* SDCC_HC_REG_DDR_CONFIG fields */ 53#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 54#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 55#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 56#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 57#define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 58#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 59 60/* SDCC_HC_REG_DLL_CONFIG2 fields */ 61#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 62#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 63#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 64#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 65#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 66 67/* SDC4_STATUS bits */ 68#define SDC4_STATUS_DLL_LOCK BIT(7) 69 70/* RGMII_IO_MACRO_CONFIG2 fields */ 71#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 72#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 73#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 74#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 75#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 76#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 77#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 78 79/* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */ 80#define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN BIT(3) 81 82#define SGMII_10M_RX_CLK_DVDR 0x31 83 84struct ethqos_emac_por { 85 unsigned int offset; 86 unsigned int value; 87}; 88 89struct ethqos_emac_driver_data { 90 const struct ethqos_emac_por *por; 91 unsigned int num_por; 92 bool rgmii_config_loopback_en; 93 bool has_emac_ge_3; 94 const char *link_clk_name; 95 u32 dma_addr_width; 96 struct dwmac4_addrs dwmac4_addrs; 97 bool needs_sgmii_loopback; 98}; 99 100struct qcom_ethqos { 101 struct platform_device *pdev; 102 void __iomem *rgmii_base; 103 void __iomem *mac_base; 104 int (*configure_func)(struct qcom_ethqos *ethqos, int speed); 105 106 unsigned int link_clk_rate; 107 struct clk *link_clk; 108 struct phy *serdes_phy; 109 int serdes_speed; 110 phy_interface_t phy_mode; 111 112 const struct ethqos_emac_por *por; 113 unsigned int num_por; 114 bool rgmii_config_loopback_en; 115 bool has_emac_ge_3; 116 bool needs_sgmii_loopback; 117}; 118 119static u32 rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 120{ 121 return readl(ethqos->rgmii_base + offset); 122} 123 124static void rgmii_writel(struct qcom_ethqos *ethqos, u32 value, 125 unsigned int offset) 126{ 127 writel(value, ethqos->rgmii_base + offset); 128} 129 130static void rgmii_updatel(struct qcom_ethqos *ethqos, u32 mask, u32 val, 131 unsigned int offset) 132{ 133 u32 temp; 134 135 temp = rgmii_readl(ethqos, offset); 136 temp = (temp & ~(mask)) | val; 137 rgmii_writel(ethqos, temp, offset); 138} 139 140static void rgmii_setmask(struct qcom_ethqos *ethqos, u32 mask, 141 unsigned int offset) 142{ 143 rgmii_updatel(ethqos, mask, mask, offset); 144} 145 146static void rgmii_clrmask(struct qcom_ethqos *ethqos, u32 mask, 147 unsigned int offset) 148{ 149 rgmii_updatel(ethqos, mask, 0, offset); 150} 151 152static void rgmii_dump(void *priv) 153{ 154 struct qcom_ethqos *ethqos = priv; 155 struct device *dev = ðqos->pdev->dev; 156 157 dev_dbg(dev, "Rgmii register dump\n"); 158 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n", 159 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 160 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 161 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 162 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 163 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 164 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 165 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 166 dev_dbg(dev, "SDC4_STATUS: %x\n", 167 rgmii_readl(ethqos, SDC4_STATUS)); 168 dev_dbg(dev, "SDCC_USR_CTL: %x\n", 169 rgmii_readl(ethqos, SDCC_USR_CTL)); 170 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 171 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 172 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 173 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 174 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 175 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 176} 177 178static void 179ethqos_update_link_clk(struct qcom_ethqos *ethqos, int speed) 180{ 181 long rate; 182 183 if (!phy_interface_mode_is_rgmii(ethqos->phy_mode)) 184 return; 185 186 rate = rgmii_clock(speed); 187 if (rate > 0) 188 ethqos->link_clk_rate = rate * 2; 189 190 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate); 191} 192 193static void 194qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable) 195{ 196 if (!ethqos->needs_sgmii_loopback || 197 ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX) 198 return; 199 200 rgmii_updatel(ethqos, 201 SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN, 202 enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0, 203 EMAC_WRAPPER_SGMII_PHY_CNTRL1); 204} 205 206static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 207{ 208 qcom_ethqos_set_sgmii_loopback(ethqos, true); 209 rgmii_setmask(ethqos, RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 210} 211 212static const struct ethqos_emac_por emac_v2_3_0_por[] = { 213 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 214 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 215 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 216 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 217 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 218 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 219}; 220 221static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 222 .por = emac_v2_3_0_por, 223 .num_por = ARRAY_SIZE(emac_v2_3_0_por), 224 .rgmii_config_loopback_en = true, 225 .has_emac_ge_3 = false, 226}; 227 228static const struct ethqos_emac_por emac_v2_1_0_por[] = { 229 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 230 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 231 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 232 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 233 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 234 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 235}; 236 237static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 238 .por = emac_v2_1_0_por, 239 .num_por = ARRAY_SIZE(emac_v2_1_0_por), 240 .rgmii_config_loopback_en = false, 241 .has_emac_ge_3 = false, 242}; 243 244static const struct ethqos_emac_por emac_v3_0_0_por[] = { 245 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 246 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 247 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 248 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 249 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 250 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 251}; 252 253static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 254 .por = emac_v3_0_0_por, 255 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 256 .rgmii_config_loopback_en = false, 257 .has_emac_ge_3 = true, 258 .dwmac4_addrs = { 259 .dma_chan = 0x00008100, 260 .dma_chan_offset = 0x1000, 261 .mtl_chan = 0x00008000, 262 .mtl_chan_offset = 0x1000, 263 .mtl_ets_ctrl = 0x00008010, 264 .mtl_ets_ctrl_offset = 0x1000, 265 .mtl_txq_weight = 0x00008018, 266 .mtl_txq_weight_offset = 0x1000, 267 .mtl_send_slp_cred = 0x0000801c, 268 .mtl_send_slp_cred_offset = 0x1000, 269 .mtl_high_cred = 0x00008020, 270 .mtl_high_cred_offset = 0x1000, 271 .mtl_low_cred = 0x00008024, 272 .mtl_low_cred_offset = 0x1000, 273 }, 274}; 275 276static const struct ethqos_emac_por emac_v4_0_0_por[] = { 277 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 278 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 279 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 280 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 281 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 282 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 283}; 284 285static const struct ethqos_emac_driver_data emac_v4_0_0_data = { 286 .por = emac_v4_0_0_por, 287 .num_por = ARRAY_SIZE(emac_v4_0_0_por), 288 .rgmii_config_loopback_en = false, 289 .has_emac_ge_3 = true, 290 .link_clk_name = "phyaux", 291 .needs_sgmii_loopback = true, 292 .dma_addr_width = 36, 293 .dwmac4_addrs = { 294 .dma_chan = 0x00008100, 295 .dma_chan_offset = 0x1000, 296 .mtl_chan = 0x00008000, 297 .mtl_chan_offset = 0x1000, 298 .mtl_ets_ctrl = 0x00008010, 299 .mtl_ets_ctrl_offset = 0x1000, 300 .mtl_txq_weight = 0x00008018, 301 .mtl_txq_weight_offset = 0x1000, 302 .mtl_send_slp_cred = 0x0000801c, 303 .mtl_send_slp_cred_offset = 0x1000, 304 .mtl_high_cred = 0x00008020, 305 .mtl_high_cred_offset = 0x1000, 306 .mtl_low_cred = 0x00008024, 307 .mtl_low_cred_offset = 0x1000, 308 }, 309}; 310 311static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 312{ 313 struct device *dev = ðqos->pdev->dev; 314 u32 val; 315 316 /* Set CDR_EN */ 317 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 318 319 /* Set CDR_EXT_EN */ 320 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 321 SDCC_HC_REG_DLL_CONFIG); 322 323 /* Clear CK_OUT_EN */ 324 rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 325 SDCC_HC_REG_DLL_CONFIG); 326 327 /* Set DLL_EN */ 328 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 329 330 if (!ethqos->has_emac_ge_3) { 331 rgmii_clrmask(ethqos, SDCC_DLL_MCLK_GATING_EN, 332 SDCC_HC_REG_DLL_CONFIG); 333 334 rgmii_clrmask(ethqos, SDCC_DLL_CDR_FINE_PHASE, 335 SDCC_HC_REG_DLL_CONFIG); 336 } 337 338 /* Wait for CK_OUT_EN clear */ 339 if (read_poll_timeout_atomic(rgmii_readl, val, 340 !(val & SDCC_DLL_CONFIG_CK_OUT_EN), 341 1000, 1000000, false, 342 ethqos, SDCC_HC_REG_DLL_CONFIG)) 343 dev_err(dev, "Clear CK_OUT_EN timedout\n"); 344 345 /* Set CK_OUT_EN */ 346 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 347 SDCC_HC_REG_DLL_CONFIG); 348 349 /* Wait for CK_OUT_EN set */ 350 if (read_poll_timeout_atomic(rgmii_readl, val, 351 val & SDCC_DLL_CONFIG_CK_OUT_EN, 352 1000, 1000000, false, 353 ethqos, SDCC_HC_REG_DLL_CONFIG)) 354 dev_err(dev, "Set CK_OUT_EN timedout\n"); 355 356 /* Set DDR_CAL_EN */ 357 rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 358 SDCC_HC_REG_DLL_CONFIG2); 359 360 if (!ethqos->has_emac_ge_3) { 361 rgmii_clrmask(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 362 SDCC_HC_REG_DLL_CONFIG2); 363 364 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 365 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 366 367 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 368 BIT(2), SDCC_HC_REG_DLL_CONFIG2); 369 370 rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 371 SDCC_HC_REG_DLL_CONFIG2); 372 } 373 374 return 0; 375} 376 377static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) 378{ 379 struct device *dev = ðqos->pdev->dev; 380 int phase_shift; 381 int loopback; 382 383 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 384 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 385 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 386 phase_shift = 0; 387 else 388 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 389 390 /* Disable loopback mode */ 391 rgmii_clrmask(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 392 RGMII_IO_MACRO_CONFIG2); 393 394 /* Determine if this platform wants loopback enabled after programming */ 395 if (ethqos->rgmii_config_loopback_en) 396 loopback = RGMII_CONFIG_LOOPBACK_EN; 397 else 398 loopback = 0; 399 400 /* Select RGMII, write 0 to interface select */ 401 rgmii_clrmask(ethqos, RGMII_CONFIG_INTF_SEL, RGMII_IO_MACRO_CONFIG); 402 403 switch (speed) { 404 case SPEED_1000: 405 rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, 406 RGMII_IO_MACRO_CONFIG); 407 rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 408 RGMII_IO_MACRO_CONFIG); 409 rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 410 RGMII_IO_MACRO_CONFIG); 411 rgmii_setmask(ethqos, RGMII_CONFIG_PROG_SWAP, 412 RGMII_IO_MACRO_CONFIG); 413 rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 414 RGMII_IO_MACRO_CONFIG2); 415 416 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 417 phase_shift, RGMII_IO_MACRO_CONFIG2); 418 rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 419 RGMII_IO_MACRO_CONFIG2); 420 rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 421 RGMII_IO_MACRO_CONFIG2); 422 423 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 424 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 425 */ 426 if (ethqos->has_emac_ge_3) { 427 /* 0.9 ns */ 428 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 429 115, SDCC_HC_REG_DDR_CONFIG); 430 } else { 431 /* 1.8 ns */ 432 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 433 57, SDCC_HC_REG_DDR_CONFIG); 434 } 435 rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 436 SDCC_HC_REG_DDR_CONFIG); 437 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 438 loopback, RGMII_IO_MACRO_CONFIG); 439 break; 440 441 case SPEED_100: 442 rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, 443 RGMII_IO_MACRO_CONFIG); 444 rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 445 RGMII_IO_MACRO_CONFIG); 446 rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 447 RGMII_IO_MACRO_CONFIG); 448 rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP, 449 RGMII_IO_MACRO_CONFIG); 450 rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 451 RGMII_IO_MACRO_CONFIG2); 452 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 453 phase_shift, RGMII_IO_MACRO_CONFIG2); 454 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 455 BIT(6), RGMII_IO_MACRO_CONFIG); 456 rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 457 RGMII_IO_MACRO_CONFIG2); 458 459 if (ethqos->has_emac_ge_3) 460 rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 461 RGMII_IO_MACRO_CONFIG2); 462 else 463 rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 464 RGMII_IO_MACRO_CONFIG2); 465 466 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 467 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 468 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 469 rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 470 SDCC_HC_REG_DDR_CONFIG); 471 rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 472 SDCC_HC_REG_DDR_CONFIG); 473 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 474 loopback, RGMII_IO_MACRO_CONFIG); 475 break; 476 477 case SPEED_10: 478 rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, 479 RGMII_IO_MACRO_CONFIG); 480 rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 481 RGMII_IO_MACRO_CONFIG); 482 rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 483 RGMII_IO_MACRO_CONFIG); 484 rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP, 485 RGMII_IO_MACRO_CONFIG); 486 rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 487 RGMII_IO_MACRO_CONFIG2); 488 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 489 phase_shift, RGMII_IO_MACRO_CONFIG2); 490 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 491 BIT(12) | GENMASK(9, 8), 492 RGMII_IO_MACRO_CONFIG); 493 rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 494 RGMII_IO_MACRO_CONFIG2); 495 if (ethqos->has_emac_ge_3) 496 rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 497 RGMII_IO_MACRO_CONFIG2); 498 else 499 rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 500 RGMII_IO_MACRO_CONFIG2); 501 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 502 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 503 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 504 rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 505 SDCC_HC_REG_DDR_CONFIG); 506 rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 507 SDCC_HC_REG_DDR_CONFIG); 508 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 509 loopback, RGMII_IO_MACRO_CONFIG); 510 break; 511 default: 512 dev_err(dev, "Invalid speed %d\n", speed); 513 return -EINVAL; 514 } 515 516 return 0; 517} 518 519static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed) 520{ 521 struct device *dev = ðqos->pdev->dev; 522 unsigned int i; 523 u32 val; 524 525 /* Reset to POR values and enable clk */ 526 for (i = 0; i < ethqos->num_por; i++) 527 rgmii_writel(ethqos, ethqos->por[i].value, 528 ethqos->por[i].offset); 529 ethqos_set_func_clk_en(ethqos); 530 531 /* Initialize the DLL first */ 532 533 /* Set DLL_RST */ 534 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_RST, 535 SDCC_HC_REG_DLL_CONFIG); 536 537 /* Set PDN */ 538 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_PDN, 539 SDCC_HC_REG_DLL_CONFIG); 540 541 if (ethqos->has_emac_ge_3) { 542 if (speed == SPEED_1000) { 543 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 544 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 545 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 546 } else { 547 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 548 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 549 } 550 } 551 552 /* Clear DLL_RST */ 553 rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 554 555 /* Clear PDN */ 556 rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 557 558 if (speed != SPEED_100 && speed != SPEED_10) { 559 /* Set DLL_EN */ 560 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN, 561 SDCC_HC_REG_DLL_CONFIG); 562 563 /* Set CK_OUT_EN */ 564 rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 565 SDCC_HC_REG_DLL_CONFIG); 566 567 /* Set USR_CTL bit 26 with mask of 3 bits */ 568 if (!ethqos->has_emac_ge_3) 569 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 570 SDCC_USR_CTL); 571 572 /* wait for DLL LOCK */ 573 if (read_poll_timeout_atomic(rgmii_readl, val, 574 val & SDC4_STATUS_DLL_LOCK, 575 1000, 1000000, true, 576 ethqos, SDC4_STATUS)) 577 dev_err(dev, "Timeout while waiting for DLL lock\n"); 578 } 579 580 if (speed == SPEED_1000) 581 ethqos_dll_configure(ethqos); 582 583 ethqos_rgmii_macro_init(ethqos, speed); 584 585 return 0; 586} 587 588static void ethqos_set_serdes_speed(struct qcom_ethqos *ethqos, int speed) 589{ 590 if (ethqos->serdes_speed != speed) { 591 phy_set_speed(ethqos->serdes_phy, speed); 592 ethqos->serdes_speed = speed; 593 } 594} 595 596static void ethqos_pcs_set_inband(struct stmmac_priv *priv, bool enable) 597{ 598 stmmac_pcs_ctrl_ane(priv, enable, 0); 599} 600 601/* On interface toggle MAC registers gets reset. 602 * Configure MAC block for SGMII on ethernet phy link up 603 */ 604static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos, int speed) 605{ 606 struct net_device *dev = platform_get_drvdata(ethqos->pdev); 607 struct stmmac_priv *priv = netdev_priv(dev); 608 609 switch (speed) { 610 case SPEED_2500: 611 rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 612 RGMII_IO_MACRO_CONFIG2); 613 ethqos_set_serdes_speed(ethqos, SPEED_2500); 614 ethqos_pcs_set_inband(priv, false); 615 break; 616 case SPEED_1000: 617 rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 618 RGMII_IO_MACRO_CONFIG2); 619 ethqos_set_serdes_speed(ethqos, SPEED_1000); 620 ethqos_pcs_set_inband(priv, true); 621 break; 622 case SPEED_100: 623 ethqos_set_serdes_speed(ethqos, SPEED_1000); 624 ethqos_pcs_set_inband(priv, true); 625 break; 626 case SPEED_10: 627 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR, 628 FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 629 SGMII_10M_RX_CLK_DVDR), 630 RGMII_IO_MACRO_CONFIG); 631 ethqos_set_serdes_speed(ethqos, SPEED_1000); 632 ethqos_pcs_set_inband(priv, true); 633 break; 634 } 635 636 return 0; 637} 638 639static int ethqos_configure(struct qcom_ethqos *ethqos, int speed) 640{ 641 return ethqos->configure_func(ethqos, speed); 642} 643 644static void ethqos_fix_mac_speed(void *priv, int speed, unsigned int mode) 645{ 646 struct qcom_ethqos *ethqos = priv; 647 648 qcom_ethqos_set_sgmii_loopback(ethqos, false); 649 ethqos_update_link_clk(ethqos, speed); 650 ethqos_configure(ethqos, speed); 651} 652 653static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) 654{ 655 struct qcom_ethqos *ethqos = priv; 656 int ret; 657 658 ret = phy_init(ethqos->serdes_phy); 659 if (ret) 660 return ret; 661 662 ret = phy_power_on(ethqos->serdes_phy); 663 if (ret) 664 return ret; 665 666 return phy_set_speed(ethqos->serdes_phy, ethqos->serdes_speed); 667} 668 669static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv) 670{ 671 struct qcom_ethqos *ethqos = priv; 672 673 phy_power_off(ethqos->serdes_phy); 674 phy_exit(ethqos->serdes_phy); 675} 676 677static int ethqos_clks_config(void *priv, bool enabled) 678{ 679 struct qcom_ethqos *ethqos = priv; 680 int ret = 0; 681 682 if (enabled) { 683 ret = clk_prepare_enable(ethqos->link_clk); 684 if (ret) { 685 dev_err(ðqos->pdev->dev, "link_clk enable failed\n"); 686 return ret; 687 } 688 689 /* Enable functional clock to prevent DMA reset to timeout due 690 * to lacking PHY clock after the hardware block has been power 691 * cycled. The actual configuration will be adjusted once 692 * ethqos_fix_mac_speed() is invoked. 693 */ 694 ethqos_set_func_clk_en(ethqos); 695 } else { 696 clk_disable_unprepare(ethqos->link_clk); 697 } 698 699 return ret; 700} 701 702static void ethqos_clks_disable(void *data) 703{ 704 ethqos_clks_config(data, false); 705} 706 707static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) 708{ 709 struct plat_stmmacenet_data *plat_dat = priv->plat; 710 int err; 711 712 if (!plat_dat->clk_ptp_ref) 713 return; 714 715 /* Max the PTP ref clock out to get the best resolution possible */ 716 err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX); 717 if (err) 718 netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err); 719 plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref); 720 721 netdev_dbg(priv->dev, "PTP rate %lu\n", plat_dat->clk_ptp_rate); 722} 723 724static int qcom_ethqos_probe(struct platform_device *pdev) 725{ 726 struct device_node *np = pdev->dev.of_node; 727 const struct ethqos_emac_driver_data *data; 728 struct plat_stmmacenet_data *plat_dat; 729 struct stmmac_resources stmmac_res; 730 struct device *dev = &pdev->dev; 731 struct qcom_ethqos *ethqos; 732 int ret, i; 733 734 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 735 if (ret) 736 return dev_err_probe(dev, ret, 737 "Failed to get platform resources\n"); 738 739 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 740 if (IS_ERR(plat_dat)) { 741 return dev_err_probe(dev, PTR_ERR(plat_dat), 742 "dt configuration failed\n"); 743 } 744 745 plat_dat->clks_config = ethqos_clks_config; 746 747 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); 748 if (!ethqos) 749 return -ENOMEM; 750 751 ethqos->phy_mode = plat_dat->phy_interface; 752 switch (ethqos->phy_mode) { 753 case PHY_INTERFACE_MODE_RGMII: 754 case PHY_INTERFACE_MODE_RGMII_ID: 755 case PHY_INTERFACE_MODE_RGMII_RXID: 756 case PHY_INTERFACE_MODE_RGMII_TXID: 757 ethqos->configure_func = ethqos_configure_rgmii; 758 break; 759 case PHY_INTERFACE_MODE_2500BASEX: 760 case PHY_INTERFACE_MODE_SGMII: 761 ethqos->configure_func = ethqos_configure_sgmii; 762 break; 763 default: 764 dev_err(dev, "Unsupported phy mode %s\n", 765 phy_modes(ethqos->phy_mode)); 766 return -EINVAL; 767 } 768 769 ethqos->pdev = pdev; 770 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 771 if (IS_ERR(ethqos->rgmii_base)) 772 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), 773 "Failed to map rgmii resource\n"); 774 775 ethqos->mac_base = stmmac_res.addr; 776 777 data = of_device_get_match_data(dev); 778 ethqos->por = data->por; 779 ethqos->num_por = data->num_por; 780 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 781 ethqos->has_emac_ge_3 = data->has_emac_ge_3; 782 ethqos->needs_sgmii_loopback = data->needs_sgmii_loopback; 783 784 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); 785 if (IS_ERR(ethqos->link_clk)) 786 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), 787 "Failed to get link_clk\n"); 788 789 ret = ethqos_clks_config(ethqos, true); 790 if (ret) 791 return ret; 792 793 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); 794 if (ret) 795 return ret; 796 797 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes"); 798 if (IS_ERR(ethqos->serdes_phy)) 799 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy), 800 "Failed to get serdes phy\n"); 801 802 ethqos->serdes_speed = SPEED_1000; 803 ethqos_update_link_clk(ethqos, SPEED_1000); 804 ethqos_set_func_clk_en(ethqos); 805 806 plat_dat->bsp_priv = ethqos; 807 plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 808 plat_dat->dump_debug_regs = rgmii_dump; 809 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; 810 plat_dat->core_type = DWMAC_CORE_GMAC4; 811 if (ethqos->has_emac_ge_3) 812 plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 813 plat_dat->pmt = 1; 814 if (of_property_read_bool(np, "snps,tso")) 815 plat_dat->flags |= STMMAC_FLAG_TSO_EN; 816 if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 817 plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI; 818 if (data->dma_addr_width) 819 plat_dat->host_dma_width = data->dma_addr_width; 820 821 if (ethqos->serdes_phy) { 822 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup; 823 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; 824 } 825 826 /* Enable TSO on queue0 and enable TBS on rest of the queues */ 827 for (i = 1; i < plat_dat->tx_queues_to_use; i++) 828 plat_dat->tx_queues_cfg[i].tbs_en = 1; 829 830 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); 831} 832 833static const struct of_device_id qcom_ethqos_match[] = { 834 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 835 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, 836 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 837 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 838 { } 839}; 840MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 841 842static struct platform_driver qcom_ethqos_driver = { 843 .probe = qcom_ethqos_probe, 844 .driver = { 845 .name = "qcom-ethqos", 846 .pm = &stmmac_pltfr_pm_ops, 847 .of_match_table = qcom_ethqos_match, 848 }, 849}; 850module_platform_driver(qcom_ethqos_driver); 851 852MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 853MODULE_LICENSE("GPL v2");
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