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dwmac-mediatek.c
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linux-6.19.14/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 */ 5#include <linux/bitfield.h> 6#include <linux/io.h> 7#include <linux/mfd/syscon.h> 8#include <linux/module.h> 9#include <linux/of.h> 10#include <linux/of_net.h> 11#include <linux/platform_device.h> 12#include <linux/regmap.h> 13#include <linux/stmmac.h> 14 15#include "stmmac.h" 16#include "stmmac_platform.h" 17 18/* Peri Configuration register for mt2712 */ 19#define PERI_ETH_PHY_INTF_SEL 0x418 20#define RMII_CLK_SRC_RXC BIT(4) 21#define RMII_CLK_SRC_INTERNAL BIT(5) 22 23#define PERI_ETH_DLY 0x428 24#define ETH_DLY_GTXC_INV BIT(6) 25#define ETH_DLY_GTXC_ENABLE BIT(5) 26#define ETH_DLY_GTXC_STAGES GENMASK(4, 0) 27#define ETH_DLY_TXC_INV BIT(20) 28#define ETH_DLY_TXC_ENABLE BIT(19) 29#define ETH_DLY_TXC_STAGES GENMASK(18, 14) 30#define ETH_DLY_RXC_INV BIT(13) 31#define ETH_DLY_RXC_ENABLE BIT(12) 32#define ETH_DLY_RXC_STAGES GENMASK(11, 7) 33 34#define PERI_ETH_DLY_FINE 0x800 35#define ETH_RMII_DLY_TX_INV BIT(2) 36#define ETH_FINE_DLY_GTXC BIT(1) 37#define ETH_FINE_DLY_RXC BIT(0) 38 39/* Peri Configuration register for mt8195 */ 40#define MT8195_PERI_ETH_CTRL0 0xFD0 41#define MT8195_RMII_CLK_SRC_INTERNAL BIT(28) 42#define MT8195_RMII_CLK_SRC_RXC BIT(27) 43#define MT8195_ETH_INTF_SEL GENMASK(26, 24) 44#define MT8195_RGMII_TXC_PHASE_CTRL BIT(22) 45#define MT8195_EXT_PHY_MODE BIT(21) 46#define MT8195_DLY_GTXC_INV BIT(12) 47#define MT8195_DLY_GTXC_ENABLE BIT(5) 48#define MT8195_DLY_GTXC_STAGES GENMASK(4, 0) 49 50#define MT8195_PERI_ETH_CTRL1 0xFD4 51#define MT8195_DLY_RXC_INV BIT(25) 52#define MT8195_DLY_RXC_ENABLE BIT(18) 53#define MT8195_DLY_RXC_STAGES GENMASK(17, 13) 54#define MT8195_DLY_TXC_INV BIT(12) 55#define MT8195_DLY_TXC_ENABLE BIT(5) 56#define MT8195_DLY_TXC_STAGES GENMASK(4, 0) 57 58#define MT8195_PERI_ETH_CTRL2 0xFD8 59#define MT8195_DLY_RMII_RXC_INV BIT(25) 60#define MT8195_DLY_RMII_RXC_ENABLE BIT(18) 61#define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13) 62#define MT8195_DLY_RMII_TXC_INV BIT(12) 63#define MT8195_DLY_RMII_TXC_ENABLE BIT(5) 64#define MT8195_DLY_RMII_TXC_STAGES GENMASK(4, 0) 65 66struct mac_delay_struct { 67 u32 tx_delay; 68 u32 rx_delay; 69 bool tx_inv; 70 bool rx_inv; 71}; 72 73struct mediatek_dwmac_plat_data { 74 const struct mediatek_dwmac_variant *variant; 75 struct mac_delay_struct mac_delay; 76 struct clk *rmii_internal_clk; 77 struct clk_bulk_data *clks; 78 struct regmap *peri_regmap; 79 struct device_node *np; 80 struct device *dev; 81 phy_interface_t phy_mode; 82 bool rmii_clk_from_mac; 83 bool rmii_rxc; 84 bool mac_wol; 85}; 86 87struct mediatek_dwmac_variant { 88 int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat, 89 u8 phy_intf_sel); 90 int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat); 91 92 /* clock ids to be requested */ 93 const char * const *clk_list; 94 int num_clks; 95 96 u32 dma_bit_mask; 97 u32 rx_delay_max; 98 u32 tx_delay_max; 99}; 100 101/* list of clocks required for mac */ 102static const char * const mt2712_dwmac_clk_l[] = { 103 "axi", "apb", "mac_main", "ptp_ref" 104}; 105 106static const char * const mt8195_dwmac_clk_l[] = { 107 "axi", "apb", "mac_cg", "mac_main", "ptp_ref" 108}; 109 110static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat, 111 u8 phy_intf_sel) 112{ 113 u32 intf_val = phy_intf_sel; 114 115 if (phy_intf_sel == PHY_INTF_SEL_RMII) { 116 if (plat->rmii_clk_from_mac) 117 intf_val |= RMII_CLK_SRC_INTERNAL; 118 if (plat->rmii_rxc) 119 intf_val |= RMII_CLK_SRC_RXC; 120 } 121 122 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); 123 124 return 0; 125} 126 127static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) 128{ 129 struct mac_delay_struct *mac_delay = &plat->mac_delay; 130 131 switch (plat->phy_mode) { 132 case PHY_INTERFACE_MODE_MII: 133 case PHY_INTERFACE_MODE_RMII: 134 /* 550ps per stage for MII/RMII */ 135 mac_delay->tx_delay /= 550; 136 mac_delay->rx_delay /= 550; 137 break; 138 case PHY_INTERFACE_MODE_RGMII: 139 case PHY_INTERFACE_MODE_RGMII_TXID: 140 case PHY_INTERFACE_MODE_RGMII_RXID: 141 case PHY_INTERFACE_MODE_RGMII_ID: 142 /* 170ps per stage for RGMII */ 143 mac_delay->tx_delay /= 170; 144 mac_delay->rx_delay /= 170; 145 break; 146 default: 147 dev_err(plat->dev, "phy interface not supported\n"); 148 break; 149 } 150} 151 152static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) 153{ 154 struct mac_delay_struct *mac_delay = &plat->mac_delay; 155 156 switch (plat->phy_mode) { 157 case PHY_INTERFACE_MODE_MII: 158 case PHY_INTERFACE_MODE_RMII: 159 /* 550ps per stage for MII/RMII */ 160 mac_delay->tx_delay *= 550; 161 mac_delay->rx_delay *= 550; 162 break; 163 case PHY_INTERFACE_MODE_RGMII: 164 case PHY_INTERFACE_MODE_RGMII_TXID: 165 case PHY_INTERFACE_MODE_RGMII_RXID: 166 case PHY_INTERFACE_MODE_RGMII_ID: 167 /* 170ps per stage for RGMII */ 168 mac_delay->tx_delay *= 170; 169 mac_delay->rx_delay *= 170; 170 break; 171 default: 172 dev_err(plat->dev, "phy interface not supported\n"); 173 break; 174 } 175} 176 177static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) 178{ 179 struct mac_delay_struct *mac_delay = &plat->mac_delay; 180 u32 delay_val = 0, fine_val = 0; 181 182 mt2712_delay_ps2stage(plat); 183 184 switch (plat->phy_mode) { 185 case PHY_INTERFACE_MODE_MII: 186 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); 187 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); 188 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); 189 190 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 191 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); 192 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); 193 break; 194 case PHY_INTERFACE_MODE_RMII: 195 if (plat->rmii_clk_from_mac) { 196 /* case 1: mac provides the rmii reference clock, 197 * and the clock output to TXC pin. 198 * The egress timing can be adjusted by GTXC delay macro circuit. 199 * The ingress timing can be adjusted by TXC delay macro circuit. 200 */ 201 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); 202 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); 203 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); 204 205 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); 206 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); 207 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); 208 } else { 209 /* case 2: the rmii reference clock is from external phy, 210 * and the property "rmii_rxc" indicates which pin(TXC/RXC) 211 * the reference clk is connected to. The reference clock is a 212 * received signal, so rx_delay/rx_inv are used to indicate 213 * the reference clock timing adjustment 214 */ 215 if (plat->rmii_rxc) { 216 /* the rmii reference clock from outside is connected 217 * to RXC pin, the reference clock will be adjusted 218 * by RXC delay macro circuit. 219 */ 220 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 221 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); 222 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); 223 } else { 224 /* the rmii reference clock from outside is connected 225 * to TXC pin, the reference clock will be adjusted 226 * by TXC delay macro circuit. 227 */ 228 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); 229 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); 230 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); 231 } 232 /* tx_inv will inverse the tx clock inside mac relateive to 233 * reference clock from external phy, 234 * and this bit is located in the same register with fine-tune 235 */ 236 if (mac_delay->tx_inv) 237 fine_val = ETH_RMII_DLY_TX_INV; 238 } 239 break; 240 case PHY_INTERFACE_MODE_RGMII: 241 case PHY_INTERFACE_MODE_RGMII_TXID: 242 case PHY_INTERFACE_MODE_RGMII_RXID: 243 case PHY_INTERFACE_MODE_RGMII_ID: 244 fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC; 245 246 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); 247 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); 248 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); 249 250 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 251 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); 252 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); 253 break; 254 default: 255 dev_err(plat->dev, "phy interface not supported\n"); 256 return -EINVAL; 257 } 258 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val); 259 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val); 260 261 mt2712_delay_stage2ps(plat); 262 263 return 0; 264} 265 266static const struct mediatek_dwmac_variant mt2712_gmac_variant = { 267 .dwmac_set_phy_interface = mt2712_set_interface, 268 .dwmac_set_delay = mt2712_set_delay, 269 .clk_list = mt2712_dwmac_clk_l, 270 .num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l), 271 .dma_bit_mask = 33, 272 .rx_delay_max = 17600, 273 .tx_delay_max = 17600, 274}; 275 276static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, 277 u8 phy_intf_sel) 278{ 279 u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel); 280 281 if (phy_intf_sel == PHY_INTF_SEL_RMII) { 282 if (plat->rmii_clk_from_mac) 283 intf_val |= MT8195_RMII_CLK_SRC_INTERNAL; 284 if (plat->rmii_rxc) 285 intf_val |= MT8195_RMII_CLK_SRC_RXC; 286 } 287 288 /* MT8195 only support external PHY */ 289 intf_val |= MT8195_EXT_PHY_MODE; 290 291 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); 292 293 return 0; 294} 295 296static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) 297{ 298 struct mac_delay_struct *mac_delay = &plat->mac_delay; 299 300 /* 290ps per stage */ 301 mac_delay->tx_delay /= 290; 302 mac_delay->rx_delay /= 290; 303} 304 305static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) 306{ 307 struct mac_delay_struct *mac_delay = &plat->mac_delay; 308 309 /* 290ps per stage */ 310 mac_delay->tx_delay *= 290; 311 mac_delay->rx_delay *= 290; 312} 313 314static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) 315{ 316 struct mac_delay_struct *mac_delay = &plat->mac_delay; 317 u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0; 318 319 mt8195_delay_ps2stage(plat); 320 321 switch (plat->phy_mode) { 322 case PHY_INTERFACE_MODE_MII: 323 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay); 324 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay); 325 delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv); 326 327 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 328 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); 329 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); 330 break; 331 case PHY_INTERFACE_MODE_RMII: 332 if (plat->rmii_clk_from_mac) { 333 /* case 1: mac provides the rmii reference clock, 334 * and the clock output to TXC pin. 335 * The egress timing can be adjusted by RMII_TXC delay macro circuit. 336 * The ingress timing can be adjusted by RMII_RXC delay macro circuit. 337 */ 338 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_ENABLE, 339 !!mac_delay->tx_delay); 340 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_STAGES, 341 mac_delay->tx_delay); 342 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_INV, 343 mac_delay->tx_inv); 344 345 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_ENABLE, 346 !!mac_delay->rx_delay); 347 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_STAGES, 348 mac_delay->rx_delay); 349 rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_INV, 350 mac_delay->rx_inv); 351 } else { 352 /* case 2: the rmii reference clock is from external phy, 353 * and the property "rmii_rxc" indicates which pin(TXC/RXC) 354 * the reference clk is connected to. The reference clock is a 355 * received signal, so rx_delay/rx_inv are used to indicate 356 * the reference clock timing adjustment 357 */ 358 if (plat->rmii_rxc) { 359 /* the rmii reference clock from outside is connected 360 * to RXC pin, the reference clock will be adjusted 361 * by RXC delay macro circuit. 362 */ 363 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, 364 !!mac_delay->rx_delay); 365 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, 366 mac_delay->rx_delay); 367 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, 368 mac_delay->rx_inv); 369 } else { 370 /* the rmii reference clock from outside is connected 371 * to TXC pin, the reference clock will be adjusted 372 * by TXC delay macro circuit. 373 */ 374 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, 375 !!mac_delay->rx_delay); 376 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, 377 mac_delay->rx_delay); 378 delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, 379 mac_delay->rx_inv); 380 } 381 } 382 break; 383 case PHY_INTERFACE_MODE_RGMII: 384 case PHY_INTERFACE_MODE_RGMII_TXID: 385 case PHY_INTERFACE_MODE_RGMII_RXID: 386 case PHY_INTERFACE_MODE_RGMII_ID: 387 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); 388 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay); 389 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv); 390 391 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 392 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); 393 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); 394 395 break; 396 default: 397 dev_err(plat->dev, "phy interface not supported\n"); 398 return -EINVAL; 399 } 400 401 regmap_update_bits(plat->peri_regmap, 402 MT8195_PERI_ETH_CTRL0, 403 MT8195_RGMII_TXC_PHASE_CTRL | 404 MT8195_DLY_GTXC_INV | 405 MT8195_DLY_GTXC_ENABLE | 406 MT8195_DLY_GTXC_STAGES, 407 gtxc_delay_val); 408 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); 409 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); 410 411 mt8195_delay_stage2ps(plat); 412 413 return 0; 414} 415 416static const struct mediatek_dwmac_variant mt8195_gmac_variant = { 417 .dwmac_set_phy_interface = mt8195_set_interface, 418 .dwmac_set_delay = mt8195_set_delay, 419 .clk_list = mt8195_dwmac_clk_l, 420 .num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l), 421 .dma_bit_mask = 35, 422 .rx_delay_max = 9280, 423 .tx_delay_max = 9280, 424}; 425 426static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) 427{ 428 struct mac_delay_struct *mac_delay = &plat->mac_delay; 429 u32 tx_delay_ps, rx_delay_ps; 430 431 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg"); 432 if (IS_ERR(plat->peri_regmap)) { 433 dev_err(plat->dev, "Failed to get pericfg syscon\n"); 434 return PTR_ERR(plat->peri_regmap); 435 } 436 437 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) { 438 if (tx_delay_ps < plat->variant->tx_delay_max) { 439 mac_delay->tx_delay = tx_delay_ps; 440 } else { 441 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); 442 return -EINVAL; 443 } 444 } 445 446 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) { 447 if (rx_delay_ps < plat->variant->rx_delay_max) { 448 mac_delay->rx_delay = rx_delay_ps; 449 } else { 450 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); 451 return -EINVAL; 452 } 453 } 454 455 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse"); 456 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); 457 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); 458 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac"); 459 plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol"); 460 461 return 0; 462} 463 464static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat) 465{ 466 const struct mediatek_dwmac_variant *variant = plat->variant; 467 int i, ret; 468 469 plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL); 470 if (!plat->clks) 471 return -ENOMEM; 472 473 for (i = 0; i < variant->num_clks; i++) 474 plat->clks[i].id = variant->clk_list[i]; 475 476 ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks); 477 if (ret) 478 return ret; 479 480 /* The clock labeled as "rmii_internal" is needed only in RMII(when 481 * MAC provides the reference clock), and useless for RGMII/MII or 482 * RMII(when PHY provides the reference clock). 483 * So, "rmii_internal" clock is got and configured only when 484 * reference clock of RMII is from MAC. 485 */ 486 if (plat->rmii_clk_from_mac) { 487 plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal"); 488 if (IS_ERR(plat->rmii_internal_clk)) 489 ret = PTR_ERR(plat->rmii_internal_clk); 490 } else { 491 plat->rmii_internal_clk = NULL; 492 } 493 494 return ret; 495} 496 497static int mediatek_dwmac_init(struct device *dev, void *priv) 498{ 499 struct mediatek_dwmac_plat_data *plat = priv; 500 const struct mediatek_dwmac_variant *variant = plat->variant; 501 int phy_intf_sel, ret; 502 503 if (variant->dwmac_set_phy_interface) { 504 phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_mode); 505 if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && 506 phy_intf_sel != PHY_INTF_SEL_RGMII && 507 phy_intf_sel != PHY_INTF_SEL_RMII) { 508 dev_err(plat->dev, "phy interface not supported\n"); 509 return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; 510 } 511 512 ret = variant->dwmac_set_phy_interface(plat, phy_intf_sel); 513 if (ret) { 514 dev_err(dev, "failed to set phy interface, err = %d\n", ret); 515 return ret; 516 } 517 } 518 519 if (variant->dwmac_set_delay) { 520 ret = variant->dwmac_set_delay(plat); 521 if (ret) { 522 dev_err(dev, "failed to set delay value, err = %d\n", ret); 523 return ret; 524 } 525 } 526 527 return 0; 528} 529 530static int mediatek_dwmac_clks_config(void *priv, bool enabled) 531{ 532 struct mediatek_dwmac_plat_data *plat = priv; 533 const struct mediatek_dwmac_variant *variant = plat->variant; 534 int ret = 0; 535 536 if (enabled) { 537 ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks); 538 if (ret) { 539 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret); 540 return ret; 541 } 542 543 ret = clk_prepare_enable(plat->rmii_internal_clk); 544 if (ret) { 545 dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret); 546 return ret; 547 } 548 } else { 549 clk_disable_unprepare(plat->rmii_internal_clk); 550 clk_bulk_disable_unprepare(variant->num_clks, plat->clks); 551 } 552 553 return ret; 554} 555 556static int mediatek_dwmac_common_data(struct platform_device *pdev, 557 struct plat_stmmacenet_data *plat, 558 struct mediatek_dwmac_plat_data *priv_plat) 559{ 560 int i; 561 562 priv_plat->phy_mode = plat->phy_interface; 563 if (priv_plat->mac_wol) 564 plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL; 565 else 566 plat->flags |= STMMAC_FLAG_USE_PHY_WOL; 567 plat->riwt_off = 1; 568 plat->maxmtu = ETH_DATA_LEN; 569 plat->host_dma_width = priv_plat->variant->dma_bit_mask; 570 plat->bsp_priv = priv_plat; 571 plat->resume = mediatek_dwmac_init; 572 plat->clks_config = mediatek_dwmac_clks_config; 573 574 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, 575 sizeof(*plat->safety_feat_cfg), 576 GFP_KERNEL); 577 if (!plat->safety_feat_cfg) 578 return -ENOMEM; 579 580 plat->safety_feat_cfg->tsoee = 1; 581 plat->safety_feat_cfg->mrxpee = 0; 582 plat->safety_feat_cfg->mestee = 1; 583 plat->safety_feat_cfg->mrxee = 1; 584 plat->safety_feat_cfg->mtxee = 1; 585 plat->safety_feat_cfg->epsi = 0; 586 plat->safety_feat_cfg->edpp = 1; 587 plat->safety_feat_cfg->prtyen = 1; 588 plat->safety_feat_cfg->tmouten = 1; 589 590 for (i = 0; i < plat->tx_queues_to_use; i++) { 591 /* Default TX Q0 to use TSO and rest TXQ for TBS */ 592 if (i > 0) 593 plat->tx_queues_cfg[i].tbs_en = 1; 594 } 595 596 return 0; 597} 598 599static int mediatek_dwmac_probe(struct platform_device *pdev) 600{ 601 struct mediatek_dwmac_plat_data *priv_plat; 602 struct plat_stmmacenet_data *plat_dat; 603 struct stmmac_resources stmmac_res; 604 int ret; 605 606 priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL); 607 if (!priv_plat) 608 return -ENOMEM; 609 610 priv_plat->variant = of_device_get_match_data(&pdev->dev); 611 if (!priv_plat->variant) { 612 dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n"); 613 return -EINVAL; 614 } 615 616 priv_plat->dev = &pdev->dev; 617 priv_plat->np = pdev->dev.of_node; 618 619 ret = mediatek_dwmac_config_dt(priv_plat); 620 if (ret) 621 return ret; 622 623 ret = mediatek_dwmac_clk_init(priv_plat); 624 if (ret) 625 return ret; 626 627 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 628 if (ret) 629 return ret; 630 631 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 632 if (IS_ERR(plat_dat)) 633 return PTR_ERR(plat_dat); 634 635 mediatek_dwmac_common_data(pdev, plat_dat, priv_plat); 636 mediatek_dwmac_init(&pdev->dev, priv_plat); 637 638 ret = mediatek_dwmac_clks_config(priv_plat, true); 639 if (ret) 640 return ret; 641 642 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 643 if (ret) 644 goto err_drv_probe; 645 646 return 0; 647 648err_drv_probe: 649 mediatek_dwmac_clks_config(priv_plat, false); 650 651 return ret; 652} 653 654static void mediatek_dwmac_remove(struct platform_device *pdev) 655{ 656 struct mediatek_dwmac_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev); 657 658 stmmac_pltfr_remove(pdev); 659 mediatek_dwmac_clks_config(priv_plat, false); 660} 661 662static const struct of_device_id mediatek_dwmac_match[] = { 663 { .compatible = "mediatek,mt2712-gmac", 664 .data = &mt2712_gmac_variant }, 665 { .compatible = "mediatek,mt8195-gmac", 666 .data = &mt8195_gmac_variant }, 667 { } 668}; 669 670MODULE_DEVICE_TABLE(of, mediatek_dwmac_match); 671 672static struct platform_driver mediatek_dwmac_driver = { 673 .probe = mediatek_dwmac_probe, 674 .remove = mediatek_dwmac_remove, 675 .driver = { 676 .name = "dwmac-mediatek", 677 .pm = &stmmac_pltfr_pm_ops, 678 .of_match_table = mediatek_dwmac_match, 679 }, 680}; 681module_platform_driver(mediatek_dwmac_driver); 682 683MODULE_AUTHOR("Biao Huang <biao.huang@mediatek.com>"); 684MODULE_DESCRIPTION("MediaTek DWMAC specific glue layer"); 685MODULE_LICENSE("GPL v2");
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