dwmac-intel.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/* Copyright (c) 2020, Intel Corporation
 3 * DWMAC Intel header file
 4 */
 5
 6#ifndef __DWMAC_INTEL_H__
 7#define __DWMAC_INTEL_H__
 8
 9#define POLL_DELAY_US 8
10
11/* SERDES Register */
12#define SERDES_GCR	0x0	/* Global Conguration */
13#define SERDES_GSR0	0x5	/* Global Status Reg0 */
14#define SERDES_GCR0	0xb	/* Global Configuration Reg0 */
15
16/* SERDES defines */
17#define SERDES_PLL_CLK		BIT(0)		/* PLL clk valid signal */
18#define SERDES_PHY_RX_CLK	BIT(1)		/* PSE SGMII PHY rx clk */
19#define SERDES_RST		BIT(2)		/* Serdes Reset */
20#define SERDES_PWR_ST_MASK	GENMASK(6, 4)	/* Serdes Power state*/
21#define SERDES_RATE_MASK	GENMASK(9, 8)
22#define SERDES_PCLK_MASK	GENMASK(14, 12)	/* PCLK rate to PHY */
23#define SERDES_LINK_MODE_MASK	GENMASK(2, 1)
24#define SERDES_PWR_ST_SHIFT	4
25#define SERDES_PWR_ST_P0	0x0
26#define SERDES_PWR_ST_P3	0x3
27#define SERDES_LINK_MODE_2G5	0x3
28#define SERSED_LINK_MODE_1G	0x2
29#define SERDES_PCLK_37p5MHZ	0x0
30#define SERDES_PCLK_70MHZ	0x1
31#define SERDES_RATE_PCIE_GEN1	0x0
32#define SERDES_RATE_PCIE_GEN2	0x1
33#define SERDES_RATE_PCIE_SHIFT	8
34#define SERDES_PCLK_SHIFT	12
35
36#define INTEL_MGBE_ADHOC_ADDR	0x15
37#define INTEL_MGBE_XPCS_ADDR	0x16
38
39/* Cross-timestamping defines */
40#define ART_CPUID_LEAF		0x15
41#define EHL_PSE_ART_MHZ		19200000
42
43/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
44#define PSE_PTP_CLK_FREQ_MASK		(GMAC_GPO0 | GMAC_GPO3)
45#define PSE_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)
46#define PSE_PTP_CLK_FREQ_200MHZ		(GMAC_GPO0 | GMAC_GPO3)
47#define PSE_PTP_CLK_FREQ_256MHZ		(0)
48#define PCH_PTP_CLK_FREQ_MASK		(GMAC_GPO0)
49#define PCH_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)
50#define PCH_PTP_CLK_FREQ_200MHZ		(0)
51
52/* Modphy Register index */
53#define R_PCH_FIA_15_PCR_LOS1_REG_BASE			8
54#define R_PCH_FIA_15_PCR_LOS2_REG_BASE			9
55#define R_PCH_FIA_15_PCR_LOS3_REG_BASE			10
56#define R_PCH_FIA_15_PCR_LOS4_REG_BASE			11
57#define R_PCH_FIA_15_PCR_LOS5_REG_BASE			12
58#define B_PCH_FIA_PCR_L0O				GENMASK(3, 0)
59#define PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0		13
60#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2		14
61#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7		15
62#define PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10		16
63#define PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30	17
64#define PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0		18
65#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2		19
66#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7		20
67#define PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10		21
68#define PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30	22
69
70#define B_MODPHY_PCR_LCPLL_DWORD0_1G		0x46AAAA41
71#define N_MODPHY_PCR_LCPLL_DWORD2_1G		0x00000139
72#define N_MODPHY_PCR_LCPLL_DWORD7_1G		0x002A0003
73#define N_MODPHY_PCR_LPPLL_DWORD10_1G		0x00170008
74#define N_MODPHY_PCR_CMN_ANA_DWORD30_1G		0x0000D4AC
75#define B_MODPHY_PCR_LCPLL_DWORD0_2P5G		0x58555551
76#define N_MODPHY_PCR_LCPLL_DWORD2_2P5G		0x0000012D
77#define N_MODPHY_PCR_LCPLL_DWORD7_2P5G		0x001F0003
78#define N_MODPHY_PCR_LPPLL_DWORD10_2P5G		0x00170008
79#define N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G	0x8200ACAC
80
81#endif /* __DWMAC_INTEL_H__ */