FILE
k1_emac.c
File preview with syntax highlighting.
linux-6.19.14/drivers/net/ethernet/spacemit/k1_emac.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SpacemiT K1 Ethernet driver 4 * 5 * Copyright (C) 2023-2025 SpacemiT (Hangzhou) Technology Co. Ltd 6 * Copyright (C) 2025 Vivian Wang <wangruikang@iscas.ac.cn> 7 */ 8 9#include <linux/bitfield.h> 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/dma-mapping.h> 13#include <linux/etherdevice.h> 14#include <linux/ethtool.h> 15#include <linux/if_vlan.h> 16#include <linux/interrupt.h> 17#include <linux/io.h> 18#include <linux/iopoll.h> 19#include <linux/kernel.h> 20#include <linux/mfd/syscon.h> 21#include <linux/module.h> 22#include <linux/of.h> 23#include <linux/of_irq.h> 24#include <linux/of_mdio.h> 25#include <linux/of_net.h> 26#include <linux/phy.h> 27#include <linux/platform_device.h> 28#include <linux/pm_runtime.h> 29#include <linux/pm.h> 30#include <linux/regmap.h> 31#include <linux/reset.h> 32#include <linux/rtnetlink.h> 33#include <linux/timer.h> 34#include <linux/types.h> 35 36#include "k1_emac.h" 37 38#define DRIVER_NAME "k1_emac" 39 40#define EMAC_DEFAULT_BUFSIZE 1536 41#define EMAC_RX_BUF_2K 2048 42#define EMAC_RX_BUF_MAX FIELD_MAX(RX_DESC_1_BUFFER_SIZE_1_MASK) 43 44/* Tuning parameters from SpacemiT */ 45#define EMAC_TX_FRAMES 64 46#define EMAC_TX_COAL_TIMEOUT 40000 47#define EMAC_RX_FRAMES 64 48#define EMAC_RX_COAL_TIMEOUT (600 * 312) 49 50#define DEFAULT_FC_PAUSE_TIME 0xffff 51#define DEFAULT_FC_FIFO_HIGH 1600 52#define DEFAULT_TX_ALMOST_FULL 0x1f8 53#define DEFAULT_TX_THRESHOLD 1518 54#define DEFAULT_RX_THRESHOLD 12 55#define DEFAULT_TX_RING_NUM 1024 56#define DEFAULT_RX_RING_NUM 1024 57#define DEFAULT_DMA_BURST MREGBIT_BURST_16WORD 58#define HASH_TABLE_SIZE 64 59 60struct desc_buf { 61 u64 dma_addr; 62 void *buff_addr; 63 u16 dma_len; 64 u8 map_as_page; 65}; 66 67struct emac_tx_desc_buffer { 68 struct sk_buff *skb; 69 struct desc_buf buf[2]; 70}; 71 72struct emac_rx_desc_buffer { 73 struct sk_buff *skb; 74 u64 dma_addr; 75 void *buff_addr; 76 u16 dma_len; 77 u8 map_as_page; 78}; 79 80/** 81 * struct emac_desc_ring - Software-side information for one descriptor ring 82 * Same structure used for both RX and TX 83 * @desc_addr: Virtual address to the descriptor ring memory 84 * @desc_dma_addr: DMA address of the descriptor ring 85 * @total_size: Size of ring in bytes 86 * @total_cnt: Number of descriptors 87 * @head: Next descriptor to associate a buffer with 88 * @tail: Next descriptor to check status bit 89 * @rx_desc_buf: Array of descriptors for RX 90 * @tx_desc_buf: Array of descriptors for TX, with max of two buffers each 91 */ 92struct emac_desc_ring { 93 void *desc_addr; 94 dma_addr_t desc_dma_addr; 95 u32 total_size; 96 u32 total_cnt; 97 u32 head; 98 u32 tail; 99 union { 100 struct emac_rx_desc_buffer *rx_desc_buf; 101 struct emac_tx_desc_buffer *tx_desc_buf; 102 }; 103}; 104 105struct emac_priv { 106 void __iomem *iobase; 107 u32 dma_buf_sz; 108 struct emac_desc_ring tx_ring; 109 struct emac_desc_ring rx_ring; 110 111 struct net_device *ndev; 112 struct napi_struct napi; 113 struct platform_device *pdev; 114 struct clk *bus_clk; 115 struct clk *ref_clk; 116 struct regmap *regmap_apmu; 117 u32 regmap_apmu_offset; 118 int irq; 119 120 phy_interface_t phy_interface; 121 122 union emac_hw_tx_stats tx_stats, tx_stats_off; 123 union emac_hw_rx_stats rx_stats, rx_stats_off; 124 125 u32 tx_count_frames; 126 u32 tx_coal_frames; 127 u32 tx_coal_timeout; 128 struct work_struct tx_timeout_task; 129 130 struct timer_list txtimer; 131 struct timer_list stats_timer; 132 133 u32 tx_delay; 134 u32 rx_delay; 135 136 bool flow_control_autoneg; 137 u8 flow_control; 138 139 /* Softirq-safe, hold while touching hardware statistics */ 140 spinlock_t stats_lock; 141}; 142 143static void emac_wr(struct emac_priv *priv, u32 reg, u32 val) 144{ 145 writel(val, priv->iobase + reg); 146} 147 148static u32 emac_rd(struct emac_priv *priv, u32 reg) 149{ 150 return readl(priv->iobase + reg); 151} 152 153static int emac_phy_interface_config(struct emac_priv *priv) 154{ 155 u32 val = 0, mask = REF_CLK_SEL | RGMII_TX_CLK_SEL | PHY_INTF_RGMII; 156 157 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 158 val |= PHY_INTF_RGMII; 159 160 regmap_update_bits(priv->regmap_apmu, 161 priv->regmap_apmu_offset + APMU_EMAC_CTRL_REG, 162 mask, val); 163 164 return 0; 165} 166 167/* 168 * Where the hardware expects a MAC address, it is laid out in this high, med, 169 * low order in three consecutive registers and in this format. 170 */ 171 172static void emac_set_mac_addr_reg(struct emac_priv *priv, 173 const unsigned char *addr, 174 u32 reg) 175{ 176 emac_wr(priv, reg + sizeof(u32) * 0, addr[1] << 8 | addr[0]); 177 emac_wr(priv, reg + sizeof(u32) * 1, addr[3] << 8 | addr[2]); 178 emac_wr(priv, reg + sizeof(u32) * 2, addr[5] << 8 | addr[4]); 179} 180 181static void emac_set_mac_addr(struct emac_priv *priv, const unsigned char *addr) 182{ 183 /* We use only one address, so set the same for flow control as well */ 184 emac_set_mac_addr_reg(priv, addr, MAC_ADDRESS1_HIGH); 185 emac_set_mac_addr_reg(priv, addr, MAC_FC_SOURCE_ADDRESS_HIGH); 186} 187 188static void emac_reset_hw(struct emac_priv *priv) 189{ 190 /* Disable all interrupts */ 191 emac_wr(priv, MAC_INTERRUPT_ENABLE, 0x0); 192 emac_wr(priv, DMA_INTERRUPT_ENABLE, 0x0); 193 194 /* Disable transmit and receive units */ 195 emac_wr(priv, MAC_RECEIVE_CONTROL, 0x0); 196 emac_wr(priv, MAC_TRANSMIT_CONTROL, 0x0); 197 198 /* Disable DMA */ 199 emac_wr(priv, DMA_CONTROL, 0x0); 200} 201 202static void emac_init_hw(struct emac_priv *priv) 203{ 204 /* Destination address for 802.3x Ethernet flow control */ 205 u8 fc_dest_addr[ETH_ALEN] = { 0x01, 0x80, 0xc2, 0x00, 0x00, 0x01 }; 206 u32 rxirq = 0, dma = 0, frame_sz; 207 208 regmap_set_bits(priv->regmap_apmu, 209 priv->regmap_apmu_offset + APMU_EMAC_CTRL_REG, 210 AXI_SINGLE_ID); 211 212 /* Disable transmit and receive units */ 213 emac_wr(priv, MAC_RECEIVE_CONTROL, 0x0); 214 emac_wr(priv, MAC_TRANSMIT_CONTROL, 0x0); 215 216 /* Enable MAC address 1 filtering */ 217 emac_wr(priv, MAC_ADDRESS_CONTROL, MREGBIT_MAC_ADDRESS1_ENABLE); 218 219 /* Zero initialize the multicast hash table */ 220 emac_wr(priv, MAC_MULTICAST_HASH_TABLE1, 0x0); 221 emac_wr(priv, MAC_MULTICAST_HASH_TABLE2, 0x0); 222 emac_wr(priv, MAC_MULTICAST_HASH_TABLE3, 0x0); 223 emac_wr(priv, MAC_MULTICAST_HASH_TABLE4, 0x0); 224 225 /* Configure thresholds */ 226 emac_wr(priv, MAC_TRANSMIT_FIFO_ALMOST_FULL, DEFAULT_TX_ALMOST_FULL); 227 emac_wr(priv, MAC_TRANSMIT_PACKET_START_THRESHOLD, 228 DEFAULT_TX_THRESHOLD); 229 emac_wr(priv, MAC_RECEIVE_PACKET_START_THRESHOLD, DEFAULT_RX_THRESHOLD); 230 231 /* Set maximum frame size and jabber size based on configured MTU, 232 * accounting for Ethernet header, double VLAN tags, and FCS. 233 */ 234 frame_sz = priv->ndev->mtu + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; 235 236 emac_wr(priv, MAC_MAXIMUM_FRAME_SIZE, frame_sz); 237 emac_wr(priv, MAC_TRANSMIT_JABBER_SIZE, frame_sz); 238 emac_wr(priv, MAC_RECEIVE_JABBER_SIZE, frame_sz); 239 240 /* Configure flow control (enabled in emac_adjust_link() later) */ 241 emac_set_mac_addr_reg(priv, fc_dest_addr, MAC_FC_SOURCE_ADDRESS_HIGH); 242 emac_wr(priv, MAC_FC_PAUSE_HIGH_THRESHOLD, DEFAULT_FC_FIFO_HIGH); 243 emac_wr(priv, MAC_FC_HIGH_PAUSE_TIME, DEFAULT_FC_PAUSE_TIME); 244 emac_wr(priv, MAC_FC_PAUSE_LOW_THRESHOLD, 0); 245 246 /* RX IRQ mitigation */ 247 rxirq = FIELD_PREP(MREGBIT_RECEIVE_IRQ_FRAME_COUNTER_MASK, 248 EMAC_RX_FRAMES); 249 rxirq |= FIELD_PREP(MREGBIT_RECEIVE_IRQ_TIMEOUT_COUNTER_MASK, 250 EMAC_RX_COAL_TIMEOUT); 251 rxirq |= MREGBIT_RECEIVE_IRQ_MITIGATION_ENABLE; 252 emac_wr(priv, DMA_RECEIVE_IRQ_MITIGATION_CTRL, rxirq); 253 254 /* Disable and set DMA config */ 255 emac_wr(priv, DMA_CONTROL, 0x0); 256 257 emac_wr(priv, DMA_CONFIGURATION, MREGBIT_SOFTWARE_RESET); 258 usleep_range(9000, 10000); 259 emac_wr(priv, DMA_CONFIGURATION, 0x0); 260 usleep_range(9000, 10000); 261 262 dma |= MREGBIT_STRICT_BURST; 263 dma |= MREGBIT_DMA_64BIT_MODE; 264 dma |= DEFAULT_DMA_BURST; 265 266 emac_wr(priv, DMA_CONFIGURATION, dma); 267} 268 269static void emac_dma_start_transmit(struct emac_priv *priv) 270{ 271 /* The actual value written does not matter */ 272 emac_wr(priv, DMA_TRANSMIT_POLL_DEMAND, 1); 273} 274 275static void emac_enable_interrupt(struct emac_priv *priv) 276{ 277 u32 val; 278 279 val = emac_rd(priv, DMA_INTERRUPT_ENABLE); 280 val |= MREGBIT_TRANSMIT_TRANSFER_DONE_INTR_ENABLE; 281 val |= MREGBIT_RECEIVE_TRANSFER_DONE_INTR_ENABLE; 282 emac_wr(priv, DMA_INTERRUPT_ENABLE, val); 283} 284 285static void emac_disable_interrupt(struct emac_priv *priv) 286{ 287 u32 val; 288 289 val = emac_rd(priv, DMA_INTERRUPT_ENABLE); 290 val &= ~MREGBIT_TRANSMIT_TRANSFER_DONE_INTR_ENABLE; 291 val &= ~MREGBIT_RECEIVE_TRANSFER_DONE_INTR_ENABLE; 292 emac_wr(priv, DMA_INTERRUPT_ENABLE, val); 293} 294 295static u32 emac_tx_avail(struct emac_priv *priv) 296{ 297 struct emac_desc_ring *tx_ring = &priv->tx_ring; 298 u32 avail; 299 300 if (tx_ring->tail > tx_ring->head) 301 avail = tx_ring->tail - tx_ring->head - 1; 302 else 303 avail = tx_ring->total_cnt - tx_ring->head + tx_ring->tail - 1; 304 305 return avail; 306} 307 308static void emac_tx_coal_timer_resched(struct emac_priv *priv) 309{ 310 mod_timer(&priv->txtimer, 311 jiffies + usecs_to_jiffies(priv->tx_coal_timeout)); 312} 313 314static void emac_tx_coal_timer(struct timer_list *t) 315{ 316 struct emac_priv *priv = timer_container_of(priv, t, txtimer); 317 318 napi_schedule(&priv->napi); 319} 320 321static bool emac_tx_should_interrupt(struct emac_priv *priv, u32 pkt_num) 322{ 323 priv->tx_count_frames += pkt_num; 324 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 325 emac_tx_coal_timer_resched(priv); 326 return false; 327 } 328 329 priv->tx_count_frames = 0; 330 return true; 331} 332 333static void emac_free_tx_buf(struct emac_priv *priv, int i) 334{ 335 struct emac_tx_desc_buffer *tx_buf; 336 struct emac_desc_ring *tx_ring; 337 struct desc_buf *buf; 338 int j; 339 340 tx_ring = &priv->tx_ring; 341 tx_buf = &tx_ring->tx_desc_buf[i]; 342 343 for (j = 0; j < 2; j++) { 344 buf = &tx_buf->buf[j]; 345 if (!buf->dma_addr) 346 continue; 347 348 if (buf->map_as_page) 349 dma_unmap_page(&priv->pdev->dev, buf->dma_addr, 350 buf->dma_len, DMA_TO_DEVICE); 351 else 352 dma_unmap_single(&priv->pdev->dev, 353 buf->dma_addr, buf->dma_len, 354 DMA_TO_DEVICE); 355 356 buf->dma_addr = 0; 357 buf->map_as_page = false; 358 buf->buff_addr = NULL; 359 } 360 361 if (tx_buf->skb) { 362 dev_kfree_skb_any(tx_buf->skb); 363 tx_buf->skb = NULL; 364 } 365} 366 367static void emac_clean_tx_desc_ring(struct emac_priv *priv) 368{ 369 struct emac_desc_ring *tx_ring = &priv->tx_ring; 370 u32 i; 371 372 for (i = 0; i < tx_ring->total_cnt; i++) 373 emac_free_tx_buf(priv, i); 374 375 tx_ring->head = 0; 376 tx_ring->tail = 0; 377} 378 379static void emac_clean_rx_desc_ring(struct emac_priv *priv) 380{ 381 struct emac_rx_desc_buffer *rx_buf; 382 struct emac_desc_ring *rx_ring; 383 u32 i; 384 385 rx_ring = &priv->rx_ring; 386 387 for (i = 0; i < rx_ring->total_cnt; i++) { 388 rx_buf = &rx_ring->rx_desc_buf[i]; 389 390 if (!rx_buf->skb) 391 continue; 392 393 dma_unmap_single(&priv->pdev->dev, rx_buf->dma_addr, 394 rx_buf->dma_len, DMA_FROM_DEVICE); 395 396 dev_kfree_skb(rx_buf->skb); 397 rx_buf->skb = NULL; 398 } 399 400 rx_ring->tail = 0; 401 rx_ring->head = 0; 402} 403 404static int emac_alloc_tx_resources(struct emac_priv *priv) 405{ 406 struct emac_desc_ring *tx_ring = &priv->tx_ring; 407 struct platform_device *pdev = priv->pdev; 408 409 tx_ring->tx_desc_buf = kcalloc(tx_ring->total_cnt, 410 sizeof(*tx_ring->tx_desc_buf), 411 GFP_KERNEL); 412 413 if (!tx_ring->tx_desc_buf) 414 return -ENOMEM; 415 416 tx_ring->total_size = tx_ring->total_cnt * sizeof(struct emac_desc); 417 tx_ring->total_size = ALIGN(tx_ring->total_size, PAGE_SIZE); 418 419 tx_ring->desc_addr = dma_alloc_coherent(&pdev->dev, tx_ring->total_size, 420 &tx_ring->desc_dma_addr, 421 GFP_KERNEL); 422 if (!tx_ring->desc_addr) { 423 kfree(tx_ring->tx_desc_buf); 424 return -ENOMEM; 425 } 426 427 tx_ring->head = 0; 428 tx_ring->tail = 0; 429 430 return 0; 431} 432 433static int emac_alloc_rx_resources(struct emac_priv *priv) 434{ 435 struct emac_desc_ring *rx_ring = &priv->rx_ring; 436 struct platform_device *pdev = priv->pdev; 437 438 rx_ring->rx_desc_buf = kcalloc(rx_ring->total_cnt, 439 sizeof(*rx_ring->rx_desc_buf), 440 GFP_KERNEL); 441 if (!rx_ring->rx_desc_buf) 442 return -ENOMEM; 443 444 rx_ring->total_size = rx_ring->total_cnt * sizeof(struct emac_desc); 445 446 rx_ring->total_size = ALIGN(rx_ring->total_size, PAGE_SIZE); 447 448 rx_ring->desc_addr = dma_alloc_coherent(&pdev->dev, rx_ring->total_size, 449 &rx_ring->desc_dma_addr, 450 GFP_KERNEL); 451 if (!rx_ring->desc_addr) { 452 kfree(rx_ring->rx_desc_buf); 453 return -ENOMEM; 454 } 455 456 rx_ring->head = 0; 457 rx_ring->tail = 0; 458 459 return 0; 460} 461 462static void emac_free_tx_resources(struct emac_priv *priv) 463{ 464 struct emac_desc_ring *tr = &priv->tx_ring; 465 struct device *dev = &priv->pdev->dev; 466 467 emac_clean_tx_desc_ring(priv); 468 469 kfree(tr->tx_desc_buf); 470 tr->tx_desc_buf = NULL; 471 472 dma_free_coherent(dev, tr->total_size, tr->desc_addr, 473 tr->desc_dma_addr); 474 tr->desc_addr = NULL; 475} 476 477static void emac_free_rx_resources(struct emac_priv *priv) 478{ 479 struct emac_desc_ring *rr = &priv->rx_ring; 480 struct device *dev = &priv->pdev->dev; 481 482 emac_clean_rx_desc_ring(priv); 483 484 kfree(rr->rx_desc_buf); 485 rr->rx_desc_buf = NULL; 486 487 dma_free_coherent(dev, rr->total_size, rr->desc_addr, 488 rr->desc_dma_addr); 489 rr->desc_addr = NULL; 490} 491 492static int emac_tx_clean_desc(struct emac_priv *priv) 493{ 494 struct net_device *ndev = priv->ndev; 495 struct emac_desc_ring *tx_ring; 496 struct emac_desc *tx_desc; 497 u32 i; 498 499 netif_tx_lock(ndev); 500 501 tx_ring = &priv->tx_ring; 502 503 i = tx_ring->tail; 504 505 while (i != tx_ring->head) { 506 tx_desc = &((struct emac_desc *)tx_ring->desc_addr)[i]; 507 508 /* Stop checking if desc still own by DMA */ 509 if (READ_ONCE(tx_desc->desc0) & TX_DESC_0_OWN) 510 break; 511 512 emac_free_tx_buf(priv, i); 513 memset(tx_desc, 0, sizeof(struct emac_desc)); 514 515 if (++i == tx_ring->total_cnt) 516 i = 0; 517 } 518 519 tx_ring->tail = i; 520 521 if (unlikely(netif_queue_stopped(ndev) && 522 emac_tx_avail(priv) > tx_ring->total_cnt / 4)) 523 netif_wake_queue(ndev); 524 525 netif_tx_unlock(ndev); 526 527 return 0; 528} 529 530static bool emac_rx_frame_good(struct emac_priv *priv, struct emac_desc *desc) 531{ 532 const char *msg; 533 u32 len; 534 535 len = FIELD_GET(RX_DESC_0_FRAME_PACKET_LENGTH_MASK, desc->desc0); 536 537 if (WARN_ON_ONCE(!(desc->desc0 & RX_DESC_0_LAST_DESCRIPTOR))) 538 msg = "Not last descriptor"; /* This would be a bug */ 539 else if (desc->desc0 & RX_DESC_0_FRAME_RUNT) 540 msg = "Runt frame"; 541 else if (desc->desc0 & RX_DESC_0_FRAME_CRC_ERR) 542 msg = "Frame CRC error"; 543 else if (desc->desc0 & RX_DESC_0_FRAME_MAX_LEN_ERR) 544 msg = "Frame exceeds max length"; 545 else if (desc->desc0 & RX_DESC_0_FRAME_JABBER_ERR) 546 msg = "Frame jabber error"; 547 else if (desc->desc0 & RX_DESC_0_FRAME_LENGTH_ERR) 548 msg = "Frame length error"; 549 else if (len <= ETH_FCS_LEN || len > priv->dma_buf_sz) 550 msg = "Frame length unacceptable"; 551 else 552 return true; /* All good */ 553 554 dev_dbg_ratelimited(&priv->ndev->dev, "RX error: %s", msg); 555 556 return false; 557} 558 559static void emac_alloc_rx_desc_buffers(struct emac_priv *priv) 560{ 561 struct emac_desc_ring *rx_ring = &priv->rx_ring; 562 struct emac_desc rx_desc, *rx_desc_addr; 563 struct net_device *ndev = priv->ndev; 564 struct emac_rx_desc_buffer *rx_buf; 565 struct sk_buff *skb; 566 u32 i; 567 568 i = rx_ring->head; 569 rx_buf = &rx_ring->rx_desc_buf[i]; 570 571 while (!rx_buf->skb) { 572 skb = netdev_alloc_skb_ip_align(ndev, priv->dma_buf_sz); 573 if (!skb) 574 break; 575 576 skb->dev = ndev; 577 578 rx_buf->skb = skb; 579 rx_buf->dma_len = priv->dma_buf_sz; 580 rx_buf->dma_addr = dma_map_single(&priv->pdev->dev, skb->data, 581 priv->dma_buf_sz, 582 DMA_FROM_DEVICE); 583 if (dma_mapping_error(&priv->pdev->dev, rx_buf->dma_addr)) { 584 dev_err_ratelimited(&ndev->dev, "Mapping skb failed\n"); 585 dev_kfree_skb_any(skb); 586 rx_buf->skb = NULL; 587 break; 588 } 589 590 rx_desc_addr = &((struct emac_desc *)rx_ring->desc_addr)[i]; 591 592 memset(&rx_desc, 0, sizeof(rx_desc)); 593 594 rx_desc.buffer_addr_1 = rx_buf->dma_addr; 595 rx_desc.desc1 = FIELD_PREP(RX_DESC_1_BUFFER_SIZE_1_MASK, 596 rx_buf->dma_len); 597 598 if (++i == rx_ring->total_cnt) { 599 rx_desc.desc1 |= RX_DESC_1_END_RING; 600 i = 0; 601 } 602 603 *rx_desc_addr = rx_desc; 604 dma_wmb(); 605 WRITE_ONCE(rx_desc_addr->desc0, rx_desc.desc0 | RX_DESC_0_OWN); 606 607 rx_buf = &rx_ring->rx_desc_buf[i]; 608 } 609 610 rx_ring->head = i; 611 return; 612} 613 614/* Returns number of packets received */ 615static int emac_rx_clean_desc(struct emac_priv *priv, int budget) 616{ 617 struct net_device *ndev = priv->ndev; 618 struct emac_rx_desc_buffer *rx_buf; 619 struct emac_desc_ring *rx_ring; 620 struct sk_buff *skb = NULL; 621 struct emac_desc *rx_desc; 622 u32 got = 0, skb_len, i; 623 624 rx_ring = &priv->rx_ring; 625 626 i = rx_ring->tail; 627 628 while (budget--) { 629 rx_desc = &((struct emac_desc *)rx_ring->desc_addr)[i]; 630 631 /* Stop checking if rx_desc still owned by DMA */ 632 if (READ_ONCE(rx_desc->desc0) & RX_DESC_0_OWN) 633 break; 634 635 dma_rmb(); 636 637 rx_buf = &rx_ring->rx_desc_buf[i]; 638 639 if (!rx_buf->skb) 640 break; 641 642 got++; 643 644 dma_unmap_single(&priv->pdev->dev, rx_buf->dma_addr, 645 rx_buf->dma_len, DMA_FROM_DEVICE); 646 647 if (likely(emac_rx_frame_good(priv, rx_desc))) { 648 skb = rx_buf->skb; 649 650 skb_len = FIELD_GET(RX_DESC_0_FRAME_PACKET_LENGTH_MASK, 651 rx_desc->desc0); 652 skb_len -= ETH_FCS_LEN; 653 654 skb_put(skb, skb_len); 655 skb->dev = ndev; 656 ndev->hard_header_len = ETH_HLEN; 657 658 skb->protocol = eth_type_trans(skb, ndev); 659 660 skb->ip_summed = CHECKSUM_NONE; 661 662 napi_gro_receive(&priv->napi, skb); 663 664 memset(rx_desc, 0, sizeof(struct emac_desc)); 665 rx_buf->skb = NULL; 666 } else { 667 dev_kfree_skb_irq(rx_buf->skb); 668 rx_buf->skb = NULL; 669 } 670 671 if (++i == rx_ring->total_cnt) 672 i = 0; 673 } 674 675 rx_ring->tail = i; 676 677 emac_alloc_rx_desc_buffers(priv); 678 679 return got; 680} 681 682static int emac_rx_poll(struct napi_struct *napi, int budget) 683{ 684 struct emac_priv *priv = container_of(napi, struct emac_priv, napi); 685 int work_done; 686 687 emac_tx_clean_desc(priv); 688 689 work_done = emac_rx_clean_desc(priv, budget); 690 if (work_done < budget && napi_complete_done(napi, work_done)) 691 emac_enable_interrupt(priv); 692 693 return work_done; 694} 695 696/* 697 * For convenience, skb->data is fragment 0, frags[0] is fragment 1, etc. 698 * 699 * Each descriptor can hold up to two fragments, called buffer 1 and 2. For each 700 * fragment f, if f % 2 == 0, it uses buffer 1, otherwise it uses buffer 2. 701 */ 702 703static int emac_tx_map_frag(struct device *dev, struct emac_desc *tx_desc, 704 struct emac_tx_desc_buffer *tx_buf, 705 struct sk_buff *skb, u32 frag_idx) 706{ 707 bool map_as_page, buf_idx; 708 const skb_frag_t *frag; 709 phys_addr_t addr; 710 u32 len; 711 int ret; 712 713 buf_idx = frag_idx % 2; 714 715 if (frag_idx == 0) { 716 /* Non-fragmented part */ 717 len = skb_headlen(skb); 718 addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE); 719 map_as_page = false; 720 } else { 721 /* Fragment */ 722 frag = &skb_shinfo(skb)->frags[frag_idx - 1]; 723 len = skb_frag_size(frag); 724 addr = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE); 725 map_as_page = true; 726 } 727 728 ret = dma_mapping_error(dev, addr); 729 if (ret) 730 return ret; 731 732 tx_buf->buf[buf_idx].dma_addr = addr; 733 tx_buf->buf[buf_idx].dma_len = len; 734 tx_buf->buf[buf_idx].map_as_page = map_as_page; 735 736 if (buf_idx == 0) { 737 tx_desc->buffer_addr_1 = addr; 738 tx_desc->desc1 |= FIELD_PREP(TX_DESC_1_BUFFER_SIZE_1_MASK, len); 739 } else { 740 tx_desc->buffer_addr_2 = addr; 741 tx_desc->desc1 |= FIELD_PREP(TX_DESC_1_BUFFER_SIZE_2_MASK, len); 742 } 743 744 return 0; 745} 746 747static void emac_tx_mem_map(struct emac_priv *priv, struct sk_buff *skb) 748{ 749 struct emac_desc_ring *tx_ring = &priv->tx_ring; 750 struct emac_desc tx_desc, *tx_desc_addr; 751 struct device *dev = &priv->pdev->dev; 752 struct emac_tx_desc_buffer *tx_buf; 753 u32 head, old_head, frag_num, f, i; 754 bool buf_idx; 755 756 frag_num = skb_shinfo(skb)->nr_frags; 757 head = tx_ring->head; 758 old_head = head; 759 760 for (f = 0; f < frag_num + 1; f++) { 761 buf_idx = f % 2; 762 763 /* 764 * If using buffer 1, initialize a new desc. Otherwise, use 765 * buffer 2 of previous fragment's desc. 766 */ 767 if (!buf_idx) { 768 tx_buf = &tx_ring->tx_desc_buf[head]; 769 tx_desc_addr = 770 &((struct emac_desc *)tx_ring->desc_addr)[head]; 771 memset(&tx_desc, 0, sizeof(tx_desc)); 772 773 /* 774 * Give ownership for all but first desc initially. For 775 * first desc, give at the end so DMA cannot start 776 * reading uninitialized descs. 777 */ 778 if (head != old_head) 779 tx_desc.desc0 |= TX_DESC_0_OWN; 780 781 if (++head == tx_ring->total_cnt) { 782 /* Just used last desc in ring */ 783 tx_desc.desc1 |= TX_DESC_1_END_RING; 784 head = 0; 785 } 786 } 787 788 if (emac_tx_map_frag(dev, &tx_desc, tx_buf, skb, f)) { 789 dev_err_ratelimited(&priv->ndev->dev, 790 "Map TX frag %d failed\n", f); 791 goto err_free_skb; 792 } 793 794 if (f == 0) 795 tx_desc.desc1 |= TX_DESC_1_FIRST_SEGMENT; 796 797 if (f == frag_num) { 798 tx_desc.desc1 |= TX_DESC_1_LAST_SEGMENT; 799 tx_buf->skb = skb; 800 if (emac_tx_should_interrupt(priv, frag_num + 1)) 801 tx_desc.desc1 |= 802 TX_DESC_1_INTERRUPT_ON_COMPLETION; 803 } 804 805 *tx_desc_addr = tx_desc; 806 } 807 808 /* All descriptors are ready, give ownership for first desc */ 809 tx_desc_addr = &((struct emac_desc *)tx_ring->desc_addr)[old_head]; 810 dma_wmb(); 811 WRITE_ONCE(tx_desc_addr->desc0, tx_desc_addr->desc0 | TX_DESC_0_OWN); 812 813 emac_dma_start_transmit(priv); 814 815 tx_ring->head = head; 816 817 return; 818 819err_free_skb: 820 dev_dstats_tx_dropped(priv->ndev); 821 822 i = old_head; 823 while (i != head) { 824 emac_free_tx_buf(priv, i); 825 826 if (++i == tx_ring->total_cnt) 827 i = 0; 828 } 829 830 dev_kfree_skb_any(skb); 831} 832 833static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 834{ 835 struct emac_priv *priv = netdev_priv(ndev); 836 int nfrags = skb_shinfo(skb)->nr_frags; 837 struct device *dev = &priv->pdev->dev; 838 839 if (unlikely(emac_tx_avail(priv) < nfrags + 1)) { 840 if (!netif_queue_stopped(ndev)) { 841 netif_stop_queue(ndev); 842 dev_err_ratelimited(dev, "TX ring full, stop TX queue\n"); 843 } 844 return NETDEV_TX_BUSY; 845 } 846 847 emac_tx_mem_map(priv, skb); 848 849 /* Make sure there is space in the ring for the next TX. */ 850 if (unlikely(emac_tx_avail(priv) <= MAX_SKB_FRAGS + 2)) 851 netif_stop_queue(ndev); 852 853 return NETDEV_TX_OK; 854} 855 856static int emac_set_mac_address(struct net_device *ndev, void *addr) 857{ 858 struct emac_priv *priv = netdev_priv(ndev); 859 int ret = eth_mac_addr(ndev, addr); 860 861 if (ret) 862 return ret; 863 864 /* If running, set now; if not running it will be set in emac_up. */ 865 if (netif_running(ndev)) 866 emac_set_mac_addr(priv, ndev->dev_addr); 867 868 return 0; 869} 870 871static void emac_mac_multicast_filter_clear(struct emac_priv *priv) 872{ 873 emac_wr(priv, MAC_MULTICAST_HASH_TABLE1, 0x0); 874 emac_wr(priv, MAC_MULTICAST_HASH_TABLE2, 0x0); 875 emac_wr(priv, MAC_MULTICAST_HASH_TABLE3, 0x0); 876 emac_wr(priv, MAC_MULTICAST_HASH_TABLE4, 0x0); 877} 878 879/* 880 * The upper 6 bits of the Ethernet CRC of the MAC address is used as the hash 881 * when matching multicast addresses. 882 */ 883static u32 emac_ether_addr_hash(u8 addr[ETH_ALEN]) 884{ 885 u32 crc32 = ether_crc(ETH_ALEN, addr); 886 887 return crc32 >> 26; 888} 889 890/* Configure Multicast and Promiscuous modes */ 891static void emac_set_rx_mode(struct net_device *ndev) 892{ 893 struct emac_priv *priv = netdev_priv(ndev); 894 struct netdev_hw_addr *ha; 895 u32 mc_filter[4] = { 0 }; 896 u32 hash, reg, bit, val; 897 898 val = emac_rd(priv, MAC_ADDRESS_CONTROL); 899 900 val &= ~MREGBIT_PROMISCUOUS_MODE; 901 902 if (ndev->flags & IFF_PROMISC) { 903 /* Enable promisc mode */ 904 val |= MREGBIT_PROMISCUOUS_MODE; 905 } else if ((ndev->flags & IFF_ALLMULTI) || 906 (netdev_mc_count(ndev) > HASH_TABLE_SIZE)) { 907 /* Accept all multicast frames by setting every bit */ 908 emac_wr(priv, MAC_MULTICAST_HASH_TABLE1, 0xffff); 909 emac_wr(priv, MAC_MULTICAST_HASH_TABLE2, 0xffff); 910 emac_wr(priv, MAC_MULTICAST_HASH_TABLE3, 0xffff); 911 emac_wr(priv, MAC_MULTICAST_HASH_TABLE4, 0xffff); 912 } else if (!netdev_mc_empty(ndev)) { 913 emac_mac_multicast_filter_clear(priv); 914 netdev_for_each_mc_addr(ha, ndev) { 915 /* 916 * The hash table is an array of 4 16-bit registers. It 917 * is treated like an array of 64 bits (bits[hash]). 918 */ 919 hash = emac_ether_addr_hash(ha->addr); 920 reg = hash / 16; 921 bit = hash % 16; 922 mc_filter[reg] |= BIT(bit); 923 } 924 emac_wr(priv, MAC_MULTICAST_HASH_TABLE1, mc_filter[0]); 925 emac_wr(priv, MAC_MULTICAST_HASH_TABLE2, mc_filter[1]); 926 emac_wr(priv, MAC_MULTICAST_HASH_TABLE3, mc_filter[2]); 927 emac_wr(priv, MAC_MULTICAST_HASH_TABLE4, mc_filter[3]); 928 } 929 930 emac_wr(priv, MAC_ADDRESS_CONTROL, val); 931} 932 933static int emac_change_mtu(struct net_device *ndev, int mtu) 934{ 935 struct emac_priv *priv = netdev_priv(ndev); 936 u32 frame_len; 937 938 if (netif_running(ndev)) { 939 netdev_err(ndev, "must be stopped to change MTU\n"); 940 return -EBUSY; 941 } 942 943 frame_len = mtu + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; 944 945 if (frame_len <= EMAC_DEFAULT_BUFSIZE) 946 priv->dma_buf_sz = EMAC_DEFAULT_BUFSIZE; 947 else if (frame_len <= EMAC_RX_BUF_2K) 948 priv->dma_buf_sz = EMAC_RX_BUF_2K; 949 else 950 priv->dma_buf_sz = EMAC_RX_BUF_MAX; 951 952 ndev->mtu = mtu; 953 954 return 0; 955} 956 957static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue) 958{ 959 struct emac_priv *priv = netdev_priv(ndev); 960 961 schedule_work(&priv->tx_timeout_task); 962} 963 964static int emac_mii_read(struct mii_bus *bus, int phy_addr, int regnum) 965{ 966 struct emac_priv *priv = bus->priv; 967 u32 cmd = 0, val; 968 int ret; 969 970 cmd |= FIELD_PREP(MREGBIT_PHY_ADDRESS, phy_addr); 971 cmd |= FIELD_PREP(MREGBIT_REGISTER_ADDRESS, regnum); 972 cmd |= MREGBIT_START_MDIO_TRANS | MREGBIT_MDIO_READ_WRITE; 973 974 emac_wr(priv, MAC_MDIO_DATA, 0x0); 975 emac_wr(priv, MAC_MDIO_CONTROL, cmd); 976 977 ret = readl_poll_timeout(priv->iobase + MAC_MDIO_CONTROL, val, 978 !(val & MREGBIT_START_MDIO_TRANS), 100, 10000); 979 980 if (ret) 981 return ret; 982 983 val = emac_rd(priv, MAC_MDIO_DATA); 984 return FIELD_GET(MREGBIT_MDIO_DATA, val); 985} 986 987static int emac_mii_write(struct mii_bus *bus, int phy_addr, int regnum, 988 u16 value) 989{ 990 struct emac_priv *priv = bus->priv; 991 u32 cmd = 0, val; 992 int ret; 993 994 emac_wr(priv, MAC_MDIO_DATA, value); 995 996 cmd |= FIELD_PREP(MREGBIT_PHY_ADDRESS, phy_addr); 997 cmd |= FIELD_PREP(MREGBIT_REGISTER_ADDRESS, regnum); 998 cmd |= MREGBIT_START_MDIO_TRANS; 999 1000 emac_wr(priv, MAC_MDIO_CONTROL, cmd); 1001 1002 ret = readl_poll_timeout(priv->iobase + MAC_MDIO_CONTROL, val, 1003 !(val & MREGBIT_START_MDIO_TRANS), 100, 10000); 1004 1005 return ret; 1006} 1007 1008static int emac_mdio_init(struct emac_priv *priv) 1009{ 1010 struct device *dev = &priv->pdev->dev; 1011 struct device_node *mii_np; 1012 struct mii_bus *mii; 1013 int ret; 1014 1015 mii = devm_mdiobus_alloc(dev); 1016 if (!mii) 1017 return -ENOMEM; 1018 1019 mii->priv = priv; 1020 mii->name = "k1_emac_mii"; 1021 mii->read = emac_mii_read; 1022 mii->write = emac_mii_write; 1023 mii->parent = dev; 1024 mii->phy_mask = ~0; 1025 snprintf(mii->id, MII_BUS_ID_SIZE, "%s", priv->pdev->name); 1026 1027 mii_np = of_get_available_child_by_name(dev->of_node, "mdio-bus"); 1028 1029 ret = devm_of_mdiobus_register(dev, mii, mii_np); 1030 if (ret) 1031 dev_err_probe(dev, ret, "Failed to register mdio bus\n"); 1032 1033 of_node_put(mii_np); 1034 return ret; 1035} 1036 1037static void emac_set_tx_fc(struct emac_priv *priv, bool enable) 1038{ 1039 u32 val; 1040 1041 val = emac_rd(priv, MAC_FC_CONTROL); 1042 1043 FIELD_MODIFY(MREGBIT_FC_GENERATION_ENABLE, &val, enable); 1044 FIELD_MODIFY(MREGBIT_AUTO_FC_GENERATION_ENABLE, &val, enable); 1045 1046 emac_wr(priv, MAC_FC_CONTROL, val); 1047} 1048 1049static void emac_set_rx_fc(struct emac_priv *priv, bool enable) 1050{ 1051 u32 val = emac_rd(priv, MAC_FC_CONTROL); 1052 1053 FIELD_MODIFY(MREGBIT_FC_DECODE_ENABLE, &val, enable); 1054 1055 emac_wr(priv, MAC_FC_CONTROL, val); 1056} 1057 1058static void emac_set_fc(struct emac_priv *priv, u8 fc) 1059{ 1060 emac_set_tx_fc(priv, fc & FLOW_CTRL_TX); 1061 emac_set_rx_fc(priv, fc & FLOW_CTRL_RX); 1062 priv->flow_control = fc; 1063} 1064 1065static void emac_set_fc_autoneg(struct emac_priv *priv) 1066{ 1067 struct phy_device *phydev = priv->ndev->phydev; 1068 u32 local_adv, remote_adv; 1069 u8 fc; 1070 1071 local_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); 1072 1073 remote_adv = 0; 1074 1075 if (phydev->pause) 1076 remote_adv |= LPA_PAUSE_CAP; 1077 1078 if (phydev->asym_pause) 1079 remote_adv |= LPA_PAUSE_ASYM; 1080 1081 fc = mii_resolve_flowctrl_fdx(local_adv, remote_adv); 1082 1083 priv->flow_control_autoneg = true; 1084 1085 emac_set_fc(priv, fc); 1086} 1087 1088/* 1089 * Even though this MAC supports gigabit operation, it only provides 32-bit 1090 * statistics counters. The most overflow-prone counters are the "bytes" ones, 1091 * which at gigabit overflow about twice a minute. 1092 * 1093 * Therefore, we maintain the high 32 bits of counters ourselves, incrementing 1094 * every time statistics seem to go backwards. Also, update periodically to 1095 * catch overflows when we are not otherwise checking the statistics often 1096 * enough. 1097 */ 1098 1099#define EMAC_STATS_TIMER_PERIOD 20 1100 1101static int emac_read_stat_cnt(struct emac_priv *priv, u8 cnt, u32 *res, 1102 u32 control_reg, u32 high_reg, u32 low_reg) 1103{ 1104 u32 val, high, low; 1105 int ret; 1106 1107 /* The "read" bit is the same for TX and RX */ 1108 1109 val = MREGBIT_START_TX_COUNTER_READ | cnt; 1110 emac_wr(priv, control_reg, val); 1111 val = emac_rd(priv, control_reg); 1112 1113 ret = readl_poll_timeout_atomic(priv->iobase + control_reg, val, 1114 !(val & MREGBIT_START_TX_COUNTER_READ), 1115 100, 10000); 1116 1117 if (ret) { 1118 /* 1119 * This could be caused by the PHY stopping its refclk even when 1120 * the link is up, for power saving. See also comments in 1121 * emac_stats_update(). 1122 */ 1123 dev_err_ratelimited(&priv->ndev->dev, 1124 "Read stat timeout. PHY clock stopped?\n"); 1125 return ret; 1126 } 1127 1128 high = emac_rd(priv, high_reg); 1129 low = emac_rd(priv, low_reg); 1130 *res = high << 16 | lower_16_bits(low); 1131 1132 return 0; 1133} 1134 1135static int emac_tx_read_stat_cnt(struct emac_priv *priv, u8 cnt, u32 *res) 1136{ 1137 return emac_read_stat_cnt(priv, cnt, res, MAC_TX_STATCTR_CONTROL, 1138 MAC_TX_STATCTR_DATA_HIGH, 1139 MAC_TX_STATCTR_DATA_LOW); 1140} 1141 1142static int emac_rx_read_stat_cnt(struct emac_priv *priv, u8 cnt, u32 *res) 1143{ 1144 return emac_read_stat_cnt(priv, cnt, res, MAC_RX_STATCTR_CONTROL, 1145 MAC_RX_STATCTR_DATA_HIGH, 1146 MAC_RX_STATCTR_DATA_LOW); 1147} 1148 1149static void emac_update_counter(u64 *counter, u32 new_low) 1150{ 1151 u32 old_low = lower_32_bits(*counter); 1152 u64 high = upper_32_bits(*counter); 1153 1154 if (old_low > new_low) { 1155 /* Overflowed, increment high 32 bits */ 1156 high++; 1157 } 1158 1159 *counter = (high << 32) | new_low; 1160} 1161 1162static void emac_stats_update(struct emac_priv *priv) 1163{ 1164 u64 *tx_stats_off = priv->tx_stats_off.array; 1165 u64 *rx_stats_off = priv->rx_stats_off.array; 1166 u64 *tx_stats = priv->tx_stats.array; 1167 u64 *rx_stats = priv->rx_stats.array; 1168 u32 i, res, offset; 1169 1170 assert_spin_locked(&priv->stats_lock); 1171 1172 /* 1173 * We can't read statistics if the interface is not up. Also, some PHYs 1174 * stop their reference clocks for link down power saving, which also 1175 * causes reading statistics to time out. Don't update and don't 1176 * reschedule in these cases. 1177 */ 1178 if (!netif_running(priv->ndev) || 1179 !netif_carrier_ok(priv->ndev) || 1180 !netif_device_present(priv->ndev)) { 1181 return; 1182 } 1183 1184 for (i = 0; i < sizeof(priv->tx_stats) / sizeof(*tx_stats); i++) { 1185 /* 1186 * If reading stats times out anyway, the stat registers will be 1187 * stuck, and we can't really recover from that. 1188 * 1189 * Reading statistics also can't return an error, so just return 1190 * without updating and without rescheduling. 1191 */ 1192 if (emac_tx_read_stat_cnt(priv, i, &res)) 1193 return; 1194 1195 /* 1196 * Re-initializing while bringing interface up resets counters 1197 * to zero, so to provide continuity, we add the values saved 1198 * last time we did emac_down() to the new hardware-provided 1199 * value. 1200 */ 1201 offset = lower_32_bits(tx_stats_off[i]); 1202 emac_update_counter(&tx_stats[i], res + offset); 1203 } 1204 1205 /* Similar remarks as TX stats */ 1206 for (i = 0; i < sizeof(priv->rx_stats) / sizeof(*rx_stats); i++) { 1207 if (emac_rx_read_stat_cnt(priv, i, &res)) 1208 return; 1209 offset = lower_32_bits(rx_stats_off[i]); 1210 emac_update_counter(&rx_stats[i], res + offset); 1211 } 1212 1213 mod_timer(&priv->stats_timer, jiffies + EMAC_STATS_TIMER_PERIOD * HZ); 1214} 1215 1216static void emac_stats_timer(struct timer_list *t) 1217{ 1218 struct emac_priv *priv = timer_container_of(priv, t, stats_timer); 1219 1220 spin_lock(&priv->stats_lock); 1221 1222 emac_stats_update(priv); 1223 1224 spin_unlock(&priv->stats_lock); 1225} 1226 1227static const struct ethtool_rmon_hist_range emac_rmon_hist_ranges[] = { 1228 { 64, 64 }, 1229 { 65, 127 }, 1230 { 128, 255 }, 1231 { 256, 511 }, 1232 { 512, 1023 }, 1233 { 1024, 1518 }, 1234 { 1519, 4096 }, 1235 { /* sentinel */ }, 1236}; 1237 1238/* Like dev_fetch_dstats(), but we only use tx_drops */ 1239static u64 emac_get_stat_tx_drops(struct emac_priv *priv) 1240{ 1241 const struct pcpu_dstats *stats; 1242 u64 tx_drops, total = 0; 1243 unsigned int start; 1244 int cpu; 1245 1246 for_each_possible_cpu(cpu) { 1247 stats = per_cpu_ptr(priv->ndev->dstats, cpu); 1248 do { 1249 start = u64_stats_fetch_begin(&stats->syncp); 1250 tx_drops = u64_stats_read(&stats->tx_drops); 1251 } while (u64_stats_fetch_retry(&stats->syncp, start)); 1252 1253 total += tx_drops; 1254 } 1255 1256 return total; 1257} 1258 1259static void emac_get_stats64(struct net_device *dev, 1260 struct rtnl_link_stats64 *storage) 1261{ 1262 struct emac_priv *priv = netdev_priv(dev); 1263 union emac_hw_tx_stats *tx_stats; 1264 union emac_hw_rx_stats *rx_stats; 1265 1266 tx_stats = &priv->tx_stats; 1267 rx_stats = &priv->rx_stats; 1268 1269 /* This is the only software counter */ 1270 storage->tx_dropped = emac_get_stat_tx_drops(priv); 1271 1272 spin_lock_bh(&priv->stats_lock); 1273 1274 emac_stats_update(priv); 1275 1276 storage->tx_packets = tx_stats->stats.tx_ok_pkts; 1277 storage->tx_bytes = tx_stats->stats.tx_ok_bytes; 1278 storage->tx_errors = tx_stats->stats.tx_err_pkts; 1279 1280 storage->rx_packets = rx_stats->stats.rx_ok_pkts; 1281 storage->rx_bytes = rx_stats->stats.rx_ok_bytes; 1282 storage->rx_errors = rx_stats->stats.rx_err_total_pkts; 1283 storage->rx_crc_errors = rx_stats->stats.rx_crc_err_pkts; 1284 storage->rx_frame_errors = rx_stats->stats.rx_align_err_pkts; 1285 storage->rx_length_errors = rx_stats->stats.rx_len_err_pkts; 1286 1287 storage->collisions = tx_stats->stats.tx_singleclsn_pkts; 1288 storage->collisions += tx_stats->stats.tx_multiclsn_pkts; 1289 storage->collisions += tx_stats->stats.tx_excessclsn_pkts; 1290 1291 storage->rx_missed_errors = rx_stats->stats.rx_drp_fifo_full_pkts; 1292 storage->rx_missed_errors += rx_stats->stats.rx_truncate_fifo_full_pkts; 1293 1294 spin_unlock_bh(&priv->stats_lock); 1295} 1296 1297static void emac_get_rmon_stats(struct net_device *dev, 1298 struct ethtool_rmon_stats *rmon_stats, 1299 const struct ethtool_rmon_hist_range **ranges) 1300{ 1301 struct emac_priv *priv = netdev_priv(dev); 1302 union emac_hw_rx_stats *rx_stats; 1303 1304 rx_stats = &priv->rx_stats; 1305 1306 *ranges = emac_rmon_hist_ranges; 1307 1308 spin_lock_bh(&priv->stats_lock); 1309 1310 emac_stats_update(priv); 1311 1312 rmon_stats->undersize_pkts = rx_stats->stats.rx_len_undersize_pkts; 1313 rmon_stats->oversize_pkts = rx_stats->stats.rx_len_oversize_pkts; 1314 rmon_stats->fragments = rx_stats->stats.rx_len_fragment_pkts; 1315 rmon_stats->jabbers = rx_stats->stats.rx_len_jabber_pkts; 1316 1317 /* Only RX has histogram stats */ 1318 1319 rmon_stats->hist[0] = rx_stats->stats.rx_64_pkts; 1320 rmon_stats->hist[1] = rx_stats->stats.rx_65_127_pkts; 1321 rmon_stats->hist[2] = rx_stats->stats.rx_128_255_pkts; 1322 rmon_stats->hist[3] = rx_stats->stats.rx_256_511_pkts; 1323 rmon_stats->hist[4] = rx_stats->stats.rx_512_1023_pkts; 1324 rmon_stats->hist[5] = rx_stats->stats.rx_1024_1518_pkts; 1325 rmon_stats->hist[6] = rx_stats->stats.rx_1519_plus_pkts; 1326 1327 spin_unlock_bh(&priv->stats_lock); 1328} 1329 1330static void emac_get_eth_mac_stats(struct net_device *dev, 1331 struct ethtool_eth_mac_stats *mac_stats) 1332{ 1333 struct emac_priv *priv = netdev_priv(dev); 1334 union emac_hw_tx_stats *tx_stats; 1335 union emac_hw_rx_stats *rx_stats; 1336 1337 tx_stats = &priv->tx_stats; 1338 rx_stats = &priv->rx_stats; 1339 1340 spin_lock_bh(&priv->stats_lock); 1341 1342 emac_stats_update(priv); 1343 1344 mac_stats->MulticastFramesXmittedOK = tx_stats->stats.tx_multicast_pkts; 1345 mac_stats->BroadcastFramesXmittedOK = tx_stats->stats.tx_broadcast_pkts; 1346 1347 mac_stats->MulticastFramesReceivedOK = 1348 rx_stats->stats.rx_multicast_pkts; 1349 mac_stats->BroadcastFramesReceivedOK = 1350 rx_stats->stats.rx_broadcast_pkts; 1351 1352 mac_stats->SingleCollisionFrames = tx_stats->stats.tx_singleclsn_pkts; 1353 mac_stats->MultipleCollisionFrames = tx_stats->stats.tx_multiclsn_pkts; 1354 mac_stats->LateCollisions = tx_stats->stats.tx_lateclsn_pkts; 1355 mac_stats->FramesAbortedDueToXSColls = 1356 tx_stats->stats.tx_excessclsn_pkts; 1357 1358 spin_unlock_bh(&priv->stats_lock); 1359} 1360 1361static void emac_get_pause_stats(struct net_device *dev, 1362 struct ethtool_pause_stats *pause_stats) 1363{ 1364 struct emac_priv *priv = netdev_priv(dev); 1365 union emac_hw_tx_stats *tx_stats; 1366 union emac_hw_rx_stats *rx_stats; 1367 1368 tx_stats = &priv->tx_stats; 1369 rx_stats = &priv->rx_stats; 1370 1371 spin_lock_bh(&priv->stats_lock); 1372 1373 emac_stats_update(priv); 1374 1375 pause_stats->tx_pause_frames = tx_stats->stats.tx_pause_pkts; 1376 pause_stats->rx_pause_frames = rx_stats->stats.rx_pause_pkts; 1377 1378 spin_unlock_bh(&priv->stats_lock); 1379} 1380 1381/* Other statistics that are not derivable from standard statistics */ 1382 1383#define EMAC_ETHTOOL_STAT(type, name) \ 1384 { offsetof(type, stats.name) / sizeof(u64), #name } 1385 1386static const struct emac_ethtool_stats { 1387 size_t offset; 1388 char str[ETH_GSTRING_LEN]; 1389} emac_ethtool_rx_stats[] = { 1390 EMAC_ETHTOOL_STAT(union emac_hw_rx_stats, rx_drp_fifo_full_pkts), 1391 EMAC_ETHTOOL_STAT(union emac_hw_rx_stats, rx_truncate_fifo_full_pkts), 1392}; 1393 1394static int emac_get_sset_count(struct net_device *dev, int sset) 1395{ 1396 switch (sset) { 1397 case ETH_SS_STATS: 1398 return ARRAY_SIZE(emac_ethtool_rx_stats); 1399 default: 1400 return -EOPNOTSUPP; 1401 } 1402} 1403 1404static void emac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1405{ 1406 int i; 1407 1408 switch (stringset) { 1409 case ETH_SS_STATS: 1410 for (i = 0; i < ARRAY_SIZE(emac_ethtool_rx_stats); i++) { 1411 memcpy(data, emac_ethtool_rx_stats[i].str, 1412 ETH_GSTRING_LEN); 1413 data += ETH_GSTRING_LEN; 1414 } 1415 break; 1416 } 1417} 1418 1419static void emac_get_ethtool_stats(struct net_device *dev, 1420 struct ethtool_stats *stats, u64 *data) 1421{ 1422 struct emac_priv *priv = netdev_priv(dev); 1423 u64 *rx_stats = (u64 *)&priv->rx_stats; 1424 int i; 1425 1426 spin_lock_bh(&priv->stats_lock); 1427 1428 emac_stats_update(priv); 1429 1430 for (i = 0; i < ARRAY_SIZE(emac_ethtool_rx_stats); i++) 1431 data[i] = rx_stats[emac_ethtool_rx_stats[i].offset]; 1432 1433 spin_unlock_bh(&priv->stats_lock); 1434} 1435 1436static int emac_ethtool_get_regs_len(struct net_device *dev) 1437{ 1438 return (EMAC_DMA_REG_CNT + EMAC_MAC_REG_CNT) * sizeof(u32); 1439} 1440 1441static void emac_ethtool_get_regs(struct net_device *dev, 1442 struct ethtool_regs *regs, void *space) 1443{ 1444 struct emac_priv *priv = netdev_priv(dev); 1445 u32 *reg_space = space; 1446 int i; 1447 1448 regs->version = 1; 1449 1450 for (i = 0; i < EMAC_DMA_REG_CNT; i++) 1451 reg_space[i] = emac_rd(priv, DMA_CONFIGURATION + i * 4); 1452 1453 for (i = 0; i < EMAC_MAC_REG_CNT; i++) 1454 reg_space[i + EMAC_DMA_REG_CNT] = 1455 emac_rd(priv, MAC_GLOBAL_CONTROL + i * 4); 1456} 1457 1458static void emac_get_pauseparam(struct net_device *dev, 1459 struct ethtool_pauseparam *pause) 1460{ 1461 struct emac_priv *priv = netdev_priv(dev); 1462 1463 pause->autoneg = priv->flow_control_autoneg; 1464 pause->tx_pause = !!(priv->flow_control & FLOW_CTRL_TX); 1465 pause->rx_pause = !!(priv->flow_control & FLOW_CTRL_RX); 1466} 1467 1468static int emac_set_pauseparam(struct net_device *dev, 1469 struct ethtool_pauseparam *pause) 1470{ 1471 struct emac_priv *priv = netdev_priv(dev); 1472 u8 fc = 0; 1473 1474 if (!netif_running(dev)) 1475 return -ENETDOWN; 1476 1477 priv->flow_control_autoneg = pause->autoneg; 1478 1479 if (pause->autoneg) { 1480 emac_set_fc_autoneg(priv); 1481 } else { 1482 if (pause->tx_pause) 1483 fc |= FLOW_CTRL_TX; 1484 1485 if (pause->rx_pause) 1486 fc |= FLOW_CTRL_RX; 1487 1488 emac_set_fc(priv, fc); 1489 } 1490 1491 return 0; 1492} 1493 1494static void emac_get_drvinfo(struct net_device *dev, 1495 struct ethtool_drvinfo *info) 1496{ 1497 strscpy(info->driver, DRIVER_NAME, sizeof(info->driver)); 1498 info->n_stats = ARRAY_SIZE(emac_ethtool_rx_stats); 1499} 1500 1501static void emac_tx_timeout_task(struct work_struct *work) 1502{ 1503 struct net_device *ndev; 1504 struct emac_priv *priv; 1505 1506 priv = container_of(work, struct emac_priv, tx_timeout_task); 1507 ndev = priv->ndev; 1508 1509 rtnl_lock(); 1510 1511 /* No need to reset if already down */ 1512 if (!netif_running(ndev)) { 1513 rtnl_unlock(); 1514 return; 1515 } 1516 1517 netdev_err(ndev, "MAC reset due to TX timeout\n"); 1518 1519 netif_trans_update(ndev); /* prevent tx timeout */ 1520 dev_close(ndev); 1521 dev_open(ndev, NULL); 1522 1523 rtnl_unlock(); 1524} 1525 1526static void emac_sw_init(struct emac_priv *priv) 1527{ 1528 priv->dma_buf_sz = EMAC_DEFAULT_BUFSIZE; 1529 1530 priv->tx_ring.total_cnt = DEFAULT_TX_RING_NUM; 1531 priv->rx_ring.total_cnt = DEFAULT_RX_RING_NUM; 1532 1533 spin_lock_init(&priv->stats_lock); 1534 1535 INIT_WORK(&priv->tx_timeout_task, emac_tx_timeout_task); 1536 1537 priv->tx_coal_frames = EMAC_TX_FRAMES; 1538 priv->tx_coal_timeout = EMAC_TX_COAL_TIMEOUT; 1539 1540 timer_setup(&priv->txtimer, emac_tx_coal_timer, 0); 1541 timer_setup(&priv->stats_timer, emac_stats_timer, 0); 1542} 1543 1544static irqreturn_t emac_interrupt_handler(int irq, void *dev_id) 1545{ 1546 struct net_device *ndev = (struct net_device *)dev_id; 1547 struct emac_priv *priv = netdev_priv(ndev); 1548 bool should_schedule = false; 1549 u32 clr = 0; 1550 u32 status; 1551 1552 status = emac_rd(priv, DMA_STATUS_IRQ); 1553 1554 if (status & MREGBIT_TRANSMIT_TRANSFER_DONE_IRQ) { 1555 clr |= MREGBIT_TRANSMIT_TRANSFER_DONE_IRQ; 1556 should_schedule = true; 1557 } 1558 1559 if (status & MREGBIT_TRANSMIT_DES_UNAVAILABLE_IRQ) 1560 clr |= MREGBIT_TRANSMIT_DES_UNAVAILABLE_IRQ; 1561 1562 if (status & MREGBIT_TRANSMIT_DMA_STOPPED_IRQ) 1563 clr |= MREGBIT_TRANSMIT_DMA_STOPPED_IRQ; 1564 1565 if (status & MREGBIT_RECEIVE_TRANSFER_DONE_IRQ) { 1566 clr |= MREGBIT_RECEIVE_TRANSFER_DONE_IRQ; 1567 should_schedule = true; 1568 } 1569 1570 if (status & MREGBIT_RECEIVE_DES_UNAVAILABLE_IRQ) 1571 clr |= MREGBIT_RECEIVE_DES_UNAVAILABLE_IRQ; 1572 1573 if (status & MREGBIT_RECEIVE_DMA_STOPPED_IRQ) 1574 clr |= MREGBIT_RECEIVE_DMA_STOPPED_IRQ; 1575 1576 if (status & MREGBIT_RECEIVE_MISSED_FRAME_IRQ) 1577 clr |= MREGBIT_RECEIVE_MISSED_FRAME_IRQ; 1578 1579 if (should_schedule) { 1580 if (napi_schedule_prep(&priv->napi)) { 1581 emac_disable_interrupt(priv); 1582 __napi_schedule_irqoff(&priv->napi); 1583 } 1584 } 1585 1586 emac_wr(priv, DMA_STATUS_IRQ, clr); 1587 1588 return IRQ_HANDLED; 1589} 1590 1591static void emac_configure_tx(struct emac_priv *priv) 1592{ 1593 u32 val; 1594 1595 /* Set base address */ 1596 val = (u32)priv->tx_ring.desc_dma_addr; 1597 emac_wr(priv, DMA_TRANSMIT_BASE_ADDRESS, val); 1598 1599 /* Set TX inter-frame gap value, enable transmit */ 1600 val = emac_rd(priv, MAC_TRANSMIT_CONTROL); 1601 val &= ~MREGBIT_IFG_LEN; 1602 val |= MREGBIT_TRANSMIT_ENABLE; 1603 val |= MREGBIT_TRANSMIT_AUTO_RETRY; 1604 emac_wr(priv, MAC_TRANSMIT_CONTROL, val); 1605 1606 emac_wr(priv, DMA_TRANSMIT_AUTO_POLL_COUNTER, 0x0); 1607 1608 /* Start TX DMA */ 1609 val = emac_rd(priv, DMA_CONTROL); 1610 val |= MREGBIT_START_STOP_TRANSMIT_DMA; 1611 emac_wr(priv, DMA_CONTROL, val); 1612} 1613 1614static void emac_configure_rx(struct emac_priv *priv) 1615{ 1616 u32 val; 1617 1618 /* Set base address */ 1619 val = (u32)priv->rx_ring.desc_dma_addr; 1620 emac_wr(priv, DMA_RECEIVE_BASE_ADDRESS, val); 1621 1622 /* Enable receive */ 1623 val = emac_rd(priv, MAC_RECEIVE_CONTROL); 1624 val |= MREGBIT_RECEIVE_ENABLE; 1625 val |= MREGBIT_STORE_FORWARD; 1626 emac_wr(priv, MAC_RECEIVE_CONTROL, val); 1627 1628 /* Start RX DMA */ 1629 val = emac_rd(priv, DMA_CONTROL); 1630 val |= MREGBIT_START_STOP_RECEIVE_DMA; 1631 emac_wr(priv, DMA_CONTROL, val); 1632} 1633 1634static void emac_adjust_link(struct net_device *dev) 1635{ 1636 struct emac_priv *priv = netdev_priv(dev); 1637 struct phy_device *phydev = dev->phydev; 1638 u32 ctrl; 1639 1640 if (phydev->link) { 1641 ctrl = emac_rd(priv, MAC_GLOBAL_CONTROL); 1642 1643 /* Update duplex and speed from PHY */ 1644 1645 FIELD_MODIFY(MREGBIT_FULL_DUPLEX_MODE, &ctrl, 1646 phydev->duplex == DUPLEX_FULL); 1647 1648 ctrl &= ~MREGBIT_SPEED; 1649 1650 switch (phydev->speed) { 1651 case SPEED_1000: 1652 ctrl |= MREGBIT_SPEED_1000M; 1653 break; 1654 case SPEED_100: 1655 ctrl |= MREGBIT_SPEED_100M; 1656 break; 1657 case SPEED_10: 1658 ctrl |= MREGBIT_SPEED_10M; 1659 break; 1660 default: 1661 netdev_err(dev, "Unknown speed: %d\n", phydev->speed); 1662 phydev->speed = SPEED_UNKNOWN; 1663 break; 1664 } 1665 1666 emac_wr(priv, MAC_GLOBAL_CONTROL, ctrl); 1667 1668 emac_set_fc_autoneg(priv); 1669 1670 /* 1671 * Reschedule stats updates now that link is up. See comments in 1672 * emac_stats_update(). 1673 */ 1674 mod_timer(&priv->stats_timer, jiffies); 1675 } 1676 1677 phy_print_status(phydev); 1678} 1679 1680static void emac_update_delay_line(struct emac_priv *priv) 1681{ 1682 u32 mask = 0, val = 0; 1683 1684 mask |= EMAC_RX_DLINE_EN; 1685 mask |= EMAC_RX_DLINE_STEP_MASK | EMAC_RX_DLINE_CODE_MASK; 1686 mask |= EMAC_TX_DLINE_EN; 1687 mask |= EMAC_TX_DLINE_STEP_MASK | EMAC_TX_DLINE_CODE_MASK; 1688 1689 if (phy_interface_mode_is_rgmii(priv->phy_interface)) { 1690 val |= EMAC_RX_DLINE_EN; 1691 val |= FIELD_PREP(EMAC_RX_DLINE_STEP_MASK, 1692 EMAC_DLINE_STEP_15P6); 1693 val |= FIELD_PREP(EMAC_RX_DLINE_CODE_MASK, priv->rx_delay); 1694 1695 val |= EMAC_TX_DLINE_EN; 1696 val |= FIELD_PREP(EMAC_TX_DLINE_STEP_MASK, 1697 EMAC_DLINE_STEP_15P6); 1698 val |= FIELD_PREP(EMAC_TX_DLINE_CODE_MASK, priv->tx_delay); 1699 } 1700 1701 regmap_update_bits(priv->regmap_apmu, 1702 priv->regmap_apmu_offset + APMU_EMAC_DLINE_REG, 1703 mask, val); 1704} 1705 1706static int emac_phy_connect(struct net_device *ndev) 1707{ 1708 struct emac_priv *priv = netdev_priv(ndev); 1709 struct device *dev = &priv->pdev->dev; 1710 struct phy_device *phydev; 1711 struct device_node *np; 1712 int ret; 1713 1714 ret = of_get_phy_mode(dev->of_node, &priv->phy_interface); 1715 if (ret) { 1716 netdev_err(ndev, "No phy-mode found"); 1717 return ret; 1718 } 1719 1720 switch (priv->phy_interface) { 1721 case PHY_INTERFACE_MODE_RMII: 1722 case PHY_INTERFACE_MODE_RGMII: 1723 case PHY_INTERFACE_MODE_RGMII_ID: 1724 case PHY_INTERFACE_MODE_RGMII_RXID: 1725 case PHY_INTERFACE_MODE_RGMII_TXID: 1726 break; 1727 default: 1728 netdev_err(ndev, "Unsupported PHY interface %s", 1729 phy_modes(priv->phy_interface)); 1730 return -EINVAL; 1731 } 1732 1733 np = of_parse_phandle(dev->of_node, "phy-handle", 0); 1734 if (!np && of_phy_is_fixed_link(dev->of_node)) 1735 np = of_node_get(dev->of_node); 1736 1737 if (!np) { 1738 netdev_err(ndev, "No PHY specified"); 1739 return -ENODEV; 1740 } 1741 1742 ret = emac_phy_interface_config(priv); 1743 if (ret) 1744 goto err_node_put; 1745 1746 phydev = of_phy_connect(ndev, np, &emac_adjust_link, 0, 1747 priv->phy_interface); 1748 if (!phydev) { 1749 netdev_err(ndev, "Could not attach to PHY\n"); 1750 ret = -ENODEV; 1751 goto err_node_put; 1752 } 1753 1754 phy_support_asym_pause(phydev); 1755 1756 phydev->mac_managed_pm = true; 1757 1758 emac_update_delay_line(priv); 1759 1760err_node_put: 1761 of_node_put(np); 1762 return ret; 1763} 1764 1765static int emac_up(struct emac_priv *priv) 1766{ 1767 struct platform_device *pdev = priv->pdev; 1768 struct net_device *ndev = priv->ndev; 1769 int ret; 1770 1771 pm_runtime_get_sync(&pdev->dev); 1772 1773 ret = emac_phy_connect(ndev); 1774 if (ret) { 1775 dev_err(&pdev->dev, "emac_phy_connect failed\n"); 1776 goto err_pm_put; 1777 } 1778 1779 emac_init_hw(priv); 1780 1781 emac_set_mac_addr(priv, ndev->dev_addr); 1782 emac_configure_tx(priv); 1783 emac_configure_rx(priv); 1784 1785 emac_alloc_rx_desc_buffers(priv); 1786 1787 phy_start(ndev->phydev); 1788 1789 ret = request_irq(priv->irq, emac_interrupt_handler, IRQF_SHARED, 1790 ndev->name, ndev); 1791 if (ret) { 1792 dev_err(&pdev->dev, "request_irq failed\n"); 1793 goto err_reset_disconnect_phy; 1794 } 1795 1796 /* Don't enable MAC interrupts */ 1797 emac_wr(priv, MAC_INTERRUPT_ENABLE, 0x0); 1798 1799 /* Enable DMA interrupts */ 1800 emac_wr(priv, DMA_INTERRUPT_ENABLE, 1801 MREGBIT_TRANSMIT_TRANSFER_DONE_INTR_ENABLE | 1802 MREGBIT_TRANSMIT_DMA_STOPPED_INTR_ENABLE | 1803 MREGBIT_RECEIVE_TRANSFER_DONE_INTR_ENABLE | 1804 MREGBIT_RECEIVE_DMA_STOPPED_INTR_ENABLE | 1805 MREGBIT_RECEIVE_MISSED_FRAME_INTR_ENABLE); 1806 1807 napi_enable(&priv->napi); 1808 1809 netif_start_queue(ndev); 1810 1811 mod_timer(&priv->stats_timer, jiffies); 1812 1813 return 0; 1814 1815err_reset_disconnect_phy: 1816 emac_reset_hw(priv); 1817 phy_disconnect(ndev->phydev); 1818 1819err_pm_put: 1820 pm_runtime_put_sync(&pdev->dev); 1821 return ret; 1822} 1823 1824static int emac_down(struct emac_priv *priv) 1825{ 1826 struct platform_device *pdev = priv->pdev; 1827 struct net_device *ndev = priv->ndev; 1828 1829 netif_stop_queue(ndev); 1830 1831 phy_disconnect(ndev->phydev); 1832 1833 emac_wr(priv, MAC_INTERRUPT_ENABLE, 0x0); 1834 emac_wr(priv, DMA_INTERRUPT_ENABLE, 0x0); 1835 1836 free_irq(priv->irq, ndev); 1837 1838 napi_disable(&priv->napi); 1839 1840 timer_delete_sync(&priv->txtimer); 1841 cancel_work_sync(&priv->tx_timeout_task); 1842 1843 timer_delete_sync(&priv->stats_timer); 1844 1845 emac_reset_hw(priv); 1846 1847 /* Update and save current stats, see emac_stats_update() for usage */ 1848 1849 spin_lock_bh(&priv->stats_lock); 1850 1851 emac_stats_update(priv); 1852 1853 priv->tx_stats_off = priv->tx_stats; 1854 priv->rx_stats_off = priv->rx_stats; 1855 1856 spin_unlock_bh(&priv->stats_lock); 1857 1858 pm_runtime_put_sync(&pdev->dev); 1859 return 0; 1860} 1861 1862/* Called when net interface is brought up. */ 1863static int emac_open(struct net_device *ndev) 1864{ 1865 struct emac_priv *priv = netdev_priv(ndev); 1866 struct device *dev = &priv->pdev->dev; 1867 int ret; 1868 1869 ret = emac_alloc_tx_resources(priv); 1870 if (ret) { 1871 dev_err(dev, "Cannot allocate TX resources\n"); 1872 return ret; 1873 } 1874 1875 ret = emac_alloc_rx_resources(priv); 1876 if (ret) { 1877 dev_err(dev, "Cannot allocate RX resources\n"); 1878 goto err_free_tx; 1879 } 1880 1881 ret = emac_up(priv); 1882 if (ret) { 1883 dev_err(dev, "Error when bringing interface up\n"); 1884 goto err_free_rx; 1885 } 1886 return 0; 1887 1888err_free_rx: 1889 emac_free_rx_resources(priv); 1890err_free_tx: 1891 emac_free_tx_resources(priv); 1892 1893 return ret; 1894} 1895 1896/* Called when interface is brought down. */ 1897static int emac_stop(struct net_device *ndev) 1898{ 1899 struct emac_priv *priv = netdev_priv(ndev); 1900 1901 emac_down(priv); 1902 emac_free_tx_resources(priv); 1903 emac_free_rx_resources(priv); 1904 1905 return 0; 1906} 1907 1908static const struct ethtool_ops emac_ethtool_ops = { 1909 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1910 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1911 .nway_reset = phy_ethtool_nway_reset, 1912 .get_drvinfo = emac_get_drvinfo, 1913 .get_link = ethtool_op_get_link, 1914 1915 .get_regs = emac_ethtool_get_regs, 1916 .get_regs_len = emac_ethtool_get_regs_len, 1917 1918 .get_rmon_stats = emac_get_rmon_stats, 1919 .get_pause_stats = emac_get_pause_stats, 1920 .get_eth_mac_stats = emac_get_eth_mac_stats, 1921 1922 .get_sset_count = emac_get_sset_count, 1923 .get_strings = emac_get_strings, 1924 .get_ethtool_stats = emac_get_ethtool_stats, 1925 1926 .get_pauseparam = emac_get_pauseparam, 1927 .set_pauseparam = emac_set_pauseparam, 1928}; 1929 1930static const struct net_device_ops emac_netdev_ops = { 1931 .ndo_open = emac_open, 1932 .ndo_stop = emac_stop, 1933 .ndo_start_xmit = emac_start_xmit, 1934 .ndo_validate_addr = eth_validate_addr, 1935 .ndo_set_mac_address = emac_set_mac_address, 1936 .ndo_eth_ioctl = phy_do_ioctl_running, 1937 .ndo_change_mtu = emac_change_mtu, 1938 .ndo_tx_timeout = emac_tx_timeout, 1939 .ndo_set_rx_mode = emac_set_rx_mode, 1940 .ndo_get_stats64 = emac_get_stats64, 1941}; 1942 1943/* Currently we always use 15.6 ps/step for the delay line */ 1944 1945static u32 delay_ps_to_unit(u32 ps) 1946{ 1947 return DIV_ROUND_CLOSEST(ps * 10, 156); 1948} 1949 1950static u32 delay_unit_to_ps(u32 unit) 1951{ 1952 return DIV_ROUND_CLOSEST(unit * 156, 10); 1953} 1954 1955#define EMAC_MAX_DELAY_UNIT FIELD_MAX(EMAC_TX_DLINE_CODE_MASK) 1956 1957/* Minus one just to be safe from rounding errors */ 1958#define EMAC_MAX_DELAY_PS (delay_unit_to_ps(EMAC_MAX_DELAY_UNIT - 1)) 1959 1960static int emac_config_dt(struct platform_device *pdev, struct emac_priv *priv) 1961{ 1962 struct device_node *np = pdev->dev.of_node; 1963 struct device *dev = &pdev->dev; 1964 u8 mac_addr[ETH_ALEN] = { 0 }; 1965 int ret; 1966 1967 priv->iobase = devm_platform_ioremap_resource(pdev, 0); 1968 if (IS_ERR(priv->iobase)) 1969 return dev_err_probe(dev, PTR_ERR(priv->iobase), 1970 "ioremap failed\n"); 1971 1972 priv->regmap_apmu = 1973 syscon_regmap_lookup_by_phandle_args(np, "spacemit,apmu", 1, 1974 &priv->regmap_apmu_offset); 1975 1976 if (IS_ERR(priv->regmap_apmu)) 1977 return dev_err_probe(dev, PTR_ERR(priv->regmap_apmu), 1978 "failed to get syscon\n"); 1979 1980 priv->irq = platform_get_irq(pdev, 0); 1981 if (priv->irq < 0) 1982 return priv->irq; 1983 1984 ret = of_get_mac_address(np, mac_addr); 1985 if (ret) { 1986 if (ret == -EPROBE_DEFER) 1987 return dev_err_probe(dev, ret, 1988 "Can't get MAC address\n"); 1989 1990 dev_info(&pdev->dev, "Using random MAC address\n"); 1991 eth_hw_addr_random(priv->ndev); 1992 } else { 1993 eth_hw_addr_set(priv->ndev, mac_addr); 1994 } 1995 1996 priv->tx_delay = 0; 1997 priv->rx_delay = 0; 1998 1999 of_property_read_u32(np, "tx-internal-delay-ps", &priv->tx_delay); 2000 of_property_read_u32(np, "rx-internal-delay-ps", &priv->rx_delay); 2001 2002 if (priv->tx_delay > EMAC_MAX_DELAY_PS) { 2003 dev_err(&pdev->dev, 2004 "tx-internal-delay-ps too large: max %d, got %d", 2005 EMAC_MAX_DELAY_PS, priv->tx_delay); 2006 return -EINVAL; 2007 } 2008 2009 if (priv->rx_delay > EMAC_MAX_DELAY_PS) { 2010 dev_err(&pdev->dev, 2011 "rx-internal-delay-ps too large: max %d, got %d", 2012 EMAC_MAX_DELAY_PS, priv->rx_delay); 2013 return -EINVAL; 2014 } 2015 2016 priv->tx_delay = delay_ps_to_unit(priv->tx_delay); 2017 priv->rx_delay = delay_ps_to_unit(priv->rx_delay); 2018 2019 return 0; 2020} 2021 2022static void emac_phy_deregister_fixed_link(void *data) 2023{ 2024 struct device_node *of_node = data; 2025 2026 of_phy_deregister_fixed_link(of_node); 2027} 2028 2029static int emac_probe(struct platform_device *pdev) 2030{ 2031 struct device *dev = &pdev->dev; 2032 struct reset_control *reset; 2033 struct net_device *ndev; 2034 struct emac_priv *priv; 2035 int ret; 2036 2037 ndev = devm_alloc_etherdev(dev, sizeof(struct emac_priv)); 2038 if (!ndev) 2039 return -ENOMEM; 2040 2041 ndev->hw_features = NETIF_F_SG; 2042 ndev->features |= ndev->hw_features; 2043 2044 ndev->max_mtu = EMAC_RX_BUF_MAX - (ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN); 2045 ndev->pcpu_stat_type = NETDEV_PCPU_STAT_DSTATS; 2046 2047 priv = netdev_priv(ndev); 2048 priv->ndev = ndev; 2049 priv->pdev = pdev; 2050 platform_set_drvdata(pdev, priv); 2051 2052 ret = emac_config_dt(pdev, priv); 2053 if (ret < 0) 2054 return dev_err_probe(dev, ret, "Configuration failed\n"); 2055 2056 ndev->watchdog_timeo = 5 * HZ; 2057 ndev->base_addr = (unsigned long)priv->iobase; 2058 ndev->irq = priv->irq; 2059 2060 ndev->ethtool_ops = &emac_ethtool_ops; 2061 ndev->netdev_ops = &emac_netdev_ops; 2062 2063 devm_pm_runtime_enable(&pdev->dev); 2064 2065 priv->bus_clk = devm_clk_get_enabled(&pdev->dev, NULL); 2066 if (IS_ERR(priv->bus_clk)) 2067 return dev_err_probe(dev, PTR_ERR(priv->bus_clk), 2068 "Failed to get clock\n"); 2069 2070 reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, 2071 NULL); 2072 if (IS_ERR(reset)) 2073 return dev_err_probe(dev, PTR_ERR(reset), 2074 "Failed to get reset\n"); 2075 2076 if (of_phy_is_fixed_link(dev->of_node)) { 2077 ret = of_phy_register_fixed_link(dev->of_node); 2078 if (ret) 2079 return dev_err_probe(dev, ret, 2080 "Failed to register fixed-link\n"); 2081 2082 ret = devm_add_action_or_reset(dev, 2083 emac_phy_deregister_fixed_link, 2084 dev->of_node); 2085 2086 if (ret) { 2087 dev_err(dev, "devm_add_action_or_reset failed\n"); 2088 return ret; 2089 } 2090 } 2091 2092 emac_sw_init(priv); 2093 2094 ret = emac_mdio_init(priv); 2095 if (ret) 2096 goto err_timer_delete; 2097 2098 SET_NETDEV_DEV(ndev, &pdev->dev); 2099 2100 ret = devm_register_netdev(dev, ndev); 2101 if (ret) { 2102 dev_err(dev, "devm_register_netdev failed\n"); 2103 goto err_timer_delete; 2104 } 2105 2106 netif_napi_add(ndev, &priv->napi, emac_rx_poll); 2107 netif_carrier_off(ndev); 2108 2109 return 0; 2110 2111err_timer_delete: 2112 timer_delete_sync(&priv->txtimer); 2113 timer_delete_sync(&priv->stats_timer); 2114 2115 return ret; 2116} 2117 2118static void emac_remove(struct platform_device *pdev) 2119{ 2120 struct emac_priv *priv = platform_get_drvdata(pdev); 2121 2122 timer_shutdown_sync(&priv->txtimer); 2123 cancel_work_sync(&priv->tx_timeout_task); 2124 2125 timer_shutdown_sync(&priv->stats_timer); 2126 2127 emac_reset_hw(priv); 2128} 2129 2130static int emac_resume(struct device *dev) 2131{ 2132 struct emac_priv *priv = dev_get_drvdata(dev); 2133 struct net_device *ndev = priv->ndev; 2134 int ret; 2135 2136 ret = clk_prepare_enable(priv->bus_clk); 2137 if (ret < 0) { 2138 dev_err(dev, "Failed to enable bus clock: %d\n", ret); 2139 return ret; 2140 } 2141 2142 if (!netif_running(ndev)) 2143 return 0; 2144 2145 ret = emac_open(ndev); 2146 if (ret) { 2147 clk_disable_unprepare(priv->bus_clk); 2148 return ret; 2149 } 2150 2151 netif_device_attach(ndev); 2152 2153 mod_timer(&priv->stats_timer, jiffies); 2154 2155 return 0; 2156} 2157 2158static int emac_suspend(struct device *dev) 2159{ 2160 struct emac_priv *priv = dev_get_drvdata(dev); 2161 struct net_device *ndev = priv->ndev; 2162 2163 if (!ndev || !netif_running(ndev)) { 2164 clk_disable_unprepare(priv->bus_clk); 2165 return 0; 2166 } 2167 2168 emac_stop(ndev); 2169 2170 clk_disable_unprepare(priv->bus_clk); 2171 netif_device_detach(ndev); 2172 return 0; 2173} 2174 2175static const struct dev_pm_ops emac_pm_ops = { 2176 SYSTEM_SLEEP_PM_OPS(emac_suspend, emac_resume) 2177}; 2178 2179static const struct of_device_id emac_of_match[] = { 2180 { .compatible = "spacemit,k1-emac" }, 2181 { /* sentinel */ }, 2182}; 2183MODULE_DEVICE_TABLE(of, emac_of_match); 2184 2185static struct platform_driver emac_driver = { 2186 .probe = emac_probe, 2187 .remove = emac_remove, 2188 .driver = { 2189 .name = DRIVER_NAME, 2190 .of_match_table = of_match_ptr(emac_of_match), 2191 .pm = &emac_pm_ops, 2192 }, 2193}; 2194module_platform_driver(emac_driver); 2195 2196MODULE_DESCRIPTION("SpacemiT K1 Ethernet driver"); 2197MODULE_AUTHOR("Vivian Wang <wangruikang@iscas.ac.cn>"); 2198MODULE_LICENSE("GPL");
~/
Read-only file preview.