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netsec.c
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linux-6.19.14/drivers/net/ethernet/socionext/netsec.c
1// SPDX-License-Identifier: GPL-2.0+ 2 3#include <linux/types.h> 4#include <linux/clk.h> 5#include <linux/platform_device.h> 6#include <linux/pm_runtime.h> 7#include <linux/acpi.h> 8#include <linux/of_mdio.h> 9#include <linux/of_net.h> 10#include <linux/etherdevice.h> 11#include <linux/interrupt.h> 12#include <linux/io.h> 13#include <linux/netlink.h> 14#include <linux/bpf.h> 15#include <linux/bpf_trace.h> 16 17#include <net/tcp.h> 18#include <net/page_pool/helpers.h> 19#include <net/ip6_checksum.h> 20 21#define NETSEC_REG_SOFT_RST 0x104 22#define NETSEC_REG_COM_INIT 0x120 23 24#define NETSEC_REG_TOP_STATUS 0x200 25#define NETSEC_IRQ_RX BIT(1) 26#define NETSEC_IRQ_TX BIT(0) 27 28#define NETSEC_REG_TOP_INTEN 0x204 29#define NETSEC_REG_INTEN_SET 0x234 30#define NETSEC_REG_INTEN_CLR 0x238 31 32#define NETSEC_REG_NRM_TX_STATUS 0x400 33#define NETSEC_REG_NRM_TX_INTEN 0x404 34#define NETSEC_REG_NRM_TX_INTEN_SET 0x428 35#define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c 36#define NRM_TX_ST_NTOWNR BIT(17) 37#define NRM_TX_ST_TR_ERR BIT(16) 38#define NRM_TX_ST_TXDONE BIT(15) 39#define NRM_TX_ST_TMREXP BIT(14) 40 41#define NETSEC_REG_NRM_RX_STATUS 0x440 42#define NETSEC_REG_NRM_RX_INTEN 0x444 43#define NETSEC_REG_NRM_RX_INTEN_SET 0x468 44#define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c 45#define NRM_RX_ST_RC_ERR BIT(16) 46#define NRM_RX_ST_PKTCNT BIT(15) 47#define NRM_RX_ST_TMREXP BIT(14) 48 49#define NETSEC_REG_PKT_CMD_BUF 0xd0 50 51#define NETSEC_REG_CLK_EN 0x100 52 53#define NETSEC_REG_PKT_CTRL 0x140 54 55#define NETSEC_REG_DMA_TMR_CTRL 0x20c 56#define NETSEC_REG_F_TAIKI_MC_VER 0x22c 57#define NETSEC_REG_F_TAIKI_VER 0x230 58#define NETSEC_REG_DMA_HM_CTRL 0x214 59#define NETSEC_REG_DMA_MH_CTRL 0x220 60#define NETSEC_REG_ADDR_DIS_CORE 0x218 61#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 62#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c 63 64#define NETSEC_REG_NRM_TX_PKTCNT 0x410 65 66#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 67#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 68 69#define NETSEC_REG_NRM_TX_TMR 0x41c 70 71#define NETSEC_REG_NRM_RX_PKTCNT 0x454 72#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 73#define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 74#define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 75 76#define NETSEC_REG_NRM_RX_TMR 0x45c 77 78#define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 79#define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 80#define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 81#define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 82 83#define NETSEC_REG_NRM_TX_CONFIG 0x430 84#define NETSEC_REG_NRM_RX_CONFIG 0x470 85 86#define MAC_REG_STATUS 0x1024 87#define MAC_REG_DATA 0x11c0 88#define MAC_REG_CMD 0x11c4 89#define MAC_REG_FLOW_TH 0x11cc 90#define MAC_REG_INTF_SEL 0x11d4 91#define MAC_REG_DESC_INIT 0x11fc 92#define MAC_REG_DESC_SOFT_RST 0x1204 93#define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 94 95#define GMAC_REG_MCR 0x0000 96#define GMAC_REG_MFFR 0x0004 97#define GMAC_REG_GAR 0x0010 98#define GMAC_REG_GDR 0x0014 99#define GMAC_REG_FCR 0x0018 100#define GMAC_REG_BMR 0x1000 101#define GMAC_REG_RDLAR 0x100c 102#define GMAC_REG_TDLAR 0x1010 103#define GMAC_REG_OMR 0x1018 104 105#define MHZ(n) ((n) * 1000 * 1000) 106 107#define NETSEC_TX_SHIFT_OWN_FIELD 31 108#define NETSEC_TX_SHIFT_LD_FIELD 30 109#define NETSEC_TX_SHIFT_DRID_FIELD 24 110#define NETSEC_TX_SHIFT_PT_FIELD 21 111#define NETSEC_TX_SHIFT_TDRID_FIELD 16 112#define NETSEC_TX_SHIFT_CC_FIELD 15 113#define NETSEC_TX_SHIFT_FS_FIELD 9 114#define NETSEC_TX_LAST 8 115#define NETSEC_TX_SHIFT_CO 7 116#define NETSEC_TX_SHIFT_SO 6 117#define NETSEC_TX_SHIFT_TRS_FIELD 4 118 119#define NETSEC_RX_PKT_OWN_FIELD 31 120#define NETSEC_RX_PKT_LD_FIELD 30 121#define NETSEC_RX_PKT_SDRID_FIELD 24 122#define NETSEC_RX_PKT_FR_FIELD 23 123#define NETSEC_RX_PKT_ER_FIELD 21 124#define NETSEC_RX_PKT_ERR_FIELD 16 125#define NETSEC_RX_PKT_TDRID_FIELD 12 126#define NETSEC_RX_PKT_FS_FIELD 9 127#define NETSEC_RX_PKT_LS_FIELD 8 128#define NETSEC_RX_PKT_CO_FIELD 6 129 130#define NETSEC_RX_PKT_ERR_MASK 3 131 132#define NETSEC_MAX_TX_PKT_LEN 1518 133#define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 134 135#define NETSEC_RING_GMAC 15 136#define NETSEC_RING_MAX 2 137 138#define NETSEC_TCP_SEG_LEN_MAX 1460 139#define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 140 141#define NETSEC_RX_CKSUM_NOTAVAIL 0 142#define NETSEC_RX_CKSUM_OK 1 143#define NETSEC_RX_CKSUM_NG 2 144 145#define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20) 146#define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) 147 148#define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) 149#define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) 150 151#define NETSEC_INT_PKTCNT_MAX 2047 152 153#define NETSEC_FLOW_START_TH_MAX 95 154#define NETSEC_FLOW_STOP_TH_MAX 95 155#define NETSEC_FLOW_PAUSE_TIME_MIN 5 156 157#define NETSEC_CLK_EN_REG_DOM_ALL 0x3f 158 159#define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) 160#define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) 161#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) 162#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) 163#define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) 164#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) 165 166#define NETSEC_CLK_EN_REG_DOM_G BIT(5) 167#define NETSEC_CLK_EN_REG_DOM_C BIT(1) 168#define NETSEC_CLK_EN_REG_DOM_D BIT(0) 169 170#define NETSEC_COM_INIT_REG_DB BIT(2) 171#define NETSEC_COM_INIT_REG_CLS BIT(1) 172#define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ 173 NETSEC_COM_INIT_REG_DB) 174 175#define NETSEC_SOFT_RST_REG_RESET 0 176#define NETSEC_SOFT_RST_REG_RUN BIT(31) 177 178#define NETSEC_DMA_CTRL_REG_STOP 1 179#define MH_CTRL__MODE_TRANS BIT(20) 180 181#define NETSEC_GMAC_CMD_ST_READ 0 182#define NETSEC_GMAC_CMD_ST_WRITE BIT(28) 183#define NETSEC_GMAC_CMD_ST_BUSY BIT(31) 184 185#define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 186#define NETSEC_GMAC_BMR_REG_RESET 0x00020181 187#define NETSEC_GMAC_BMR_REG_SWR 0x00000001 188 189#define NETSEC_GMAC_OMR_REG_ST BIT(13) 190#define NETSEC_GMAC_OMR_REG_SR BIT(1) 191 192#define NETSEC_GMAC_MCR_REG_IBN BIT(30) 193#define NETSEC_GMAC_MCR_REG_CST BIT(25) 194#define NETSEC_GMAC_MCR_REG_JE BIT(20) 195#define NETSEC_MCR_PS BIT(15) 196#define NETSEC_GMAC_MCR_REG_FES BIT(14) 197#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c 198#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c 199 200#define NETSEC_FCR_RFE BIT(2) 201#define NETSEC_FCR_TFE BIT(1) 202 203#define NETSEC_GMAC_GAR_REG_GW BIT(1) 204#define NETSEC_GMAC_GAR_REG_GB BIT(0) 205 206#define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 207#define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 208#define GMAC_REG_SHIFT_CR_GAR 2 209 210#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 211#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 212#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 213#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 214#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 215#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 216 217#define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 218#define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 219 220#define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 221 222#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) 223#define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) 224#define NETSEC_REG_DESC_TMR_MODE 4 225#define NETSEC_REG_DESC_ENDIAN 0 226 227#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 228#define NETSEC_MAC_DESC_INIT_REG_INIT 1 229 230#define NETSEC_EEPROM_MAC_ADDRESS 0x00 231#define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 232#define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C 233#define NETSEC_EEPROM_HM_ME_SIZE 0x10 234#define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 235#define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 236#define NETSEC_EEPROM_MH_ME_SIZE 0x1C 237#define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 238#define NETSEC_EEPROM_PKT_ME_SIZE 0x24 239 240#define DESC_NUM 256 241 242#define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 243#define NETSEC_RXBUF_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ 244 NET_IP_ALIGN) 245#define NETSEC_RX_BUF_NON_DATA (NETSEC_RXBUF_HEADROOM + \ 246 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 247#define NETSEC_RX_BUF_SIZE (PAGE_SIZE - NETSEC_RX_BUF_NON_DATA) 248 249#define DESC_SZ sizeof(struct netsec_de) 250 251#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) 252 253#define NETSEC_XDP_PASS 0 254#define NETSEC_XDP_CONSUMED BIT(0) 255#define NETSEC_XDP_TX BIT(1) 256#define NETSEC_XDP_REDIR BIT(2) 257 258enum ring_id { 259 NETSEC_RING_TX = 0, 260 NETSEC_RING_RX 261}; 262 263enum buf_type { 264 TYPE_NETSEC_SKB = 0, 265 TYPE_NETSEC_XDP_TX, 266 TYPE_NETSEC_XDP_NDO, 267}; 268 269struct netsec_desc { 270 union { 271 struct sk_buff *skb; 272 struct xdp_frame *xdpf; 273 }; 274 dma_addr_t dma_addr; 275 void *addr; 276 u16 len; 277 u8 buf_type; 278}; 279 280struct netsec_desc_ring { 281 dma_addr_t desc_dma; 282 struct netsec_desc *desc; 283 void *vaddr; 284 u16 head, tail; 285 u16 xdp_xmit; /* netsec_xdp_xmit packets */ 286 struct page_pool *page_pool; 287 struct xdp_rxq_info xdp_rxq; 288 spinlock_t lock; /* XDP tx queue locking */ 289}; 290 291struct netsec_priv { 292 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX]; 293 struct ethtool_coalesce et_coalesce; 294 struct bpf_prog *xdp_prog; 295 spinlock_t reglock; /* protect reg access */ 296 struct napi_struct napi; 297 phy_interface_t phy_interface; 298 struct net_device *ndev; 299 struct device_node *phy_np; 300 struct phy_device *phydev; 301 struct mii_bus *mii_bus; 302 void __iomem *ioaddr; 303 void __iomem *eeprom_base; 304 struct device *dev; 305 struct clk *clk; 306 u32 msg_enable; 307 u32 freq; 308 u32 phy_addr; 309 bool rx_cksum_offload_flag; 310}; 311 312struct netsec_de { /* Netsec Descriptor layout */ 313 u32 attr; 314 u32 data_buf_addr_up; 315 u32 data_buf_addr_lw; 316 u32 buf_len_info; 317}; 318 319struct netsec_tx_pkt_ctrl { 320 u16 tcp_seg_len; 321 bool tcp_seg_offload_flag; 322 bool cksum_offload_flag; 323}; 324 325struct netsec_rx_pkt_info { 326 int rx_cksum_result; 327 int err_code; 328 bool err_flag; 329}; 330 331static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val) 332{ 333 writel(val, priv->ioaddr + reg_addr); 334} 335 336static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr) 337{ 338 return readl(priv->ioaddr + reg_addr); 339} 340 341/************* MDIO BUS OPS FOLLOW *************/ 342 343#define TIMEOUT_SPINS_MAC 1000 344#define TIMEOUT_SECONDARY_MS_MAC 100 345 346static u32 netsec_clk_type(u32 freq) 347{ 348 if (freq < MHZ(35)) 349 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; 350 if (freq < MHZ(60)) 351 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; 352 if (freq < MHZ(100)) 353 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; 354 if (freq < MHZ(150)) 355 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; 356 if (freq < MHZ(250)) 357 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; 358 359 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; 360} 361 362static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) 363{ 364 u32 timeout = TIMEOUT_SPINS_MAC; 365 366 while (--timeout && netsec_read(priv, addr) & mask) 367 cpu_relax(); 368 if (timeout) 369 return 0; 370 371 timeout = TIMEOUT_SECONDARY_MS_MAC; 372 while (--timeout && netsec_read(priv, addr) & mask) 373 usleep_range(1000, 2000); 374 375 if (timeout) 376 return 0; 377 378 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 379 380 return -ETIMEDOUT; 381} 382 383static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value) 384{ 385 netsec_write(priv, MAC_REG_DATA, value); 386 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); 387 return netsec_wait_while_busy(priv, 388 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 389} 390 391static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read) 392{ 393 int ret; 394 395 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); 396 ret = netsec_wait_while_busy(priv, 397 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); 398 if (ret) 399 return ret; 400 401 *read = netsec_read(priv, MAC_REG_DATA); 402 403 return 0; 404} 405 406static int netsec_mac_wait_while_busy(struct netsec_priv *priv, 407 u32 addr, u32 mask) 408{ 409 u32 timeout = TIMEOUT_SPINS_MAC; 410 int ret, data; 411 412 do { 413 ret = netsec_mac_read(priv, addr, &data); 414 if (ret) 415 break; 416 cpu_relax(); 417 } while (--timeout && (data & mask)); 418 419 if (timeout) 420 return 0; 421 422 timeout = TIMEOUT_SECONDARY_MS_MAC; 423 do { 424 usleep_range(1000, 2000); 425 426 ret = netsec_mac_read(priv, addr, &data); 427 if (ret) 428 break; 429 cpu_relax(); 430 } while (--timeout && (data & mask)); 431 432 if (timeout && !ret) 433 return 0; 434 435 netdev_WARN(priv->ndev, "%s: timeout\n", __func__); 436 437 return -ETIMEDOUT; 438} 439 440static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) 441{ 442 struct phy_device *phydev = priv->ndev->phydev; 443 u32 value = 0; 444 445 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : 446 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; 447 448 if (phydev->speed != SPEED_1000) 449 value |= NETSEC_MCR_PS; 450 451 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII && 452 phydev->speed == SPEED_100) 453 value |= NETSEC_GMAC_MCR_REG_FES; 454 455 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; 456 457 if (phy_interface_mode_is_rgmii(priv->phy_interface)) 458 value |= NETSEC_GMAC_MCR_REG_IBN; 459 460 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 461 return -ETIMEDOUT; 462 463 return 0; 464} 465 466static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); 467 468static int netsec_phy_write(struct mii_bus *bus, 469 int phy_addr, int reg, u16 val) 470{ 471 int status; 472 struct netsec_priv *priv = bus->priv; 473 474 if (netsec_mac_write(priv, GMAC_REG_GDR, val)) 475 return -ETIMEDOUT; 476 if (netsec_mac_write(priv, GMAC_REG_GAR, 477 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 478 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | 479 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | 480 (netsec_clk_type(priv->freq) << 481 GMAC_REG_SHIFT_CR_GAR))) 482 return -ETIMEDOUT; 483 484 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 485 NETSEC_GMAC_GAR_REG_GB); 486 487 /* Developerbox implements RTL8211E PHY and there is 488 * a compatibility problem with F_GMAC4. 489 * RTL8211E expects MDC clock must be kept toggling for several 490 * clock cycle with MDIO high before entering the IDLE state. 491 * To meet this requirement, netsec driver needs to issue dummy 492 * read(e.g. read PHYID1(offset 0x2) register) right after write. 493 */ 494 netsec_phy_read(bus, phy_addr, MII_PHYSID1); 495 496 return status; 497} 498 499static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) 500{ 501 struct netsec_priv *priv = bus->priv; 502 u32 data; 503 int ret; 504 505 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | 506 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | 507 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | 508 (netsec_clk_type(priv->freq) << 509 GMAC_REG_SHIFT_CR_GAR))) 510 return -ETIMEDOUT; 511 512 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, 513 NETSEC_GMAC_GAR_REG_GB); 514 if (ret) 515 return ret; 516 517 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data); 518 if (ret) 519 return ret; 520 521 return data; 522} 523 524/************* ETHTOOL_OPS FOLLOW *************/ 525 526static void netsec_et_get_drvinfo(struct net_device *net_device, 527 struct ethtool_drvinfo *info) 528{ 529 strscpy(info->driver, "netsec", sizeof(info->driver)); 530 strscpy(info->bus_info, dev_name(net_device->dev.parent), 531 sizeof(info->bus_info)); 532} 533 534static int netsec_et_get_coalesce(struct net_device *net_device, 535 struct ethtool_coalesce *et_coalesce, 536 struct kernel_ethtool_coalesce *kernel_coal, 537 struct netlink_ext_ack *extack) 538{ 539 struct netsec_priv *priv = netdev_priv(net_device); 540 541 *et_coalesce = priv->et_coalesce; 542 543 return 0; 544} 545 546static int netsec_et_set_coalesce(struct net_device *net_device, 547 struct ethtool_coalesce *et_coalesce, 548 struct kernel_ethtool_coalesce *kernel_coal, 549 struct netlink_ext_ack *extack) 550{ 551 struct netsec_priv *priv = netdev_priv(net_device); 552 553 priv->et_coalesce = *et_coalesce; 554 555 if (priv->et_coalesce.tx_coalesce_usecs < 50) 556 priv->et_coalesce.tx_coalesce_usecs = 50; 557 if (priv->et_coalesce.tx_max_coalesced_frames < 1) 558 priv->et_coalesce.tx_max_coalesced_frames = 1; 559 560 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT, 561 priv->et_coalesce.tx_max_coalesced_frames); 562 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR, 563 priv->et_coalesce.tx_coalesce_usecs); 564 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE); 565 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP); 566 567 if (priv->et_coalesce.rx_coalesce_usecs < 50) 568 priv->et_coalesce.rx_coalesce_usecs = 50; 569 if (priv->et_coalesce.rx_max_coalesced_frames < 1) 570 priv->et_coalesce.rx_max_coalesced_frames = 1; 571 572 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT, 573 priv->et_coalesce.rx_max_coalesced_frames); 574 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR, 575 priv->et_coalesce.rx_coalesce_usecs); 576 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT); 577 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP); 578 579 return 0; 580} 581 582static u32 netsec_et_get_msglevel(struct net_device *dev) 583{ 584 struct netsec_priv *priv = netdev_priv(dev); 585 586 return priv->msg_enable; 587} 588 589static void netsec_et_set_msglevel(struct net_device *dev, u32 datum) 590{ 591 struct netsec_priv *priv = netdev_priv(dev); 592 593 priv->msg_enable = datum; 594} 595 596static const struct ethtool_ops netsec_ethtool_ops = { 597 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 598 ETHTOOL_COALESCE_MAX_FRAMES, 599 .get_drvinfo = netsec_et_get_drvinfo, 600 .get_link_ksettings = phy_ethtool_get_link_ksettings, 601 .set_link_ksettings = phy_ethtool_set_link_ksettings, 602 .get_link = ethtool_op_get_link, 603 .get_coalesce = netsec_et_get_coalesce, 604 .set_coalesce = netsec_et_set_coalesce, 605 .get_msglevel = netsec_et_get_msglevel, 606 .set_msglevel = netsec_et_set_msglevel, 607}; 608 609/************* NETDEV_OPS FOLLOW *************/ 610 611 612static void netsec_set_rx_de(struct netsec_priv *priv, 613 struct netsec_desc_ring *dring, u16 idx, 614 const struct netsec_desc *desc) 615{ 616 struct netsec_de *de = dring->vaddr + DESC_SZ * idx; 617 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | 618 (1 << NETSEC_RX_PKT_FS_FIELD) | 619 (1 << NETSEC_RX_PKT_LS_FIELD); 620 621 if (idx == DESC_NUM - 1) 622 attr |= (1 << NETSEC_RX_PKT_LD_FIELD); 623 624 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 625 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 626 de->buf_len_info = desc->len; 627 de->attr = attr; 628 dma_wmb(); 629 630 dring->desc[idx].dma_addr = desc->dma_addr; 631 dring->desc[idx].addr = desc->addr; 632 dring->desc[idx].len = desc->len; 633} 634 635static bool netsec_clean_tx_dring(struct netsec_priv *priv) 636{ 637 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 638 struct xdp_frame_bulk bq; 639 struct netsec_de *entry; 640 int tail = dring->tail; 641 unsigned int bytes; 642 int cnt = 0; 643 644 spin_lock(&dring->lock); 645 646 bytes = 0; 647 xdp_frame_bulk_init(&bq); 648 entry = dring->vaddr + DESC_SZ * tail; 649 650 rcu_read_lock(); /* need for xdp_return_frame_bulk */ 651 652 while (!(entry->attr & (1U << NETSEC_TX_SHIFT_OWN_FIELD)) && 653 cnt < DESC_NUM) { 654 struct netsec_desc *desc; 655 int eop; 656 657 desc = &dring->desc[tail]; 658 eop = (entry->attr >> NETSEC_TX_LAST) & 1; 659 dma_rmb(); 660 661 /* if buf_type is either TYPE_NETSEC_SKB or 662 * TYPE_NETSEC_XDP_NDO we mapped it 663 */ 664 if (desc->buf_type != TYPE_NETSEC_XDP_TX) 665 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 666 DMA_TO_DEVICE); 667 668 if (!eop) 669 goto next; 670 671 if (desc->buf_type == TYPE_NETSEC_SKB) { 672 bytes += desc->skb->len; 673 dev_kfree_skb(desc->skb); 674 } else { 675 bytes += desc->xdpf->len; 676 if (desc->buf_type == TYPE_NETSEC_XDP_TX) 677 xdp_return_frame_rx_napi(desc->xdpf); 678 else 679 xdp_return_frame_bulk(desc->xdpf, &bq); 680 } 681next: 682 /* clean up so netsec_uninit_pkt_dring() won't free the skb 683 * again 684 */ 685 *desc = (struct netsec_desc){}; 686 687 /* entry->attr is not going to be accessed by the NIC until 688 * netsec_set_tx_de() is called. No need for a dma_wmb() here 689 */ 690 entry->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 691 /* move tail ahead */ 692 dring->tail = (tail + 1) % DESC_NUM; 693 694 tail = dring->tail; 695 entry = dring->vaddr + DESC_SZ * tail; 696 cnt++; 697 } 698 xdp_flush_frame_bulk(&bq); 699 700 rcu_read_unlock(); 701 702 spin_unlock(&dring->lock); 703 704 if (!cnt) 705 return false; 706 707 /* reading the register clears the irq */ 708 netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); 709 710 priv->ndev->stats.tx_packets += cnt; 711 priv->ndev->stats.tx_bytes += bytes; 712 713 netdev_completed_queue(priv->ndev, cnt, bytes); 714 715 return true; 716} 717 718static void netsec_process_tx(struct netsec_priv *priv) 719{ 720 struct net_device *ndev = priv->ndev; 721 bool cleaned; 722 723 cleaned = netsec_clean_tx_dring(priv); 724 725 if (cleaned && netif_queue_stopped(ndev)) { 726 /* Make sure we update the value, anyone stopping the queue 727 * after this will read the proper consumer idx 728 */ 729 smp_wmb(); 730 netif_wake_queue(ndev); 731 } 732} 733 734static void *netsec_alloc_rx_data(struct netsec_priv *priv, 735 dma_addr_t *dma_handle, u16 *desc_len) 736 737{ 738 739 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 740 struct page *page; 741 742 page = page_pool_dev_alloc_pages(dring->page_pool); 743 if (!page) 744 return NULL; 745 746 /* We allocate the same buffer length for XDP and non-XDP cases. 747 * page_pool API will map the whole page, skip what's needed for 748 * network payloads and/or XDP 749 */ 750 *dma_handle = page_pool_get_dma_addr(page) + NETSEC_RXBUF_HEADROOM; 751 /* Make sure the incoming payload fits in the page for XDP and non-XDP 752 * cases and reserve enough space for headroom + skb_shared_info 753 */ 754 *desc_len = NETSEC_RX_BUF_SIZE; 755 756 return page_address(page); 757} 758 759static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num) 760{ 761 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 762 u16 idx = from; 763 764 while (num) { 765 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]); 766 idx++; 767 if (idx >= DESC_NUM) 768 idx = 0; 769 num--; 770 } 771} 772 773static void netsec_xdp_ring_tx_db(struct netsec_priv *priv, u16 pkts) 774{ 775 if (likely(pkts)) 776 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts); 777} 778 779static void netsec_finalize_xdp_rx(struct netsec_priv *priv, u32 xdp_res, 780 u16 pkts) 781{ 782 if (xdp_res & NETSEC_XDP_REDIR) 783 xdp_do_flush(); 784 785 if (xdp_res & NETSEC_XDP_TX) 786 netsec_xdp_ring_tx_db(priv, pkts); 787} 788 789static void netsec_set_tx_de(struct netsec_priv *priv, 790 struct netsec_desc_ring *dring, 791 const struct netsec_tx_pkt_ctrl *tx_ctrl, 792 const struct netsec_desc *desc, void *buf) 793{ 794 int idx = dring->head; 795 struct netsec_de *de; 796 u32 attr; 797 798 de = dring->vaddr + (DESC_SZ * idx); 799 800 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | 801 (1 << NETSEC_TX_SHIFT_PT_FIELD) | 802 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | 803 (1 << NETSEC_TX_SHIFT_FS_FIELD) | 804 (1 << NETSEC_TX_LAST) | 805 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | 806 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | 807 (1 << NETSEC_TX_SHIFT_TRS_FIELD); 808 if (idx == DESC_NUM - 1) 809 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD); 810 811 de->data_buf_addr_up = upper_32_bits(desc->dma_addr); 812 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr); 813 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; 814 de->attr = attr; 815 816 dring->desc[idx] = *desc; 817 if (desc->buf_type == TYPE_NETSEC_SKB) 818 dring->desc[idx].skb = buf; 819 else if (desc->buf_type == TYPE_NETSEC_XDP_TX || 820 desc->buf_type == TYPE_NETSEC_XDP_NDO) 821 dring->desc[idx].xdpf = buf; 822 823 /* move head ahead */ 824 dring->head = (dring->head + 1) % DESC_NUM; 825} 826 827/* The current driver only supports 1 Txq, this should run under spin_lock() */ 828static u32 netsec_xdp_queue_one(struct netsec_priv *priv, 829 struct xdp_frame *xdpf, bool is_ndo) 830 831{ 832 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 833 struct page *page = virt_to_page(xdpf->data); 834 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 835 struct netsec_desc tx_desc; 836 dma_addr_t dma_handle; 837 u16 filled; 838 839 if (tx_ring->head >= tx_ring->tail) 840 filled = tx_ring->head - tx_ring->tail; 841 else 842 filled = tx_ring->head + DESC_NUM - tx_ring->tail; 843 844 if (DESC_NUM - filled <= 1) 845 return NETSEC_XDP_CONSUMED; 846 847 if (is_ndo) { 848 /* this is for ndo_xdp_xmit, the buffer needs mapping before 849 * sending 850 */ 851 dma_handle = dma_map_single(priv->dev, xdpf->data, xdpf->len, 852 DMA_TO_DEVICE); 853 if (dma_mapping_error(priv->dev, dma_handle)) 854 return NETSEC_XDP_CONSUMED; 855 tx_desc.buf_type = TYPE_NETSEC_XDP_NDO; 856 } else { 857 /* This is the device Rx buffer from page_pool. No need to remap 858 * just sync and send it 859 */ 860 struct netsec_desc_ring *rx_ring = 861 &priv->desc_ring[NETSEC_RING_RX]; 862 enum dma_data_direction dma_dir = 863 page_pool_get_dma_dir(rx_ring->page_pool); 864 865 dma_handle = page_pool_get_dma_addr(page) + xdpf->headroom + 866 sizeof(*xdpf); 867 dma_sync_single_for_device(priv->dev, dma_handle, xdpf->len, 868 dma_dir); 869 tx_desc.buf_type = TYPE_NETSEC_XDP_TX; 870 } 871 872 tx_desc.dma_addr = dma_handle; 873 tx_desc.addr = xdpf->data; 874 tx_desc.len = xdpf->len; 875 876 netdev_sent_queue(priv->ndev, xdpf->len); 877 netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf); 878 879 return NETSEC_XDP_TX; 880} 881 882static u32 netsec_xdp_xmit_back(struct netsec_priv *priv, struct xdp_buff *xdp) 883{ 884 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 885 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 886 u32 ret; 887 888 if (unlikely(!xdpf)) 889 return NETSEC_XDP_CONSUMED; 890 891 spin_lock(&tx_ring->lock); 892 ret = netsec_xdp_queue_one(priv, xdpf, false); 893 spin_unlock(&tx_ring->lock); 894 895 return ret; 896} 897 898static u32 netsec_run_xdp(struct netsec_priv *priv, struct bpf_prog *prog, 899 struct xdp_buff *xdp) 900{ 901 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 902 unsigned int sync, len = xdp->data_end - xdp->data; 903 u32 ret = NETSEC_XDP_PASS; 904 struct page *page; 905 int err; 906 u32 act; 907 908 act = bpf_prog_run_xdp(prog, xdp); 909 910 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 911 sync = xdp->data_end - xdp->data_hard_start - NETSEC_RXBUF_HEADROOM; 912 sync = max(sync, len); 913 914 switch (act) { 915 case XDP_PASS: 916 ret = NETSEC_XDP_PASS; 917 break; 918 case XDP_TX: 919 ret = netsec_xdp_xmit_back(priv, xdp); 920 if (ret != NETSEC_XDP_TX) { 921 page = virt_to_head_page(xdp->data); 922 page_pool_put_page(dring->page_pool, page, sync, true); 923 } 924 break; 925 case XDP_REDIRECT: 926 err = xdp_do_redirect(priv->ndev, xdp, prog); 927 if (!err) { 928 ret = NETSEC_XDP_REDIR; 929 } else { 930 ret = NETSEC_XDP_CONSUMED; 931 page = virt_to_head_page(xdp->data); 932 page_pool_put_page(dring->page_pool, page, sync, true); 933 } 934 break; 935 default: 936 bpf_warn_invalid_xdp_action(priv->ndev, prog, act); 937 fallthrough; 938 case XDP_ABORTED: 939 trace_xdp_exception(priv->ndev, prog, act); 940 fallthrough; /* handle aborts by dropping packet */ 941 case XDP_DROP: 942 ret = NETSEC_XDP_CONSUMED; 943 page = virt_to_head_page(xdp->data); 944 page_pool_put_page(dring->page_pool, page, sync, true); 945 break; 946 } 947 948 return ret; 949} 950 951static int netsec_process_rx(struct netsec_priv *priv, int budget) 952{ 953 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 954 struct net_device *ndev = priv->ndev; 955 struct netsec_rx_pkt_info rx_info; 956 enum dma_data_direction dma_dir; 957 struct bpf_prog *xdp_prog; 958 struct xdp_buff xdp; 959 u16 xdp_xmit = 0; 960 u32 xdp_act = 0; 961 int done = 0; 962 963 xdp_init_buff(&xdp, PAGE_SIZE, &dring->xdp_rxq); 964 965 xdp_prog = READ_ONCE(priv->xdp_prog); 966 dma_dir = page_pool_get_dma_dir(dring->page_pool); 967 968 while (done < budget) { 969 u16 idx = dring->tail; 970 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx); 971 struct netsec_desc *desc = &dring->desc[idx]; 972 struct page *page = virt_to_page(desc->addr); 973 u32 metasize, xdp_result = NETSEC_XDP_PASS; 974 struct sk_buff *skb = NULL; 975 u16 pkt_len, desc_len; 976 dma_addr_t dma_handle; 977 void *buf_addr; 978 979 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) { 980 /* reading the register clears the irq */ 981 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT); 982 break; 983 } 984 985 /* This barrier is needed to keep us from reading 986 * any other fields out of the netsec_de until we have 987 * verified the descriptor has been written back 988 */ 989 dma_rmb(); 990 done++; 991 992 pkt_len = de->buf_len_info >> 16; 993 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) & 994 NETSEC_RX_PKT_ERR_MASK; 995 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1; 996 if (rx_info.err_flag) { 997 netif_err(priv, drv, priv->ndev, 998 "%s: rx fail err(%d)\n", __func__, 999 rx_info.err_code); 1000 ndev->stats.rx_dropped++; 1001 dring->tail = (dring->tail + 1) % DESC_NUM; 1002 /* reuse buffer page frag */ 1003 netsec_rx_fill(priv, idx, 1); 1004 continue; 1005 } 1006 rx_info.rx_cksum_result = 1007 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3; 1008 1009 /* allocate a fresh buffer and map it to the hardware. 1010 * This will eventually replace the old buffer in the hardware 1011 */ 1012 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len); 1013 1014 if (unlikely(!buf_addr)) 1015 break; 1016 1017 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len, 1018 dma_dir); 1019 prefetch(desc->addr); 1020 1021 xdp_prepare_buff(&xdp, desc->addr, NETSEC_RXBUF_HEADROOM, 1022 pkt_len, true); 1023 1024 if (xdp_prog) { 1025 xdp_result = netsec_run_xdp(priv, xdp_prog, &xdp); 1026 if (xdp_result != NETSEC_XDP_PASS) { 1027 xdp_act |= xdp_result; 1028 if (xdp_result == NETSEC_XDP_TX) 1029 xdp_xmit++; 1030 goto next; 1031 } 1032 } 1033 skb = build_skb(desc->addr, desc->len + NETSEC_RX_BUF_NON_DATA); 1034 1035 if (unlikely(!skb)) { 1036 /* If skb fails recycle_direct will either unmap and 1037 * free the page or refill the cache depending on the 1038 * cache state. Since we paid the allocation cost if 1039 * building an skb fails try to put the page into cache 1040 */ 1041 page_pool_put_page(dring->page_pool, page, pkt_len, 1042 true); 1043 netif_err(priv, drv, priv->ndev, 1044 "rx failed to build skb\n"); 1045 break; 1046 } 1047 skb_mark_for_recycle(skb); 1048 1049 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1050 skb_put(skb, xdp.data_end - xdp.data); 1051 metasize = xdp.data - xdp.data_meta; 1052 if (metasize) 1053 skb_metadata_set(skb, metasize); 1054 skb->protocol = eth_type_trans(skb, priv->ndev); 1055 1056 if (priv->rx_cksum_offload_flag && 1057 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK) 1058 skb->ip_summed = CHECKSUM_UNNECESSARY; 1059 1060next: 1061 if (skb) 1062 napi_gro_receive(&priv->napi, skb); 1063 if (skb || xdp_result) { 1064 ndev->stats.rx_packets++; 1065 ndev->stats.rx_bytes += xdp.data_end - xdp.data; 1066 } 1067 1068 /* Update the descriptor with fresh buffers */ 1069 desc->len = desc_len; 1070 desc->dma_addr = dma_handle; 1071 desc->addr = buf_addr; 1072 1073 netsec_rx_fill(priv, idx, 1); 1074 dring->tail = (dring->tail + 1) % DESC_NUM; 1075 } 1076 netsec_finalize_xdp_rx(priv, xdp_act, xdp_xmit); 1077 1078 return done; 1079} 1080 1081static int netsec_napi_poll(struct napi_struct *napi, int budget) 1082{ 1083 struct netsec_priv *priv; 1084 int done; 1085 1086 priv = container_of(napi, struct netsec_priv, napi); 1087 1088 netsec_process_tx(priv); 1089 done = netsec_process_rx(priv, budget); 1090 1091 if (done < budget && napi_complete_done(napi, done)) { 1092 unsigned long flags; 1093 1094 spin_lock_irqsave(&priv->reglock, flags); 1095 netsec_write(priv, NETSEC_REG_INTEN_SET, 1096 NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1097 spin_unlock_irqrestore(&priv->reglock, flags); 1098 } 1099 1100 return done; 1101} 1102 1103 1104static int netsec_desc_used(struct netsec_desc_ring *dring) 1105{ 1106 int used; 1107 1108 if (dring->head >= dring->tail) 1109 used = dring->head - dring->tail; 1110 else 1111 used = dring->head + DESC_NUM - dring->tail; 1112 1113 return used; 1114} 1115 1116static int netsec_check_stop_tx(struct netsec_priv *priv, int used) 1117{ 1118 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1119 1120 /* keep tail from touching the queue */ 1121 if (DESC_NUM - used < 2) { 1122 netif_stop_queue(priv->ndev); 1123 1124 /* Make sure we read the updated value in case 1125 * descriptors got freed 1126 */ 1127 smp_rmb(); 1128 1129 used = netsec_desc_used(dring); 1130 if (DESC_NUM - used < 2) 1131 return NETDEV_TX_BUSY; 1132 1133 netif_wake_queue(priv->ndev); 1134 } 1135 1136 return 0; 1137} 1138 1139static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb, 1140 struct net_device *ndev) 1141{ 1142 struct netsec_priv *priv = netdev_priv(ndev); 1143 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1144 struct netsec_tx_pkt_ctrl tx_ctrl = {}; 1145 struct netsec_desc tx_desc; 1146 u16 tso_seg_len = 0; 1147 int filled; 1148 1149 spin_lock_bh(&dring->lock); 1150 filled = netsec_desc_used(dring); 1151 if (netsec_check_stop_tx(priv, filled)) { 1152 spin_unlock_bh(&dring->lock); 1153 net_warn_ratelimited("%s %s Tx queue full\n", 1154 dev_name(priv->dev), ndev->name); 1155 return NETDEV_TX_BUSY; 1156 } 1157 1158 if (skb->ip_summed == CHECKSUM_PARTIAL) 1159 tx_ctrl.cksum_offload_flag = true; 1160 1161 if (skb_is_gso(skb)) 1162 tso_seg_len = skb_shinfo(skb)->gso_size; 1163 1164 if (tso_seg_len > 0) { 1165 if (skb->protocol == htons(ETH_P_IP)) { 1166 ip_hdr(skb)->tot_len = 0; 1167 tcp_hdr(skb)->check = 1168 ~tcp_v4_check(0, ip_hdr(skb)->saddr, 1169 ip_hdr(skb)->daddr, 0); 1170 } else { 1171 tcp_v6_gso_csum_prep(skb); 1172 } 1173 1174 tx_ctrl.tcp_seg_offload_flag = true; 1175 tx_ctrl.tcp_seg_len = tso_seg_len; 1176 } 1177 1178 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data, 1179 skb_headlen(skb), DMA_TO_DEVICE); 1180 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) { 1181 spin_unlock_bh(&dring->lock); 1182 netif_err(priv, drv, priv->ndev, 1183 "%s: DMA mapping failed\n", __func__); 1184 ndev->stats.tx_dropped++; 1185 dev_kfree_skb_any(skb); 1186 return NETDEV_TX_OK; 1187 } 1188 tx_desc.addr = skb->data; 1189 tx_desc.len = skb_headlen(skb); 1190 tx_desc.buf_type = TYPE_NETSEC_SKB; 1191 1192 skb_tx_timestamp(skb); 1193 netdev_sent_queue(priv->ndev, skb->len); 1194 1195 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); 1196 spin_unlock_bh(&dring->lock); 1197 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ 1198 1199 return NETDEV_TX_OK; 1200} 1201 1202static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id) 1203{ 1204 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1205 struct netsec_desc *desc; 1206 u16 idx; 1207 1208 if (!dring->vaddr || !dring->desc) 1209 return; 1210 for (idx = 0; idx < DESC_NUM; idx++) { 1211 desc = &dring->desc[idx]; 1212 if (!desc->addr) 1213 continue; 1214 1215 if (id == NETSEC_RING_RX) { 1216 struct page *page = virt_to_page(desc->addr); 1217 1218 page_pool_put_full_page(dring->page_pool, page, false); 1219 } else if (id == NETSEC_RING_TX) { 1220 dma_unmap_single(priv->dev, desc->dma_addr, desc->len, 1221 DMA_TO_DEVICE); 1222 dev_kfree_skb(desc->skb); 1223 } 1224 } 1225 1226 /* Rx is currently using page_pool */ 1227 if (id == NETSEC_RING_RX) { 1228 if (xdp_rxq_info_is_reg(&dring->xdp_rxq)) 1229 xdp_rxq_info_unreg(&dring->xdp_rxq); 1230 page_pool_destroy(dring->page_pool); 1231 } 1232 1233 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM); 1234 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM); 1235 1236 dring->head = 0; 1237 dring->tail = 0; 1238 1239 if (id == NETSEC_RING_TX) 1240 netdev_reset_queue(priv->ndev); 1241} 1242 1243static void netsec_free_dring(struct netsec_priv *priv, int id) 1244{ 1245 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1246 1247 if (dring->vaddr) { 1248 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM, 1249 dring->vaddr, dring->desc_dma); 1250 dring->vaddr = NULL; 1251 } 1252 1253 kfree(dring->desc); 1254 dring->desc = NULL; 1255} 1256 1257static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id) 1258{ 1259 struct netsec_desc_ring *dring = &priv->desc_ring[id]; 1260 1261 dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM, 1262 &dring->desc_dma, GFP_KERNEL); 1263 if (!dring->vaddr) 1264 goto err; 1265 1266 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL); 1267 if (!dring->desc) 1268 goto err; 1269 1270 return 0; 1271err: 1272 netsec_free_dring(priv, id); 1273 1274 return -ENOMEM; 1275} 1276 1277static void netsec_setup_tx_dring(struct netsec_priv *priv) 1278{ 1279 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX]; 1280 int i; 1281 1282 for (i = 0; i < DESC_NUM; i++) { 1283 struct netsec_de *de; 1284 1285 de = dring->vaddr + (DESC_SZ * i); 1286 /* de->attr is not going to be accessed by the NIC 1287 * until netsec_set_tx_de() is called. 1288 * No need for a dma_wmb() here 1289 */ 1290 de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD; 1291 } 1292} 1293 1294static int netsec_setup_rx_dring(struct netsec_priv *priv) 1295{ 1296 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX]; 1297 struct bpf_prog *xdp_prog = READ_ONCE(priv->xdp_prog); 1298 struct page_pool_params pp_params = { 1299 .order = 0, 1300 /* internal DMA mapping in page_pool */ 1301 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1302 .pool_size = DESC_NUM, 1303 .nid = NUMA_NO_NODE, 1304 .dev = priv->dev, 1305 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 1306 .offset = NETSEC_RXBUF_HEADROOM, 1307 .max_len = NETSEC_RX_BUF_SIZE, 1308 .napi = &priv->napi, 1309 .netdev = priv->ndev, 1310 }; 1311 int i, err; 1312 1313 dring->page_pool = page_pool_create(&pp_params); 1314 if (IS_ERR(dring->page_pool)) { 1315 err = PTR_ERR(dring->page_pool); 1316 dring->page_pool = NULL; 1317 goto err_out; 1318 } 1319 1320 err = xdp_rxq_info_reg(&dring->xdp_rxq, priv->ndev, 0, priv->napi.napi_id); 1321 if (err) 1322 goto err_out; 1323 1324 err = xdp_rxq_info_reg_mem_model(&dring->xdp_rxq, MEM_TYPE_PAGE_POOL, 1325 dring->page_pool); 1326 if (err) 1327 goto err_out; 1328 1329 for (i = 0; i < DESC_NUM; i++) { 1330 struct netsec_desc *desc = &dring->desc[i]; 1331 dma_addr_t dma_handle; 1332 void *buf; 1333 u16 len; 1334 1335 buf = netsec_alloc_rx_data(priv, &dma_handle, &len); 1336 1337 if (!buf) { 1338 err = -ENOMEM; 1339 goto err_out; 1340 } 1341 desc->dma_addr = dma_handle; 1342 desc->addr = buf; 1343 desc->len = len; 1344 } 1345 1346 netsec_rx_fill(priv, 0, DESC_NUM); 1347 1348 return 0; 1349 1350err_out: 1351 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1352 return err; 1353} 1354 1355static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, 1356 u32 addr_h, u32 addr_l, u32 size) 1357{ 1358 u64 base = (u64)addr_h << 32 | addr_l; 1359 void __iomem *ucode; 1360 u32 i; 1361 1362 ucode = ioremap(base, size * sizeof(u32)); 1363 if (!ucode) 1364 return -ENOMEM; 1365 1366 for (i = 0; i < size; i++) 1367 netsec_write(priv, reg, readl(ucode + i * 4)); 1368 1369 iounmap(ucode); 1370 return 0; 1371} 1372 1373static int netsec_netdev_load_microcode(struct netsec_priv *priv) 1374{ 1375 u32 addr_h, addr_l, size; 1376 int err; 1377 1378 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H); 1379 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L); 1380 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE); 1381 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, 1382 addr_h, addr_l, size); 1383 if (err) 1384 return err; 1385 1386 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H); 1387 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L); 1388 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE); 1389 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, 1390 addr_h, addr_l, size); 1391 if (err) 1392 return err; 1393 1394 addr_h = 0; 1395 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS); 1396 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE); 1397 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, 1398 addr_h, addr_l, size); 1399 if (err) 1400 return err; 1401 1402 return 0; 1403} 1404 1405static int netsec_reset_hardware(struct netsec_priv *priv, 1406 bool load_ucode) 1407{ 1408 u32 value; 1409 int err; 1410 1411 /* stop DMA engines */ 1412 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) { 1413 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL, 1414 NETSEC_DMA_CTRL_REG_STOP); 1415 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, 1416 NETSEC_DMA_CTRL_REG_STOP); 1417 1418 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) & 1419 NETSEC_DMA_CTRL_REG_STOP) 1420 cpu_relax(); 1421 1422 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) & 1423 NETSEC_DMA_CTRL_REG_STOP) 1424 cpu_relax(); 1425 } 1426 1427 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); 1428 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); 1429 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); 1430 1431 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0) 1432 cpu_relax(); 1433 1434 /* set desc_start addr */ 1435 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP, 1436 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1437 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW, 1438 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma)); 1439 1440 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP, 1441 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1442 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW, 1443 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma)); 1444 1445 /* set normal tx dring ring config */ 1446 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG, 1447 1 << NETSEC_REG_DESC_ENDIAN); 1448 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG, 1449 1 << NETSEC_REG_DESC_ENDIAN); 1450 1451 if (load_ucode) { 1452 err = netsec_netdev_load_microcode(priv); 1453 if (err) { 1454 netif_err(priv, probe, priv->ndev, 1455 "%s: failed to load microcode (%d)\n", 1456 __func__, err); 1457 return err; 1458 } 1459 } 1460 1461 /* start DMA engines */ 1462 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); 1463 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0); 1464 1465 usleep_range(1000, 2000); 1466 1467 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) & 1468 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) { 1469 netif_err(priv, probe, priv->ndev, 1470 "microengine start failed\n"); 1471 return -ENXIO; 1472 } 1473 netsec_write(priv, NETSEC_REG_TOP_STATUS, 1474 NETSEC_TOP_IRQ_REG_CODE_LOAD_END); 1475 1476 value = NETSEC_PKT_CTRL_REG_MODE_NRM; 1477 if (priv->ndev->mtu > ETH_DATA_LEN) 1478 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO; 1479 1480 /* change to normal mode */ 1481 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); 1482 netsec_write(priv, NETSEC_REG_PKT_CTRL, value); 1483 1484 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & 1485 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) 1486 cpu_relax(); 1487 1488 /* clear any pending EMPTY/ERR irq status */ 1489 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0); 1490 1491 /* Disable TX & RX intr */ 1492 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1493 1494 return 0; 1495} 1496 1497static int netsec_start_gmac(struct netsec_priv *priv) 1498{ 1499 struct phy_device *phydev = priv->ndev->phydev; 1500 u32 value = 0; 1501 int ret; 1502 1503 if (phydev->speed != SPEED_1000) 1504 value = (NETSEC_GMAC_MCR_REG_CST | 1505 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); 1506 1507 if (netsec_mac_write(priv, GMAC_REG_MCR, value)) 1508 return -ETIMEDOUT; 1509 if (netsec_mac_write(priv, GMAC_REG_BMR, 1510 NETSEC_GMAC_BMR_REG_RESET)) 1511 return -ETIMEDOUT; 1512 1513 /* Wait soft reset */ 1514 usleep_range(1000, 5000); 1515 1516 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value); 1517 if (ret) 1518 return ret; 1519 if (value & NETSEC_GMAC_BMR_REG_SWR) 1520 return -EAGAIN; 1521 1522 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1); 1523 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) 1524 return -ETIMEDOUT; 1525 1526 netsec_write(priv, MAC_REG_DESC_INIT, 1); 1527 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) 1528 return -ETIMEDOUT; 1529 1530 if (netsec_mac_write(priv, GMAC_REG_BMR, 1531 NETSEC_GMAC_BMR_REG_COMMON)) 1532 return -ETIMEDOUT; 1533 if (netsec_mac_write(priv, GMAC_REG_RDLAR, 1534 NETSEC_GMAC_RDLAR_REG_COMMON)) 1535 return -ETIMEDOUT; 1536 if (netsec_mac_write(priv, GMAC_REG_TDLAR, 1537 NETSEC_GMAC_TDLAR_REG_COMMON)) 1538 return -ETIMEDOUT; 1539 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001)) 1540 return -ETIMEDOUT; 1541 1542 ret = netsec_mac_update_to_phy_state(priv); 1543 if (ret) 1544 return ret; 1545 1546 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1547 if (ret) 1548 return ret; 1549 1550 value |= NETSEC_GMAC_OMR_REG_SR; 1551 value |= NETSEC_GMAC_OMR_REG_ST; 1552 1553 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1554 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1555 1556 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce, NULL, NULL); 1557 1558 if (netsec_mac_write(priv, GMAC_REG_OMR, value)) 1559 return -ETIMEDOUT; 1560 1561 return 0; 1562} 1563 1564static int netsec_stop_gmac(struct netsec_priv *priv) 1565{ 1566 u32 value; 1567 int ret; 1568 1569 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value); 1570 if (ret) 1571 return ret; 1572 value &= ~NETSEC_GMAC_OMR_REG_SR; 1573 value &= ~NETSEC_GMAC_OMR_REG_ST; 1574 1575 /* disable all interrupts */ 1576 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); 1577 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); 1578 1579 return netsec_mac_write(priv, GMAC_REG_OMR, value); 1580} 1581 1582static void netsec_phy_adjust_link(struct net_device *ndev) 1583{ 1584 struct netsec_priv *priv = netdev_priv(ndev); 1585 1586 if (ndev->phydev->link) 1587 netsec_start_gmac(priv); 1588 else 1589 netsec_stop_gmac(priv); 1590 1591 phy_print_status(ndev->phydev); 1592} 1593 1594static irqreturn_t netsec_irq_handler(int irq, void *dev_id) 1595{ 1596 struct netsec_priv *priv = dev_id; 1597 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS); 1598 unsigned long flags; 1599 1600 /* Disable interrupts */ 1601 if (status & NETSEC_IRQ_TX) { 1602 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS); 1603 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val); 1604 } 1605 if (status & NETSEC_IRQ_RX) { 1606 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS); 1607 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val); 1608 } 1609 1610 spin_lock_irqsave(&priv->reglock, flags); 1611 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1612 spin_unlock_irqrestore(&priv->reglock, flags); 1613 1614 napi_schedule(&priv->napi); 1615 1616 return IRQ_HANDLED; 1617} 1618 1619static int netsec_netdev_open(struct net_device *ndev) 1620{ 1621 struct netsec_priv *priv = netdev_priv(ndev); 1622 int ret; 1623 1624 pm_runtime_get_sync(priv->dev); 1625 1626 netsec_setup_tx_dring(priv); 1627 ret = netsec_setup_rx_dring(priv); 1628 if (ret) { 1629 netif_err(priv, probe, priv->ndev, 1630 "%s: fail setup ring\n", __func__); 1631 goto err1; 1632 } 1633 1634 ret = request_irq(priv->ndev->irq, netsec_irq_handler, 1635 IRQF_SHARED, "netsec", priv); 1636 if (ret) { 1637 netif_err(priv, drv, priv->ndev, "request_irq failed\n"); 1638 goto err2; 1639 } 1640 1641 if (dev_of_node(priv->dev)) { 1642 if (!of_phy_connect(priv->ndev, priv->phy_np, 1643 netsec_phy_adjust_link, 0, 1644 priv->phy_interface)) { 1645 netif_err(priv, link, priv->ndev, "missing PHY\n"); 1646 ret = -ENODEV; 1647 goto err3; 1648 } 1649 } else { 1650 ret = phy_connect_direct(priv->ndev, priv->phydev, 1651 netsec_phy_adjust_link, 1652 priv->phy_interface); 1653 if (ret) { 1654 netif_err(priv, link, priv->ndev, 1655 "phy_connect_direct() failed (%d)\n", ret); 1656 goto err3; 1657 } 1658 } 1659 1660 phy_start(ndev->phydev); 1661 1662 netsec_start_gmac(priv); 1663 napi_enable(&priv->napi); 1664 netif_start_queue(ndev); 1665 1666 /* Enable TX+RX intr. */ 1667 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX); 1668 1669 return 0; 1670err3: 1671 free_irq(priv->ndev->irq, priv); 1672err2: 1673 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1674err1: 1675 pm_runtime_put_sync(priv->dev); 1676 return ret; 1677} 1678 1679static int netsec_netdev_stop(struct net_device *ndev) 1680{ 1681 int ret; 1682 struct netsec_priv *priv = netdev_priv(ndev); 1683 1684 netif_stop_queue(priv->ndev); 1685 dma_wmb(); 1686 1687 napi_disable(&priv->napi); 1688 1689 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0); 1690 netsec_stop_gmac(priv); 1691 1692 free_irq(priv->ndev->irq, priv); 1693 1694 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX); 1695 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX); 1696 1697 phy_stop(ndev->phydev); 1698 phy_disconnect(ndev->phydev); 1699 1700 ret = netsec_reset_hardware(priv, false); 1701 1702 pm_runtime_put_sync(priv->dev); 1703 1704 return ret; 1705} 1706 1707static int netsec_netdev_init(struct net_device *ndev) 1708{ 1709 struct netsec_priv *priv = netdev_priv(ndev); 1710 int ret; 1711 u16 data; 1712 1713 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM); 1714 1715 ret = netsec_alloc_dring(priv, NETSEC_RING_TX); 1716 if (ret) 1717 return ret; 1718 1719 ret = netsec_alloc_dring(priv, NETSEC_RING_RX); 1720 if (ret) 1721 goto err1; 1722 1723 /* set phy power down */ 1724 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR); 1725 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, 1726 data | BMCR_PDOWN); 1727 1728 ret = netsec_reset_hardware(priv, true); 1729 if (ret) 1730 goto err2; 1731 1732 /* Restore phy power state */ 1733 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data); 1734 1735 spin_lock_init(&priv->desc_ring[NETSEC_RING_TX].lock); 1736 spin_lock_init(&priv->desc_ring[NETSEC_RING_RX].lock); 1737 1738 return 0; 1739err2: 1740 netsec_free_dring(priv, NETSEC_RING_RX); 1741err1: 1742 netsec_free_dring(priv, NETSEC_RING_TX); 1743 return ret; 1744} 1745 1746static void netsec_netdev_uninit(struct net_device *ndev) 1747{ 1748 struct netsec_priv *priv = netdev_priv(ndev); 1749 1750 netsec_free_dring(priv, NETSEC_RING_RX); 1751 netsec_free_dring(priv, NETSEC_RING_TX); 1752} 1753 1754static int netsec_netdev_set_features(struct net_device *ndev, 1755 netdev_features_t features) 1756{ 1757 struct netsec_priv *priv = netdev_priv(ndev); 1758 1759 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM); 1760 1761 return 0; 1762} 1763 1764static int netsec_xdp_xmit(struct net_device *ndev, int n, 1765 struct xdp_frame **frames, u32 flags) 1766{ 1767 struct netsec_priv *priv = netdev_priv(ndev); 1768 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; 1769 int i, nxmit = 0; 1770 1771 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1772 return -EINVAL; 1773 1774 spin_lock(&tx_ring->lock); 1775 for (i = 0; i < n; i++) { 1776 struct xdp_frame *xdpf = frames[i]; 1777 int err; 1778 1779 err = netsec_xdp_queue_one(priv, xdpf, true); 1780 if (err != NETSEC_XDP_TX) 1781 break; 1782 1783 tx_ring->xdp_xmit++; 1784 nxmit++; 1785 } 1786 spin_unlock(&tx_ring->lock); 1787 1788 if (unlikely(flags & XDP_XMIT_FLUSH)) { 1789 netsec_xdp_ring_tx_db(priv, tx_ring->xdp_xmit); 1790 tx_ring->xdp_xmit = 0; 1791 } 1792 1793 return nxmit; 1794} 1795 1796static int netsec_xdp_setup(struct netsec_priv *priv, struct bpf_prog *prog, 1797 struct netlink_ext_ack *extack) 1798{ 1799 struct net_device *dev = priv->ndev; 1800 struct bpf_prog *old_prog; 1801 1802 /* For now just support only the usual MTU sized frames */ 1803 if (prog && dev->mtu > 1500) { 1804 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 1805 return -EOPNOTSUPP; 1806 } 1807 1808 if (netif_running(dev)) 1809 netsec_netdev_stop(dev); 1810 1811 /* Detach old prog, if any */ 1812 old_prog = xchg(&priv->xdp_prog, prog); 1813 if (old_prog) 1814 bpf_prog_put(old_prog); 1815 1816 if (netif_running(dev)) 1817 netsec_netdev_open(dev); 1818 1819 return 0; 1820} 1821 1822static int netsec_xdp(struct net_device *ndev, struct netdev_bpf *xdp) 1823{ 1824 struct netsec_priv *priv = netdev_priv(ndev); 1825 1826 switch (xdp->command) { 1827 case XDP_SETUP_PROG: 1828 return netsec_xdp_setup(priv, xdp->prog, xdp->extack); 1829 default: 1830 return -EINVAL; 1831 } 1832} 1833 1834static const struct net_device_ops netsec_netdev_ops = { 1835 .ndo_init = netsec_netdev_init, 1836 .ndo_uninit = netsec_netdev_uninit, 1837 .ndo_open = netsec_netdev_open, 1838 .ndo_stop = netsec_netdev_stop, 1839 .ndo_start_xmit = netsec_netdev_start_xmit, 1840 .ndo_set_features = netsec_netdev_set_features, 1841 .ndo_set_mac_address = eth_mac_addr, 1842 .ndo_validate_addr = eth_validate_addr, 1843 .ndo_eth_ioctl = phy_do_ioctl, 1844 .ndo_xdp_xmit = netsec_xdp_xmit, 1845 .ndo_bpf = netsec_xdp, 1846}; 1847 1848static int netsec_of_probe(struct platform_device *pdev, 1849 struct netsec_priv *priv, u32 *phy_addr) 1850{ 1851 int err; 1852 1853 err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_interface); 1854 if (err) { 1855 dev_err(&pdev->dev, "missing required property 'phy-mode'\n"); 1856 return err; 1857 } 1858 1859 /* 1860 * SynQuacer is physically configured with TX and RX delays 1861 * but the standard firmware claimed otherwise for a long 1862 * time, ignore it. 1863 */ 1864 if (of_machine_is_compatible("socionext,developer-box") && 1865 priv->phy_interface != PHY_INTERFACE_MODE_RGMII_ID) { 1866 dev_warn(&pdev->dev, "Outdated firmware reports incorrect PHY mode, overriding\n"); 1867 priv->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 1868 } 1869 1870 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1871 if (!priv->phy_np) { 1872 dev_err(&pdev->dev, "missing required property 'phy-handle'\n"); 1873 return -EINVAL; 1874 } 1875 1876 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np); 1877 1878 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */ 1879 if (IS_ERR(priv->clk)) 1880 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), 1881 "phy_ref_clk not found\n"); 1882 priv->freq = clk_get_rate(priv->clk); 1883 1884 return 0; 1885} 1886 1887static int netsec_acpi_probe(struct platform_device *pdev, 1888 struct netsec_priv *priv, u32 *phy_addr) 1889{ 1890 int ret; 1891 1892 if (!IS_ENABLED(CONFIG_ACPI)) 1893 return -ENODEV; 1894 1895 /* ACPI systems are assumed to configure the PHY in firmware, so 1896 * there is really no need to discover the PHY mode from the DSDT. 1897 * Since firmware is known to exist in the field that configures the 1898 * PHY correctly but passes the wrong mode string in the phy-mode 1899 * device property, we have no choice but to ignore it. 1900 */ 1901 priv->phy_interface = PHY_INTERFACE_MODE_NA; 1902 1903 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr); 1904 if (ret) 1905 return dev_err_probe(&pdev->dev, ret, 1906 "missing required property 'phy-channel'\n"); 1907 1908 ret = device_property_read_u32(&pdev->dev, 1909 "socionext,phy-clock-frequency", 1910 &priv->freq); 1911 if (ret) 1912 return dev_err_probe(&pdev->dev, ret, 1913 "missing required property 'socionext,phy-clock-frequency'\n"); 1914 return 0; 1915} 1916 1917static void netsec_unregister_mdio(struct netsec_priv *priv) 1918{ 1919 struct phy_device *phydev = priv->phydev; 1920 1921 if (!dev_of_node(priv->dev) && phydev) { 1922 phy_device_remove(phydev); 1923 phy_device_free(phydev); 1924 } 1925 1926 mdiobus_unregister(priv->mii_bus); 1927} 1928 1929static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr) 1930{ 1931 struct mii_bus *bus; 1932 int ret; 1933 1934 bus = devm_mdiobus_alloc(priv->dev); 1935 if (!bus) 1936 return -ENOMEM; 1937 1938 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev)); 1939 bus->priv = priv; 1940 bus->name = "SNI NETSEC MDIO"; 1941 bus->read = netsec_phy_read; 1942 bus->write = netsec_phy_write; 1943 bus->parent = priv->dev; 1944 priv->mii_bus = bus; 1945 1946 if (dev_of_node(priv->dev)) { 1947 struct device_node *mdio_node, *parent = dev_of_node(priv->dev); 1948 1949 mdio_node = of_get_child_by_name(parent, "mdio"); 1950 if (mdio_node) { 1951 parent = mdio_node; 1952 } else { 1953 /* older f/w doesn't populate the mdio subnode, 1954 * allow relaxed upgrade of f/w in due time. 1955 */ 1956 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n"); 1957 } 1958 1959 ret = of_mdiobus_register(bus, parent); 1960 of_node_put(mdio_node); 1961 1962 if (ret) { 1963 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1964 return ret; 1965 } 1966 } else { 1967 /* Mask out all PHYs from auto probing. */ 1968 bus->phy_mask = ~0; 1969 ret = mdiobus_register(bus); 1970 if (ret) { 1971 dev_err(priv->dev, "mdiobus register err(%d)\n", ret); 1972 return ret; 1973 } 1974 1975 priv->phydev = get_phy_device(bus, phy_addr, false); 1976 if (IS_ERR(priv->phydev)) { 1977 ret = PTR_ERR(priv->phydev); 1978 dev_err(priv->dev, "get_phy_device err(%d)\n", ret); 1979 priv->phydev = NULL; 1980 mdiobus_unregister(bus); 1981 return -ENODEV; 1982 } 1983 1984 ret = phy_device_register(priv->phydev); 1985 if (ret) { 1986 phy_device_free(priv->phydev); 1987 mdiobus_unregister(bus); 1988 dev_err(priv->dev, 1989 "phy_device_register err(%d)\n", ret); 1990 } 1991 } 1992 1993 return ret; 1994} 1995 1996static int netsec_probe(struct platform_device *pdev) 1997{ 1998 struct resource *mmio_res, *eeprom_res; 1999 struct netsec_priv *priv; 2000 u32 hw_ver, phy_addr = 0; 2001 struct net_device *ndev; 2002 int ret; 2003 int irq; 2004 2005 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2006 if (!mmio_res) { 2007 dev_err(&pdev->dev, "No MMIO resource found.\n"); 2008 return -ENODEV; 2009 } 2010 2011 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2012 if (!eeprom_res) { 2013 dev_info(&pdev->dev, "No EEPROM resource found.\n"); 2014 return -ENODEV; 2015 } 2016 2017 irq = platform_get_irq(pdev, 0); 2018 if (irq < 0) 2019 return irq; 2020 2021 ndev = alloc_etherdev(sizeof(*priv)); 2022 if (!ndev) 2023 return -ENOMEM; 2024 2025 priv = netdev_priv(ndev); 2026 2027 spin_lock_init(&priv->reglock); 2028 SET_NETDEV_DEV(ndev, &pdev->dev); 2029 platform_set_drvdata(pdev, priv); 2030 ndev->irq = irq; 2031 priv->dev = &pdev->dev; 2032 priv->ndev = ndev; 2033 2034 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | 2035 NETIF_MSG_LINK | NETIF_MSG_PROBE; 2036 2037 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start, 2038 resource_size(mmio_res)); 2039 if (!priv->ioaddr) { 2040 dev_err(&pdev->dev, "devm_ioremap() failed\n"); 2041 ret = -ENXIO; 2042 goto free_ndev; 2043 } 2044 2045 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start, 2046 resource_size(eeprom_res)); 2047 if (!priv->eeprom_base) { 2048 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n"); 2049 ret = -ENXIO; 2050 goto free_ndev; 2051 } 2052 2053 ret = device_get_ethdev_address(&pdev->dev, ndev); 2054 if (ret && priv->eeprom_base) { 2055 void __iomem *macp = priv->eeprom_base + 2056 NETSEC_EEPROM_MAC_ADDRESS; 2057 u8 addr[ETH_ALEN]; 2058 2059 addr[0] = readb(macp + 3); 2060 addr[1] = readb(macp + 2); 2061 addr[2] = readb(macp + 1); 2062 addr[3] = readb(macp + 0); 2063 addr[4] = readb(macp + 7); 2064 addr[5] = readb(macp + 6); 2065 eth_hw_addr_set(ndev, addr); 2066 } 2067 2068 if (!is_valid_ether_addr(ndev->dev_addr)) { 2069 dev_warn(&pdev->dev, "No MAC address found, using random\n"); 2070 eth_hw_addr_random(ndev); 2071 } 2072 2073 if (dev_of_node(&pdev->dev)) 2074 ret = netsec_of_probe(pdev, priv, &phy_addr); 2075 else 2076 ret = netsec_acpi_probe(pdev, priv, &phy_addr); 2077 if (ret) 2078 goto free_ndev; 2079 2080 priv->phy_addr = phy_addr; 2081 2082 if (!priv->freq) { 2083 dev_err(&pdev->dev, "missing PHY reference clock frequency\n"); 2084 ret = -ENODEV; 2085 goto free_ndev; 2086 } 2087 2088 /* default for throughput */ 2089 priv->et_coalesce.rx_coalesce_usecs = 500; 2090 priv->et_coalesce.rx_max_coalesced_frames = 8; 2091 priv->et_coalesce.tx_coalesce_usecs = 500; 2092 priv->et_coalesce.tx_max_coalesced_frames = 8; 2093 2094 ret = device_property_read_u32(&pdev->dev, "max-frame-size", 2095 &ndev->max_mtu); 2096 if (ret < 0) 2097 ndev->max_mtu = ETH_DATA_LEN; 2098 2099 /* runtime_pm coverage just for probe, open/close also cover it */ 2100 pm_runtime_enable(&pdev->dev); 2101 pm_runtime_get_sync(&pdev->dev); 2102 2103 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER); 2104 /* this driver only supports F_TAIKI style NETSEC */ 2105 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) != 2106 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) { 2107 ret = -ENODEV; 2108 goto pm_disable; 2109 } 2110 2111 dev_info(&pdev->dev, "hardware revision %d.%d\n", 2112 hw_ver >> 16, hw_ver & 0xffff); 2113 2114 netif_napi_add(ndev, &priv->napi, netsec_napi_poll); 2115 2116 ndev->netdev_ops = &netsec_netdev_ops; 2117 ndev->ethtool_ops = &netsec_ethtool_ops; 2118 2119 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO | 2120 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2121 ndev->hw_features = ndev->features; 2122 2123 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 2124 NETDEV_XDP_ACT_NDO_XMIT; 2125 2126 priv->rx_cksum_offload_flag = true; 2127 2128 ret = netsec_register_mdio(priv, phy_addr); 2129 if (ret) 2130 goto unreg_napi; 2131 2132 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) 2133 dev_warn(&pdev->dev, "Failed to set DMA mask\n"); 2134 2135 ret = register_netdev(ndev); 2136 if (ret) { 2137 netif_err(priv, probe, ndev, "register_netdev() failed\n"); 2138 goto unreg_mii; 2139 } 2140 2141 pm_runtime_put_sync(&pdev->dev); 2142 return 0; 2143 2144unreg_mii: 2145 netsec_unregister_mdio(priv); 2146unreg_napi: 2147 netif_napi_del(&priv->napi); 2148pm_disable: 2149 pm_runtime_put_sync(&pdev->dev); 2150 pm_runtime_disable(&pdev->dev); 2151free_ndev: 2152 free_netdev(ndev); 2153 dev_err(&pdev->dev, "init failed\n"); 2154 2155 return ret; 2156} 2157 2158static void netsec_remove(struct platform_device *pdev) 2159{ 2160 struct netsec_priv *priv = platform_get_drvdata(pdev); 2161 2162 unregister_netdev(priv->ndev); 2163 2164 netsec_unregister_mdio(priv); 2165 2166 netif_napi_del(&priv->napi); 2167 2168 pm_runtime_disable(&pdev->dev); 2169 free_netdev(priv->ndev); 2170} 2171 2172#ifdef CONFIG_PM 2173static int netsec_runtime_suspend(struct device *dev) 2174{ 2175 struct netsec_priv *priv = dev_get_drvdata(dev); 2176 2177 netsec_write(priv, NETSEC_REG_CLK_EN, 0); 2178 2179 clk_disable_unprepare(priv->clk); 2180 2181 return 0; 2182} 2183 2184static int netsec_runtime_resume(struct device *dev) 2185{ 2186 struct netsec_priv *priv = dev_get_drvdata(dev); 2187 2188 clk_prepare_enable(priv->clk); 2189 2190 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D | 2191 NETSEC_CLK_EN_REG_DOM_C | 2192 NETSEC_CLK_EN_REG_DOM_G); 2193 return 0; 2194} 2195#endif 2196 2197static const struct dev_pm_ops netsec_pm_ops = { 2198 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL) 2199}; 2200 2201static const struct of_device_id netsec_dt_ids[] = { 2202 { .compatible = "socionext,synquacer-netsec" }, 2203 { } 2204}; 2205MODULE_DEVICE_TABLE(of, netsec_dt_ids); 2206 2207#ifdef CONFIG_ACPI 2208static const struct acpi_device_id netsec_acpi_ids[] = { 2209 { "SCX0001" }, 2210 { } 2211}; 2212MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids); 2213#endif 2214 2215static struct platform_driver netsec_driver = { 2216 .probe = netsec_probe, 2217 .remove = netsec_remove, 2218 .driver = { 2219 .name = "netsec", 2220 .pm = &netsec_pm_ops, 2221 .of_match_table = netsec_dt_ids, 2222 .acpi_match_table = ACPI_PTR(netsec_acpi_ids), 2223 }, 2224}; 2225module_platform_driver(netsec_driver); 2226 2227MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>"); 2228MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); 2229MODULE_DESCRIPTION("NETSEC Ethernet driver"); 2230MODULE_LICENSE("GPL");
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