efx_common.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/****************************************************************************
   3 * Driver for Solarflare network controllers and boards
   4 * Copyright 2018 Solarflare Communications Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License version 2 as published
   8 * by the Free Software Foundation, incorporated herein by reference.
   9 */
  10
  11#include "net_driver.h"
  12#include <linux/filter.h>
  13#include <linux/module.h>
  14#include <linux/netdevice.h>
  15#include <net/gre.h>
  16#include "efx_common.h"
  17#include "efx_channels.h"
  18#include "efx.h"
  19#include "mcdi.h"
  20#include "selftest.h"
  21#include "rx_common.h"
  22#include "tx_common.h"
  23#include "nic.h"
  24#include "mcdi_port_common.h"
  25#include "io.h"
  26#include "mcdi_pcol.h"
  27
  28static unsigned int debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  29			     NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
  30			     NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
  31			     NETIF_MSG_TX_ERR | NETIF_MSG_HW);
  32module_param(debug, uint, 0);
  33MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
  34
  35/* This is the time (in jiffies) between invocations of the hardware
  36 * monitor.
  37 * On Falcon-based NICs, this will:
  38 * - Check the on-board hardware monitor;
  39 * - Poll the link state and reconfigure the hardware as necessary.
  40 * On Siena-based NICs for power systems with EEH support, this will give EEH a
  41 * chance to start.
  42 */
  43static unsigned int efx_monitor_interval = 1 * HZ;
  44
  45/* How often and how many times to poll for a reset while waiting for a
  46 * BIST that another function started to complete.
  47 */
  48#define BIST_WAIT_DELAY_MS	100
  49#define BIST_WAIT_DELAY_COUNT	100
  50
  51/* Default stats update time */
  52#define STATS_PERIOD_MS_DEFAULT 1000
  53
  54static const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
  55static const char *const efx_reset_type_names[] = {
  56	[RESET_TYPE_INVISIBLE]          = "INVISIBLE",
  57	[RESET_TYPE_ALL]                = "ALL",
  58	[RESET_TYPE_RECOVER_OR_ALL]     = "RECOVER_OR_ALL",
  59	[RESET_TYPE_WORLD]              = "WORLD",
  60	[RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
  61	[RESET_TYPE_DATAPATH]           = "DATAPATH",
  62	[RESET_TYPE_MC_BIST]		= "MC_BIST",
  63	[RESET_TYPE_DISABLE]            = "DISABLE",
  64	[RESET_TYPE_TX_WATCHDOG]        = "TX_WATCHDOG",
  65	[RESET_TYPE_INT_ERROR]          = "INT_ERROR",
  66	[RESET_TYPE_DMA_ERROR]          = "DMA_ERROR",
  67	[RESET_TYPE_TX_SKIP]            = "TX_SKIP",
  68	[RESET_TYPE_MC_FAILURE]         = "MC_FAILURE",
  69	[RESET_TYPE_MCDI_TIMEOUT]	= "MCDI_TIMEOUT (FLR)",
  70};
  71
  72#define RESET_TYPE(type) \
  73	STRING_TABLE_LOOKUP(type, efx_reset_type)
  74
  75/* Loopback mode names (see LOOPBACK_MODE()) */
  76const unsigned int efx_siena_loopback_mode_max = LOOPBACK_MAX;
  77const char *const efx_siena_loopback_mode_names[] = {
  78	[LOOPBACK_NONE]		= "NONE",
  79	[LOOPBACK_DATA]		= "DATAPATH",
  80	[LOOPBACK_GMAC]		= "GMAC",
  81	[LOOPBACK_XGMII]	= "XGMII",
  82	[LOOPBACK_XGXS]		= "XGXS",
  83	[LOOPBACK_XAUI]		= "XAUI",
  84	[LOOPBACK_GMII]		= "GMII",
  85	[LOOPBACK_SGMII]	= "SGMII",
  86	[LOOPBACK_XGBR]		= "XGBR",
  87	[LOOPBACK_XFI]		= "XFI",
  88	[LOOPBACK_XAUI_FAR]	= "XAUI_FAR",
  89	[LOOPBACK_GMII_FAR]	= "GMII_FAR",
  90	[LOOPBACK_SGMII_FAR]	= "SGMII_FAR",
  91	[LOOPBACK_XFI_FAR]	= "XFI_FAR",
  92	[LOOPBACK_GPHY]		= "GPHY",
  93	[LOOPBACK_PHYXS]	= "PHYXS",
  94	[LOOPBACK_PCS]		= "PCS",
  95	[LOOPBACK_PMAPMD]	= "PMA/PMD",
  96	[LOOPBACK_XPORT]	= "XPORT",
  97	[LOOPBACK_XGMII_WS]	= "XGMII_WS",
  98	[LOOPBACK_XAUI_WS]	= "XAUI_WS",
  99	[LOOPBACK_XAUI_WS_FAR]  = "XAUI_WS_FAR",
 100	[LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
 101	[LOOPBACK_GMII_WS]	= "GMII_WS",
 102	[LOOPBACK_XFI_WS]	= "XFI_WS",
 103	[LOOPBACK_XFI_WS_FAR]	= "XFI_WS_FAR",
 104	[LOOPBACK_PHYXS_WS]	= "PHYXS_WS",
 105};
 106
 107/* Reset workqueue. If any NIC has a hardware failure then a reset will be
 108 * queued onto this work queue. This is not a per-nic work queue, because
 109 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
 110 */
 111static struct workqueue_struct *reset_workqueue;
 112
 113int efx_siena_create_reset_workqueue(void)
 114{
 115	reset_workqueue = create_singlethread_workqueue("sfc_siena_reset");
 116	if (!reset_workqueue) {
 117		printk(KERN_ERR "Failed to create reset workqueue\n");
 118		return -ENOMEM;
 119	}
 120
 121	return 0;
 122}
 123
 124void efx_siena_queue_reset_work(struct efx_nic *efx)
 125{
 126	queue_work(reset_workqueue, &efx->reset_work);
 127}
 128
 129void efx_siena_flush_reset_workqueue(struct efx_nic *efx)
 130{
 131	cancel_work_sync(&efx->reset_work);
 132}
 133
 134void efx_siena_destroy_reset_workqueue(void)
 135{
 136	if (reset_workqueue) {
 137		destroy_workqueue(reset_workqueue);
 138		reset_workqueue = NULL;
 139	}
 140}
 141
 142/* We assume that efx->type->reconfigure_mac will always try to sync RX
 143 * filters and therefore needs to read-lock the filter table against freeing
 144 */
 145void efx_siena_mac_reconfigure(struct efx_nic *efx, bool mtu_only)
 146{
 147	if (efx->type->reconfigure_mac) {
 148		down_read(&efx->filter_sem);
 149		efx->type->reconfigure_mac(efx, mtu_only);
 150		up_read(&efx->filter_sem);
 151	}
 152}
 153
 154/* Asynchronous work item for changing MAC promiscuity and multicast
 155 * hash.  Avoid a drain/rx_ingress enable by reconfiguring the current
 156 * MAC directly.
 157 */
 158static void efx_mac_work(struct work_struct *data)
 159{
 160	struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
 161
 162	mutex_lock(&efx->mac_lock);
 163	if (efx->port_enabled)
 164		efx_siena_mac_reconfigure(efx, false);
 165	mutex_unlock(&efx->mac_lock);
 166}
 167
 168int efx_siena_set_mac_address(struct net_device *net_dev, void *data)
 169{
 170	struct efx_nic *efx = netdev_priv(net_dev);
 171	struct sockaddr *addr = data;
 172	u8 *new_addr = addr->sa_data;
 173	u8 old_addr[6];
 174	int rc;
 175
 176	if (!is_valid_ether_addr(new_addr)) {
 177		netif_err(efx, drv, efx->net_dev,
 178			  "invalid ethernet MAC address requested: %pM\n",
 179			  new_addr);
 180		return -EADDRNOTAVAIL;
 181	}
 182
 183	/* save old address */
 184	ether_addr_copy(old_addr, net_dev->dev_addr);
 185	eth_hw_addr_set(net_dev, new_addr);
 186	if (efx->type->set_mac_address) {
 187		rc = efx->type->set_mac_address(efx);
 188		if (rc) {
 189			eth_hw_addr_set(net_dev, old_addr);
 190			return rc;
 191		}
 192	}
 193
 194	/* Reconfigure the MAC */
 195	mutex_lock(&efx->mac_lock);
 196	efx_siena_mac_reconfigure(efx, false);
 197	mutex_unlock(&efx->mac_lock);
 198
 199	return 0;
 200}
 201
 202/* Context: netif_addr_lock held, BHs disabled. */
 203void efx_siena_set_rx_mode(struct net_device *net_dev)
 204{
 205	struct efx_nic *efx = netdev_priv(net_dev);
 206
 207	if (efx->port_enabled)
 208		queue_work(efx->workqueue, &efx->mac_work);
 209	/* Otherwise efx_start_port() will do this */
 210}
 211
 212int efx_siena_set_features(struct net_device *net_dev, netdev_features_t data)
 213{
 214	struct efx_nic *efx = netdev_priv(net_dev);
 215	int rc;
 216
 217	/* If disabling RX n-tuple filtering, clear existing filters */
 218	if (net_dev->features & ~data & NETIF_F_NTUPLE) {
 219		rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
 220		if (rc)
 221			return rc;
 222	}
 223
 224	/* If Rx VLAN filter is changed, update filters via mac_reconfigure.
 225	 * If rx-fcs is changed, mac_reconfigure updates that too.
 226	 */
 227	if ((net_dev->features ^ data) & (NETIF_F_HW_VLAN_CTAG_FILTER |
 228					  NETIF_F_RXFCS)) {
 229		/* efx_siena_set_rx_mode() will schedule MAC work to update filters
 230		 * when a new features are finally set in net_dev.
 231		 */
 232		efx_siena_set_rx_mode(net_dev);
 233	}
 234
 235	return 0;
 236}
 237
 238/* This ensures that the kernel is kept informed (via
 239 * netif_carrier_on/off) of the link status, and also maintains the
 240 * link status's stop on the port's TX queue.
 241 */
 242void efx_siena_link_status_changed(struct efx_nic *efx)
 243{
 244	struct efx_link_state *link_state = &efx->link_state;
 245
 246	/* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
 247	 * that no events are triggered between unregister_netdev() and the
 248	 * driver unloading. A more general condition is that NETDEV_CHANGE
 249	 * can only be generated between NETDEV_UP and NETDEV_DOWN
 250	 */
 251	if (!netif_running(efx->net_dev))
 252		return;
 253
 254	if (link_state->up != netif_carrier_ok(efx->net_dev)) {
 255		efx->n_link_state_changes++;
 256
 257		if (link_state->up)
 258			netif_carrier_on(efx->net_dev);
 259		else
 260			netif_carrier_off(efx->net_dev);
 261	}
 262
 263	/* Status message for kernel log */
 264	if (link_state->up)
 265		netif_info(efx, link, efx->net_dev,
 266			   "link up at %uMbps %s-duplex (MTU %d)\n",
 267			   link_state->speed, link_state->fd ? "full" : "half",
 268			   efx->net_dev->mtu);
 269	else
 270		netif_info(efx, link, efx->net_dev, "link down\n");
 271}
 272
 273unsigned int efx_siena_xdp_max_mtu(struct efx_nic *efx)
 274{
 275	/* The maximum MTU that we can fit in a single page, allowing for
 276	 * framing, overhead and XDP headroom + tailroom.
 277	 */
 278	int overhead = EFX_MAX_FRAME_LEN(0) + sizeof(struct efx_rx_page_state) +
 279		       efx->rx_prefix_size + efx->type->rx_buffer_padding +
 280		       efx->rx_ip_align + EFX_XDP_HEADROOM + EFX_XDP_TAILROOM;
 281
 282	return PAGE_SIZE - overhead;
 283}
 284
 285/* Context: process, rtnl_lock() held. */
 286int efx_siena_change_mtu(struct net_device *net_dev, int new_mtu)
 287{
 288	struct efx_nic *efx = netdev_priv(net_dev);
 289	int rc;
 290
 291	rc = efx_check_disabled(efx);
 292	if (rc)
 293		return rc;
 294
 295	if (rtnl_dereference(efx->xdp_prog) &&
 296	    new_mtu > efx_siena_xdp_max_mtu(efx)) {
 297		netif_err(efx, drv, efx->net_dev,
 298			  "Requested MTU of %d too big for XDP (max: %d)\n",
 299			  new_mtu, efx_siena_xdp_max_mtu(efx));
 300		return -EINVAL;
 301	}
 302
 303	netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
 304
 305	efx_device_detach_sync(efx);
 306	efx_siena_stop_all(efx);
 307
 308	mutex_lock(&efx->mac_lock);
 309	WRITE_ONCE(net_dev->mtu, new_mtu);
 310	efx_siena_mac_reconfigure(efx, true);
 311	mutex_unlock(&efx->mac_lock);
 312
 313	efx_siena_start_all(efx);
 314	efx_device_attach_if_not_resetting(efx);
 315	return 0;
 316}
 317
 318/**************************************************************************
 319 *
 320 * Hardware monitor
 321 *
 322 **************************************************************************/
 323
 324/* Run periodically off the general workqueue */
 325static void efx_monitor(struct work_struct *data)
 326{
 327	struct efx_nic *efx = container_of(data, struct efx_nic,
 328					   monitor_work.work);
 329
 330	netif_vdbg(efx, timer, efx->net_dev,
 331		   "hardware monitor executing on CPU %d\n",
 332		   raw_smp_processor_id());
 333	BUG_ON(efx->type->monitor == NULL);
 334
 335	/* If the mac_lock is already held then it is likely a port
 336	 * reconfiguration is already in place, which will likely do
 337	 * most of the work of monitor() anyway.
 338	 */
 339	if (mutex_trylock(&efx->mac_lock)) {
 340		if (efx->port_enabled && efx->type->monitor)
 341			efx->type->monitor(efx);
 342		mutex_unlock(&efx->mac_lock);
 343	}
 344
 345	efx_siena_start_monitor(efx);
 346}
 347
 348void efx_siena_start_monitor(struct efx_nic *efx)
 349{
 350	if (efx->type->monitor)
 351		queue_delayed_work(efx->workqueue, &efx->monitor_work,
 352				   efx_monitor_interval);
 353}
 354
 355/**************************************************************************
 356 *
 357 * Event queue processing
 358 *
 359 *************************************************************************/
 360
 361/* Channels are shutdown and reinitialised whilst the NIC is running
 362 * to propagate configuration changes (mtu, checksum offload), or
 363 * to clear hardware error conditions
 364 */
 365static void efx_start_datapath(struct efx_nic *efx)
 366{
 367	netdev_features_t old_features = efx->net_dev->features;
 368	bool old_rx_scatter = efx->rx_scatter;
 369	size_t rx_buf_len;
 370
 371	/* Calculate the rx buffer allocation parameters required to
 372	 * support the current MTU, including padding for header
 373	 * alignment and overruns.
 374	 */
 375	efx->rx_dma_len = (efx->rx_prefix_size +
 376			   EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
 377			   efx->type->rx_buffer_padding);
 378	rx_buf_len = (sizeof(struct efx_rx_page_state)   + EFX_XDP_HEADROOM +
 379		      efx->rx_ip_align + efx->rx_dma_len + EFX_XDP_TAILROOM);
 380
 381	if (rx_buf_len <= PAGE_SIZE) {
 382		efx->rx_scatter = efx->type->always_rx_scatter;
 383		efx->rx_buffer_order = 0;
 384	} else if (efx->type->can_rx_scatter) {
 385		BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
 386		BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
 387			     2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
 388				       EFX_RX_BUF_ALIGNMENT) >
 389			     PAGE_SIZE);
 390		efx->rx_scatter = true;
 391		efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
 392		efx->rx_buffer_order = 0;
 393	} else {
 394		efx->rx_scatter = false;
 395		efx->rx_buffer_order = get_order(rx_buf_len);
 396	}
 397
 398	efx_siena_rx_config_page_split(efx);
 399	if (efx->rx_buffer_order)
 400		netif_dbg(efx, drv, efx->net_dev,
 401			  "RX buf len=%u; page order=%u batch=%u\n",
 402			  efx->rx_dma_len, efx->rx_buffer_order,
 403			  efx->rx_pages_per_batch);
 404	else
 405		netif_dbg(efx, drv, efx->net_dev,
 406			  "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
 407			  efx->rx_dma_len, efx->rx_page_buf_step,
 408			  efx->rx_bufs_per_page, efx->rx_pages_per_batch);
 409
 410	/* Restore previously fixed features in hw_features and remove
 411	 * features which are fixed now
 412	 */
 413	efx->net_dev->hw_features |= efx->net_dev->features;
 414	efx->net_dev->hw_features &= ~efx->fixed_features;
 415	efx->net_dev->features |= efx->fixed_features;
 416	if (efx->net_dev->features != old_features)
 417		netdev_features_change(efx->net_dev);
 418
 419	/* RX filters may also have scatter-enabled flags */
 420	if ((efx->rx_scatter != old_rx_scatter) &&
 421	    efx->type->filter_update_rx_scatter)
 422		efx->type->filter_update_rx_scatter(efx);
 423
 424	/* We must keep at least one descriptor in a TX ring empty.
 425	 * We could avoid this when the queue size does not exactly
 426	 * match the hardware ring size, but it's not that important.
 427	 * Therefore we stop the queue when one more skb might fill
 428	 * the ring completely.  We wake it when half way back to
 429	 * empty.
 430	 */
 431	efx->txq_stop_thresh = efx->txq_entries - efx_siena_tx_max_skb_descs(efx);
 432	efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
 433
 434	/* Initialise the channels */
 435	efx_siena_start_channels(efx);
 436
 437	efx_siena_ptp_start_datapath(efx);
 438
 439	if (netif_device_present(efx->net_dev))
 440		netif_tx_wake_all_queues(efx->net_dev);
 441}
 442
 443static void efx_stop_datapath(struct efx_nic *efx)
 444{
 445	EFX_ASSERT_RESET_SERIALISED(efx);
 446	BUG_ON(efx->port_enabled);
 447
 448	efx_siena_ptp_stop_datapath(efx);
 449
 450	efx_siena_stop_channels(efx);
 451}
 452
 453/**************************************************************************
 454 *
 455 * Port handling
 456 *
 457 **************************************************************************/
 458
 459/* Equivalent to efx_siena_link_set_advertising with all-zeroes, except does not
 460 * force the Autoneg bit on.
 461 */
 462void efx_siena_link_clear_advertising(struct efx_nic *efx)
 463{
 464	bitmap_zero(efx->link_advertising, __ETHTOOL_LINK_MODE_MASK_NBITS);
 465	efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
 466}
 467
 468void efx_siena_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
 469{
 470	efx->wanted_fc = wanted_fc;
 471	if (efx->link_advertising[0]) {
 472		if (wanted_fc & EFX_FC_RX)
 473			efx->link_advertising[0] |= (ADVERTISED_Pause |
 474						     ADVERTISED_Asym_Pause);
 475		else
 476			efx->link_advertising[0] &= ~(ADVERTISED_Pause |
 477						      ADVERTISED_Asym_Pause);
 478		if (wanted_fc & EFX_FC_TX)
 479			efx->link_advertising[0] ^= ADVERTISED_Asym_Pause;
 480	}
 481}
 482
 483static void efx_start_port(struct efx_nic *efx)
 484{
 485	netif_dbg(efx, ifup, efx->net_dev, "start port\n");
 486	BUG_ON(efx->port_enabled);
 487
 488	mutex_lock(&efx->mac_lock);
 489	efx->port_enabled = true;
 490
 491	/* Ensure MAC ingress/egress is enabled */
 492	efx_siena_mac_reconfigure(efx, false);
 493
 494	mutex_unlock(&efx->mac_lock);
 495}
 496
 497/* Cancel work for MAC reconfiguration, periodic hardware monitoring
 498 * and the async self-test, wait for them to finish and prevent them
 499 * being scheduled again.  This doesn't cover online resets, which
 500 * should only be cancelled when removing the device.
 501 */
 502static void efx_stop_port(struct efx_nic *efx)
 503{
 504	netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
 505
 506	EFX_ASSERT_RESET_SERIALISED(efx);
 507
 508	mutex_lock(&efx->mac_lock);
 509	efx->port_enabled = false;
 510	mutex_unlock(&efx->mac_lock);
 511
 512	/* Serialise against efx_set_multicast_list() */
 513	netif_addr_lock_bh(efx->net_dev);
 514	netif_addr_unlock_bh(efx->net_dev);
 515
 516	cancel_delayed_work_sync(&efx->monitor_work);
 517	efx_siena_selftest_async_cancel(efx);
 518	cancel_work_sync(&efx->mac_work);
 519}
 520
 521/* If the interface is supposed to be running but is not, start
 522 * the hardware and software data path, regular activity for the port
 523 * (MAC statistics, link polling, etc.) and schedule the port to be
 524 * reconfigured.  Interrupts must already be enabled.  This function
 525 * is safe to call multiple times, so long as the NIC is not disabled.
 526 * Requires the RTNL lock.
 527 */
 528void efx_siena_start_all(struct efx_nic *efx)
 529{
 530	EFX_ASSERT_RESET_SERIALISED(efx);
 531	BUG_ON(efx->state == STATE_DISABLED);
 532
 533	/* Check that it is appropriate to restart the interface. All
 534	 * of these flags are safe to read under just the rtnl lock
 535	 */
 536	if (efx->port_enabled || !netif_running(efx->net_dev) ||
 537	    efx->reset_pending)
 538		return;
 539
 540	efx_start_port(efx);
 541	efx_start_datapath(efx);
 542
 543	/* Start the hardware monitor if there is one */
 544	efx_siena_start_monitor(efx);
 545
 546	/* Link state detection is normally event-driven; we have
 547	 * to poll now because we could have missed a change
 548	 */
 549	mutex_lock(&efx->mac_lock);
 550	if (efx_siena_mcdi_phy_poll(efx))
 551		efx_siena_link_status_changed(efx);
 552	mutex_unlock(&efx->mac_lock);
 553
 554	if (efx->type->start_stats) {
 555		efx->type->start_stats(efx);
 556		efx->type->pull_stats(efx);
 557		spin_lock_bh(&efx->stats_lock);
 558		efx->type->update_stats(efx, NULL, NULL);
 559		spin_unlock_bh(&efx->stats_lock);
 560	}
 561}
 562
 563/* Quiesce the hardware and software data path, and regular activity
 564 * for the port without bringing the link down.  Safe to call multiple
 565 * times with the NIC in almost any state, but interrupts should be
 566 * enabled.  Requires the RTNL lock.
 567 */
 568void efx_siena_stop_all(struct efx_nic *efx)
 569{
 570	EFX_ASSERT_RESET_SERIALISED(efx);
 571
 572	/* port_enabled can be read safely under the rtnl lock */
 573	if (!efx->port_enabled)
 574		return;
 575
 576	if (efx->type->update_stats) {
 577		/* update stats before we go down so we can accurately count
 578		 * rx_nodesc_drops
 579		 */
 580		efx->type->pull_stats(efx);
 581		spin_lock_bh(&efx->stats_lock);
 582		efx->type->update_stats(efx, NULL, NULL);
 583		spin_unlock_bh(&efx->stats_lock);
 584		efx->type->stop_stats(efx);
 585	}
 586
 587	efx_stop_port(efx);
 588
 589	/* Stop the kernel transmit interface.  This is only valid if
 590	 * the device is stopped or detached; otherwise the watchdog
 591	 * may fire immediately.
 592	 */
 593	WARN_ON(netif_running(efx->net_dev) &&
 594		netif_device_present(efx->net_dev));
 595	netif_tx_disable(efx->net_dev);
 596
 597	efx_stop_datapath(efx);
 598}
 599
 600static size_t efx_siena_update_stats_atomic(struct efx_nic *efx, u64 *full_stats,
 601					    struct rtnl_link_stats64 *core_stats)
 602{
 603	if (efx->type->update_stats_atomic)
 604		return efx->type->update_stats_atomic(efx, full_stats, core_stats);
 605	return efx->type->update_stats(efx, full_stats, core_stats);
 606}
 607
 608/* Context: process, rcu_read_lock or RTNL held, non-blocking. */
 609void efx_siena_net_stats(struct net_device *net_dev,
 610			 struct rtnl_link_stats64 *stats)
 611{
 612	struct efx_nic *efx = netdev_priv(net_dev);
 613
 614	spin_lock_bh(&efx->stats_lock);
 615	efx_siena_update_stats_atomic(efx, NULL, stats);
 616	spin_unlock_bh(&efx->stats_lock);
 617}
 618
 619/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
 620 * the MAC appropriately. All other PHY configuration changes are pushed
 621 * through phy_op->set_settings(), and pushed asynchronously to the MAC
 622 * through efx_monitor().
 623 *
 624 * Callers must hold the mac_lock
 625 */
 626int __efx_siena_reconfigure_port(struct efx_nic *efx)
 627{
 628	enum efx_phy_mode phy_mode;
 629	int rc = 0;
 630
 631	WARN_ON(!mutex_is_locked(&efx->mac_lock));
 632
 633	/* Disable PHY transmit in mac level loopbacks */
 634	phy_mode = efx->phy_mode;
 635	if (LOOPBACK_INTERNAL(efx))
 636		efx->phy_mode |= PHY_MODE_TX_DISABLED;
 637	else
 638		efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
 639
 640	if (efx->type->reconfigure_port)
 641		rc = efx->type->reconfigure_port(efx);
 642
 643	if (rc)
 644		efx->phy_mode = phy_mode;
 645
 646	return rc;
 647}
 648
 649/* Reinitialise the MAC to pick up new PHY settings, even if the port is
 650 * disabled.
 651 */
 652int efx_siena_reconfigure_port(struct efx_nic *efx)
 653{
 654	int rc;
 655
 656	EFX_ASSERT_RESET_SERIALISED(efx);
 657
 658	mutex_lock(&efx->mac_lock);
 659	rc = __efx_siena_reconfigure_port(efx);
 660	mutex_unlock(&efx->mac_lock);
 661
 662	return rc;
 663}
 664
 665/**************************************************************************
 666 *
 667 * Device reset and suspend
 668 *
 669 **************************************************************************/
 670
 671static void efx_wait_for_bist_end(struct efx_nic *efx)
 672{
 673	int i;
 674
 675	for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
 676		if (efx_siena_mcdi_poll_reboot(efx))
 677			goto out;
 678		msleep(BIST_WAIT_DELAY_MS);
 679	}
 680
 681	netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
 682out:
 683	/* Either way unset the BIST flag. If we found no reboot we probably
 684	 * won't recover, but we should try.
 685	 */
 686	efx->mc_bist_for_other_fn = false;
 687}
 688
 689/* Try recovery mechanisms.
 690 * For now only EEH is supported.
 691 * Returns 0 if the recovery mechanisms are unsuccessful.
 692 * Returns a non-zero value otherwise.
 693 */
 694int efx_siena_try_recovery(struct efx_nic *efx)
 695{
 696#ifdef CONFIG_EEH
 697	/* A PCI error can occur and not be seen by EEH because nothing
 698	 * happens on the PCI bus. In this case the driver may fail and
 699	 * schedule a 'recover or reset', leading to this recovery handler.
 700	 * Manually call the eeh failure check function.
 701	 */
 702	struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
 703	if (eeh_dev_check_failure(eehdev)) {
 704		/* The EEH mechanisms will handle the error and reset the
 705		 * device if necessary.
 706		 */
 707		return 1;
 708	}
 709#endif
 710	return 0;
 711}
 712
 713/* Tears down the entire software state and most of the hardware state
 714 * before reset.
 715 */
 716void efx_siena_reset_down(struct efx_nic *efx, enum reset_type method)
 717{
 718	EFX_ASSERT_RESET_SERIALISED(efx);
 719
 720	if (method == RESET_TYPE_MCDI_TIMEOUT)
 721		efx->type->prepare_flr(efx);
 722
 723	efx_siena_stop_all(efx);
 724	efx_siena_disable_interrupts(efx);
 725
 726	mutex_lock(&efx->mac_lock);
 727	down_write(&efx->filter_sem);
 728	efx->type->fini(efx);
 729}
 730
 731/* Context: netif_tx_lock held, BHs disabled. */
 732void efx_siena_watchdog(struct net_device *net_dev, unsigned int txqueue)
 733{
 734	struct efx_nic *efx = netdev_priv(net_dev);
 735
 736	netif_err(efx, tx_err, efx->net_dev,
 737		  "TX stuck with port_enabled=%d: resetting channels\n",
 738		  efx->port_enabled);
 739
 740	efx_siena_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
 741}
 742
 743/* This function will always ensure that the locks acquired in
 744 * efx_siena_reset_down() are released. A failure return code indicates
 745 * that we were unable to reinitialise the hardware, and the
 746 * driver should be disabled. If ok is false, then the rx and tx
 747 * engines are not restarted, pending a RESET_DISABLE.
 748 */
 749int efx_siena_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
 750{
 751	int rc;
 752
 753	EFX_ASSERT_RESET_SERIALISED(efx);
 754
 755	if (method == RESET_TYPE_MCDI_TIMEOUT)
 756		efx->type->finish_flr(efx);
 757
 758	/* Ensure that SRAM is initialised even if we're disabling the device */
 759	rc = efx->type->init(efx);
 760	if (rc) {
 761		netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
 762		goto fail;
 763	}
 764
 765	if (!ok)
 766		goto fail;
 767
 768	if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
 769	    method != RESET_TYPE_DATAPATH) {
 770		rc = efx_siena_mcdi_port_reconfigure(efx);
 771		if (rc && rc != -EPERM)
 772			netif_err(efx, drv, efx->net_dev,
 773				  "could not restore PHY settings\n");
 774	}
 775
 776	rc = efx_siena_enable_interrupts(efx);
 777	if (rc)
 778		goto fail;
 779
 780#ifdef CONFIG_SFC_SIENA_SRIOV
 781	rc = efx->type->vswitching_restore(efx);
 782	if (rc) /* not fatal; the PF will still work fine */
 783		netif_warn(efx, probe, efx->net_dev,
 784			   "failed to restore vswitching rc=%d;"
 785			   " VFs may not function\n", rc);
 786#endif
 787
 788	efx->type->filter_table_restore(efx);
 789	up_write(&efx->filter_sem);
 790	if (efx->type->sriov_reset)
 791		efx->type->sriov_reset(efx);
 792
 793	mutex_unlock(&efx->mac_lock);
 794
 795	efx_siena_start_all(efx);
 796
 797	if (efx->type->udp_tnl_push_ports)
 798		efx->type->udp_tnl_push_ports(efx);
 799
 800	return 0;
 801
 802fail:
 803	efx->port_initialized = false;
 804
 805	up_write(&efx->filter_sem);
 806	mutex_unlock(&efx->mac_lock);
 807
 808	return rc;
 809}
 810
 811/* Reset the NIC using the specified method.  Note that the reset may
 812 * fail, in which case the card will be left in an unusable state.
 813 *
 814 * Caller must hold the rtnl_lock.
 815 */
 816int efx_siena_reset(struct efx_nic *efx, enum reset_type method)
 817{
 818	int rc, rc2 = 0;
 819	bool disabled;
 820
 821	netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
 822		   RESET_TYPE(method));
 823
 824	efx_device_detach_sync(efx);
 825	/* efx_siena_reset_down() grabs locks that prevent recovery on EF100.
 826	 * EF100 reset is handled in the efx_nic_type callback below.
 827	 */
 828	if (efx_nic_rev(efx) != EFX_REV_EF100)
 829		efx_siena_reset_down(efx, method);
 830
 831	rc = efx->type->reset(efx, method);
 832	if (rc) {
 833		netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
 834		goto out;
 835	}
 836
 837	/* Clear flags for the scopes we covered.  We assume the NIC and
 838	 * driver are now quiescent so that there is no race here.
 839	 */
 840	if (method < RESET_TYPE_MAX_METHOD)
 841		efx->reset_pending &= -(1 << (method + 1));
 842	else /* it doesn't fit into the well-ordered scope hierarchy */
 843		__clear_bit(method, &efx->reset_pending);
 844
 845	/* Reinitialise bus-mastering, which may have been turned off before
 846	 * the reset was scheduled. This is still appropriate, even in the
 847	 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
 848	 * can respond to requests.
 849	 */
 850	pci_set_master(efx->pci_dev);
 851
 852out:
 853	/* Leave device stopped if necessary */
 854	disabled = rc ||
 855		method == RESET_TYPE_DISABLE ||
 856		method == RESET_TYPE_RECOVER_OR_DISABLE;
 857	if (efx_nic_rev(efx) != EFX_REV_EF100)
 858		rc2 = efx_siena_reset_up(efx, method, !disabled);
 859	if (rc2) {
 860		disabled = true;
 861		if (!rc)
 862			rc = rc2;
 863	}
 864
 865	if (disabled) {
 866		dev_close(efx->net_dev);
 867		netif_err(efx, drv, efx->net_dev, "has been disabled\n");
 868		efx->state = STATE_DISABLED;
 869	} else {
 870		netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
 871		efx_device_attach_if_not_resetting(efx);
 872	}
 873	return rc;
 874}
 875
 876/* The worker thread exists so that code that cannot sleep can
 877 * schedule a reset for later.
 878 */
 879static void efx_reset_work(struct work_struct *data)
 880{
 881	struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
 882	unsigned long pending;
 883	enum reset_type method;
 884
 885	pending = READ_ONCE(efx->reset_pending);
 886	method = fls(pending) - 1;
 887
 888	if (method == RESET_TYPE_MC_BIST)
 889		efx_wait_for_bist_end(efx);
 890
 891	if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
 892	     method == RESET_TYPE_RECOVER_OR_ALL) &&
 893	    efx_siena_try_recovery(efx))
 894		return;
 895
 896	if (!pending)
 897		return;
 898
 899	rtnl_lock();
 900
 901	/* We checked the state in efx_siena_schedule_reset() but it may
 902	 * have changed by now.  Now that we have the RTNL lock,
 903	 * it cannot change again.
 904	 */
 905	if (efx->state == STATE_READY)
 906		(void)efx_siena_reset(efx, method);
 907
 908	rtnl_unlock();
 909}
 910
 911void efx_siena_schedule_reset(struct efx_nic *efx, enum reset_type type)
 912{
 913	enum reset_type method;
 914
 915	if (efx->state == STATE_RECOVERY) {
 916		netif_dbg(efx, drv, efx->net_dev,
 917			  "recovering: skip scheduling %s reset\n",
 918			  RESET_TYPE(type));
 919		return;
 920	}
 921
 922	switch (type) {
 923	case RESET_TYPE_INVISIBLE:
 924	case RESET_TYPE_ALL:
 925	case RESET_TYPE_RECOVER_OR_ALL:
 926	case RESET_TYPE_WORLD:
 927	case RESET_TYPE_DISABLE:
 928	case RESET_TYPE_RECOVER_OR_DISABLE:
 929	case RESET_TYPE_DATAPATH:
 930	case RESET_TYPE_MC_BIST:
 931	case RESET_TYPE_MCDI_TIMEOUT:
 932		method = type;
 933		netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
 934			  RESET_TYPE(method));
 935		break;
 936	default:
 937		method = efx->type->map_reset_reason(type);
 938		netif_dbg(efx, drv, efx->net_dev,
 939			  "scheduling %s reset for %s\n",
 940			  RESET_TYPE(method), RESET_TYPE(type));
 941		break;
 942	}
 943
 944	set_bit(method, &efx->reset_pending);
 945	smp_mb(); /* ensure we change reset_pending before checking state */
 946
 947	/* If we're not READY then just leave the flags set as the cue
 948	 * to abort probing or reschedule the reset later.
 949	 */
 950	if (READ_ONCE(efx->state) != STATE_READY)
 951		return;
 952
 953	/* efx_process_channel() will no longer read events once a
 954	 * reset is scheduled. So switch back to poll'd MCDI completions.
 955	 */
 956	efx_siena_mcdi_mode_poll(efx);
 957
 958	efx_siena_queue_reset_work(efx);
 959}
 960
 961/**************************************************************************
 962 *
 963 * Dummy NIC operations
 964 *
 965 * Can be used for some unimplemented operations
 966 * Needed so all function pointers are valid and do not have to be tested
 967 * before use
 968 *
 969 **************************************************************************/
 970int efx_siena_port_dummy_op_int(struct efx_nic *efx)
 971{
 972	return 0;
 973}
 974
 975void efx_siena_port_dummy_op_void(struct efx_nic *efx) {}
 976
 977/**************************************************************************
 978 *
 979 * Data housekeeping
 980 *
 981 **************************************************************************/
 982
 983/* This zeroes out and then fills in the invariants in a struct
 984 * efx_nic (including all sub-structures).
 985 */
 986int efx_siena_init_struct(struct efx_nic *efx,
 987			  struct pci_dev *pci_dev, struct net_device *net_dev)
 988{
 989	int rc = -ENOMEM;
 990
 991	/* Initialise common structures */
 992	INIT_LIST_HEAD(&efx->node);
 993	INIT_LIST_HEAD(&efx->secondary_list);
 994	spin_lock_init(&efx->biu_lock);
 995#ifdef CONFIG_SFC_SIENA_MTD
 996	INIT_LIST_HEAD(&efx->mtd_list);
 997#endif
 998	INIT_WORK(&efx->reset_work, efx_reset_work);
 999	INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
1000	efx_siena_selftest_async_init(efx);
1001	efx->pci_dev = pci_dev;
1002	efx->msg_enable = debug;
1003	efx->state = STATE_UNINIT;
1004	strscpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
1005
1006	efx->net_dev = net_dev;
1007	efx->rx_prefix_size = efx->type->rx_prefix_size;
1008	efx->rx_ip_align =
1009		NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
1010	efx->rx_packet_hash_offset =
1011		efx->type->rx_hash_offset - efx->type->rx_prefix_size;
1012	efx->rx_packet_ts_offset =
1013		efx->type->rx_ts_offset - efx->type->rx_prefix_size;
1014	efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID;
1015	efx->vport_id = EVB_PORT_ID_ASSIGNED;
1016	spin_lock_init(&efx->stats_lock);
1017	efx->vi_stride = EFX_DEFAULT_VI_STRIDE;
1018	efx->num_mac_stats = MC_CMD_MAC_NSTATS;
1019	BUILD_BUG_ON(MC_CMD_MAC_NSTATS - 1 != MC_CMD_MAC_GENERATION_END);
1020	mutex_init(&efx->mac_lock);
1021	init_rwsem(&efx->filter_sem);
1022#ifdef CONFIG_RFS_ACCEL
1023	mutex_init(&efx->rps_mutex);
1024	spin_lock_init(&efx->rps_hash_lock);
1025	/* Failure to allocate is not fatal, but may degrade ARFS performance */
1026	efx->rps_hash_table = kcalloc(EFX_ARFS_HASH_TABLE_SIZE,
1027				      sizeof(*efx->rps_hash_table), GFP_KERNEL);
1028#endif
1029	efx->mdio.dev = net_dev;
1030	INIT_WORK(&efx->mac_work, efx_mac_work);
1031	init_waitqueue_head(&efx->flush_wq);
1032
1033	efx->tx_queues_per_channel = 1;
1034	efx->rxq_entries = EFX_DEFAULT_DMAQ_SIZE;
1035	efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
1036
1037	efx->mem_bar = UINT_MAX;
1038
1039	rc = efx_siena_init_channels(efx);
1040	if (rc)
1041		goto fail;
1042
1043	/* Would be good to use the net_dev name, but we're too early */
1044	snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
1045		 pci_name(pci_dev));
1046	efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1047	if (!efx->workqueue) {
1048		rc = -ENOMEM;
1049		goto fail;
1050	}
1051
1052	return 0;
1053
1054fail:
1055	efx_siena_fini_struct(efx);
1056	return rc;
1057}
1058
1059void efx_siena_fini_struct(struct efx_nic *efx)
1060{
1061#ifdef CONFIG_RFS_ACCEL
1062	kfree(efx->rps_hash_table);
1063#endif
1064
1065	efx_siena_fini_channels(efx);
1066
1067	kfree(efx->vpd_sn);
1068
1069	if (efx->workqueue) {
1070		destroy_workqueue(efx->workqueue);
1071		efx->workqueue = NULL;
1072	}
1073}
1074
1075/* This configures the PCI device to enable I/O and DMA. */
1076int efx_siena_init_io(struct efx_nic *efx, int bar, dma_addr_t dma_mask,
1077		      unsigned int mem_map_size)
1078{
1079	struct pci_dev *pci_dev = efx->pci_dev;
1080	int rc;
1081
1082	efx->mem_bar = UINT_MAX;
1083
1084	netif_dbg(efx, probe, efx->net_dev, "initialising I/O bar=%d\n", bar);
1085
1086	rc = pci_enable_device(pci_dev);
1087	if (rc) {
1088		netif_err(efx, probe, efx->net_dev,
1089			  "failed to enable PCI device\n");
1090		goto fail1;
1091	}
1092
1093	pci_set_master(pci_dev);
1094
1095	rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
1096	if (rc) {
1097		netif_err(efx, probe, efx->net_dev,
1098			  "could not find a suitable DMA mask\n");
1099		goto fail2;
1100	}
1101	netif_dbg(efx, probe, efx->net_dev,
1102		  "using DMA mask %llx\n", (unsigned long long)dma_mask);
1103
1104	efx->membase_phys = pci_resource_start(efx->pci_dev, bar);
1105	if (!efx->membase_phys) {
1106		netif_err(efx, probe, efx->net_dev,
1107			  "ERROR: No BAR%d mapping from the BIOS. "
1108			  "Try pci=realloc on the kernel command line\n", bar);
1109		rc = -ENODEV;
1110		goto fail3;
1111	}
1112
1113	rc = pci_request_region(pci_dev, bar, "sfc");
1114	if (rc) {
1115		netif_err(efx, probe, efx->net_dev,
1116			  "request for memory BAR[%d] failed\n", bar);
1117		rc = -EIO;
1118		goto fail3;
1119	}
1120	efx->mem_bar = bar;
1121	efx->membase = ioremap(efx->membase_phys, mem_map_size);
1122	if (!efx->membase) {
1123		netif_err(efx, probe, efx->net_dev,
1124			  "could not map memory BAR[%d] at %llx+%x\n", bar,
1125			  (unsigned long long)efx->membase_phys, mem_map_size);
1126		rc = -ENOMEM;
1127		goto fail4;
1128	}
1129	netif_dbg(efx, probe, efx->net_dev,
1130		  "memory BAR[%d] at %llx+%x (virtual %p)\n", bar,
1131		  (unsigned long long)efx->membase_phys, mem_map_size,
1132		  efx->membase);
1133
1134	return 0;
1135
1136fail4:
1137	pci_release_region(efx->pci_dev, bar);
1138fail3:
1139	efx->membase_phys = 0;
1140fail2:
1141	pci_disable_device(efx->pci_dev);
1142fail1:
1143	return rc;
1144}
1145
1146void efx_siena_fini_io(struct efx_nic *efx)
1147{
1148	netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
1149
1150	if (efx->membase) {
1151		iounmap(efx->membase);
1152		efx->membase = NULL;
1153	}
1154
1155	if (efx->membase_phys) {
1156		pci_release_region(efx->pci_dev, efx->mem_bar);
1157		efx->membase_phys = 0;
1158		efx->mem_bar = UINT_MAX;
1159	}
1160
1161	/* Don't disable bus-mastering if VFs are assigned */
1162	if (!pci_vfs_assigned(efx->pci_dev))
1163		pci_disable_device(efx->pci_dev);
1164}
1165
1166#ifdef CONFIG_SFC_SIENA_MCDI_LOGGING
1167static ssize_t mcdi_logging_show(struct device *dev,
1168				 struct device_attribute *attr,
1169				 char *buf)
1170{
1171	struct efx_nic *efx = dev_get_drvdata(dev);
1172	struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
1173
1174	return sysfs_emit(buf, "%d\n", mcdi->logging_enabled);
1175}
1176
1177static ssize_t mcdi_logging_store(struct device *dev,
1178				  struct device_attribute *attr,
1179				  const char *buf, size_t count)
1180{
1181	struct efx_nic *efx = dev_get_drvdata(dev);
1182	struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
1183	bool enable = count > 0 && *buf != '0';
1184
1185	mcdi->logging_enabled = enable;
1186	return count;
1187}
1188
1189static DEVICE_ATTR_RW(mcdi_logging);
1190
1191void efx_siena_init_mcdi_logging(struct efx_nic *efx)
1192{
1193	int rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
1194
1195	if (rc) {
1196		netif_warn(efx, drv, efx->net_dev,
1197			   "failed to init net dev attributes\n");
1198	}
1199}
1200
1201void efx_siena_fini_mcdi_logging(struct efx_nic *efx)
1202{
1203	device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
1204}
1205#endif
1206
1207/* A PCI error affecting this device was detected.
1208 * At this point MMIO and DMA may be disabled.
1209 * Stop the software path and request a slot reset.
1210 */
1211static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
1212					      pci_channel_state_t state)
1213{
1214	pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
1215	struct efx_nic *efx = pci_get_drvdata(pdev);
1216
1217	if (state == pci_channel_io_perm_failure)
1218		return PCI_ERS_RESULT_DISCONNECT;
1219
1220	rtnl_lock();
1221
1222	if (efx->state != STATE_DISABLED) {
1223		efx->state = STATE_RECOVERY;
1224		efx->reset_pending = 0;
1225
1226		efx_device_detach_sync(efx);
1227
1228		efx_siena_stop_all(efx);
1229		efx_siena_disable_interrupts(efx);
1230
1231		status = PCI_ERS_RESULT_NEED_RESET;
1232	} else {
1233		/* If the interface is disabled we don't want to do anything
1234		 * with it.
1235		 */
1236		status = PCI_ERS_RESULT_RECOVERED;
1237	}
1238
1239	rtnl_unlock();
1240
1241	pci_disable_device(pdev);
1242
1243	return status;
1244}
1245
1246/* Fake a successful reset, which will be performed later in efx_io_resume. */
1247static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
1248{
1249	struct efx_nic *efx = pci_get_drvdata(pdev);
1250	pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
1251
1252	if (pci_enable_device(pdev)) {
1253		netif_err(efx, hw, efx->net_dev,
1254			  "Cannot re-enable PCI device after reset.\n");
1255		status =  PCI_ERS_RESULT_DISCONNECT;
1256	}
1257
1258	return status;
1259}
1260
1261/* Perform the actual reset and resume I/O operations. */
1262static void efx_io_resume(struct pci_dev *pdev)
1263{
1264	struct efx_nic *efx = pci_get_drvdata(pdev);
1265	int rc;
1266
1267	rtnl_lock();
1268
1269	if (efx->state == STATE_DISABLED)
1270		goto out;
1271
1272	rc = efx_siena_reset(efx, RESET_TYPE_ALL);
1273	if (rc) {
1274		netif_err(efx, hw, efx->net_dev,
1275			  "efx_siena_reset failed after PCI error (%d)\n", rc);
1276	} else {
1277		efx->state = STATE_READY;
1278		netif_dbg(efx, hw, efx->net_dev,
1279			  "Done resetting and resuming IO after PCI error.\n");
1280	}
1281
1282out:
1283	rtnl_unlock();
1284}
1285
1286/* For simplicity and reliability, we always require a slot reset and try to
1287 * reset the hardware when a pci error affecting the device is detected.
1288 */
1289const struct pci_error_handlers efx_siena_err_handlers = {
1290	.error_detected = efx_io_error_detected,
1291	.slot_reset	= efx_io_slot_reset,
1292	.resume		= efx_io_resume,
1293};
1294
1295/* Determine whether the NIC will be able to handle TX offloads for a given
1296 * encapsulated packet.
1297 */
1298static bool efx_can_encap_offloads(struct efx_nic *efx, struct sk_buff *skb)
1299{
1300	struct gre_base_hdr *greh;
1301	__be16 dst_port;
1302	u8 ipproto;
1303
1304	/* Does the NIC support encap offloads?
1305	 * If not, we should never get here, because we shouldn't have
1306	 * advertised encap offload feature flags in the first place.
1307	 */
1308	if (WARN_ON_ONCE(!efx->type->udp_tnl_has_port))
1309		return false;
1310
1311	/* Determine encapsulation protocol in use */
1312	switch (skb->protocol) {
1313	case htons(ETH_P_IP):
1314		ipproto = ip_hdr(skb)->protocol;
1315		break;
1316	case htons(ETH_P_IPV6):
1317		/* If there are extension headers, this will cause us to
1318		 * think we can't offload something that we maybe could have.
1319		 */
1320		ipproto = ipv6_hdr(skb)->nexthdr;
1321		break;
1322	default:
1323		/* Not IP, so can't offload it */
1324		return false;
1325	}
1326	switch (ipproto) {
1327	case IPPROTO_GRE:
1328		/* We support NVGRE but not IP over GRE or random gretaps.
1329		 * Specifically, the NIC will accept GRE as encapsulated if
1330		 * the inner protocol is Ethernet, but only handle it
1331		 * correctly if the GRE header is 8 bytes long.  Moreover,
1332		 * it will not update the Checksum or Sequence Number fields
1333		 * if they are present.  (The Routing Present flag,
1334		 * GRE_ROUTING, cannot be set else the header would be more
1335		 * than 8 bytes long; so we don't have to worry about it.)
1336		 */
1337		if (skb->inner_protocol_type != ENCAP_TYPE_ETHER)
1338			return false;
1339		if (ntohs(skb->inner_protocol) != ETH_P_TEB)
1340			return false;
1341		if (skb_inner_mac_header(skb) - skb_transport_header(skb) != 8)
1342			return false;
1343		greh = (struct gre_base_hdr *)skb_transport_header(skb);
1344		return !(greh->flags & (GRE_CSUM | GRE_SEQ));
1345	case IPPROTO_UDP:
1346		/* If the port is registered for a UDP tunnel, we assume the
1347		 * packet is for that tunnel, and the NIC will handle it as
1348		 * such.  If not, the NIC won't know what to do with it.
1349		 */
1350		dst_port = udp_hdr(skb)->dest;
1351		return efx->type->udp_tnl_has_port(efx, dst_port);
1352	default:
1353		return false;
1354	}
1355}
1356
1357netdev_features_t efx_siena_features_check(struct sk_buff *skb,
1358					   struct net_device *dev,
1359					   netdev_features_t features)
1360{
1361	struct efx_nic *efx = netdev_priv(dev);
1362
1363	if (skb->encapsulation) {
1364		if (features & NETIF_F_GSO_MASK)
1365			/* Hardware can only do TSO with at most 208 bytes
1366			 * of headers.
1367			 */
1368			if (skb_inner_transport_offset(skb) >
1369			    EFX_TSO2_MAX_HDRLEN)
1370				features &= ~(NETIF_F_GSO_MASK);
1371		if (features & (NETIF_F_GSO_MASK | NETIF_F_CSUM_MASK))
1372			if (!efx_can_encap_offloads(efx, skb))
1373				features &= ~(NETIF_F_GSO_MASK |
1374					      NETIF_F_CSUM_MASK);
1375	}
1376	return features;
1377}
1378
1379int efx_siena_get_phys_port_id(struct net_device *net_dev,
1380			       struct netdev_phys_item_id *ppid)
1381{
1382	struct efx_nic *efx = netdev_priv(net_dev);
1383
1384	if (efx->type->get_phys_port_id)
1385		return efx->type->get_phys_port_id(efx, ppid);
1386	else
1387		return -EOPNOTSUPP;
1388}
1389
1390int efx_siena_get_phys_port_name(struct net_device *net_dev,
1391				 char *name, size_t len)
1392{
1393	struct efx_nic *efx = netdev_priv(net_dev);
1394
1395	if (snprintf(name, len, "p%u", efx->port_num) >= len)
1396		return -EINVAL;
1397	return 0;
1398}