FILE
sxgbe_main.c
File preview with syntax highlighting.
linux-6.19.14/drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 10G controller driver for Samsung SoCs 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 8 */ 9 10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12#include <linux/clk.h> 13#include <linux/crc32.h> 14#include <linux/dma-mapping.h> 15#include <linux/etherdevice.h> 16#include <linux/ethtool.h> 17#include <linux/if.h> 18#include <linux/if_ether.h> 19#include <linux/if_vlan.h> 20#include <linux/init.h> 21#include <linux/interrupt.h> 22#include <linux/ip.h> 23#include <linux/kernel.h> 24#include <linux/mii.h> 25#include <linux/module.h> 26#include <linux/net_tstamp.h> 27#include <linux/netdevice.h> 28#include <linux/phy.h> 29#include <linux/platform_device.h> 30#include <linux/prefetch.h> 31#include <linux/skbuff.h> 32#include <linux/slab.h> 33#include <linux/tcp.h> 34#include <linux/sxgbe_platform.h> 35 36#include "sxgbe_common.h" 37#include "sxgbe_desc.h" 38#include "sxgbe_dma.h" 39#include "sxgbe_mtl.h" 40#include "sxgbe_reg.h" 41 42#define SXGBE_ALIGN(x) L1_CACHE_ALIGN(x) 43#define JUMBO_LEN 9000 44 45/* Module parameters */ 46#define TX_TIMEO 5000 47#define DMA_TX_SIZE 512 48#define DMA_RX_SIZE 1024 49#define TC_DEFAULT 64 50#define DMA_BUFFER_SIZE BUF_SIZE_2KiB 51/* The default timer value as per the sxgbe specification 1 sec(1000 ms) */ 52#define SXGBE_DEFAULT_LPI_TIMER 1000 53 54static int debug = -1; 55static int eee_timer = SXGBE_DEFAULT_LPI_TIMER; 56 57module_param(eee_timer, int, 0644); 58 59module_param(debug, int, 0644); 60static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 61 NETIF_MSG_LINK | NETIF_MSG_IFUP | 62 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 63 64static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id); 65static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id); 66static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id); 67 68#define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 69 70#define SXGBE_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x)) 71 72/** 73 * sxgbe_verify_args - verify the driver parameters. 74 * Description: it verifies if some wrong parameter is passed to the driver. 75 * Note that wrong parameters are replaced with the default values. 76 */ 77static void sxgbe_verify_args(void) 78{ 79 if (unlikely(eee_timer < 0)) 80 eee_timer = SXGBE_DEFAULT_LPI_TIMER; 81} 82 83static void sxgbe_enable_eee_mode(const struct sxgbe_priv_data *priv) 84{ 85 /* Check and enter in LPI mode */ 86 if (!priv->tx_path_in_lpi_mode) 87 priv->hw->mac->set_eee_mode(priv->ioaddr); 88} 89 90void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv) 91{ 92 /* Exit and disable EEE in case of we are in LPI state. */ 93 priv->hw->mac->reset_eee_mode(priv->ioaddr); 94 timer_delete_sync(&priv->eee_ctrl_timer); 95 priv->tx_path_in_lpi_mode = false; 96} 97 98/** 99 * sxgbe_eee_ctrl_timer 100 * @t: timer list containing a data 101 * Description: 102 * If there is no data transfer and if we are not in LPI state, 103 * then MAC Transmitter can be moved to LPI state. 104 */ 105static void sxgbe_eee_ctrl_timer(struct timer_list *t) 106{ 107 struct sxgbe_priv_data *priv = timer_container_of(priv, t, 108 eee_ctrl_timer); 109 110 sxgbe_enable_eee_mode(priv); 111 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer)); 112} 113 114/** 115 * sxgbe_eee_init 116 * @priv: private device pointer 117 * Description: 118 * If the EEE support has been enabled while configuring the driver, 119 * if the GMAC actually supports the EEE (from the HW cap reg) and the 120 * phy can also manage EEE, so enable the LPI state and start the timer 121 * to verify if the tx path can enter in LPI state. 122 */ 123bool sxgbe_eee_init(struct sxgbe_priv_data * const priv) 124{ 125 struct net_device *ndev = priv->dev; 126 bool ret = false; 127 128 /* MAC core supports the EEE feature. */ 129 if (priv->hw_cap.eee) { 130 /* Check if the PHY supports EEE */ 131 if (phy_init_eee(ndev->phydev, true)) 132 return false; 133 134 timer_setup(&priv->eee_ctrl_timer, sxgbe_eee_ctrl_timer, 0); 135 priv->eee_ctrl_timer.expires = SXGBE_LPI_TIMER(eee_timer); 136 add_timer(&priv->eee_ctrl_timer); 137 138 priv->hw->mac->set_eee_timer(priv->ioaddr, 139 SXGBE_DEFAULT_LPI_TIMER, 140 priv->tx_lpi_timer); 141 142 pr_info("Energy-Efficient Ethernet initialized\n"); 143 144 ret = true; 145 } 146 147 return ret; 148} 149 150static void sxgbe_eee_adjust(const struct sxgbe_priv_data *priv) 151{ 152 struct net_device *ndev = priv->dev; 153 154 /* When the EEE has been already initialised we have to 155 * modify the PLS bit in the LPI ctrl & status reg according 156 * to the PHY link status. For this reason. 157 */ 158 if (priv->eee_enabled) 159 priv->hw->mac->set_eee_pls(priv->ioaddr, ndev->phydev->link); 160} 161 162/** 163 * sxgbe_clk_csr_set - dynamically set the MDC clock 164 * @priv: driver private structure 165 * Description: this is to dynamically set the MDC clock according to the csr 166 * clock input. 167 */ 168static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv) 169{ 170 u32 clk_rate = clk_get_rate(priv->sxgbe_clk); 171 172 /* assign the proper divider, this will be used during 173 * mdio communication 174 */ 175 if (clk_rate < SXGBE_CSR_F_150M) 176 priv->clk_csr = SXGBE_CSR_100_150M; 177 else if (clk_rate <= SXGBE_CSR_F_250M) 178 priv->clk_csr = SXGBE_CSR_150_250M; 179 else if (clk_rate <= SXGBE_CSR_F_300M) 180 priv->clk_csr = SXGBE_CSR_250_300M; 181 else if (clk_rate <= SXGBE_CSR_F_350M) 182 priv->clk_csr = SXGBE_CSR_300_350M; 183 else if (clk_rate <= SXGBE_CSR_F_400M) 184 priv->clk_csr = SXGBE_CSR_350_400M; 185 else if (clk_rate <= SXGBE_CSR_F_500M) 186 priv->clk_csr = SXGBE_CSR_400_500M; 187} 188 189/* minimum number of free TX descriptors required to wake up TX process */ 190#define SXGBE_TX_THRESH(x) (x->dma_tx_size/4) 191 192static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize) 193{ 194 return queue->dirty_tx + tx_qsize - queue->cur_tx - 1; 195} 196 197/** 198 * sxgbe_adjust_link 199 * @dev: net device structure 200 * Description: it adjusts the link parameters. 201 */ 202static void sxgbe_adjust_link(struct net_device *dev) 203{ 204 struct sxgbe_priv_data *priv = netdev_priv(dev); 205 struct phy_device *phydev = dev->phydev; 206 u8 new_state = 0; 207 u8 speed = 0xff; 208 209 if (!phydev) 210 return; 211 212 /* SXGBE is not supporting auto-negotiation and 213 * half duplex mode. so, not handling duplex change 214 * in this function. only handling speed and link status 215 */ 216 if (phydev->link) { 217 if (phydev->speed != priv->speed) { 218 new_state = 1; 219 switch (phydev->speed) { 220 case SPEED_10000: 221 speed = SXGBE_SPEED_10G; 222 break; 223 case SPEED_2500: 224 speed = SXGBE_SPEED_2_5G; 225 break; 226 case SPEED_1000: 227 speed = SXGBE_SPEED_1G; 228 break; 229 default: 230 netif_err(priv, link, dev, 231 "Speed (%d) not supported\n", 232 phydev->speed); 233 } 234 235 priv->speed = phydev->speed; 236 priv->hw->mac->set_speed(priv->ioaddr, speed); 237 } 238 239 if (!priv->oldlink) { 240 new_state = 1; 241 priv->oldlink = 1; 242 } 243 } else if (priv->oldlink) { 244 new_state = 1; 245 priv->oldlink = 0; 246 priv->speed = SPEED_UNKNOWN; 247 } 248 249 if (new_state & netif_msg_link(priv)) 250 phy_print_status(phydev); 251 252 /* Alter the MAC settings for EEE */ 253 sxgbe_eee_adjust(priv); 254} 255 256/** 257 * sxgbe_init_phy - PHY initialization 258 * @ndev: net device structure 259 * Description: it initializes the driver's PHY state, and attaches the PHY 260 * to the mac driver. 261 * Return value: 262 * 0 on success 263 */ 264static int sxgbe_init_phy(struct net_device *ndev) 265{ 266 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 267 char bus_id[MII_BUS_ID_SIZE]; 268 struct phy_device *phydev; 269 struct sxgbe_priv_data *priv = netdev_priv(ndev); 270 int phy_iface = priv->plat->interface; 271 272 /* assign default link status */ 273 priv->oldlink = 0; 274 priv->speed = SPEED_UNKNOWN; 275 priv->oldduplex = DUPLEX_UNKNOWN; 276 277 if (priv->plat->phy_bus_name) 278 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 279 priv->plat->phy_bus_name, priv->plat->bus_id); 280 else 281 snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x", 282 priv->plat->bus_id); 283 284 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 285 priv->plat->phy_addr); 286 netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt); 287 288 phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface); 289 290 if (IS_ERR(phydev)) { 291 netdev_err(ndev, "Could not attach to PHY\n"); 292 return PTR_ERR(phydev); 293 } 294 295 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 296 if ((phy_iface == PHY_INTERFACE_MODE_MII) || 297 (phy_iface == PHY_INTERFACE_MODE_RMII)) 298 phy_set_max_speed(phydev, SPEED_1000); 299 300 if (phydev->phy_id == 0) { 301 phy_disconnect(phydev); 302 return -ENODEV; 303 } 304 305 netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n", 306 __func__, phydev->phy_id, phydev->link); 307 308 return 0; 309} 310 311/** 312 * sxgbe_clear_descriptors: clear descriptors 313 * @priv: driver private structure 314 * Description: this function is called to clear the tx and rx descriptors 315 * in case of both basic and extended descriptors are used. 316 */ 317static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv) 318{ 319 int i, j; 320 unsigned int txsize = priv->dma_tx_size; 321 unsigned int rxsize = priv->dma_rx_size; 322 323 /* Clear the Rx/Tx descriptors */ 324 for (j = 0; j < SXGBE_RX_QUEUES; j++) { 325 for (i = 0; i < rxsize; i++) 326 priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i], 327 priv->use_riwt, priv->mode, 328 (i == rxsize - 1)); 329 } 330 331 for (j = 0; j < SXGBE_TX_QUEUES; j++) { 332 for (i = 0; i < txsize; i++) 333 priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]); 334 } 335} 336 337static int sxgbe_init_rx_buffers(struct net_device *dev, 338 struct sxgbe_rx_norm_desc *p, int i, 339 unsigned int dma_buf_sz, 340 struct sxgbe_rx_queue *rx_ring) 341{ 342 struct sxgbe_priv_data *priv = netdev_priv(dev); 343 struct sk_buff *skb; 344 345 skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL); 346 if (!skb) 347 return -ENOMEM; 348 349 rx_ring->rx_skbuff[i] = skb; 350 rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 351 dma_buf_sz, DMA_FROM_DEVICE); 352 353 if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) { 354 netdev_err(dev, "%s: DMA mapping error\n", __func__); 355 dev_kfree_skb_any(skb); 356 return -EINVAL; 357 } 358 359 p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i]; 360 361 return 0; 362} 363 364/** 365 * sxgbe_free_rx_buffers - free what sxgbe_init_rx_buffers() allocated 366 * @dev: net device structure 367 * @p: dec pointer 368 * @i: index 369 * @dma_buf_sz: size 370 * @rx_ring: ring to be freed 371 * 372 * Description: this function initializes the DMA RX descriptor 373 */ 374static void sxgbe_free_rx_buffers(struct net_device *dev, 375 struct sxgbe_rx_norm_desc *p, int i, 376 unsigned int dma_buf_sz, 377 struct sxgbe_rx_queue *rx_ring) 378{ 379 struct sxgbe_priv_data *priv = netdev_priv(dev); 380 381 kfree_skb(rx_ring->rx_skbuff[i]); 382 dma_unmap_single(priv->device, rx_ring->rx_skbuff_dma[i], 383 dma_buf_sz, DMA_FROM_DEVICE); 384} 385 386/** 387 * init_tx_ring - init the TX descriptor ring 388 * @dev: net device structure 389 * @queue_no: queue 390 * @tx_ring: ring to be initialised 391 * @tx_rsize: ring size 392 * Description: this function initializes the DMA TX descriptor 393 */ 394static int init_tx_ring(struct device *dev, u8 queue_no, 395 struct sxgbe_tx_queue *tx_ring, int tx_rsize) 396{ 397 /* TX ring is not allcoated */ 398 if (!tx_ring) { 399 dev_err(dev, "No memory for TX queue of SXGBE\n"); 400 return -ENOMEM; 401 } 402 403 /* allocate memory for TX descriptors */ 404 tx_ring->dma_tx = dma_alloc_coherent(dev, 405 tx_rsize * sizeof(struct sxgbe_tx_norm_desc), 406 &tx_ring->dma_tx_phy, GFP_KERNEL); 407 if (!tx_ring->dma_tx) 408 return -ENOMEM; 409 410 /* allocate memory for TX skbuff array */ 411 tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize, 412 sizeof(dma_addr_t), GFP_KERNEL); 413 if (!tx_ring->tx_skbuff_dma) 414 goto dmamem_err; 415 416 tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize, 417 sizeof(struct sk_buff *), GFP_KERNEL); 418 419 if (!tx_ring->tx_skbuff) 420 goto dmamem_err; 421 422 /* assign queue number */ 423 tx_ring->queue_no = queue_no; 424 425 /* initialise counters */ 426 tx_ring->dirty_tx = 0; 427 tx_ring->cur_tx = 0; 428 429 return 0; 430 431dmamem_err: 432 dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc), 433 tx_ring->dma_tx, tx_ring->dma_tx_phy); 434 return -ENOMEM; 435} 436 437/** 438 * free_rx_ring - free the RX descriptor ring 439 * @dev: net device structure 440 * @rx_ring: ring to be initialised 441 * @rx_rsize: ring size 442 * Description: this function initializes the DMA RX descriptor 443 */ 444static void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring, 445 int rx_rsize) 446{ 447 dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc), 448 rx_ring->dma_rx, rx_ring->dma_rx_phy); 449 kfree(rx_ring->rx_skbuff_dma); 450 kfree(rx_ring->rx_skbuff); 451} 452 453/** 454 * init_rx_ring - init the RX descriptor ring 455 * @dev: net device structure 456 * @queue_no: queue 457 * @rx_ring: ring to be initialised 458 * @rx_rsize: ring size 459 * Description: this function initializes the DMA RX descriptor 460 */ 461static int init_rx_ring(struct net_device *dev, u8 queue_no, 462 struct sxgbe_rx_queue *rx_ring, int rx_rsize) 463{ 464 struct sxgbe_priv_data *priv = netdev_priv(dev); 465 int desc_index; 466 unsigned int bfsize = 0; 467 unsigned int ret = 0; 468 469 /* Set the max buffer size according to the MTU. */ 470 bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8); 471 472 netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize); 473 474 /* RX ring is not allcoated */ 475 if (rx_ring == NULL) { 476 netdev_err(dev, "No memory for RX queue\n"); 477 return -ENOMEM; 478 } 479 480 /* assign queue number */ 481 rx_ring->queue_no = queue_no; 482 483 /* allocate memory for RX descriptors */ 484 rx_ring->dma_rx = dma_alloc_coherent(priv->device, 485 rx_rsize * sizeof(struct sxgbe_rx_norm_desc), 486 &rx_ring->dma_rx_phy, GFP_KERNEL); 487 488 if (rx_ring->dma_rx == NULL) 489 return -ENOMEM; 490 491 /* allocate memory for RX skbuff array */ 492 rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize, 493 sizeof(dma_addr_t), GFP_KERNEL); 494 if (!rx_ring->rx_skbuff_dma) { 495 ret = -ENOMEM; 496 goto err_free_dma_rx; 497 } 498 499 rx_ring->rx_skbuff = kmalloc_array(rx_rsize, 500 sizeof(struct sk_buff *), GFP_KERNEL); 501 if (!rx_ring->rx_skbuff) { 502 ret = -ENOMEM; 503 goto err_free_skbuff_dma; 504 } 505 506 /* initialise the buffers */ 507 for (desc_index = 0; desc_index < rx_rsize; desc_index++) { 508 struct sxgbe_rx_norm_desc *p; 509 p = rx_ring->dma_rx + desc_index; 510 ret = sxgbe_init_rx_buffers(dev, p, desc_index, 511 bfsize, rx_ring); 512 if (ret) 513 goto err_free_rx_buffers; 514 } 515 516 /* initialise counters */ 517 rx_ring->cur_rx = 0; 518 rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize); 519 priv->dma_buf_sz = bfsize; 520 521 return 0; 522 523err_free_rx_buffers: 524 while (--desc_index >= 0) { 525 struct sxgbe_rx_norm_desc *p; 526 527 p = rx_ring->dma_rx + desc_index; 528 sxgbe_free_rx_buffers(dev, p, desc_index, bfsize, rx_ring); 529 } 530 kfree(rx_ring->rx_skbuff); 531err_free_skbuff_dma: 532 kfree(rx_ring->rx_skbuff_dma); 533err_free_dma_rx: 534 dma_free_coherent(priv->device, 535 rx_rsize * sizeof(struct sxgbe_rx_norm_desc), 536 rx_ring->dma_rx, rx_ring->dma_rx_phy); 537 538 return ret; 539} 540/** 541 * free_tx_ring - free the TX descriptor ring 542 * @dev: net device structure 543 * @tx_ring: ring to be initialised 544 * @tx_rsize: ring size 545 * Description: this function initializes the DMA TX descriptor 546 */ 547static void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring, 548 int tx_rsize) 549{ 550 dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc), 551 tx_ring->dma_tx, tx_ring->dma_tx_phy); 552} 553 554/** 555 * init_dma_desc_rings - init the RX/TX descriptor rings 556 * @netd: net device structure 557 * Description: this function initializes the DMA RX/TX descriptors 558 * and allocates the socket buffers. It suppors the chained and ring 559 * modes. 560 */ 561static int init_dma_desc_rings(struct net_device *netd) 562{ 563 int queue_num, ret; 564 struct sxgbe_priv_data *priv = netdev_priv(netd); 565 int tx_rsize = priv->dma_tx_size; 566 int rx_rsize = priv->dma_rx_size; 567 568 /* Allocate memory for queue structures and TX descs */ 569 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 570 ret = init_tx_ring(priv->device, queue_num, 571 priv->txq[queue_num], tx_rsize); 572 if (ret) { 573 dev_err(&netd->dev, "TX DMA ring allocation failed!\n"); 574 goto txalloc_err; 575 } 576 577 /* save private pointer in each ring this 578 * pointer is needed during cleaing TX queue 579 */ 580 priv->txq[queue_num]->priv_ptr = priv; 581 } 582 583 /* Allocate memory for queue structures and RX descs */ 584 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { 585 ret = init_rx_ring(netd, queue_num, 586 priv->rxq[queue_num], rx_rsize); 587 if (ret) { 588 netdev_err(netd, "RX DMA ring allocation failed!!\n"); 589 goto rxalloc_err; 590 } 591 592 /* save private pointer in each ring this 593 * pointer is needed during cleaing TX queue 594 */ 595 priv->rxq[queue_num]->priv_ptr = priv; 596 } 597 598 sxgbe_clear_descriptors(priv); 599 600 return 0; 601 602txalloc_err: 603 while (queue_num--) 604 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize); 605 return ret; 606 607rxalloc_err: 608 while (queue_num--) 609 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize); 610 return ret; 611} 612 613static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue) 614{ 615 int dma_desc; 616 struct sxgbe_priv_data *priv = txqueue->priv_ptr; 617 int tx_rsize = priv->dma_tx_size; 618 619 for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) { 620 struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc; 621 622 if (txqueue->tx_skbuff_dma[dma_desc]) 623 dma_unmap_single(priv->device, 624 txqueue->tx_skbuff_dma[dma_desc], 625 priv->hw->desc->get_tx_len(tdesc), 626 DMA_TO_DEVICE); 627 628 dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]); 629 txqueue->tx_skbuff[dma_desc] = NULL; 630 txqueue->tx_skbuff_dma[dma_desc] = 0; 631 } 632} 633 634 635static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv) 636{ 637 int queue_num; 638 639 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 640 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num]; 641 tx_free_ring_skbufs(tqueue); 642 } 643} 644 645static void free_dma_desc_resources(struct sxgbe_priv_data *priv) 646{ 647 int queue_num; 648 int tx_rsize = priv->dma_tx_size; 649 int rx_rsize = priv->dma_rx_size; 650 651 /* Release the DMA TX buffers */ 652 dma_free_tx_skbufs(priv); 653 654 /* Release the TX ring memory also */ 655 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 656 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize); 657 } 658 659 /* Release the RX ring memory also */ 660 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { 661 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize); 662 } 663} 664 665static int txring_mem_alloc(struct sxgbe_priv_data *priv) 666{ 667 int queue_num; 668 669 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 670 priv->txq[queue_num] = devm_kmalloc(priv->device, 671 sizeof(struct sxgbe_tx_queue), GFP_KERNEL); 672 if (!priv->txq[queue_num]) 673 return -ENOMEM; 674 } 675 676 return 0; 677} 678 679static int rxring_mem_alloc(struct sxgbe_priv_data *priv) 680{ 681 int queue_num; 682 683 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { 684 priv->rxq[queue_num] = devm_kmalloc(priv->device, 685 sizeof(struct sxgbe_rx_queue), GFP_KERNEL); 686 if (!priv->rxq[queue_num]) 687 return -ENOMEM; 688 } 689 690 return 0; 691} 692 693/** 694 * sxgbe_mtl_operation_mode - HW MTL operation mode 695 * @priv: driver private structure 696 * Description: it sets the MTL operation mode: tx/rx MTL thresholds 697 * or Store-And-Forward capability. 698 */ 699static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv) 700{ 701 int queue_num; 702 703 /* TX/RX threshold control */ 704 if (likely(priv->plat->force_sf_dma_mode)) { 705 /* set TC mode for TX QUEUES */ 706 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num) 707 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num, 708 SXGBE_MTL_SFMODE); 709 priv->tx_tc = SXGBE_MTL_SFMODE; 710 711 /* set TC mode for RX QUEUES */ 712 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num) 713 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num, 714 SXGBE_MTL_SFMODE); 715 priv->rx_tc = SXGBE_MTL_SFMODE; 716 } else if (unlikely(priv->plat->force_thresh_dma_mode)) { 717 /* set TC mode for TX QUEUES */ 718 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num) 719 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num, 720 priv->tx_tc); 721 /* set TC mode for RX QUEUES */ 722 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num) 723 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num, 724 priv->rx_tc); 725 } else { 726 pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__); 727 } 728} 729 730/** 731 * sxgbe_tx_queue_clean: 732 * @tqueue: queue pointer 733 * Description: it reclaims resources after transmission completes. 734 */ 735static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue) 736{ 737 struct sxgbe_priv_data *priv = tqueue->priv_ptr; 738 unsigned int tx_rsize = priv->dma_tx_size; 739 struct netdev_queue *dev_txq; 740 u8 queue_no = tqueue->queue_no; 741 742 dev_txq = netdev_get_tx_queue(priv->dev, queue_no); 743 744 __netif_tx_lock(dev_txq, smp_processor_id()); 745 746 priv->xstats.tx_clean++; 747 while (tqueue->dirty_tx != tqueue->cur_tx) { 748 unsigned int entry = tqueue->dirty_tx % tx_rsize; 749 struct sk_buff *skb = tqueue->tx_skbuff[entry]; 750 struct sxgbe_tx_norm_desc *p; 751 752 p = tqueue->dma_tx + entry; 753 754 /* Check if the descriptor is owned by the DMA. */ 755 if (priv->hw->desc->get_tx_owner(p)) 756 break; 757 758 if (netif_msg_tx_done(priv)) 759 pr_debug("%s: curr %d, dirty %d\n", 760 __func__, tqueue->cur_tx, tqueue->dirty_tx); 761 762 if (likely(tqueue->tx_skbuff_dma[entry])) { 763 dma_unmap_single(priv->device, 764 tqueue->tx_skbuff_dma[entry], 765 priv->hw->desc->get_tx_len(p), 766 DMA_TO_DEVICE); 767 tqueue->tx_skbuff_dma[entry] = 0; 768 } 769 770 if (likely(skb)) { 771 dev_kfree_skb(skb); 772 tqueue->tx_skbuff[entry] = NULL; 773 } 774 775 priv->hw->desc->release_tx_desc(p); 776 777 tqueue->dirty_tx++; 778 } 779 780 /* wake up queue */ 781 if (unlikely(netif_tx_queue_stopped(dev_txq) && 782 sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) { 783 if (netif_msg_tx_done(priv)) 784 pr_debug("%s: restart transmit\n", __func__); 785 netif_tx_wake_queue(dev_txq); 786 } 787 788 __netif_tx_unlock(dev_txq); 789} 790 791/** 792 * sxgbe_tx_all_clean: 793 * @priv: driver private structure 794 * Description: it reclaims resources after transmission completes. 795 */ 796static void sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv) 797{ 798 u8 queue_num; 799 800 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 801 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num]; 802 803 sxgbe_tx_queue_clean(tqueue); 804 } 805 806 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 807 sxgbe_enable_eee_mode(priv); 808 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer)); 809 } 810} 811 812/** 813 * sxgbe_restart_tx_queue: irq tx error mng function 814 * @priv: driver private structure 815 * @queue_num: queue number 816 * Description: it cleans the descriptors and restarts the transmission 817 * in case of errors. 818 */ 819static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num) 820{ 821 struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num]; 822 struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev, 823 queue_num); 824 825 /* stop the queue */ 826 netif_tx_stop_queue(dev_txq); 827 828 /* stop the tx dma */ 829 priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num); 830 831 /* free the skbuffs of the ring */ 832 tx_free_ring_skbufs(tx_ring); 833 834 /* initialise counters */ 835 tx_ring->cur_tx = 0; 836 tx_ring->dirty_tx = 0; 837 838 /* start the tx dma */ 839 priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num); 840 841 priv->dev->stats.tx_errors++; 842 843 /* wakeup the queue */ 844 netif_tx_wake_queue(dev_txq); 845} 846 847/** 848 * sxgbe_reset_all_tx_queues: irq tx error mng function 849 * @priv: driver private structure 850 * Description: it cleans all the descriptors and 851 * restarts the transmission on all queues in case of errors. 852 */ 853static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv) 854{ 855 int queue_num; 856 857 /* On TX timeout of net device, resetting of all queues 858 * may not be proper way, revisit this later if needed 859 */ 860 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) 861 sxgbe_restart_tx_queue(priv, queue_num); 862} 863 864/** 865 * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register. 866 * @priv: driver private structure 867 * Description: 868 * new GMAC chip generations have a new register to indicate the 869 * presence of the optional feature/functions. 870 * This can be also used to override the value passed through the 871 * platform and necessary for old MAC10/100 and GMAC chips. 872 */ 873static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv) 874{ 875 int rval = 0; 876 struct sxgbe_hw_features *features = &priv->hw_cap; 877 878 /* Read First Capability Register CAP[0] */ 879 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0); 880 if (rval) { 881 features->pmt_remote_wake_up = 882 SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval); 883 features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval); 884 features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval); 885 features->tx_csum_offload = 886 SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval); 887 features->rx_csum_offload = 888 SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval); 889 features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval); 890 features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval); 891 features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval); 892 features->eee = SXGBE_HW_FEAT_EEE(rval); 893 } 894 895 /* Read First Capability Register CAP[1] */ 896 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1); 897 if (rval) { 898 features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval); 899 features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval); 900 features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval); 901 features->dcb_enable = SXGBE_HW_FEAT_DCB(rval); 902 features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval); 903 features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval); 904 features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval); 905 features->rss_enable = SXGBE_HW_FEAT_RSS(rval); 906 features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval); 907 features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval); 908 } 909 910 /* Read First Capability Register CAP[2] */ 911 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2); 912 if (rval) { 913 features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval); 914 features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval); 915 features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval); 916 features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval); 917 features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval); 918 features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval); 919 } 920 921 return rval; 922} 923 924/** 925 * sxgbe_check_ether_addr: check if the MAC addr is valid 926 * @priv: driver private structure 927 * Description: 928 * it is to verify if the MAC address is valid, in case of failures it 929 * generates a random MAC address 930 */ 931static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv) 932{ 933 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 934 u8 addr[ETH_ALEN]; 935 936 priv->hw->mac->get_umac_addr((void __iomem *) 937 priv->ioaddr, addr, 0); 938 if (is_valid_ether_addr(addr)) 939 eth_hw_addr_set(priv->dev, addr); 940 else 941 eth_hw_addr_random(priv->dev); 942 } 943 dev_info(priv->device, "device MAC address %pM\n", 944 priv->dev->dev_addr); 945} 946 947/** 948 * sxgbe_init_dma_engine: DMA init. 949 * @priv: driver private structure 950 * Description: 951 * It inits the DMA invoking the specific SXGBE callback. 952 * Some DMA parameters can be passed from the platform; 953 * in case of these are not passed a default is kept for the MAC or GMAC. 954 */ 955static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv) 956{ 957 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0; 958 int queue_num; 959 960 if (priv->plat->dma_cfg) { 961 pbl = priv->plat->dma_cfg->pbl; 962 fixed_burst = priv->plat->dma_cfg->fixed_burst; 963 burst_map = priv->plat->dma_cfg->burst_map; 964 } 965 966 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) 967 priv->hw->dma->cha_init(priv->ioaddr, queue_num, 968 fixed_burst, pbl, 969 (priv->txq[queue_num])->dma_tx_phy, 970 (priv->rxq[queue_num])->dma_rx_phy, 971 priv->dma_tx_size, priv->dma_rx_size); 972 973 return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map); 974} 975 976/** 977 * sxgbe_init_mtl_engine: MTL init. 978 * @priv: driver private structure 979 * Description: 980 * It inits the MTL invoking the specific SXGBE callback. 981 */ 982static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv) 983{ 984 int queue_num; 985 986 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 987 priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num, 988 priv->hw_cap.tx_mtl_qsize); 989 priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num); 990 } 991} 992 993/** 994 * sxgbe_disable_mtl_engine: MTL disable. 995 * @priv: driver private structure 996 * Description: 997 * It disables the MTL queues by invoking the specific SXGBE callback. 998 */ 999static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv) 1000{ 1001 int queue_num; 1002 1003 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) 1004 priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num); 1005} 1006 1007 1008/** 1009 * sxgbe_tx_timer: mitigation sw timer for tx. 1010 * @t: timer pointer 1011 * Description: 1012 * This is the timer handler to directly invoke the sxgbe_tx_clean. 1013 */ 1014static void sxgbe_tx_timer(struct timer_list *t) 1015{ 1016 struct sxgbe_tx_queue *p = timer_container_of(p, t, txtimer); 1017 sxgbe_tx_queue_clean(p); 1018} 1019 1020/** 1021 * sxgbe_tx_init_coalesce: init tx mitigation options. 1022 * @priv: driver private structure 1023 * Description: 1024 * This inits the transmit coalesce parameters: i.e. timer rate, 1025 * timer handler and default threshold used for enabling the 1026 * interrupt on completion bit. 1027 */ 1028static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv) 1029{ 1030 u8 queue_num; 1031 1032 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 1033 struct sxgbe_tx_queue *p = priv->txq[queue_num]; 1034 p->tx_coal_frames = SXGBE_TX_FRAMES; 1035 p->tx_coal_timer = SXGBE_COAL_TX_TIMER; 1036 timer_setup(&p->txtimer, sxgbe_tx_timer, 0); 1037 p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer); 1038 add_timer(&p->txtimer); 1039 } 1040} 1041 1042static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv) 1043{ 1044 u8 queue_num; 1045 1046 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 1047 struct sxgbe_tx_queue *p = priv->txq[queue_num]; 1048 timer_delete_sync(&p->txtimer); 1049 } 1050} 1051 1052/** 1053 * sxgbe_open - open entry point of the driver 1054 * @dev : pointer to the device structure. 1055 * Description: 1056 * This function is the open entry point of the driver. 1057 * Return value: 1058 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1059 * file on failure. 1060 */ 1061static int sxgbe_open(struct net_device *dev) 1062{ 1063 struct sxgbe_priv_data *priv = netdev_priv(dev); 1064 int ret, queue_num; 1065 1066 clk_prepare_enable(priv->sxgbe_clk); 1067 1068 sxgbe_check_ether_addr(priv); 1069 1070 /* Init the phy */ 1071 ret = sxgbe_init_phy(dev); 1072 if (ret) { 1073 netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n", 1074 __func__, ret); 1075 goto phy_error; 1076 } 1077 1078 /* Create and initialize the TX/RX descriptors chains. */ 1079 priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE); 1080 priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE); 1081 priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE); 1082 priv->tx_tc = TC_DEFAULT; 1083 priv->rx_tc = TC_DEFAULT; 1084 init_dma_desc_rings(dev); 1085 1086 /* DMA initialization and SW reset */ 1087 ret = sxgbe_init_dma_engine(priv); 1088 if (ret < 0) { 1089 netdev_err(dev, "%s: DMA initialization failed\n", __func__); 1090 goto init_error; 1091 } 1092 1093 /* MTL initialization */ 1094 sxgbe_init_mtl_engine(priv); 1095 1096 /* Copy the MAC addr into the HW */ 1097 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); 1098 1099 /* Initialize the MAC Core */ 1100 priv->hw->mac->core_init(priv->ioaddr); 1101 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { 1102 priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num); 1103 } 1104 1105 /* Request the IRQ lines */ 1106 ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt, 1107 IRQF_SHARED, dev->name, dev); 1108 if (unlikely(ret < 0)) { 1109 netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n", 1110 __func__, priv->irq, ret); 1111 goto init_error; 1112 } 1113 1114 /* If the LPI irq is different from the mac irq 1115 * register a dedicated handler 1116 */ 1117 if (priv->lpi_irq != dev->irq) { 1118 ret = devm_request_irq(priv->device, priv->lpi_irq, 1119 sxgbe_common_interrupt, 1120 IRQF_SHARED, dev->name, dev); 1121 if (unlikely(ret < 0)) { 1122 netdev_err(dev, "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1123 __func__, priv->lpi_irq, ret); 1124 goto init_error; 1125 } 1126 } 1127 1128 /* Request TX DMA irq lines */ 1129 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 1130 ret = devm_request_irq(priv->device, 1131 (priv->txq[queue_num])->irq_no, 1132 sxgbe_tx_interrupt, 0, 1133 dev->name, priv->txq[queue_num]); 1134 if (unlikely(ret < 0)) { 1135 netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n", 1136 __func__, priv->irq, ret); 1137 goto init_error; 1138 } 1139 } 1140 1141 /* Request RX DMA irq lines */ 1142 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { 1143 ret = devm_request_irq(priv->device, 1144 (priv->rxq[queue_num])->irq_no, 1145 sxgbe_rx_interrupt, 0, 1146 dev->name, priv->rxq[queue_num]); 1147 if (unlikely(ret < 0)) { 1148 netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n", 1149 __func__, priv->irq, ret); 1150 goto init_error; 1151 } 1152 } 1153 1154 /* Enable the MAC Rx/Tx */ 1155 priv->hw->mac->enable_tx(priv->ioaddr, true); 1156 priv->hw->mac->enable_rx(priv->ioaddr, true); 1157 1158 /* Set the HW DMA mode and the COE */ 1159 sxgbe_mtl_operation_mode(priv); 1160 1161 /* Extra statistics */ 1162 memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats)); 1163 1164 priv->xstats.tx_threshold = priv->tx_tc; 1165 priv->xstats.rx_threshold = priv->rx_tc; 1166 1167 /* Start the ball rolling... */ 1168 netdev_dbg(dev, "DMA RX/TX processes started...\n"); 1169 priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES); 1170 priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES); 1171 1172 if (dev->phydev) 1173 phy_start(dev->phydev); 1174 1175 /* initialise TX coalesce parameters */ 1176 sxgbe_tx_init_coalesce(priv); 1177 1178 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1179 priv->rx_riwt = SXGBE_MAX_DMA_RIWT; 1180 priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT); 1181 } 1182 1183 priv->tx_lpi_timer = SXGBE_DEFAULT_LPI_TIMER; 1184 priv->eee_enabled = sxgbe_eee_init(priv); 1185 1186 napi_enable(&priv->napi); 1187 netif_start_queue(dev); 1188 1189 return 0; 1190 1191init_error: 1192 free_dma_desc_resources(priv); 1193 if (dev->phydev) 1194 phy_disconnect(dev->phydev); 1195phy_error: 1196 clk_disable_unprepare(priv->sxgbe_clk); 1197 1198 return ret; 1199} 1200 1201/** 1202 * sxgbe_release - close entry point of the driver 1203 * @dev : device pointer. 1204 * Description: 1205 * This is the stop entry point of the driver. 1206 */ 1207static int sxgbe_release(struct net_device *dev) 1208{ 1209 struct sxgbe_priv_data *priv = netdev_priv(dev); 1210 1211 if (priv->eee_enabled) 1212 timer_delete_sync(&priv->eee_ctrl_timer); 1213 1214 /* Stop and disconnect the PHY */ 1215 if (dev->phydev) { 1216 phy_stop(dev->phydev); 1217 phy_disconnect(dev->phydev); 1218 } 1219 1220 netif_tx_stop_all_queues(dev); 1221 1222 napi_disable(&priv->napi); 1223 1224 /* delete TX timers */ 1225 sxgbe_tx_del_timer(priv); 1226 1227 /* Stop TX/RX DMA and clear the descriptors */ 1228 priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES); 1229 priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES); 1230 1231 /* disable MTL queue */ 1232 sxgbe_disable_mtl_engine(priv); 1233 1234 /* Release and free the Rx/Tx resources */ 1235 free_dma_desc_resources(priv); 1236 1237 /* Disable the MAC Rx/Tx */ 1238 priv->hw->mac->enable_tx(priv->ioaddr, false); 1239 priv->hw->mac->enable_rx(priv->ioaddr, false); 1240 1241 clk_disable_unprepare(priv->sxgbe_clk); 1242 1243 return 0; 1244} 1245/* Prepare first Tx descriptor for doing TSO operation */ 1246static void sxgbe_tso_prepare(struct sxgbe_priv_data *priv, 1247 struct sxgbe_tx_norm_desc *first_desc, 1248 struct sk_buff *skb) 1249{ 1250 unsigned int total_hdr_len, tcp_hdr_len; 1251 1252 /* Write first Tx descriptor with appropriate value */ 1253 tcp_hdr_len = tcp_hdrlen(skb); 1254 total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len; 1255 1256 first_desc->tdes01 = dma_map_single(priv->device, skb->data, 1257 total_hdr_len, DMA_TO_DEVICE); 1258 if (dma_mapping_error(priv->device, first_desc->tdes01)) 1259 pr_err("%s: TX dma mapping failed!!\n", __func__); 1260 1261 first_desc->tdes23.tx_rd_des23.first_desc = 1; 1262 priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len, 1263 tcp_hdr_len, 1264 skb->len - total_hdr_len); 1265} 1266 1267/** 1268 * sxgbe_xmit: Tx entry point of the driver 1269 * @skb : the socket buffer 1270 * @dev : device pointer 1271 * Description : this is the tx entry point of the driver. 1272 * It programs the chain or the ring and supports oversized frames 1273 * and SG feature. 1274 */ 1275static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev) 1276{ 1277 unsigned int entry, frag_num; 1278 int cksum_flag = 0; 1279 struct netdev_queue *dev_txq; 1280 unsigned txq_index = skb_get_queue_mapping(skb); 1281 struct sxgbe_priv_data *priv = netdev_priv(dev); 1282 unsigned int tx_rsize = priv->dma_tx_size; 1283 struct sxgbe_tx_queue *tqueue = priv->txq[txq_index]; 1284 struct sxgbe_tx_norm_desc *tx_desc, *first_desc; 1285 struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL; 1286 int nr_frags = skb_shinfo(skb)->nr_frags; 1287 int no_pagedlen = skb_headlen(skb); 1288 int is_jumbo = 0; 1289 u16 cur_mss = skb_shinfo(skb)->gso_size; 1290 u32 ctxt_desc_req = 0; 1291 1292 /* get the TX queue handle */ 1293 dev_txq = netdev_get_tx_queue(dev, txq_index); 1294 1295 if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss)) 1296 ctxt_desc_req = 1; 1297 1298 if (unlikely(skb_vlan_tag_present(skb) || 1299 ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1300 tqueue->hwts_tx_en))) 1301 ctxt_desc_req = 1; 1302 1303 if (priv->tx_path_in_lpi_mode) 1304 sxgbe_disable_eee_mode(priv); 1305 1306 if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) { 1307 if (!netif_tx_queue_stopped(dev_txq)) { 1308 netif_tx_stop_queue(dev_txq); 1309 netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n", 1310 __func__, txq_index); 1311 } 1312 return NETDEV_TX_BUSY; 1313 } 1314 1315 entry = tqueue->cur_tx % tx_rsize; 1316 tx_desc = tqueue->dma_tx + entry; 1317 1318 first_desc = tx_desc; 1319 if (ctxt_desc_req) 1320 ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc; 1321 1322 /* save the skb address */ 1323 tqueue->tx_skbuff[entry] = skb; 1324 1325 if (!is_jumbo) { 1326 if (likely(skb_is_gso(skb))) { 1327 /* TSO support */ 1328 if (unlikely(tqueue->prev_mss != cur_mss)) { 1329 priv->hw->desc->tx_ctxt_desc_set_mss( 1330 ctxt_desc, cur_mss); 1331 priv->hw->desc->tx_ctxt_desc_set_tcmssv( 1332 ctxt_desc); 1333 priv->hw->desc->tx_ctxt_desc_reset_ostc( 1334 ctxt_desc); 1335 priv->hw->desc->tx_ctxt_desc_set_ctxt( 1336 ctxt_desc); 1337 priv->hw->desc->tx_ctxt_desc_set_owner( 1338 ctxt_desc); 1339 1340 entry = (++tqueue->cur_tx) % tx_rsize; 1341 first_desc = tqueue->dma_tx + entry; 1342 1343 tqueue->prev_mss = cur_mss; 1344 } 1345 sxgbe_tso_prepare(priv, first_desc, skb); 1346 } else { 1347 tx_desc->tdes01 = dma_map_single(priv->device, 1348 skb->data, no_pagedlen, DMA_TO_DEVICE); 1349 if (dma_mapping_error(priv->device, tx_desc->tdes01)) 1350 netdev_err(dev, "%s: TX dma mapping failed!!\n", 1351 __func__); 1352 1353 priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen, 1354 no_pagedlen, cksum_flag); 1355 } 1356 } 1357 1358 for (frag_num = 0; frag_num < nr_frags; frag_num++) { 1359 const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num]; 1360 int len = skb_frag_size(frag); 1361 1362 entry = (++tqueue->cur_tx) % tx_rsize; 1363 tx_desc = tqueue->dma_tx + entry; 1364 tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len, 1365 DMA_TO_DEVICE); 1366 1367 tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01; 1368 tqueue->tx_skbuff[entry] = NULL; 1369 1370 /* prepare the descriptor */ 1371 priv->hw->desc->prepare_tx_desc(tx_desc, 0, len, 1372 len, cksum_flag); 1373 /* memory barrier to flush descriptor */ 1374 wmb(); 1375 1376 /* set the owner */ 1377 priv->hw->desc->set_tx_owner(tx_desc); 1378 } 1379 1380 /* close the descriptors */ 1381 priv->hw->desc->close_tx_desc(tx_desc); 1382 1383 /* memory barrier to flush descriptor */ 1384 wmb(); 1385 1386 tqueue->tx_count_frames += nr_frags + 1; 1387 if (tqueue->tx_count_frames > tqueue->tx_coal_frames) { 1388 priv->hw->desc->clear_tx_ic(tx_desc); 1389 priv->xstats.tx_reset_ic_bit++; 1390 mod_timer(&tqueue->txtimer, 1391 SXGBE_COAL_TIMER(tqueue->tx_coal_timer)); 1392 } else { 1393 tqueue->tx_count_frames = 0; 1394 } 1395 1396 /* set owner for first desc */ 1397 priv->hw->desc->set_tx_owner(first_desc); 1398 1399 /* memory barrier to flush descriptor */ 1400 wmb(); 1401 1402 tqueue->cur_tx++; 1403 1404 /* display current ring */ 1405 netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n", 1406 __func__, tqueue->cur_tx % tx_rsize, 1407 tqueue->dirty_tx % tx_rsize, entry, 1408 first_desc, nr_frags); 1409 1410 if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) { 1411 netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n", 1412 __func__); 1413 netif_tx_stop_queue(dev_txq); 1414 } 1415 1416 dev->stats.tx_bytes += skb->len; 1417 1418 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1419 tqueue->hwts_tx_en)) { 1420 /* declare that device is doing timestamping */ 1421 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1422 priv->hw->desc->tx_enable_tstamp(first_desc); 1423 } 1424 1425 skb_tx_timestamp(skb); 1426 1427 priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index); 1428 1429 return NETDEV_TX_OK; 1430} 1431 1432/** 1433 * sxgbe_rx_refill: refill used skb preallocated buffers 1434 * @priv: driver private structure 1435 * Description : this is to reallocate the skb for the reception process 1436 * that is based on zero-copy. 1437 */ 1438static void sxgbe_rx_refill(struct sxgbe_priv_data *priv) 1439{ 1440 unsigned int rxsize = priv->dma_rx_size; 1441 int bfsize = priv->dma_buf_sz; 1442 u8 qnum = priv->cur_rx_qnum; 1443 1444 for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0; 1445 priv->rxq[qnum]->dirty_rx++) { 1446 unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize; 1447 struct sxgbe_rx_norm_desc *p; 1448 1449 p = priv->rxq[qnum]->dma_rx + entry; 1450 1451 if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) { 1452 struct sk_buff *skb; 1453 1454 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 1455 1456 if (unlikely(skb == NULL)) 1457 break; 1458 1459 priv->rxq[qnum]->rx_skbuff[entry] = skb; 1460 priv->rxq[qnum]->rx_skbuff_dma[entry] = 1461 dma_map_single(priv->device, skb->data, bfsize, 1462 DMA_FROM_DEVICE); 1463 1464 p->rdes23.rx_rd_des23.buf2_addr = 1465 priv->rxq[qnum]->rx_skbuff_dma[entry]; 1466 } 1467 1468 /* Added memory barrier for RX descriptor modification */ 1469 wmb(); 1470 priv->hw->desc->set_rx_owner(p); 1471 priv->hw->desc->set_rx_int_on_com(p); 1472 /* Added memory barrier for RX descriptor modification */ 1473 wmb(); 1474 } 1475} 1476 1477/** 1478 * sxgbe_rx: receive the frames from the remote host 1479 * @priv: driver private structure 1480 * @limit: napi bugget. 1481 * Description : this the function called by the napi poll method. 1482 * It gets all the frames inside the ring. 1483 */ 1484static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit) 1485{ 1486 u8 qnum = priv->cur_rx_qnum; 1487 unsigned int rxsize = priv->dma_rx_size; 1488 unsigned int entry = priv->rxq[qnum]->cur_rx; 1489 unsigned int next_entry = 0; 1490 unsigned int count = 0; 1491 int checksum; 1492 int status; 1493 1494 while (count < limit) { 1495 struct sxgbe_rx_norm_desc *p; 1496 struct sk_buff *skb; 1497 int frame_len; 1498 1499 p = priv->rxq[qnum]->dma_rx + entry; 1500 1501 if (priv->hw->desc->get_rx_owner(p)) 1502 break; 1503 1504 count++; 1505 1506 next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize; 1507 prefetch(priv->rxq[qnum]->dma_rx + next_entry); 1508 1509 /* Read the status of the incoming frame and also get checksum 1510 * value based on whether it is enabled in SXGBE hardware or 1511 * not. 1512 */ 1513 status = priv->hw->desc->rx_wbstatus(p, &priv->xstats, 1514 &checksum); 1515 if (unlikely(status < 0)) { 1516 entry = next_entry; 1517 continue; 1518 } 1519 if (unlikely(!priv->rxcsum_insertion)) 1520 checksum = CHECKSUM_NONE; 1521 1522 skb = priv->rxq[qnum]->rx_skbuff[entry]; 1523 1524 if (unlikely(!skb)) { 1525 netdev_err(priv->dev, "rx descriptor is not consistent\n"); 1526 break; 1527 } 1528 1529 prefetch(skb->data - NET_IP_ALIGN); 1530 priv->rxq[qnum]->rx_skbuff[entry] = NULL; 1531 1532 frame_len = priv->hw->desc->get_rx_frame_len(p); 1533 1534 skb_put(skb, frame_len); 1535 1536 skb->ip_summed = checksum; 1537 if (checksum == CHECKSUM_NONE) 1538 netif_receive_skb(skb); 1539 else 1540 napi_gro_receive(&priv->napi, skb); 1541 1542 entry = next_entry; 1543 } 1544 1545 sxgbe_rx_refill(priv); 1546 1547 return count; 1548} 1549 1550/** 1551 * sxgbe_poll - sxgbe poll method (NAPI) 1552 * @napi : pointer to the napi structure. 1553 * @budget : maximum number of packets that the current CPU can receive from 1554 * all interfaces. 1555 * Description : 1556 * To look at the incoming frames and clear the tx resources. 1557 */ 1558static int sxgbe_poll(struct napi_struct *napi, int budget) 1559{ 1560 struct sxgbe_priv_data *priv = container_of(napi, 1561 struct sxgbe_priv_data, napi); 1562 int work_done = 0; 1563 u8 qnum = priv->cur_rx_qnum; 1564 1565 priv->xstats.napi_poll++; 1566 /* first, clean the tx queues */ 1567 sxgbe_tx_all_clean(priv); 1568 1569 work_done = sxgbe_rx(priv, budget); 1570 if (work_done < budget) { 1571 napi_complete_done(napi, work_done); 1572 priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum); 1573 } 1574 1575 return work_done; 1576} 1577 1578/** 1579 * sxgbe_tx_timeout 1580 * @dev : Pointer to net device structure 1581 * @txqueue: index of the hanging queue 1582 * Description: this function is called when a packet transmission fails to 1583 * complete within a reasonable time. The driver will mark the error in the 1584 * netdev structure and arrange for the device to be reset to a sane state 1585 * in order to transmit a new packet. 1586 */ 1587static void sxgbe_tx_timeout(struct net_device *dev, unsigned int txqueue) 1588{ 1589 struct sxgbe_priv_data *priv = netdev_priv(dev); 1590 1591 sxgbe_reset_all_tx_queues(priv); 1592} 1593 1594/** 1595 * sxgbe_common_interrupt - main ISR 1596 * @irq: interrupt number. 1597 * @dev_id: to pass the net device pointer. 1598 * Description: this is the main driver interrupt service routine. 1599 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI 1600 * interrupts. 1601 */ 1602static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id) 1603{ 1604 struct net_device *netdev = (struct net_device *)dev_id; 1605 struct sxgbe_priv_data *priv = netdev_priv(netdev); 1606 int status; 1607 1608 status = priv->hw->mac->host_irq_status(priv->ioaddr, &priv->xstats); 1609 /* For LPI we need to save the tx status */ 1610 if (status & TX_ENTRY_LPI_MODE) { 1611 priv->xstats.tx_lpi_entry_n++; 1612 priv->tx_path_in_lpi_mode = true; 1613 } 1614 if (status & TX_EXIT_LPI_MODE) { 1615 priv->xstats.tx_lpi_exit_n++; 1616 priv->tx_path_in_lpi_mode = false; 1617 } 1618 if (status & RX_ENTRY_LPI_MODE) 1619 priv->xstats.rx_lpi_entry_n++; 1620 if (status & RX_EXIT_LPI_MODE) 1621 priv->xstats.rx_lpi_exit_n++; 1622 1623 return IRQ_HANDLED; 1624} 1625 1626/** 1627 * sxgbe_tx_interrupt - TX DMA ISR 1628 * @irq: interrupt number. 1629 * @dev_id: to pass the net device pointer. 1630 * Description: this is the tx dma interrupt service routine. 1631 */ 1632static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id) 1633{ 1634 int status; 1635 struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id; 1636 struct sxgbe_priv_data *priv = txq->priv_ptr; 1637 1638 /* get the channel status */ 1639 status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no, 1640 &priv->xstats); 1641 /* check for normal path */ 1642 if (likely((status & handle_tx))) 1643 napi_schedule(&priv->napi); 1644 1645 /* check for unrecoverable error */ 1646 if (unlikely((status & tx_hard_error))) 1647 sxgbe_restart_tx_queue(priv, txq->queue_no); 1648 1649 /* check for TC configuration change */ 1650 if (unlikely((status & tx_bump_tc) && 1651 (priv->tx_tc != SXGBE_MTL_SFMODE) && 1652 (priv->tx_tc < 512))) { 1653 /* step of TX TC is 32 till 128, otherwise 64 */ 1654 priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64; 1655 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, 1656 txq->queue_no, priv->tx_tc); 1657 priv->xstats.tx_threshold = priv->tx_tc; 1658 } 1659 1660 return IRQ_HANDLED; 1661} 1662 1663/** 1664 * sxgbe_rx_interrupt - RX DMA ISR 1665 * @irq: interrupt number. 1666 * @dev_id: to pass the net device pointer. 1667 * Description: this is the rx dma interrupt service routine. 1668 */ 1669static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id) 1670{ 1671 int status; 1672 struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id; 1673 struct sxgbe_priv_data *priv = rxq->priv_ptr; 1674 1675 /* get the channel status */ 1676 status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no, 1677 &priv->xstats); 1678 1679 if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) { 1680 priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no); 1681 __napi_schedule(&priv->napi); 1682 } 1683 1684 /* check for TC configuration change */ 1685 if (unlikely((status & rx_bump_tc) && 1686 (priv->rx_tc != SXGBE_MTL_SFMODE) && 1687 (priv->rx_tc < 128))) { 1688 /* step of TC is 32 */ 1689 priv->rx_tc += 32; 1690 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, 1691 rxq->queue_no, priv->rx_tc); 1692 priv->xstats.rx_threshold = priv->rx_tc; 1693 } 1694 1695 return IRQ_HANDLED; 1696} 1697 1698static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi) 1699{ 1700 u64 val = readl(ioaddr + reg_lo); 1701 1702 val |= ((u64)readl(ioaddr + reg_hi)) << 32; 1703 1704 return val; 1705} 1706 1707 1708/* sxgbe_get_stats64 - entry point to see statistical information of device 1709 * @dev : device pointer. 1710 * @stats : pointer to hold all the statistical information of device. 1711 * Description: 1712 * This function is a driver entry point whenever ifconfig command gets 1713 * executed to see device statistics. Statistics are number of 1714 * bytes sent or received, errors occurred etc. 1715 */ 1716static void sxgbe_get_stats64(struct net_device *dev, 1717 struct rtnl_link_stats64 *stats) 1718{ 1719 struct sxgbe_priv_data *priv = netdev_priv(dev); 1720 void __iomem *ioaddr = priv->ioaddr; 1721 u64 count; 1722 1723 spin_lock(&priv->stats_lock); 1724 /* Freeze the counter registers before reading value otherwise it may 1725 * get updated by hardware while we are reading them 1726 */ 1727 writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG); 1728 1729 stats->rx_bytes = sxgbe_get_stat64(ioaddr, 1730 SXGBE_MMC_RXOCTETLO_GCNT_REG, 1731 SXGBE_MMC_RXOCTETHI_GCNT_REG); 1732 1733 stats->rx_packets = sxgbe_get_stat64(ioaddr, 1734 SXGBE_MMC_RXFRAMELO_GBCNT_REG, 1735 SXGBE_MMC_RXFRAMEHI_GBCNT_REG); 1736 1737 stats->multicast = sxgbe_get_stat64(ioaddr, 1738 SXGBE_MMC_RXMULTILO_GCNT_REG, 1739 SXGBE_MMC_RXMULTIHI_GCNT_REG); 1740 1741 stats->rx_crc_errors = sxgbe_get_stat64(ioaddr, 1742 SXGBE_MMC_RXCRCERRLO_REG, 1743 SXGBE_MMC_RXCRCERRHI_REG); 1744 1745 stats->rx_length_errors = sxgbe_get_stat64(ioaddr, 1746 SXGBE_MMC_RXLENERRLO_REG, 1747 SXGBE_MMC_RXLENERRHI_REG); 1748 1749 stats->rx_missed_errors = sxgbe_get_stat64(ioaddr, 1750 SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG, 1751 SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG); 1752 1753 stats->tx_bytes = sxgbe_get_stat64(ioaddr, 1754 SXGBE_MMC_TXOCTETLO_GCNT_REG, 1755 SXGBE_MMC_TXOCTETHI_GCNT_REG); 1756 1757 count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG, 1758 SXGBE_MMC_TXFRAMEHI_GBCNT_REG); 1759 1760 stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG, 1761 SXGBE_MMC_TXFRAMEHI_GCNT_REG); 1762 stats->tx_errors = count - stats->tx_errors; 1763 stats->tx_packets = count; 1764 stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG, 1765 SXGBE_MMC_TXUFLWHI_GBCNT_REG); 1766 writel(0, ioaddr + SXGBE_MMC_CTL_REG); 1767 spin_unlock(&priv->stats_lock); 1768} 1769 1770/* sxgbe_set_features - entry point to set offload features of the device. 1771 * @dev : device pointer. 1772 * @features : features which are required to be set. 1773 * Description: 1774 * This function is a driver entry point and called by Linux kernel whenever 1775 * any device features are set or reset by user. 1776 * Return value: 1777 * This function returns 0 after setting or resetting device features. 1778 */ 1779static int sxgbe_set_features(struct net_device *dev, 1780 netdev_features_t features) 1781{ 1782 struct sxgbe_priv_data *priv = netdev_priv(dev); 1783 netdev_features_t changed = dev->features ^ features; 1784 1785 if (changed & NETIF_F_RXCSUM) { 1786 if (features & NETIF_F_RXCSUM) { 1787 priv->hw->mac->enable_rx_csum(priv->ioaddr); 1788 priv->rxcsum_insertion = true; 1789 } else { 1790 priv->hw->mac->disable_rx_csum(priv->ioaddr); 1791 priv->rxcsum_insertion = false; 1792 } 1793 } 1794 1795 return 0; 1796} 1797 1798/* sxgbe_change_mtu - entry point to change MTU size for the device. 1799 * @dev : device pointer. 1800 * @new_mtu : the new MTU size for the device. 1801 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 1802 * to drive packet transmission. Ethernet has an MTU of 1500 octets 1803 * (ETH_DATA_LEN). This value can be changed with ifconfig. 1804 * Return value: 1805 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1806 * file on failure. 1807 */ 1808static int sxgbe_change_mtu(struct net_device *dev, int new_mtu) 1809{ 1810 WRITE_ONCE(dev->mtu, new_mtu); 1811 1812 if (!netif_running(dev)) 1813 return 0; 1814 1815 /* Recevice ring buffer size is needed to be set based on MTU. If MTU is 1816 * changed then reinitilisation of the receive ring buffers need to be 1817 * done. Hence bring interface down and bring interface back up 1818 */ 1819 sxgbe_release(dev); 1820 return sxgbe_open(dev); 1821} 1822 1823static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr, 1824 unsigned int reg_n) 1825{ 1826 unsigned long data; 1827 1828 data = (addr[5] << 8) | addr[4]; 1829 /* For MAC Addr registers se have to set the Address Enable (AE) 1830 * bit that has no effect on the High Reg 0 where the bit 31 (MO) 1831 * is RO. 1832 */ 1833 writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n)); 1834 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 1835 writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n)); 1836} 1837 1838/** 1839 * sxgbe_set_rx_mode - entry point for setting different receive mode of 1840 * a device. unicast, multicast addressing 1841 * @dev : pointer to the device structure 1842 * Description: 1843 * This function is a driver entry point which gets called by the kernel 1844 * whenever different receive mode like unicast, multicast and promiscuous 1845 * must be enabled/disabled. 1846 * Return value: 1847 * void. 1848 */ 1849static void sxgbe_set_rx_mode(struct net_device *dev) 1850{ 1851 struct sxgbe_priv_data *priv = netdev_priv(dev); 1852 void __iomem *ioaddr = (void __iomem *)priv->ioaddr; 1853 unsigned int value = 0; 1854 u32 mc_filter[2]; 1855 struct netdev_hw_addr *ha; 1856 int reg = 1; 1857 1858 netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n", 1859 __func__, netdev_mc_count(dev), netdev_uc_count(dev)); 1860 1861 if (dev->flags & IFF_PROMISC) { 1862 value = SXGBE_FRAME_FILTER_PR; 1863 1864 } else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) || 1865 (dev->flags & IFF_ALLMULTI)) { 1866 value = SXGBE_FRAME_FILTER_PM; /* pass all multi */ 1867 writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH); 1868 writel(0xffffffff, ioaddr + SXGBE_HASH_LOW); 1869 1870 } else if (!netdev_mc_empty(dev)) { 1871 /* Hash filter for multicast */ 1872 value = SXGBE_FRAME_FILTER_HMC; 1873 1874 memset(mc_filter, 0, sizeof(mc_filter)); 1875 netdev_for_each_mc_addr(ha, dev) { 1876 /* The upper 6 bits of the calculated CRC are used to 1877 * index the contens of the hash table 1878 */ 1879 int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26; 1880 1881 /* The most significant bit determines the register to 1882 * use (H/L) while the other 5 bits determine the bit 1883 * within the register. 1884 */ 1885 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1886 } 1887 writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW); 1888 writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH); 1889 } 1890 1891 /* Handle multiple unicast addresses (perfect filtering) */ 1892 if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES) 1893 /* Switch to promiscuous mode if more than 16 addrs 1894 * are required 1895 */ 1896 value |= SXGBE_FRAME_FILTER_PR; 1897 else { 1898 netdev_for_each_uc_addr(ha, dev) { 1899 sxgbe_set_umac_addr(ioaddr, ha->addr, reg); 1900 reg++; 1901 } 1902 } 1903#ifdef FRAME_FILTER_DEBUG 1904 /* Enable Receive all mode (to debug filtering_fail errors) */ 1905 value |= SXGBE_FRAME_FILTER_RA; 1906#endif 1907 writel(value, ioaddr + SXGBE_FRAME_FILTER); 1908 1909 netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n", 1910 readl(ioaddr + SXGBE_FRAME_FILTER), 1911 readl(ioaddr + SXGBE_HASH_HIGH), 1912 readl(ioaddr + SXGBE_HASH_LOW)); 1913} 1914 1915#ifdef CONFIG_NET_POLL_CONTROLLER 1916/** 1917 * sxgbe_poll_controller - entry point for polling receive by device 1918 * @dev : pointer to the device structure 1919 * Description: 1920 * This function is used by NETCONSOLE and other diagnostic tools 1921 * to allow network I/O with interrupts disabled. 1922 * Return value: 1923 * Void. 1924 */ 1925static void sxgbe_poll_controller(struct net_device *dev) 1926{ 1927 struct sxgbe_priv_data *priv = netdev_priv(dev); 1928 1929 disable_irq(priv->irq); 1930 sxgbe_rx_interrupt(priv->irq, dev); 1931 enable_irq(priv->irq); 1932} 1933#endif 1934 1935/* sxgbe_ioctl - Entry point for the Ioctl 1936 * @dev: Device pointer. 1937 * @rq: An IOCTL specefic structure, that can contain a pointer to 1938 * a proprietary structure used to pass information to the driver. 1939 * @cmd: IOCTL command 1940 * Description: 1941 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 1942 */ 1943static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1944{ 1945 int ret = -EOPNOTSUPP; 1946 1947 if (!netif_running(dev)) 1948 return -EINVAL; 1949 1950 switch (cmd) { 1951 case SIOCGMIIPHY: 1952 case SIOCGMIIREG: 1953 case SIOCSMIIREG: 1954 ret = phy_do_ioctl(dev, rq, cmd); 1955 break; 1956 default: 1957 break; 1958 } 1959 1960 return ret; 1961} 1962 1963static const struct net_device_ops sxgbe_netdev_ops = { 1964 .ndo_open = sxgbe_open, 1965 .ndo_start_xmit = sxgbe_xmit, 1966 .ndo_stop = sxgbe_release, 1967 .ndo_get_stats64 = sxgbe_get_stats64, 1968 .ndo_change_mtu = sxgbe_change_mtu, 1969 .ndo_set_features = sxgbe_set_features, 1970 .ndo_set_rx_mode = sxgbe_set_rx_mode, 1971 .ndo_tx_timeout = sxgbe_tx_timeout, 1972 .ndo_eth_ioctl = sxgbe_ioctl, 1973#ifdef CONFIG_NET_POLL_CONTROLLER 1974 .ndo_poll_controller = sxgbe_poll_controller, 1975#endif 1976 .ndo_set_mac_address = eth_mac_addr, 1977}; 1978 1979/* Get the hardware ops */ 1980static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr) 1981{ 1982 ops_ptr->mac = sxgbe_get_core_ops(); 1983 ops_ptr->desc = sxgbe_get_desc_ops(); 1984 ops_ptr->dma = sxgbe_get_dma_ops(); 1985 ops_ptr->mtl = sxgbe_get_mtl_ops(); 1986 1987 /* set the MDIO communication Address/Data regisers */ 1988 ops_ptr->mii.addr = SXGBE_MDIO_SCMD_ADD_REG; 1989 ops_ptr->mii.data = SXGBE_MDIO_SCMD_DATA_REG; 1990 1991 /* Assigning the default link settings 1992 * no SXGBE defined default values to be set in registers, 1993 * so assigning as 0 for port and duplex 1994 */ 1995 ops_ptr->link.port = 0; 1996 ops_ptr->link.duplex = 0; 1997 ops_ptr->link.speed = SXGBE_SPEED_10G; 1998} 1999 2000/** 2001 * sxgbe_hw_init - Init the GMAC device 2002 * @priv: driver private structure 2003 * Description: this function checks the HW capability 2004 * (if supported) and sets the driver's features. 2005 */ 2006static int sxgbe_hw_init(struct sxgbe_priv_data * const priv) 2007{ 2008 u32 ctrl_ids; 2009 2010 priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL); 2011 if(!priv->hw) 2012 return -ENOMEM; 2013 2014 /* get the hardware ops */ 2015 sxgbe_get_ops(priv->hw); 2016 2017 /* get the controller id */ 2018 ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr); 2019 priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16; 2020 priv->hw->ctrl_id = (ctrl_ids & 0x000000ff); 2021 pr_info("user ID: 0x%x, Controller ID: 0x%x\n", 2022 priv->hw->ctrl_uid, priv->hw->ctrl_id); 2023 2024 /* get the H/W features */ 2025 if (!sxgbe_get_hw_features(priv)) 2026 pr_info("Hardware features not found\n"); 2027 2028 if (priv->hw_cap.tx_csum_offload) 2029 pr_info("TX Checksum offload supported\n"); 2030 2031 if (priv->hw_cap.rx_csum_offload) 2032 pr_info("RX Checksum offload supported\n"); 2033 2034 return 0; 2035} 2036 2037static int sxgbe_sw_reset(void __iomem *addr) 2038{ 2039 int retry_count = 10; 2040 2041 writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG); 2042 while (retry_count--) { 2043 if (!(readl(addr + SXGBE_DMA_MODE_REG) & 2044 SXGBE_DMA_SOFT_RESET)) 2045 break; 2046 mdelay(10); 2047 } 2048 2049 if (retry_count < 0) 2050 return -EBUSY; 2051 2052 return 0; 2053} 2054 2055/** 2056 * sxgbe_drv_probe 2057 * @device: device pointer 2058 * @plat_dat: platform data pointer 2059 * @addr: iobase memory address 2060 * Description: this is the main probe function used to 2061 * call the alloc_etherdev, allocate the priv structure. 2062 */ 2063struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device, 2064 struct sxgbe_plat_data *plat_dat, 2065 void __iomem *addr) 2066{ 2067 struct sxgbe_priv_data *priv; 2068 struct net_device *ndev; 2069 int ret; 2070 u8 queue_num; 2071 2072 ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data), 2073 SXGBE_TX_QUEUES, SXGBE_RX_QUEUES); 2074 if (!ndev) 2075 return NULL; 2076 2077 SET_NETDEV_DEV(ndev, device); 2078 2079 priv = netdev_priv(ndev); 2080 priv->device = device; 2081 priv->dev = ndev; 2082 2083 sxgbe_set_ethtool_ops(ndev); 2084 priv->plat = plat_dat; 2085 priv->ioaddr = addr; 2086 2087 ret = sxgbe_sw_reset(priv->ioaddr); 2088 if (ret) 2089 goto error_free_netdev; 2090 2091 /* Verify driver arguments */ 2092 sxgbe_verify_args(); 2093 2094 /* Init MAC and get the capabilities */ 2095 ret = sxgbe_hw_init(priv); 2096 if (ret) 2097 goto error_free_netdev; 2098 2099 /* allocate memory resources for Descriptor rings */ 2100 ret = txring_mem_alloc(priv); 2101 if (ret) 2102 goto error_free_hw; 2103 2104 ret = rxring_mem_alloc(priv); 2105 if (ret) 2106 goto error_free_hw; 2107 2108 ndev->netdev_ops = &sxgbe_netdev_ops; 2109 2110 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2111 NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 | 2112 NETIF_F_GRO; 2113 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2114 ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO); 2115 2116 /* assign filtering support */ 2117 ndev->priv_flags |= IFF_UNICAST_FLT; 2118 2119 /* MTU range: 68 - 9000 */ 2120 ndev->min_mtu = MIN_MTU; 2121 ndev->max_mtu = MAX_MTU; 2122 2123 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2124 2125 /* Enable TCP segmentation offload for all DMA channels */ 2126 if (priv->hw_cap.tcpseg_offload) { 2127 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) { 2128 priv->hw->dma->enable_tso(priv->ioaddr, queue_num); 2129 } 2130 } 2131 2132 /* Enable Rx checksum offload */ 2133 if (priv->hw_cap.rx_csum_offload) { 2134 priv->hw->mac->enable_rx_csum(priv->ioaddr); 2135 priv->rxcsum_insertion = true; 2136 } 2137 2138 /* Initialise pause frame settings */ 2139 priv->rx_pause = 1; 2140 priv->tx_pause = 1; 2141 2142 /* Rx Watchdog is available, enable depend on platform data */ 2143 if (!priv->plat->riwt_off) { 2144 priv->use_riwt = 1; 2145 pr_info("Enable RX Mitigation via HW Watchdog Timer\n"); 2146 } 2147 2148 netif_napi_add(ndev, &priv->napi, sxgbe_poll); 2149 2150 spin_lock_init(&priv->stats_lock); 2151 2152 priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME); 2153 if (IS_ERR(priv->sxgbe_clk)) { 2154 netdev_warn(ndev, "%s: warning: cannot get CSR clock\n", 2155 __func__); 2156 goto error_napi_del; 2157 } 2158 2159 /* If a specific clk_csr value is passed from the platform 2160 * this means that the CSR Clock Range selection cannot be 2161 * changed at run-time and it is fixed. Viceversa the driver'll try to 2162 * set the MDC clock dynamically according to the csr actual 2163 * clock input. 2164 */ 2165 if (!priv->plat->clk_csr) 2166 sxgbe_clk_csr_set(priv); 2167 else 2168 priv->clk_csr = priv->plat->clk_csr; 2169 2170 /* MDIO bus Registration */ 2171 ret = sxgbe_mdio_register(ndev); 2172 if (ret < 0) { 2173 netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n", 2174 __func__, priv->plat->bus_id); 2175 goto error_clk_put; 2176 } 2177 2178 ret = register_netdev(ndev); 2179 if (ret) { 2180 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2181 goto error_mdio_unregister; 2182 } 2183 2184 sxgbe_check_ether_addr(priv); 2185 2186 return priv; 2187 2188error_mdio_unregister: 2189 sxgbe_mdio_unregister(ndev); 2190error_clk_put: 2191 clk_put(priv->sxgbe_clk); 2192error_napi_del: 2193 netif_napi_del(&priv->napi); 2194error_free_hw: 2195 kfree(priv->hw); 2196error_free_netdev: 2197 free_netdev(ndev); 2198 2199 return NULL; 2200} 2201 2202/** 2203 * sxgbe_drv_remove 2204 * @ndev: net device pointer 2205 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2206 * changes the link status, releases the DMA descriptor rings. 2207 */ 2208void sxgbe_drv_remove(struct net_device *ndev) 2209{ 2210 struct sxgbe_priv_data *priv = netdev_priv(ndev); 2211 u8 queue_num; 2212 2213 netdev_info(ndev, "%s: removing driver\n", __func__); 2214 2215 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) { 2216 priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num); 2217 } 2218 2219 priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES); 2220 priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES); 2221 2222 priv->hw->mac->enable_tx(priv->ioaddr, false); 2223 priv->hw->mac->enable_rx(priv->ioaddr, false); 2224 2225 unregister_netdev(ndev); 2226 2227 sxgbe_mdio_unregister(ndev); 2228 2229 clk_put(priv->sxgbe_clk); 2230 2231 netif_napi_del(&priv->napi); 2232 2233 kfree(priv->hw); 2234 2235 free_netdev(ndev); 2236} 2237 2238#ifdef CONFIG_PM 2239int sxgbe_suspend(struct net_device *ndev) 2240{ 2241 return 0; 2242} 2243 2244int sxgbe_resume(struct net_device *ndev) 2245{ 2246 return 0; 2247} 2248 2249int sxgbe_freeze(struct net_device *ndev) 2250{ 2251 return -ENOSYS; 2252} 2253 2254int sxgbe_restore(struct net_device *ndev) 2255{ 2256 return -ENOSYS; 2257} 2258#endif /* CONFIG_PM */ 2259 2260/* Driver is configured as Platform driver */ 2261static int __init sxgbe_init(void) 2262{ 2263 int ret; 2264 2265 ret = sxgbe_register_platform(); 2266 if (ret) 2267 goto err; 2268 return 0; 2269err: 2270 pr_err("driver registration failed\n"); 2271 return ret; 2272} 2273 2274static void __exit sxgbe_exit(void) 2275{ 2276 sxgbe_unregister_platform(); 2277} 2278 2279module_init(sxgbe_init); 2280module_exit(sxgbe_exit); 2281 2282#ifndef MODULE 2283static int __init sxgbe_cmdline_opt(char *str) 2284{ 2285 char *opt; 2286 2287 if (!str || !*str) 2288 return 1; 2289 while ((opt = strsep(&str, ",")) != NULL) { 2290 if (!strncmp(opt, "eee_timer:", 10)) { 2291 if (kstrtoint(opt + 10, 0, &eee_timer)) 2292 goto err; 2293 } 2294 } 2295 return 1; 2296 2297err: 2298 pr_err("%s: ERROR broken module parameter conversion\n", __func__); 2299 return 1; 2300} 2301 2302__setup("sxgbeeth=", sxgbe_cmdline_opt); 2303#endif /* MODULE */ 2304 2305 2306 2307MODULE_DESCRIPTION("Samsung 10G/2.5G/1G Ethernet PLATFORM driver"); 2308 2309MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 2310MODULE_PARM_DESC(eee_timer, "EEE-LPI Default LS timer value"); 2311 2312MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>"); 2313MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>"); 2314MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>"); 2315MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>"); 2316 2317MODULE_LICENSE("GPL");
~/
Read-only file preview.