rswitch.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Renesas Ethernet Switch device driver
   3 *
   4 * Copyright (C) 2022-2025 Renesas Electronics Corporation
   5 */
   6
   7#ifndef __RSWITCH_H__
   8#define __RSWITCH_H__
   9
  10#include <linux/platform_device.h>
  11#include <linux/phy.h>
  12
  13#include "rcar_gen4_ptp.h"
  14
  15#define RSWITCH_MAX_NUM_QUEUES	128
  16
  17#define RSWITCH_NUM_AGENTS	5
  18#define RSWITCH_NUM_PORTS	3
  19
  20#define rswitch_for_all_ports(_priv, _rdev)			\
  21	list_for_each_entry(_rdev, &_priv->port_list, list)
  22
  23#define rswitch_for_each_enabled_port(priv, i)		\
  24	for (i = 0; i < RSWITCH_NUM_PORTS; i++)		\
  25		if (priv->rdev[i]->disabled)		\
  26			continue;			\
  27		else
  28
  29#define rswitch_for_each_enabled_port_continue_reverse(priv, i)	\
  30	for (; i-- > 0; )					\
  31		if (priv->rdev[i]->disabled)			\
  32			continue;				\
  33		else
  34
  35#define TX_RING_SIZE		1024
  36#define RX_RING_SIZE		4096
  37#define TS_RING_SIZE		(TX_RING_SIZE * RSWITCH_NUM_PORTS)
  38
  39#define RSWITCH_MAX_MTU		9600
  40#define RSWITCH_HEADROOM	(NET_SKB_PAD + NET_IP_ALIGN)
  41#define RSWITCH_DESC_BUF_SIZE	2048
  42#define RSWITCH_TAILROOM	SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
  43#define RSWITCH_ALIGN		128
  44#define RSWITCH_BUF_SIZE	(RSWITCH_HEADROOM + RSWITCH_DESC_BUF_SIZE + \
  45				 RSWITCH_TAILROOM + RSWITCH_ALIGN)
  46#define RSWITCH_MAP_BUF_SIZE	(RSWITCH_BUF_SIZE - RSWITCH_HEADROOM)
  47#define RSWITCH_MAX_CTAG_PCP	7
  48
  49#define RSWITCH_TIMEOUT_US	100000
  50
  51#define RSWITCH_TOP_OFFSET	0x00008000
  52#define RSWITCH_COMA_OFFSET	0x00009000
  53#define RSWITCH_ETHA_OFFSET	0x0000a000	/* with RMAC */
  54#define RSWITCH_ETHA_SIZE	0x00002000	/* with RMAC */
  55#define RSWITCH_GWCA0_OFFSET	0x00010000
  56#define RSWITCH_GWCA1_OFFSET	0x00012000
  57
  58/* TODO: hardcoded ETHA/GWCA settings for now */
  59#define GWCA_IRQ_RESOURCE_NAME	"gwca0_rxtx%d"
  60#define GWCA_IRQ_NAME		"rswitch: gwca0_rxtx%d"
  61#define GWCA_NUM_IRQS		8
  62#define GWCA_INDEX		0
  63#define AGENT_INDEX_GWCA	3
  64#define GWCA_IPV_NUM		0
  65#define GWRO			RSWITCH_GWCA0_OFFSET
  66
  67#define GWCA_TS_IRQ_RESOURCE_NAME	"gwca0_rxts0"
  68#define GWCA_TS_IRQ_NAME		"rswitch: gwca0_rxts0"
  69#define GWCA_TS_IRQ_BIT			BIT(0)
  70
  71#define FWRO	0
  72#define TPRO	RSWITCH_TOP_OFFSET
  73#define CARO	RSWITCH_COMA_OFFSET
  74#define TARO	0
  75#define RMRO	0x1000
  76enum rswitch_reg {
  77	FWGC		= FWRO + 0x0000,
  78	FWTTC0		= FWRO + 0x0010,
  79	FWTTC1		= FWRO + 0x0014,
  80	FWLBMC		= FWRO + 0x0018,
  81	FWCEPTC		= FWRO + 0x0020,
  82	FWCEPRC0	= FWRO + 0x0024,
  83	FWCEPRC1	= FWRO + 0x0028,
  84	FWCEPRC2	= FWRO + 0x002c,
  85	FWCLPTC		= FWRO + 0x0030,
  86	FWCLPRC		= FWRO + 0x0034,
  87	FWCMPTC		= FWRO + 0x0040,
  88	FWEMPTC		= FWRO + 0x0044,
  89	FWSDMPTC	= FWRO + 0x0050,
  90	FWSDMPVC	= FWRO + 0x0054,
  91	FWLBWMC0	= FWRO + 0x0080,
  92	FWPC00		= FWRO + 0x0100,
  93	FWPC10		= FWRO + 0x0104,
  94	FWPC20		= FWRO + 0x0108,
  95	FWCTGC00	= FWRO + 0x0400,
  96	FWCTGC10	= FWRO + 0x0404,
  97	FWCTTC00	= FWRO + 0x0408,
  98	FWCTTC10	= FWRO + 0x040c,
  99	FWCTTC200	= FWRO + 0x0410,
 100	FWCTSC00	= FWRO + 0x0420,
 101	FWCTSC10	= FWRO + 0x0424,
 102	FWCTSC20	= FWRO + 0x0428,
 103	FWCTSC30	= FWRO + 0x042c,
 104	FWCTSC40	= FWRO + 0x0430,
 105	FWTWBFC0	= FWRO + 0x1000,
 106	FWTWBFVC0	= FWRO + 0x1004,
 107	FWTHBFC0	= FWRO + 0x1400,
 108	FWTHBFV0C0	= FWRO + 0x1404,
 109	FWTHBFV1C0	= FWRO + 0x1408,
 110	FWFOBFC0	= FWRO + 0x1800,
 111	FWFOBFV0C0	= FWRO + 0x1804,
 112	FWFOBFV1C0	= FWRO + 0x1808,
 113	FWRFC0		= FWRO + 0x1c00,
 114	FWRFVC0		= FWRO + 0x1c04,
 115	FWCFC0		= FWRO + 0x2000,
 116	FWCFMC00	= FWRO + 0x2004,
 117	FWIP4SC		= FWRO + 0x4008,
 118	FWIP6SC		= FWRO + 0x4018,
 119	FWIP6OC		= FWRO + 0x401c,
 120	FWL2SC		= FWRO + 0x4020,
 121	FWSFHEC		= FWRO + 0x4030,
 122	FWSHCR0		= FWRO + 0x4040,
 123	FWSHCR1		= FWRO + 0x4044,
 124	FWSHCR2		= FWRO + 0x4048,
 125	FWSHCR3		= FWRO + 0x404c,
 126	FWSHCR4		= FWRO + 0x4050,
 127	FWSHCR5		= FWRO + 0x4054,
 128	FWSHCR6		= FWRO + 0x4058,
 129	FWSHCR7		= FWRO + 0x405c,
 130	FWSHCR8		= FWRO + 0x4060,
 131	FWSHCR9		= FWRO + 0x4064,
 132	FWSHCR10	= FWRO + 0x4068,
 133	FWSHCR11	= FWRO + 0x406c,
 134	FWSHCR12	= FWRO + 0x4070,
 135	FWSHCR13	= FWRO + 0x4074,
 136	FWSHCRR		= FWRO + 0x4078,
 137	FWLTHHEC	= FWRO + 0x4090,
 138	FWLTHHC		= FWRO + 0x4094,
 139	FWLTHTL0	= FWRO + 0x40a0,
 140	FWLTHTL1	= FWRO + 0x40a4,
 141	FWLTHTL2	= FWRO + 0x40a8,
 142	FWLTHTL3	= FWRO + 0x40ac,
 143	FWLTHTL4	= FWRO + 0x40b0,
 144	FWLTHTL5	= FWRO + 0x40b4,
 145	FWLTHTL6	= FWRO + 0x40b8,
 146	FWLTHTL7	= FWRO + 0x40bc,
 147	FWLTHTL80	= FWRO + 0x40c0,
 148	FWLTHTL9	= FWRO + 0x40d0,
 149	FWLTHTLR	= FWRO + 0x40d4,
 150	FWLTHTIM	= FWRO + 0x40e0,
 151	FWLTHTEM	= FWRO + 0x40e4,
 152	FWLTHTS0	= FWRO + 0x4100,
 153	FWLTHTS1	= FWRO + 0x4104,
 154	FWLTHTS2	= FWRO + 0x4108,
 155	FWLTHTS3	= FWRO + 0x410c,
 156	FWLTHTS4	= FWRO + 0x4110,
 157	FWLTHTSR0	= FWRO + 0x4120,
 158	FWLTHTSR1	= FWRO + 0x4124,
 159	FWLTHTSR2	= FWRO + 0x4128,
 160	FWLTHTSR3	= FWRO + 0x412c,
 161	FWLTHTSR40	= FWRO + 0x4130,
 162	FWLTHTSR5	= FWRO + 0x4140,
 163	FWLTHTR		= FWRO + 0x4150,
 164	FWLTHTRR0	= FWRO + 0x4154,
 165	FWLTHTRR1	= FWRO + 0x4158,
 166	FWLTHTRR2	= FWRO + 0x415c,
 167	FWLTHTRR3	= FWRO + 0x4160,
 168	FWLTHTRR4	= FWRO + 0x4164,
 169	FWLTHTRR5	= FWRO + 0x4168,
 170	FWLTHTRR6	= FWRO + 0x416c,
 171	FWLTHTRR7	= FWRO + 0x4170,
 172	FWLTHTRR8	= FWRO + 0x4174,
 173	FWLTHTRR9	= FWRO + 0x4180,
 174	FWLTHTRR10	= FWRO + 0x4190,
 175	FWIPHEC		= FWRO + 0x4214,
 176	FWIPHC		= FWRO + 0x4218,
 177	FWIPTL0		= FWRO + 0x4220,
 178	FWIPTL1		= FWRO + 0x4224,
 179	FWIPTL2		= FWRO + 0x4228,
 180	FWIPTL3		= FWRO + 0x422c,
 181	FWIPTL4		= FWRO + 0x4230,
 182	FWIPTL5		= FWRO + 0x4234,
 183	FWIPTL6		= FWRO + 0x4238,
 184	FWIPTL7		= FWRO + 0x4240,
 185	FWIPTL8		= FWRO + 0x4250,
 186	FWIPTLR		= FWRO + 0x4254,
 187	FWIPTIM		= FWRO + 0x4260,
 188	FWIPTEM		= FWRO + 0x4264,
 189	FWIPTS0		= FWRO + 0x4270,
 190	FWIPTS1		= FWRO + 0x4274,
 191	FWIPTS2		= FWRO + 0x4278,
 192	FWIPTS3		= FWRO + 0x427c,
 193	FWIPTS4		= FWRO + 0x4280,
 194	FWIPTSR0	= FWRO + 0x4284,
 195	FWIPTSR1	= FWRO + 0x4288,
 196	FWIPTSR2	= FWRO + 0x428c,
 197	FWIPTSR3	= FWRO + 0x4290,
 198	FWIPTSR4	= FWRO + 0x42a0,
 199	FWIPTR		= FWRO + 0x42b0,
 200	FWIPTRR0	= FWRO + 0x42b4,
 201	FWIPTRR1	= FWRO + 0x42b8,
 202	FWIPTRR2	= FWRO + 0x42bc,
 203	FWIPTRR3	= FWRO + 0x42c0,
 204	FWIPTRR4	= FWRO + 0x42c4,
 205	FWIPTRR5	= FWRO + 0x42c8,
 206	FWIPTRR6	= FWRO + 0x42cc,
 207	FWIPTRR7	= FWRO + 0x42d0,
 208	FWIPTRR8	= FWRO + 0x42e0,
 209	FWIPTRR9	= FWRO + 0x42f0,
 210	FWIPHLEC	= FWRO + 0x4300,
 211	FWIPAGUSPC	= FWRO + 0x4500,
 212	FWIPAGC		= FWRO + 0x4504,
 213	FWIPAGM0	= FWRO + 0x4510,
 214	FWIPAGM1	= FWRO + 0x4514,
 215	FWIPAGM2	= FWRO + 0x4518,
 216	FWIPAGM3	= FWRO + 0x451c,
 217	FWIPAGM4	= FWRO + 0x4520,
 218	FWMACHEC	= FWRO + 0x4620,
 219	FWMACHC		= FWRO + 0x4624,
 220	FWMACTL0	= FWRO + 0x4630,
 221	FWMACTL1	= FWRO + 0x4634,
 222	FWMACTL2	= FWRO + 0x4638,
 223	FWMACTL3	= FWRO + 0x463c,
 224	FWMACTL4	= FWRO + 0x4640,
 225	FWMACTL5	= FWRO + 0x4650,
 226	FWMACTLR	= FWRO + 0x4654,
 227	FWMACTIM	= FWRO + 0x4660,
 228	FWMACTEM	= FWRO + 0x4664,
 229	FWMACTS0	= FWRO + 0x4670,
 230	FWMACTS1	= FWRO + 0x4674,
 231	FWMACTSR0	= FWRO + 0x4678,
 232	FWMACTSR1	= FWRO + 0x467c,
 233	FWMACTSR2	= FWRO + 0x4680,
 234	FWMACTSR3	= FWRO + 0x4690,
 235	FWMACTR		= FWRO + 0x46a0,
 236	FWMACTRR0	= FWRO + 0x46a4,
 237	FWMACTRR1	= FWRO + 0x46a8,
 238	FWMACTRR2	= FWRO + 0x46ac,
 239	FWMACTRR3	= FWRO + 0x46b0,
 240	FWMACTRR4	= FWRO + 0x46b4,
 241	FWMACTRR5	= FWRO + 0x46c0,
 242	FWMACTRR6	= FWRO + 0x46d0,
 243	FWMACHLEC	= FWRO + 0x4700,
 244	FWMACAGUSPC	= FWRO + 0x4880,
 245	FWMACAGC	= FWRO + 0x4884,
 246	FWMACAGM0	= FWRO + 0x4888,
 247	FWMACAGM1	= FWRO + 0x488c,
 248	FWVLANTEC	= FWRO + 0x4900,
 249	FWVLANTL0	= FWRO + 0x4910,
 250	FWVLANTL1	= FWRO + 0x4914,
 251	FWVLANTL2	= FWRO + 0x4918,
 252	FWVLANTL3	= FWRO + 0x4920,
 253	FWVLANTL4	= FWRO + 0x4930,
 254	FWVLANTLR	= FWRO + 0x4934,
 255	FWVLANTIM	= FWRO + 0x4940,
 256	FWVLANTEM	= FWRO + 0x4944,
 257	FWVLANTS	= FWRO + 0x4950,
 258	FWVLANTSR0	= FWRO + 0x4954,
 259	FWVLANTSR1	= FWRO + 0x4958,
 260	FWVLANTSR2	= FWRO + 0x4960,
 261	FWVLANTSR3	= FWRO + 0x4970,
 262	FWPBFC0		= FWRO + 0x4a00,
 263	FWPBFCSDC00	= FWRO + 0x4a04,
 264	FWL23URL0	= FWRO + 0x4e00,
 265	FWL23URL1	= FWRO + 0x4e04,
 266	FWL23URL2	= FWRO + 0x4e08,
 267	FWL23URL3	= FWRO + 0x4e0c,
 268	FWL23URLR	= FWRO + 0x4e10,
 269	FWL23UTIM	= FWRO + 0x4e20,
 270	FWL23URR	= FWRO + 0x4e30,
 271	FWL23URRR0	= FWRO + 0x4e34,
 272	FWL23URRR1	= FWRO + 0x4e38,
 273	FWL23URRR2	= FWRO + 0x4e3c,
 274	FWL23URRR3	= FWRO + 0x4e40,
 275	FWL23URMC0	= FWRO + 0x4f00,
 276	FWPMFGC0	= FWRO + 0x5000,
 277	FWPGFC0		= FWRO + 0x5100,
 278	FWPGFIGSC0	= FWRO + 0x5104,
 279	FWPGFENC0	= FWRO + 0x5108,
 280	FWPGFENM0	= FWRO + 0x510c,
 281	FWPGFCSTC00	= FWRO + 0x5110,
 282	FWPGFCSTC10	= FWRO + 0x5114,
 283	FWPGFCSTM00	= FWRO + 0x5118,
 284	FWPGFCSTM10	= FWRO + 0x511c,
 285	FWPGFCTC0	= FWRO + 0x5120,
 286	FWPGFCTM0	= FWRO + 0x5124,
 287	FWPGFHCC0	= FWRO + 0x5128,
 288	FWPGFSM0	= FWRO + 0x512c,
 289	FWPGFGC0	= FWRO + 0x5130,
 290	FWPGFGL0	= FWRO + 0x5500,
 291	FWPGFGL1	= FWRO + 0x5504,
 292	FWPGFGLR	= FWRO + 0x5518,
 293	FWPGFGR		= FWRO + 0x5510,
 294	FWPGFGRR0	= FWRO + 0x5514,
 295	FWPGFGRR1	= FWRO + 0x5518,
 296	FWPGFRIM	= FWRO + 0x5520,
 297	FWPMTRFC0	= FWRO + 0x5600,
 298	FWPMTRCBSC0	= FWRO + 0x5604,
 299	FWPMTRC0RC0	= FWRO + 0x5608,
 300	FWPMTREBSC0	= FWRO + 0x560c,
 301	FWPMTREIRC0	= FWRO + 0x5610,
 302	FWPMTRFM0	= FWRO + 0x5614,
 303	FWFTL0		= FWRO + 0x6000,
 304	FWFTL1		= FWRO + 0x6004,
 305	FWFTLR		= FWRO + 0x6008,
 306	FWFTOC		= FWRO + 0x6010,
 307	FWFTOPC		= FWRO + 0x6014,
 308	FWFTIM		= FWRO + 0x6020,
 309	FWFTR		= FWRO + 0x6030,
 310	FWFTRR0		= FWRO + 0x6034,
 311	FWFTRR1		= FWRO + 0x6038,
 312	FWFTRR2		= FWRO + 0x603c,
 313	FWSEQNGC0	= FWRO + 0x6100,
 314	FWSEQNGM0	= FWRO + 0x6104,
 315	FWSEQNRC	= FWRO + 0x6200,
 316	FWCTFDCN0	= FWRO + 0x6300,
 317	FWLTHFDCN0	= FWRO + 0x6304,
 318	FWIPFDCN0	= FWRO + 0x6308,
 319	FWLTWFDCN0	= FWRO + 0x630c,
 320	FWPBFDCN0	= FWRO + 0x6310,
 321	FWMHLCN0	= FWRO + 0x6314,
 322	FWIHLCN0	= FWRO + 0x6318,
 323	FWICRDCN0	= FWRO + 0x6500,
 324	FWWMRDCN0	= FWRO + 0x6504,
 325	FWCTRDCN0	= FWRO + 0x6508,
 326	FWLTHRDCN0	= FWRO + 0x650c,
 327	FWIPRDCN0	= FWRO + 0x6510,
 328	FWLTWRDCN0	= FWRO + 0x6514,
 329	FWPBRDCN0	= FWRO + 0x6518,
 330	FWPMFDCN0	= FWRO + 0x6700,
 331	FWPGFDCN0	= FWRO + 0x6780,
 332	FWPMGDCN0	= FWRO + 0x6800,
 333	FWPMYDCN0	= FWRO + 0x6804,
 334	FWPMRDCN0	= FWRO + 0x6808,
 335	FWFRPPCN0	= FWRO + 0x6a00,
 336	FWFRDPCN0	= FWRO + 0x6a04,
 337	FWEIS00		= FWRO + 0x7900,
 338	FWEIE00		= FWRO + 0x7904,
 339	FWEID00		= FWRO + 0x7908,
 340	FWEIS1		= FWRO + 0x7a00,
 341	FWEIE1		= FWRO + 0x7a04,
 342	FWEID1		= FWRO + 0x7a08,
 343	FWEIS2		= FWRO + 0x7a10,
 344	FWEIE2		= FWRO + 0x7a14,
 345	FWEID2		= FWRO + 0x7a18,
 346	FWEIS3		= FWRO + 0x7a20,
 347	FWEIE3		= FWRO + 0x7a24,
 348	FWEID3		= FWRO + 0x7a28,
 349	FWEIS4		= FWRO + 0x7a30,
 350	FWEIE4		= FWRO + 0x7a34,
 351	FWEID4		= FWRO + 0x7a38,
 352	FWEIS5		= FWRO + 0x7a40,
 353	FWEIE5		= FWRO + 0x7a44,
 354	FWEID5		= FWRO + 0x7a48,
 355	FWEIS60		= FWRO + 0x7a50,
 356	FWEIE60		= FWRO + 0x7a54,
 357	FWEID60		= FWRO + 0x7a58,
 358	FWEIS61		= FWRO + 0x7a60,
 359	FWEIE61		= FWRO + 0x7a64,
 360	FWEID61		= FWRO + 0x7a68,
 361	FWEIS62		= FWRO + 0x7a70,
 362	FWEIE62		= FWRO + 0x7a74,
 363	FWEID62		= FWRO + 0x7a78,
 364	FWEIS63		= FWRO + 0x7a80,
 365	FWEIE63		= FWRO + 0x7a84,
 366	FWEID63		= FWRO + 0x7a88,
 367	FWEIS70		= FWRO + 0x7a90,
 368	FWEIE70		= FWRO + 0x7A94,
 369	FWEID70		= FWRO + 0x7a98,
 370	FWEIS71		= FWRO + 0x7aa0,
 371	FWEIE71		= FWRO + 0x7aa4,
 372	FWEID71		= FWRO + 0x7aa8,
 373	FWEIS72		= FWRO + 0x7ab0,
 374	FWEIE72		= FWRO + 0x7ab4,
 375	FWEID72		= FWRO + 0x7ab8,
 376	FWEIS73		= FWRO + 0x7ac0,
 377	FWEIE73		= FWRO + 0x7ac4,
 378	FWEID73		= FWRO + 0x7ac8,
 379	FWEIS80		= FWRO + 0x7ad0,
 380	FWEIE80		= FWRO + 0x7ad4,
 381	FWEID80		= FWRO + 0x7ad8,
 382	FWEIS81		= FWRO + 0x7ae0,
 383	FWEIE81		= FWRO + 0x7ae4,
 384	FWEID81		= FWRO + 0x7ae8,
 385	FWEIS82		= FWRO + 0x7af0,
 386	FWEIE82		= FWRO + 0x7af4,
 387	FWEID82		= FWRO + 0x7af8,
 388	FWEIS83		= FWRO + 0x7b00,
 389	FWEIE83		= FWRO + 0x7b04,
 390	FWEID83		= FWRO + 0x7b08,
 391	FWMIS0		= FWRO + 0x7c00,
 392	FWMIE0		= FWRO + 0x7c04,
 393	FWMID0		= FWRO + 0x7c08,
 394	FWSCR0		= FWRO + 0x7d00,
 395	FWSCR1		= FWRO + 0x7d04,
 396	FWSCR2		= FWRO + 0x7d08,
 397	FWSCR3		= FWRO + 0x7d0c,
 398	FWSCR4		= FWRO + 0x7d10,
 399	FWSCR5		= FWRO + 0x7d14,
 400	FWSCR6		= FWRO + 0x7d18,
 401	FWSCR7		= FWRO + 0x7d1c,
 402	FWSCR8		= FWRO + 0x7d20,
 403	FWSCR9		= FWRO + 0x7d24,
 404	FWSCR10		= FWRO + 0x7d28,
 405	FWSCR11		= FWRO + 0x7d2c,
 406	FWSCR12		= FWRO + 0x7d30,
 407	FWSCR13		= FWRO + 0x7d34,
 408	FWSCR14		= FWRO + 0x7d38,
 409	FWSCR15		= FWRO + 0x7d3c,
 410	FWSCR16		= FWRO + 0x7d40,
 411	FWSCR17		= FWRO + 0x7d44,
 412	FWSCR18		= FWRO + 0x7d48,
 413	FWSCR19		= FWRO + 0x7d4c,
 414	FWSCR20		= FWRO + 0x7d50,
 415	FWSCR21		= FWRO + 0x7d54,
 416	FWSCR22		= FWRO + 0x7d58,
 417	FWSCR23		= FWRO + 0x7d5c,
 418	FWSCR24		= FWRO + 0x7d60,
 419	FWSCR25		= FWRO + 0x7d64,
 420	FWSCR26		= FWRO + 0x7d68,
 421	FWSCR27		= FWRO + 0x7d6c,
 422	FWSCR28		= FWRO + 0x7d70,
 423	FWSCR29		= FWRO + 0x7d74,
 424	FWSCR30		= FWRO + 0x7d78,
 425	FWSCR31		= FWRO + 0x7d7c,
 426	FWSCR32		= FWRO + 0x7d80,
 427	FWSCR33		= FWRO + 0x7d84,
 428	FWSCR34		= FWRO + 0x7d88,
 429	FWSCR35		= FWRO + 0x7d8c,
 430	FWSCR36		= FWRO + 0x7d90,
 431	FWSCR37		= FWRO + 0x7d94,
 432	FWSCR38		= FWRO + 0x7d98,
 433	FWSCR39		= FWRO + 0x7d9c,
 434	FWSCR40		= FWRO + 0x7da0,
 435	FWSCR41		= FWRO + 0x7da4,
 436	FWSCR42		= FWRO + 0x7da8,
 437	FWSCR43		= FWRO + 0x7dac,
 438	FWSCR44		= FWRO + 0x7db0,
 439	FWSCR45		= FWRO + 0x7db4,
 440	FWSCR46		= FWRO + 0x7db8,
 441
 442	TPEMIMC0	= TPRO + 0x0000,
 443	TPEMIMC1	= TPRO + 0x0004,
 444	TPEMIMC2	= TPRO + 0x0008,
 445	TPEMIMC3	= TPRO + 0x000c,
 446	TPEMIMC4	= TPRO + 0x0010,
 447	TPEMIMC5	= TPRO + 0x0014,
 448	TPEMIMC60	= TPRO + 0x0080,
 449	TPEMIMC70	= TPRO + 0x0100,
 450	TSIM		= TPRO + 0x0700,
 451	TFIM		= TPRO + 0x0704,
 452	TCIM		= TPRO + 0x0708,
 453	TGIM0		= TPRO + 0x0710,
 454	TGIM1		= TPRO + 0x0714,
 455	TEIM0		= TPRO + 0x0720,
 456	TEIM1		= TPRO + 0x0724,
 457	TEIM2		= TPRO + 0x0728,
 458
 459	RIPV		= CARO + 0x0000,
 460	RRC		= CARO + 0x0004,
 461	RCEC		= CARO + 0x0008,
 462	RCDC		= CARO + 0x000c,
 463	RSSIS		= CARO + 0x0010,
 464	RSSIE		= CARO + 0x0014,
 465	RSSID		= CARO + 0x0018,
 466	CABPIBWMC	= CARO + 0x0020,
 467	CABPWMLC	= CARO + 0x0040,
 468	CABPPFLC0	= CARO + 0x0050,
 469	CABPPWMLC0	= CARO + 0x0060,
 470	CABPPPFLC00	= CARO + 0x00a0,
 471	CABPULC		= CARO + 0x0100,
 472	CABPIRM		= CARO + 0x0140,
 473	CABPPCM		= CARO + 0x0144,
 474	CABPLCM		= CARO + 0x0148,
 475	CABPCPM		= CARO + 0x0180,
 476	CABPMCPM	= CARO + 0x0200,
 477	CARDNM		= CARO + 0x0280,
 478	CARDMNM		= CARO + 0x0284,
 479	CARDCN		= CARO + 0x0290,
 480	CAEIS0		= CARO + 0x0300,
 481	CAEIE0		= CARO + 0x0304,
 482	CAEID0		= CARO + 0x0308,
 483	CAEIS1		= CARO + 0x0310,
 484	CAEIE1		= CARO + 0x0314,
 485	CAEID1		= CARO + 0x0318,
 486	CAMIS0		= CARO + 0x0340,
 487	CAMIE0		= CARO + 0x0344,
 488	CAMID0		= CARO + 0x0348,
 489	CAMIS1		= CARO + 0x0350,
 490	CAMIE1		= CARO + 0x0354,
 491	CAMID1		= CARO + 0x0358,
 492	CASCR		= CARO + 0x0380,
 493
 494	EAMC		= TARO + 0x0000,
 495	EAMS		= TARO + 0x0004,
 496	EAIRC		= TARO + 0x0010,
 497	EATDQSC		= TARO + 0x0014,
 498	EATDQC		= TARO + 0x0018,
 499	EATDQAC		= TARO + 0x001c,
 500	EATPEC		= TARO + 0x0020,
 501	EATMFSC0	= TARO + 0x0040,
 502	EATDQDC0	= TARO + 0x0060,
 503	EATDQM0		= TARO + 0x0080,
 504	EATDQMLM0	= TARO + 0x00a0,
 505	EACTQC		= TARO + 0x0100,
 506	EACTDQDC	= TARO + 0x0104,
 507	EACTDQM		= TARO + 0x0108,
 508	EACTDQMLM	= TARO + 0x010c,
 509	EAVCC		= TARO + 0x0130,
 510	EAVTC		= TARO + 0x0134,
 511	EATTFC		= TARO + 0x0138,
 512	EACAEC		= TARO + 0x0200,
 513	EACC		= TARO + 0x0204,
 514	EACAIVC0	= TARO + 0x0220,
 515	EACAULC0	= TARO + 0x0240,
 516	EACOEM		= TARO + 0x0260,
 517	EACOIVM0	= TARO + 0x0280,
 518	EACOULM0	= TARO + 0x02a0,
 519	EACGSM		= TARO + 0x02c0,
 520	EATASC		= TARO + 0x0300,
 521	EATASENC0	= TARO + 0x0320,
 522	EATASCTENC	= TARO + 0x0340,
 523	EATASENM0	= TARO + 0x0360,
 524	EATASCTENM	= TARO + 0x0380,
 525	EATASCSTC0	= TARO + 0x03a0,
 526	EATASCSTC1	= TARO + 0x03a4,
 527	EATASCSTM0	= TARO + 0x03a8,
 528	EATASCSTM1	= TARO + 0x03ac,
 529	EATASCTC	= TARO + 0x03b0,
 530	EATASCTM	= TARO + 0x03b4,
 531	EATASGL0	= TARO + 0x03c0,
 532	EATASGL1	= TARO + 0x03c4,
 533	EATASGLR	= TARO + 0x03c8,
 534	EATASGR		= TARO + 0x03d0,
 535	EATASGRR	= TARO + 0x03d4,
 536	EATASHCC	= TARO + 0x03e0,
 537	EATASRIRM	= TARO + 0x03e4,
 538	EATASSM		= TARO + 0x03e8,
 539	EAUSMFSECN	= TARO + 0x0400,
 540	EATFECN		= TARO + 0x0404,
 541	EAFSECN		= TARO + 0x0408,
 542	EADQOECN	= TARO + 0x040c,
 543	EADQSECN	= TARO + 0x0410,
 544	EACKSECN	= TARO + 0x0414,
 545	EAEIS0		= TARO + 0x0500,
 546	EAEIE0		= TARO + 0x0504,
 547	EAEID0		= TARO + 0x0508,
 548	EAEIS1		= TARO + 0x0510,
 549	EAEIE1		= TARO + 0x0514,
 550	EAEID1		= TARO + 0x0518,
 551	EAEIS2		= TARO + 0x0520,
 552	EAEIE2		= TARO + 0x0524,
 553	EAEID2		= TARO + 0x0528,
 554	EASCR		= TARO + 0x0580,
 555
 556	MPSM		= RMRO + 0x0000,
 557	MPIC		= RMRO + 0x0004,
 558	MPIM		= RMRO + 0x0008,
 559	MIOC		= RMRO + 0x0010,
 560	MIOM		= RMRO + 0x0014,
 561	MXMS		= RMRO + 0x0018,
 562	MTFFC		= RMRO + 0x0020,
 563	MTPFC		= RMRO + 0x0024,
 564	MTPFC2		= RMRO + 0x0028,
 565	MTPFC30		= RMRO + 0x0030,
 566	MTATC0		= RMRO + 0x0050,
 567	MTIM		= RMRO + 0x0060,
 568	MRGC		= RMRO + 0x0080,
 569	MRMAC0		= RMRO + 0x0084,
 570	MRMAC1		= RMRO + 0x0088,
 571	MRAFC		= RMRO + 0x008c,
 572	MRSCE		= RMRO + 0x0090,
 573	MRSCP		= RMRO + 0x0094,
 574	MRSCC		= RMRO + 0x0098,
 575	MRFSCE		= RMRO + 0x009c,
 576	MRFSCP		= RMRO + 0x00a0,
 577	MTRC		= RMRO + 0x00a4,
 578	MRIM		= RMRO + 0x00a8,
 579	MRPFM		= RMRO + 0x00ac,
 580	MPFC0		= RMRO + 0x0100,
 581	MLVC		= RMRO + 0x0180,
 582	MEEEC		= RMRO + 0x0184,
 583	MLBC		= RMRO + 0x0188,
 584	MXGMIIC		= RMRO + 0x0190,
 585	MPCH		= RMRO + 0x0194,
 586	MANC		= RMRO + 0x0198,
 587	MANM		= RMRO + 0x019c,
 588	MPLCA1		= RMRO + 0x01a0,
 589	MPLCA2		= RMRO + 0x01a4,
 590	MPLCA3		= RMRO + 0x01a8,
 591	MPLCA4		= RMRO + 0x01ac,
 592	MPLCAM		= RMRO + 0x01b0,
 593	MHDC1		= RMRO + 0x01c0,
 594	MHDC2		= RMRO + 0x01c4,
 595	MEIS		= RMRO + 0x0200,
 596	MEIE		= RMRO + 0x0204,
 597	MEID		= RMRO + 0x0208,
 598	MMIS0		= RMRO + 0x0210,
 599	MMIE0		= RMRO + 0x0214,
 600	MMID0		= RMRO + 0x0218,
 601	MMIS1		= RMRO + 0x0220,
 602	MMIE1		= RMRO + 0x0224,
 603	MMID1		= RMRO + 0x0228,
 604	MMIS2		= RMRO + 0x0230,
 605	MMIE2		= RMRO + 0x0234,
 606	MMID2		= RMRO + 0x0238,
 607	MMPFTCT		= RMRO + 0x0300,
 608	MAPFTCT		= RMRO + 0x0304,
 609	MPFRCT		= RMRO + 0x0308,
 610	MFCICT		= RMRO + 0x030c,
 611	MEEECT		= RMRO + 0x0310,
 612	MMPCFTCT0	= RMRO + 0x0320,
 613	MAPCFTCT0	= RMRO + 0x0330,
 614	MPCFRCT0	= RMRO + 0x0340,
 615	MHDCC		= RMRO + 0x0350,
 616	MROVFC		= RMRO + 0x0354,
 617	MRHCRCEC	= RMRO + 0x0358,
 618	MRXBCE		= RMRO + 0x0400,
 619	MRXBCP		= RMRO + 0x0404,
 620	MRGFCE		= RMRO + 0x0408,
 621	MRGFCP		= RMRO + 0x040c,
 622	MRBFC		= RMRO + 0x0410,
 623	MRMFC		= RMRO + 0x0414,
 624	MRUFC		= RMRO + 0x0418,
 625	MRPEFC		= RMRO + 0x041c,
 626	MRNEFC		= RMRO + 0x0420,
 627	MRFMEFC		= RMRO + 0x0424,
 628	MRFFMEFC	= RMRO + 0x0428,
 629	MRCFCEFC	= RMRO + 0x042c,
 630	MRFCEFC		= RMRO + 0x0430,
 631	MRRCFEFC	= RMRO + 0x0434,
 632	MRUEFC		= RMRO + 0x043c,
 633	MROEFC		= RMRO + 0x0440,
 634	MRBOEC		= RMRO + 0x0444,
 635	MTXBCE		= RMRO + 0x0500,
 636	MTXBCP		= RMRO + 0x0504,
 637	MTGFCE		= RMRO + 0x0508,
 638	MTGFCP		= RMRO + 0x050c,
 639	MTBFC		= RMRO + 0x0510,
 640	MTMFC		= RMRO + 0x0514,
 641	MTUFC		= RMRO + 0x0518,
 642	MTEFC		= RMRO + 0x051c,
 643
 644	GWMC		= GWRO + 0x0000,
 645	GWMS		= GWRO + 0x0004,
 646	GWIRC		= GWRO + 0x0010,
 647	GWRDQSC		= GWRO + 0x0014,
 648	GWRDQC		= GWRO + 0x0018,
 649	GWRDQAC		= GWRO + 0x001c,
 650	GWRGC		= GWRO + 0x0020,
 651	GWRMFSC0	= GWRO + 0x0040,
 652	GWRDQDC0	= GWRO + 0x0060,
 653	GWRDQM0		= GWRO + 0x0080,
 654	GWRDQMLM0	= GWRO + 0x00a0,
 655	GWMTIRM		= GWRO + 0x0100,
 656	GWMSTLS		= GWRO + 0x0104,
 657	GWMSTLR		= GWRO + 0x0108,
 658	GWMSTSS		= GWRO + 0x010c,
 659	GWMSTSR		= GWRO + 0x0110,
 660	GWMAC0		= GWRO + 0x0120,
 661	GWMAC1		= GWRO + 0x0124,
 662	GWVCC		= GWRO + 0x0130,
 663	GWVTC		= GWRO + 0x0134,
 664	GWTTFC		= GWRO + 0x0138,
 665	GWTDCAC00	= GWRO + 0x0140,
 666	GWTDCAC10	= GWRO + 0x0144,
 667	GWTSDCC0	= GWRO + 0x0160,
 668	GWTNM		= GWRO + 0x0180,
 669	GWTMNM		= GWRO + 0x0184,
 670	GWAC		= GWRO + 0x0190,
 671	GWDCBAC0	= GWRO + 0x0194,
 672	GWDCBAC1	= GWRO + 0x0198,
 673	GWIICBSC	= GWRO + 0x019c,
 674	GWMDNC		= GWRO + 0x01a0,
 675	GWTRC0		= GWRO + 0x0200,
 676	GWTPC0		= GWRO + 0x0300,
 677	GWARIRM		= GWRO + 0x0380,
 678	GWDCC0		= GWRO + 0x0400,
 679	GWAARSS		= GWRO + 0x0800,
 680	GWAARSR0	= GWRO + 0x0804,
 681	GWAARSR1	= GWRO + 0x0808,
 682	GWIDAUAS0	= GWRO + 0x0840,
 683	GWIDASM0	= GWRO + 0x0880,
 684	GWIDASAM00	= GWRO + 0x0900,
 685	GWIDASAM10	= GWRO + 0x0904,
 686	GWIDACAM00	= GWRO + 0x0980,
 687	GWIDACAM10	= GWRO + 0x0984,
 688	GWGRLC		= GWRO + 0x0a00,
 689	GWGRLULC	= GWRO + 0x0a04,
 690	GWRLIVC0	= GWRO + 0x0a80,
 691	GWRLULC0	= GWRO + 0x0a84,
 692	GWIDPC		= GWRO + 0x0b00,
 693	GWIDC0		= GWRO + 0x0c00,
 694	GWDIS0		= GWRO + 0x1100,
 695	GWDIE0		= GWRO + 0x1104,
 696	GWDID0		= GWRO + 0x1108,
 697	GWTSDIS		= GWRO + 0x1180,
 698	GWTSDIE		= GWRO + 0x1184,
 699	GWTSDID		= GWRO + 0x1188,
 700	GWEIS0		= GWRO + 0x1190,
 701	GWEIE0		= GWRO + 0x1194,
 702	GWEID0		= GWRO + 0x1198,
 703	GWEIS1		= GWRO + 0x11a0,
 704	GWEIE1		= GWRO + 0x11a4,
 705	GWEID1		= GWRO + 0x11a8,
 706	GWEIS20		= GWRO + 0x1200,
 707	GWEIE20		= GWRO + 0x1204,
 708	GWEID20		= GWRO + 0x1208,
 709	GWEIS3		= GWRO + 0x1280,
 710	GWEIE3		= GWRO + 0x1284,
 711	GWEID3		= GWRO + 0x1288,
 712	GWEIS4		= GWRO + 0x1290,
 713	GWEIE4		= GWRO + 0x1294,
 714	GWEID4		= GWRO + 0x1298,
 715	GWEIS5		= GWRO + 0x12a0,
 716	GWEIE5		= GWRO + 0x12a4,
 717	GWEID5		= GWRO + 0x12a8,
 718	GWSCR0		= GWRO + 0x1800,
 719	GWSCR1		= GWRO + 0x1900,
 720};
 721
 722/* ETHA/RMAC */
 723enum rswitch_etha_mode {
 724	EAMC_OPC_RESET,
 725	EAMC_OPC_DISABLE,
 726	EAMC_OPC_CONFIG,
 727	EAMC_OPC_OPERATION,
 728};
 729
 730#define EAMS_OPS_MASK		EAMC_OPC_OPERATION
 731
 732#define EAVCC_VEM_SC_TAG	(0x3 << 16)
 733
 734#define MPIC_PIS		GENMASK(2, 0)
 735#define MPIC_PIS_GMII		2
 736#define MPIC_PIS_XGMII		4
 737#define MPIC_LSC		GENMASK(5, 3)
 738#define MPIC_LSC_100M		1
 739#define MPIC_LSC_1G		2
 740#define MPIC_LSC_2_5G		3
 741#define MPIC_PSMCS		GENMASK(22, 16)
 742#define MPIC_PSMHT		GENMASK(26, 24)
 743
 744#define MPSM_PSME		BIT(0)
 745#define MPSM_MFF		BIT(2)
 746#define MPSM_MMF_C22		0
 747#define MPSM_MMF_C45		1
 748#define MPSM_PDA		GENMASK(7, 3)
 749#define MPSM_PRA		GENMASK(12, 8)
 750#define MPSM_POP		GENMASK(14, 13)
 751#define MPSM_POP_ADDRESS	0
 752#define MPSM_POP_WRITE		1
 753#define MPSM_POP_READ_C22	2
 754#define MPSM_POP_READ_C45	3
 755#define MPSM_PRD		GENMASK(31, 16)
 756
 757#define MLVC_PLV		BIT(16)
 758
 759/* GWCA */
 760enum rswitch_gwca_mode {
 761	GWMC_OPC_RESET,
 762	GWMC_OPC_DISABLE,
 763	GWMC_OPC_CONFIG,
 764	GWMC_OPC_OPERATION,
 765};
 766
 767#define GWMS_OPS_MASK		GWMC_OPC_OPERATION
 768
 769#define GWMTIRM_MTIOG		BIT(0)
 770#define GWMTIRM_MTR		BIT(1)
 771
 772#define GWVCC_VEM_SC_TAG	(0x3 << 16)
 773
 774#define GWARIRM_ARIOG		BIT(0)
 775#define GWARIRM_ARR		BIT(1)
 776
 777#define GWMDNC_TSDMN(num)	(((num) << 16) & GENMASK(17, 16))
 778#define GWMDNC_TXDMN(num)	(((num) << 8) & GENMASK(12, 8))
 779#define GWMDNC_RXDMN(num)	((num) & GENMASK(4, 0))
 780
 781#define GWDCC_BALR		BIT(24)
 782#define GWDCC_DCP_MASK		GENMASK(18, 16)
 783#define GWDCC_DCP(prio)		FIELD_PREP(GWDCC_DCP_MASK, (prio))
 784#define GWDCC_DQT		BIT(11)
 785#define GWDCC_ETS		BIT(9)
 786#define GWDCC_EDE		BIT(8)
 787
 788#define GWTRC(queue)		(GWTRC0 + (queue) / 32 * 4)
 789#define GWTPC_PPPL(ipv)		BIT(ipv)
 790#define GWDCC_OFFS(queue)	(GWDCC0 + (queue) * 4)
 791
 792#define GWDIS(i)		(GWDIS0 + (i) * 0x10)
 793#define GWDIE(i)		(GWDIE0 + (i) * 0x10)
 794#define GWDID(i)		(GWDID0 + (i) * 0x10)
 795
 796/* COMA */
 797#define RRC_RR			BIT(0)
 798#define RRC_RR_CLR		0
 799#define	RCEC_ACE_DEFAULT	(BIT(0) | BIT(AGENT_INDEX_GWCA))
 800#define RCEC_RCE		BIT(16)
 801#define RCDC_RCD		BIT(16)
 802
 803#define CABPIRM_BPIOG		BIT(0)
 804#define CABPIRM_BPR		BIT(1)
 805
 806#define CABPPFLC_INIT_VALUE	0x00800080
 807
 808/* MFWD */
 809#define FWPC0(i)		(FWPC00 + (i) * 0x10)
 810#define FWPC0_LTHTA		BIT(0)
 811#define FWPC0_IP4UE		BIT(3)
 812#define FWPC0_IP4TE		BIT(4)
 813#define FWPC0_IP4OE		BIT(5)
 814#define FWPC0_L2SE		BIT(9)
 815#define FWPC0_IP4EA		BIT(10)
 816#define FWPC0_IPDSA		BIT(12)
 817#define FWPC0_IPHLA		BIT(18)
 818#define FWPC0_MACDSA		BIT(20)
 819#define FWPC0_MACSSA		BIT(23)
 820#define FWPC0_MACHLA		BIT(26)
 821#define FWPC0_MACHMA		BIT(27)
 822#define FWPC0_VLANSA		BIT(28)
 823
 824#define FWPC1(i)		(FWPC10 + (i) * 0x10)
 825#define FWCP1_LTHFW		GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
 826#define FWPC1_DDE		BIT(0)
 827
 828#define FWPC2(i)		(FWPC20 + (i) * 0x10)
 829#define FWCP2_LTWFW		GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
 830#define FWCP2_LTWFW_MASK	GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
 831
 832#define FWPBFC(i)		(FWPBFC0 + (i) * 0x10)
 833#define FWPBFC_PBDV		GENMASK(RSWITCH_NUM_AGENTS - 1, 0)
 834
 835#define FWPBFCSDC(j, i)         (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04)
 836
 837#define FWMACHEC_MACHMUE_MASK	GENMASK(26, 16)
 838
 839#define FWMACTIM_MACTIOG	BIT(0)
 840#define FWMACTIM_MACTR		BIT(1)
 841
 842#define FWMACAGUSPC_MACAGUSP	GENMASK(9, 0)
 843#define FWMACAGC_MACAGT		GENMASK(15, 0)
 844#define FWMACAGC_MACAGE		BIT(16)
 845#define FWMACAGC_MACAGSL	BIT(17)
 846#define FWMACAGC_MACAGPM	BIT(18)
 847#define FWMACAGC_MACDES		BIT(24)
 848#define FWMACAGC_MACAGOG	BIT(28)
 849#define FWMACAGC_MACDESOG	BIT(29)
 850
 851#define RSW_AGEING_CLK_PER_US	0x140
 852#define RSW_AGEING_TIME		300
 853
 854/* TOP */
 855#define TPEMIMC7(queue)		(TPEMIMC70 + (queue) * 4)
 856
 857/* Descriptors */
 858enum RX_DS_CC_BIT {
 859	RX_DS	= 0x0fff, /* Data size */
 860	RX_TR	= 0x1000, /* Truncation indication */
 861	RX_EI	= 0x2000, /* Error indication */
 862	RX_PS	= 0xc000, /* Padding selection */
 863};
 864
 865enum TX_DS_TAGL_BIT {
 866	TX_DS	= 0x0fff, /* Data size */
 867	TX_TAGL	= 0xf000, /* Frame tag LSBs */
 868};
 869
 870enum DIE_DT {
 871	/* Frame data */
 872	DT_FSINGLE	= 0x80,
 873	DT_FSTART	= 0x90,
 874	DT_FMID		= 0xa0,
 875	DT_FEND		= 0xb0,
 876
 877	/* Chain control */
 878	DT_LEMPTY	= 0xc0,
 879	DT_EEMPTY	= 0xd0,
 880	DT_LINKFIX	= 0x00,
 881	DT_LINK		= 0xe0,
 882	DT_EOS		= 0xf0,
 883	/* HW/SW arbitration */
 884	DT_FEMPTY	= 0x40,
 885	DT_FEMPTY_IS	= 0x10,
 886	DT_FEMPTY_IC	= 0x20,
 887	DT_FEMPTY_ND	= 0x30,
 888	DT_FEMPTY_START	= 0x50,
 889	DT_FEMPTY_MID	= 0x60,
 890	DT_FEMPTY_END	= 0x70,
 891
 892	DT_MASK		= 0xf0,
 893	DIE		= 0x08,	/* Descriptor Interrupt Enable */
 894};
 895
 896/* Both transmission and reception */
 897#define INFO1_FMT		BIT(2)
 898#define INFO1_TXC		BIT(3)
 899
 900/* For transmission */
 901#define INFO1_TSUN(val)		((u64)(val) << 8ULL)
 902#define INFO1_IPV(prio)		((u64)(prio) << 28ULL)
 903#define INFO1_CSD0(index)	((u64)(index) << 32ULL)
 904#define INFO1_CSD1(index)	((u64)(index) << 40ULL)
 905#define INFO1_DV(port_vector)	((u64)(port_vector) << 48ULL)
 906
 907/* For reception */
 908#define INFO1_SPN(port)		((u64)(port) << 36ULL)
 909
 910/* For timestamp descriptor in dptrl (Byte 4 to 7) */
 911#define TS_DESC_TSUN(dptrl)	((dptrl) & GENMASK(7, 0))
 912#define TS_DESC_SPN(dptrl)	(((dptrl) & GENMASK(10, 8)) >> 8)
 913#define TS_DESC_DPN(dptrl)	(((dptrl) & GENMASK(17, 16)) >> 16)
 914#define TS_DESC_TN(dptrl)	((dptrl) & BIT(24))
 915
 916struct rswitch_desc {
 917	__le16 info_ds;	/* Descriptor size */
 918	u8 die_dt;	/* Descriptor interrupt enable and type */
 919	__u8  dptrh;	/* Descriptor pointer MSB */
 920	__le32 dptrl;	/* Descriptor pointer LSW */
 921} __packed;
 922
 923struct rswitch_ts_desc {
 924	struct rswitch_desc desc;
 925	__le32 ts_nsec;
 926	__le32 ts_sec;
 927} __packed;
 928
 929struct rswitch_ext_desc {
 930	struct rswitch_desc desc;
 931	__le64 info1;
 932} __packed;
 933
 934struct rswitch_ext_ts_desc {
 935	struct rswitch_desc desc;
 936	__le64 info1;
 937	__le32 ts_nsec;
 938	__le32 ts_sec;
 939} __packed;
 940
 941struct rswitch_etha {
 942	unsigned int index;
 943	void __iomem *addr;
 944	void __iomem *coma_addr;
 945	bool external_phy;
 946	struct mii_bus *mii;
 947	phy_interface_t phy_interface;
 948	u32 psmcs;
 949	u8 mac_addr[MAX_ADDR_LEN];
 950	int link;
 951	int speed;
 952
 953	/* This hardware could not be initialized twice so that marked
 954	 * this flag to avoid multiple initialization.
 955	 */
 956	bool operated;
 957};
 958
 959/* The datasheet said descriptor "chain" and/or "queue". For consistency of
 960 * name, this driver calls "queue".
 961 */
 962struct rswitch_gwca_queue {
 963	union {
 964		struct rswitch_ext_desc *tx_ring;
 965		struct rswitch_ext_ts_desc *rx_ring;
 966		struct rswitch_ts_desc *ts_ring;
 967	};
 968
 969	/* Common */
 970	dma_addr_t ring_dma;
 971	unsigned int ring_size;
 972	unsigned int cur;
 973	unsigned int dirty;
 974
 975	/* For [rt]x_ring */
 976	unsigned int index;
 977	bool dir_tx;
 978	struct net_device *ndev;	/* queue to ndev for irq */
 979
 980	union {
 981		/* For TX */
 982		struct {
 983			struct sk_buff **skbs;
 984			dma_addr_t *unmap_addrs;
 985		};
 986		/* For RX */
 987		struct {
 988			void **rx_bufs;
 989			struct sk_buff *skb_fstart;
 990			u16 pkt_len;
 991		};
 992	};
 993};
 994
 995#define RSWITCH_NUM_IRQ_REGS	(RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32))
 996struct rswitch_gwca {
 997	unsigned int index;
 998	struct rswitch_desc *linkfix_table;
 999	dma_addr_t linkfix_table_dma;
1000	u32 linkfix_table_size;
1001	struct rswitch_gwca_queue *queues;
1002	int num_queues;
1003	struct rswitch_gwca_queue ts_queue;
1004	DECLARE_BITMAP(used, RSWITCH_MAX_NUM_QUEUES);
1005	u32 tx_irq_bits[RSWITCH_NUM_IRQ_REGS];
1006	u32 rx_irq_bits[RSWITCH_NUM_IRQ_REGS];
1007};
1008
1009#define NUM_QUEUES_PER_NDEV	2
1010#define TS_TAGS_PER_PORT	256
1011struct rswitch_device {
1012	struct rswitch_private *priv;
1013	struct net_device *ndev;
1014	struct napi_struct napi;
1015	void __iomem *addr;
1016	struct rswitch_gwca_queue *tx_queue;
1017	struct rswitch_gwca_queue *rx_queue;
1018	struct sk_buff *ts_skb[TS_TAGS_PER_PORT];
1019	DECLARE_BITMAP(ts_skb_used, TS_TAGS_PER_PORT);
1020	bool disabled;
1021
1022	struct list_head list;
1023
1024	int port;
1025	struct rswitch_etha *etha;
1026	struct device_node *np_port;
1027	struct phy *serdes;
1028
1029	struct net_device *brdev;	/* master bridge device */
1030	unsigned int learning_requested : 1;
1031	unsigned int learning_offloaded : 1;
1032	unsigned int forwarding_requested : 1;
1033	unsigned int forwarding_offloaded : 1;
1034};
1035
1036struct rswitch_mfwd_mac_table_entry {
1037	int queue_index;
1038	unsigned char addr[MAX_ADDR_LEN];
1039};
1040
1041struct rswitch_mfwd {
1042	struct rswitch_mac_table_entry *mac_table_entries;
1043	int num_mac_table_entries;
1044};
1045
1046struct rswitch_private {
1047	struct platform_device *pdev;
1048	void __iomem *addr;
1049	struct rcar_gen4_ptp_private *ptp_priv;
1050
1051	struct rswitch_device *rdev[RSWITCH_NUM_PORTS];
1052	DECLARE_BITMAP(opened_ports, RSWITCH_NUM_PORTS);
1053
1054	struct rswitch_gwca gwca;
1055	struct rswitch_etha etha[RSWITCH_NUM_PORTS];
1056	struct rswitch_mfwd mfwd;
1057
1058	struct list_head port_list;
1059
1060	spinlock_t lock;	/* lock interrupt registers' control */
1061	struct clk *clk;
1062
1063	bool etha_no_runtime_change;
1064	bool gwca_halt;
1065	struct net_device *offload_brdev;
1066
1067	enum hwtstamp_tx_types tstamp_tx_ctrl;
1068	enum hwtstamp_rx_filters tstamp_rx_ctrl;
1069};
1070
1071bool is_rdev(const struct net_device *ndev);
1072void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set);
1073
1074#endif	/* #ifndef __RSWITCH_H__ */