rtase.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 *  rtase is the Linux device driver released for Realtek Automotive Switch
  4 *  controllers with PCI-Express interface.
  5 *
  6 *  Copyright(c) 2024 Realtek Semiconductor Corp.
  7 */
  8
  9#ifndef RTASE_H
 10#define RTASE_H
 11
 12#define RTASE_HW_VER_MASK     0x7C800000
 13#define RTASE_HW_VER_906X_7XA 0x00800000
 14#define RTASE_HW_VER_906X_7XC 0x04000000
 15#define RTASE_HW_VER_907XD_V1 0x04800000
 16#define RTASE_HW_VER_907XD_VA 0x08000000
 17
 18#define RTASE_RX_DMA_BURST_256       4
 19#define RTASE_TX_DMA_BURST_UNLIMITED 7
 20
 21#define RTASE_RX_BUF_SIZE    (PAGE_SIZE - \
 22			      SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
 23#define RTASE_MAX_JUMBO_SIZE (RTASE_RX_BUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN)
 24
 25/* 3 means InterFrameGap = the shortest one */
 26#define RTASE_INTERFRAMEGAP 0x03
 27
 28#define RTASE_REGS_SIZE     256
 29#define RTASE_PCI_REGS_SIZE 0x100
 30
 31#define RTASE_MULTICAST_FILTER_MASK GENMASK(30, 26)
 32
 33#define RTASE_VLAN_FILTER_ENTRY_NUM 32
 34#define RTASE_NUM_TX_QUEUE 8
 35#define RTASE_NUM_RX_QUEUE 4
 36
 37#define RTASE_TXQ_CTRL      1
 38#define RTASE_FUNC_TXQ_NUM  1
 39#define RTASE_FUNC_RXQ_NUM  1
 40#define RTASE_INTERRUPT_NUM 1
 41
 42#define RTASE_MITI_TIME_COUNT_MASK    GENMASK(3, 0)
 43#define RTASE_MITI_TIME_UNIT_MASK     GENMASK(7, 4)
 44#define RTASE_MITI_DEFAULT_TIME       128
 45#define RTASE_MITI_MAX_TIME           491520
 46#define RTASE_MITI_PKT_NUM_COUNT_MASK GENMASK(11, 8)
 47#define RTASE_MITI_PKT_NUM_UNIT_MASK  GENMASK(13, 12)
 48#define RTASE_MITI_DEFAULT_PKT_NUM    64
 49#define RTASE_MITI_MAX_PKT_NUM_IDX    3
 50#define RTASE_MITI_MAX_PKT_NUM_UNIT   16
 51#define RTASE_MITI_MAX_PKT_NUM        240
 52#define RTASE_MITI_COUNT_BIT_NUM      4
 53
 54#define RTASE_NUM_MSIX 4
 55
 56#define RTASE_DWORD_MOD 16
 57
 58/*****************************************************************************/
 59enum rtase_registers {
 60	RTASE_MAC0   = 0x0000,
 61	RTASE_MAC4   = 0x0004,
 62	RTASE_MAR0   = 0x0008,
 63	RTASE_MAR1   = 0x000C,
 64	RTASE_DTCCR0 = 0x0010,
 65	RTASE_DTCCR4 = 0x0014,
 66#define RTASE_COUNTER_RESET BIT(0)
 67#define RTASE_COUNTER_DUMP  BIT(3)
 68
 69	RTASE_FCR = 0x0018,
 70#define RTASE_FCR_RXQ_MASK GENMASK(5, 4)
 71
 72	RTASE_LBK_CTRL = 0x001A,
 73#define RTASE_LBK_ATLD BIT(1)
 74#define RTASE_LBK_CLR  BIT(0)
 75
 76	RTASE_TX_DESC_ADDR0   = 0x0020,
 77	RTASE_TX_DESC_ADDR4   = 0x0024,
 78	RTASE_TX_DESC_COMMAND = 0x0028,
 79#define RTASE_TX_DESC_CMD_CS BIT(15)
 80#define RTASE_TX_DESC_CMD_WE BIT(14)
 81
 82	RTASE_BOOT_CTL  = 0x6004,
 83	RTASE_CLKSW_SET = 0x6018,
 84
 85	RTASE_CHIP_CMD = 0x0037,
 86#define RTASE_STOP_REQ      BIT(7)
 87#define RTASE_STOP_REQ_DONE BIT(6)
 88#define RTASE_RE            BIT(3)
 89#define RTASE_TE            BIT(2)
 90
 91	RTASE_IMR0 = 0x0038,
 92	RTASE_ISR0 = 0x003C,
 93#define RTASE_TOK7 BIT(30)
 94#define RTASE_TOK6 BIT(28)
 95#define RTASE_TOK5 BIT(26)
 96#define RTASE_TOK4 BIT(24)
 97#define RTASE_FOVW BIT(6)
 98#define RTASE_RDU  BIT(4)
 99#define RTASE_TOK  BIT(2)
100#define RTASE_ROK  BIT(0)
101
102	RTASE_IMR1 = 0x0800,
103	RTASE_ISR1 = 0x0802,
104#define RTASE_Q_TOK BIT(4)
105#define RTASE_Q_RDU BIT(1)
106#define RTASE_Q_ROK BIT(0)
107
108	RTASE_EPHY_ISR = 0x6014,
109	RTASE_EPHY_IMR = 0x6016,
110
111	RTASE_TX_CONFIG_0 = 0x0040,
112#define RTASE_TX_INTER_FRAME_GAP_MASK GENMASK(25, 24)
113	/* DMA burst value (0-7) is shift this many bits */
114#define RTASE_TX_DMA_MASK             GENMASK(10, 8)
115
116	RTASE_RX_CONFIG_0 = 0x0044,
117#define RTASE_RX_SINGLE_FETCH  BIT(14)
118#define RTASE_RX_SINGLE_TAG    BIT(13)
119#define RTASE_RX_MX_DMA_MASK   GENMASK(10, 8)
120#define RTASE_ACPT_FLOW        BIT(7)
121#define RTASE_ACCEPT_ERR       BIT(5)
122#define RTASE_ACCEPT_RUNT      BIT(4)
123#define RTASE_ACCEPT_BROADCAST BIT(3)
124#define RTASE_ACCEPT_MULTICAST BIT(2)
125#define RTASE_ACCEPT_MYPHYS    BIT(1)
126#define RTASE_ACCEPT_ALLPHYS   BIT(0)
127#define RTASE_ACCEPT_MASK      (RTASE_ACPT_FLOW | RTASE_ACCEPT_ERR | \
128				RTASE_ACCEPT_RUNT | RTASE_ACCEPT_BROADCAST | \
129				RTASE_ACCEPT_MULTICAST | RTASE_ACCEPT_MYPHYS | \
130				RTASE_ACCEPT_ALLPHYS)
131
132	RTASE_RX_CONFIG_1 = 0x0046,
133#define RTASE_RX_MAX_FETCH_DESC_MASK GENMASK(15, 11)
134#define RTASE_RX_NEW_DESC_FORMAT_EN  BIT(8)
135#define RTASE_OUTER_VLAN_DETAG_EN    BIT(7)
136#define RTASE_INNER_VLAN_DETAG_EN    BIT(6)
137#define RTASE_PCIE_NEW_FLOW          BIT(2)
138#define RTASE_PCIE_RELOAD_EN         BIT(0)
139
140	RTASE_EEM = 0x0050,
141#define RTASE_EEM_UNLOCK 0xC0
142
143	RTASE_TDFNR  = 0x0057,
144	RTASE_TPPOLL = 0x0090,
145	RTASE_PDR    = 0x00B0,
146	RTASE_FIFOR  = 0x00D3,
147#define RTASE_TX_FIFO_EMPTY BIT(5)
148#define RTASE_RX_FIFO_EMPTY BIT(4)
149
150	RTASE_RMS       = 0x00DA,
151	RTASE_CPLUS_CMD = 0x00E0,
152#define RTASE_FORCE_RXFLOW_EN BIT(11)
153#define RTASE_FORCE_TXFLOW_EN BIT(10)
154#define RTASE_RX_CHKSUM       BIT(5)
155
156	RTASE_Q0_RX_DESC_ADDR0 = 0x00E4,
157	RTASE_Q0_RX_DESC_ADDR4 = 0x00E8,
158	RTASE_Q1_RX_DESC_ADDR0 = 0x4000,
159	RTASE_Q1_RX_DESC_ADDR4 = 0x4004,
160	RTASE_MTPS             = 0x00EC,
161#define RTASE_TAG_NUM_SEL_MASK GENMASK(10, 8)
162
163	RTASE_MISC = 0x00F2,
164#define RTASE_RX_DV_GATE_EN BIT(3)
165
166	RTASE_TFUN_CTRL = 0x0400,
167#define RTASE_TX_NEW_DESC_FORMAT_EN BIT(0)
168
169	RTASE_TX_CONFIG_1 = 0x203E,
170#define RTASE_TC_MODE_MASK GENMASK(11, 10)
171
172	RTASE_TOKSEL      = 0x2046,
173	RTASE_TXQCRDT_0   = 0x2500,
174	RTASE_RFIFONFULL  = 0x4406,
175	RTASE_INT_MITI_TX = 0x0A00,
176	RTASE_INT_MITI_RX = 0x0A80,
177
178	RTASE_VLAN_ENTRY_0 = 0xAC80,
179};
180
181enum rtase_desc_status_bit {
182	RTASE_DESC_OWN = BIT(31), /* Descriptor is owned by NIC */
183	RTASE_RING_END = BIT(30), /* End of descriptor ring */
184};
185
186enum rtase_sw_flag_content {
187	RTASE_SWF_MSI_ENABLED  = BIT(1),
188	RTASE_SWF_MSIX_ENABLED = BIT(2),
189};
190
191#define RSVD_MASK 0x3FFFC000
192
193struct rtase_tx_desc {
194	__le32 opts1;
195	__le32 opts2;
196	__le64 addr;
197	__le32 opts3;
198	__le32 reserved1;
199	__le32 reserved2;
200	__le32 reserved3;
201} __packed;
202
203/*------ offset 0 of tx descriptor ------*/
204#define RTASE_TX_FIRST_FRAG BIT(29) /* Tx First segment of a packet */
205#define RTASE_TX_LAST_FRAG  BIT(28) /* Tx Final segment of a packet */
206#define RTASE_GIANT_SEND_V4 BIT(26) /* TCP Giant Send Offload V4 (GSOv4) */
207#define RTASE_GIANT_SEND_V6 BIT(25) /* TCP Giant Send Offload V6 (GSOv6) */
208#define RTASE_TX_VLAN_TAG   BIT(17) /* Add VLAN tag */
209
210/*------ offset 4 of tx descriptor ------*/
211#define RTASE_TX_UDPCS_C BIT(31) /* Calculate UDP/IP checksum */
212#define RTASE_TX_TCPCS_C BIT(30) /* Calculate TCP/IP checksum */
213#define RTASE_TX_IPCS_C  BIT(29) /* Calculate IP checksum */
214#define RTASE_TX_IPV6F_C BIT(28) /* Indicate it is an IPv6 packet */
215
216union rtase_rx_desc {
217	struct {
218		__le64 header_buf_addr;
219		__le32 reserved1;
220		__le32 opts_header_len;
221		__le64 addr;
222		__le32 reserved2;
223		__le32 opts1;
224	} __packed desc_cmd;
225
226	struct {
227		__le32 reserved1;
228		__le32 reserved2;
229		__le32 rss;
230		__le32 opts4;
231		__le32 reserved3;
232		__le32 opts3;
233		__le32 opts2;
234		__le32 opts1;
235	} __packed desc_status;
236} __packed;
237
238/*------ offset 28 of rx descriptor ------*/
239#define RTASE_RX_FIRST_FRAG BIT(25) /* Rx First segment of a packet */
240#define RTASE_RX_LAST_FRAG  BIT(24) /* Rx Final segment of a packet */
241#define RTASE_RX_RES        BIT(20)
242#define RTASE_RX_RUNT       BIT(19)
243#define RTASE_RX_RWT        BIT(18)
244#define RTASE_RX_CRC        BIT(17)
245#define RTASE_RX_V6F        BIT(31)
246#define RTASE_RX_V4F        BIT(30)
247#define RTASE_RX_UDPT       BIT(29)
248#define RTASE_RX_TCPT       BIT(28)
249#define RTASE_RX_IPF        BIT(26) /* IP checksum failed */
250#define RTASE_RX_UDPF       BIT(25) /* UDP/IP checksum failed */
251#define RTASE_RX_TCPF       BIT(24) /* TCP/IP checksum failed */
252#define RTASE_RX_VLAN_TAG   BIT(16) /* VLAN tag available */
253
254#define RTASE_NUM_DESC          1024
255#define RTASE_TX_BUDGET_DEFAULT 256
256#define RTASE_TX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(struct rtase_tx_desc))
257#define RTASE_RX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(union rtase_rx_desc))
258#define RTASE_TX_STOP_THRS      (MAX_SKB_FRAGS + 1)
259#define RTASE_TX_START_THRS     (2 * RTASE_TX_STOP_THRS)
260#define RTASE_VLAN_TAG_MASK     GENMASK(15, 0)
261#define RTASE_RX_PKT_SIZE_MASK  GENMASK(13, 0)
262
263/* txqos hardware definitions */
264#define RTASE_1T_CLOCK            64
265#define RTASE_1T_POWER            10000000
266#define RTASE_IDLESLOPE_INT_SHIFT 25
267#define RTASE_IDLESLOPE_INT_MASK  GENMASK(31, 25)
268
269#define RTASE_IVEC_NAME_SIZE (IFNAMSIZ + 10)
270
271struct rtase_int_vector {
272	struct rtase_private *tp;
273	unsigned int irq;
274	char name[RTASE_IVEC_NAME_SIZE];
275	u16 index;
276	u16 imr_addr;
277	u16 isr_addr;
278	u32 imr;
279	struct list_head ring_list;
280	struct napi_struct napi;
281	int (*poll)(struct napi_struct *napi, int budget);
282};
283
284struct rtase_ring {
285	struct rtase_int_vector *ivec;
286	void *desc;
287	dma_addr_t phy_addr;
288	u32 cur_idx;
289	u32 dirty_idx;
290	u16 index;
291	u8 type;
292
293	struct sk_buff *skbuff[RTASE_NUM_DESC];
294	void *data_buf[RTASE_NUM_DESC];
295	union {
296		u32 len[RTASE_NUM_DESC];
297		dma_addr_t data_phy_addr[RTASE_NUM_DESC];
298	} mis;
299
300	struct list_head ring_entry;
301	int (*ring_handler)(struct rtase_ring *ring, int budget);
302	u64 alloc_fail;
303};
304
305struct rtase_txqos {
306	int hicredit;
307	int locredit;
308	int idleslope;
309	int sendslope;
310};
311
312struct rtase_stats {
313	u64 tx_dropped;
314	u64 rx_dropped;
315	u64 multicast;
316	u64 rx_errors;
317	u64 rx_length_errors;
318	u64 rx_crc_errors;
319};
320
321struct rtase_private {
322	void __iomem *mmio_addr;
323	u32 sw_flag;
324
325	struct pci_dev *pdev;
326	struct net_device *dev;
327	u32 rx_buf_sz;
328
329	struct page_pool *page_pool;
330	struct rtase_ring tx_ring[RTASE_NUM_TX_QUEUE];
331	struct rtase_txqos tx_qos[RTASE_NUM_TX_QUEUE];
332	struct rtase_ring rx_ring[RTASE_NUM_RX_QUEUE];
333	struct rtase_counters *tally_vaddr;
334	dma_addr_t tally_paddr;
335
336	u32 vlan_filter_ctrl;
337	u16 vlan_filter_vid[RTASE_VLAN_FILTER_ENTRY_NUM];
338
339	struct msix_entry msix_entry[RTASE_NUM_MSIX];
340	struct rtase_int_vector int_vector[RTASE_NUM_MSIX];
341
342	struct rtase_stats stats;
343
344	u16 tx_queue_ctrl;
345	u16 func_tx_queue_num;
346	u16 func_rx_queue_num;
347	u16 int_nums;
348	u16 tx_int_mit;
349	u16 rx_int_mit;
350
351	u32 hw_ver;
352};
353
354#define RTASE_LSO_64K 64000
355
356#define RTASE_NIC_MAX_PHYS_BUF_COUNT_LSO2 (16 * 4)
357
358#define RTASE_TCPHO_MASK GENMASK(24, 18)
359
360#define RTASE_MSS_MASK GENMASK(28, 18)
361
362#endif /* RTASE_H */