ppe_regs.h

  1/* SPDX-License-Identifier: GPL-2.0-only
  2 *
  3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  4 */
  5
  6/* PPE hardware register and table declarations. */
  7#ifndef __PPE_REGS_H__
  8#define __PPE_REGS_H__
  9
 10#include <linux/bitfield.h>
 11
 12/* PPE scheduler configurations for buffer manager block. */
 13#define PPE_BM_SCH_CTRL_ADDR			0xb000
 14#define PPE_BM_SCH_CTRL_INC			4
 15#define PPE_BM_SCH_CTRL_SCH_DEPTH		GENMASK(7, 0)
 16#define PPE_BM_SCH_CTRL_SCH_OFFSET		GENMASK(14, 8)
 17#define PPE_BM_SCH_CTRL_SCH_EN			BIT(31)
 18
 19/* PPE drop counters. */
 20#define PPE_DROP_CNT_TBL_ADDR			0xb024
 21#define PPE_DROP_CNT_TBL_ENTRIES		8
 22#define PPE_DROP_CNT_TBL_INC			4
 23
 24/* BM port drop counters. */
 25#define PPE_DROP_STAT_TBL_ADDR			0xe000
 26#define PPE_DROP_STAT_TBL_ENTRIES		30
 27#define PPE_DROP_STAT_TBL_INC			0x10
 28
 29/* Egress VLAN counters. */
 30#define PPE_EG_VSI_COUNTER_TBL_ADDR		0x41000
 31#define PPE_EG_VSI_COUNTER_TBL_ENTRIES		64
 32#define PPE_EG_VSI_COUNTER_TBL_INC		0x10
 33
 34/* Port TX counters. */
 35#define PPE_PORT_TX_COUNTER_TBL_ADDR		0x45000
 36#define PPE_PORT_TX_COUNTER_TBL_ENTRIES		8
 37#define PPE_PORT_TX_COUNTER_TBL_INC		0x10
 38
 39/* Virtual port TX counters. */
 40#define PPE_VPORT_TX_COUNTER_TBL_ADDR		0x47000
 41#define PPE_VPORT_TX_COUNTER_TBL_ENTRIES	256
 42#define PPE_VPORT_TX_COUNTER_TBL_INC		0x10
 43
 44/* Queue counters. */
 45#define PPE_QUEUE_TX_COUNTER_TBL_ADDR		0x4a000
 46#define PPE_QUEUE_TX_COUNTER_TBL_ENTRIES	300
 47#define PPE_QUEUE_TX_COUNTER_TBL_INC		0x10
 48
 49/* RSS settings are to calculate the random RSS hash value generated during
 50 * packet receive to ARM cores. This hash is then used to generate the queue
 51 * offset used to determine the queue used to transmit the packet to ARM cores.
 52 */
 53#define PPE_RSS_HASH_MASK_ADDR			0xb4318
 54#define PPE_RSS_HASH_MASK_HASH_MASK		GENMASK(20, 0)
 55#define PPE_RSS_HASH_MASK_FRAGMENT		BIT(28)
 56
 57#define PPE_RSS_HASH_SEED_ADDR			0xb431c
 58#define PPE_RSS_HASH_SEED_VAL			GENMASK(31, 0)
 59
 60#define PPE_RSS_HASH_MIX_ADDR			0xb4320
 61#define PPE_RSS_HASH_MIX_ENTRIES		11
 62#define PPE_RSS_HASH_MIX_INC			4
 63#define PPE_RSS_HASH_MIX_VAL			GENMASK(4, 0)
 64
 65#define PPE_RSS_HASH_FIN_ADDR			0xb4350
 66#define PPE_RSS_HASH_FIN_ENTRIES		5
 67#define PPE_RSS_HASH_FIN_INC			4
 68#define PPE_RSS_HASH_FIN_INNER			GENMASK(4, 0)
 69#define PPE_RSS_HASH_FIN_OUTER			GENMASK(9, 5)
 70
 71#define PPE_RSS_HASH_MASK_IPV4_ADDR		0xb4380
 72#define PPE_RSS_HASH_MASK_IPV4_HASH_MASK	GENMASK(20, 0)
 73#define PPE_RSS_HASH_MASK_IPV4_FRAGMENT		BIT(28)
 74
 75#define PPE_RSS_HASH_SEED_IPV4_ADDR		0xb4384
 76#define PPE_RSS_HASH_SEED_IPV4_VAL		GENMASK(31, 0)
 77
 78#define PPE_RSS_HASH_MIX_IPV4_ADDR		0xb4390
 79#define PPE_RSS_HASH_MIX_IPV4_ENTRIES		5
 80#define PPE_RSS_HASH_MIX_IPV4_INC		4
 81#define PPE_RSS_HASH_MIX_IPV4_VAL		GENMASK(4, 0)
 82
 83#define PPE_RSS_HASH_FIN_IPV4_ADDR		0xb43b0
 84#define PPE_RSS_HASH_FIN_IPV4_ENTRIES		5
 85#define PPE_RSS_HASH_FIN_IPV4_INC		4
 86#define PPE_RSS_HASH_FIN_IPV4_INNER		GENMASK(4, 0)
 87#define PPE_RSS_HASH_FIN_IPV4_OUTER		GENMASK(9, 5)
 88
 89#define PPE_BM_SCH_CFG_TBL_ADDR			0xc000
 90#define PPE_BM_SCH_CFG_TBL_ENTRIES		128
 91#define PPE_BM_SCH_CFG_TBL_INC			0x10
 92#define PPE_BM_SCH_CFG_TBL_PORT_NUM		GENMASK(3, 0)
 93#define PPE_BM_SCH_CFG_TBL_DIR			BIT(4)
 94#define PPE_BM_SCH_CFG_TBL_VALID		BIT(5)
 95#define PPE_BM_SCH_CFG_TBL_SECOND_PORT_VALID	BIT(6)
 96#define PPE_BM_SCH_CFG_TBL_SECOND_PORT		GENMASK(11, 8)
 97
 98/* PPE service code configuration for the ingress direction functions,
 99 * including bypass configuration for relevant PPE switch core functions
100 * such as flow entry lookup bypass.
101 */
102#define PPE_SERVICE_TBL_ADDR			0x15000
103#define PPE_SERVICE_TBL_ENTRIES			256
104#define PPE_SERVICE_TBL_INC			0x10
105#define PPE_SERVICE_W0_BYPASS_BITMAP		GENMASK(31, 0)
106#define PPE_SERVICE_W1_RX_CNT_EN		BIT(0)
107
108#define PPE_SERVICE_SET_BYPASS_BITMAP(tbl_cfg, value)	\
109	FIELD_MODIFY(PPE_SERVICE_W0_BYPASS_BITMAP, tbl_cfg, value)
110#define PPE_SERVICE_SET_RX_CNT_EN(tbl_cfg, value)	\
111	FIELD_MODIFY(PPE_SERVICE_W1_RX_CNT_EN, (tbl_cfg) + 0x1, value)
112
113/* PPE port egress VLAN configurations. */
114#define PPE_PORT_EG_VLAN_TBL_ADDR		0x20020
115#define PPE_PORT_EG_VLAN_TBL_ENTRIES		8
116#define PPE_PORT_EG_VLAN_TBL_INC		4
117#define PPE_PORT_EG_VLAN_TBL_VLAN_TYPE		BIT(0)
118#define PPE_PORT_EG_VLAN_TBL_CTAG_MODE		GENMASK(2, 1)
119#define PPE_PORT_EG_VLAN_TBL_STAG_MODE		GENMASK(4, 3)
120#define PPE_PORT_EG_VLAN_TBL_VSI_TAG_MODE_EN	BIT(5)
121#define PPE_PORT_EG_VLAN_TBL_PCP_PROP_CMD	BIT(6)
122#define PPE_PORT_EG_VLAN_TBL_DEI_PROP_CMD	BIT(7)
123#define PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN	BIT(8)
124
125/* PPE queue counters enable/disable control. */
126#define PPE_EG_BRIDGE_CONFIG_ADDR		0x20044
127#define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN	BIT(2)
128
129/* PPE service code configuration on the egress direction. */
130#define PPE_EG_SERVICE_TBL_ADDR			0x43000
131#define PPE_EG_SERVICE_TBL_ENTRIES		256
132#define PPE_EG_SERVICE_TBL_INC			0x10
133#define PPE_EG_SERVICE_W0_UPDATE_ACTION		GENMASK(31, 0)
134#define PPE_EG_SERVICE_W1_NEXT_SERVCODE		GENMASK(7, 0)
135#define PPE_EG_SERVICE_W1_HW_SERVICE		GENMASK(13, 8)
136#define PPE_EG_SERVICE_W1_OFFSET_SEL		BIT(14)
137#define PPE_EG_SERVICE_W1_TX_CNT_EN		BIT(15)
138
139#define PPE_EG_SERVICE_SET_UPDATE_ACTION(tbl_cfg, value)	\
140	FIELD_MODIFY(PPE_EG_SERVICE_W0_UPDATE_ACTION, tbl_cfg, value)
141#define PPE_EG_SERVICE_SET_NEXT_SERVCODE(tbl_cfg, value)	\
142	FIELD_MODIFY(PPE_EG_SERVICE_W1_NEXT_SERVCODE, (tbl_cfg) + 0x1, value)
143#define PPE_EG_SERVICE_SET_HW_SERVICE(tbl_cfg, value)	\
144	FIELD_MODIFY(PPE_EG_SERVICE_W1_HW_SERVICE, (tbl_cfg) + 0x1, value)
145#define PPE_EG_SERVICE_SET_OFFSET_SEL(tbl_cfg, value)	\
146	FIELD_MODIFY(PPE_EG_SERVICE_W1_OFFSET_SEL, (tbl_cfg) + 0x1, value)
147#define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value)	\
148	FIELD_MODIFY(PPE_EG_SERVICE_W1_TX_CNT_EN, (tbl_cfg) + 0x1, value)
149
150/* PPE port bridge configuration */
151#define PPE_PORT_BRIDGE_CTRL_ADDR		0x60300
152#define PPE_PORT_BRIDGE_CTRL_ENTRIES		8
153#define PPE_PORT_BRIDGE_CTRL_INC		4
154#define PPE_PORT_BRIDGE_NEW_LRN_EN		BIT(0)
155#define PPE_PORT_BRIDGE_STA_MOVE_LRN_EN		BIT(3)
156#define PPE_PORT_BRIDGE_TXMAC_EN		BIT(16)
157
158/* PPE port control configurations for the traffic to the multicast queues. */
159#define PPE_MC_MTU_CTRL_TBL_ADDR		0x60a00
160#define PPE_MC_MTU_CTRL_TBL_ENTRIES		8
161#define PPE_MC_MTU_CTRL_TBL_INC			4
162#define PPE_MC_MTU_CTRL_TBL_MTU			GENMASK(13, 0)
163#define PPE_MC_MTU_CTRL_TBL_MTU_CMD		GENMASK(15, 14)
164#define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN		BIT(16)
165
166/* PPE VSI configurations */
167#define PPE_VSI_TBL_ADDR			0x63800
168#define PPE_VSI_TBL_ENTRIES			64
169#define PPE_VSI_TBL_INC				0x10
170#define PPE_VSI_W0_MEMBER_PORT_BITMAP		GENMASK(7, 0)
171#define PPE_VSI_W0_UUC_BITMAP			GENMASK(15, 8)
172#define PPE_VSI_W0_UMC_BITMAP			GENMASK(23, 16)
173#define PPE_VSI_W0_BC_BITMAP			GENMASK(31, 24)
174#define PPE_VSI_W1_NEW_ADDR_LRN_EN		BIT(0)
175#define PPE_VSI_W1_NEW_ADDR_FWD_CMD		GENMASK(2, 1)
176#define PPE_VSI_W1_STATION_MOVE_LRN_EN		BIT(3)
177#define PPE_VSI_W1_STATION_MOVE_FWD_CMD		GENMASK(5, 4)
178
179#define PPE_VSI_SET_MEMBER_PORT_BITMAP(tbl_cfg, value)		\
180	FIELD_MODIFY(PPE_VSI_W0_MEMBER_PORT_BITMAP, tbl_cfg, value)
181#define PPE_VSI_SET_UUC_BITMAP(tbl_cfg, value)			\
182	FIELD_MODIFY(PPE_VSI_W0_UUC_BITMAP, tbl_cfg, value)
183#define PPE_VSI_SET_UMC_BITMAP(tbl_cfg, value)			\
184	FIELD_MODIFY(PPE_VSI_W0_UMC_BITMAP, tbl_cfg, value)
185#define PPE_VSI_SET_BC_BITMAP(tbl_cfg, value)			\
186	FIELD_MODIFY(PPE_VSI_W0_BC_BITMAP, tbl_cfg, value)
187#define PPE_VSI_SET_NEW_ADDR_LRN_EN(tbl_cfg, value)		\
188	FIELD_MODIFY(PPE_VSI_W1_NEW_ADDR_LRN_EN, (tbl_cfg) + 0x1, value)
189#define PPE_VSI_SET_NEW_ADDR_FWD_CMD(tbl_cfg, value)		\
190	FIELD_MODIFY(PPE_VSI_W1_NEW_ADDR_FWD_CMD, (tbl_cfg) + 0x1, value)
191#define PPE_VSI_SET_STATION_MOVE_LRN_EN(tbl_cfg, value)		\
192	FIELD_MODIFY(PPE_VSI_W1_STATION_MOVE_LRN_EN, (tbl_cfg) + 0x1, value)
193#define PPE_VSI_SET_STATION_MOVE_FWD_CMD(tbl_cfg, value)	\
194	FIELD_MODIFY(PPE_VSI_W1_STATION_MOVE_FWD_CMD, (tbl_cfg) + 0x1, value)
195
196/* PPE port control configurations for the traffic to the unicast queues. */
197#define PPE_MRU_MTU_CTRL_TBL_ADDR		0x65000
198#define PPE_MRU_MTU_CTRL_TBL_ENTRIES		256
199#define PPE_MRU_MTU_CTRL_TBL_INC		0x10
200#define PPE_MRU_MTU_CTRL_W0_MRU			GENMASK(13, 0)
201#define PPE_MRU_MTU_CTRL_W0_MRU_CMD		GENMASK(15, 14)
202#define PPE_MRU_MTU_CTRL_W0_MTU			GENMASK(29, 16)
203#define PPE_MRU_MTU_CTRL_W0_MTU_CMD		GENMASK(31, 30)
204#define PPE_MRU_MTU_CTRL_W1_RX_CNT_EN		BIT(0)
205#define PPE_MRU_MTU_CTRL_W1_TX_CNT_EN		BIT(1)
206#define PPE_MRU_MTU_CTRL_W1_SRC_PROFILE		GENMASK(3, 2)
207#define PPE_MRU_MTU_CTRL_W1_INNER_PREC_LOW	BIT(31)
208#define PPE_MRU_MTU_CTRL_W2_INNER_PREC_HIGH	GENMASK(1, 0)
209
210#define PPE_MRU_MTU_CTRL_SET_MRU(tbl_cfg, value)	\
211	FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MRU, tbl_cfg, value)
212#define PPE_MRU_MTU_CTRL_SET_MRU_CMD(tbl_cfg, value)	\
213	FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MRU_CMD, tbl_cfg, value)
214#define PPE_MRU_MTU_CTRL_SET_MTU(tbl_cfg, value)	\
215	FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MTU, tbl_cfg, value)
216#define PPE_MRU_MTU_CTRL_SET_MTU_CMD(tbl_cfg, value)	\
217	FIELD_MODIFY(PPE_MRU_MTU_CTRL_W0_MTU_CMD, tbl_cfg, value)
218#define PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(tbl_cfg, value)	\
219	FIELD_MODIFY(PPE_MRU_MTU_CTRL_W1_RX_CNT_EN, (tbl_cfg) + 0x1, value)
220#define PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(tbl_cfg, value)	\
221	FIELD_MODIFY(PPE_MRU_MTU_CTRL_W1_TX_CNT_EN, (tbl_cfg) + 0x1, value)
222
223/* PPE service code configuration for destination port and counter. */
224#define PPE_IN_L2_SERVICE_TBL_ADDR		0x66000
225#define PPE_IN_L2_SERVICE_TBL_ENTRIES		256
226#define PPE_IN_L2_SERVICE_TBL_INC		0x10
227#define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID_VALID	BIT(0)
228#define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID	GENMASK(4, 1)
229#define PPE_IN_L2_SERVICE_TBL_DST_DIRECTION	BIT(5)
230#define PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP	GENMASK(29, 6)
231#define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN		BIT(30)
232#define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN		BIT(31)
233
234/* L2 Port configurations */
235#define PPE_L2_VP_PORT_TBL_ADDR			0x98000
236#define PPE_L2_VP_PORT_TBL_ENTRIES		256
237#define PPE_L2_VP_PORT_TBL_INC			0x10
238#define PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN	BIT(0)
239#define PPE_L2_VP_PORT_W0_DST_INFO		GENMASK(9, 2)
240
241#define PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(tbl_cfg, value)	\
242	FIELD_MODIFY(PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN, tbl_cfg, value)
243#define PPE_L2_PORT_SET_DST_INFO(tbl_cfg, value)		\
244	FIELD_MODIFY(PPE_L2_VP_PORT_W0_DST_INFO, tbl_cfg, value)
245
246/* Port RX and RX drop counters. */
247#define PPE_PORT_RX_CNT_TBL_ADDR		0x150000
248#define PPE_PORT_RX_CNT_TBL_ENTRIES		256
249#define PPE_PORT_RX_CNT_TBL_INC			0x20
250
251/* Physical port RX and RX drop counters. */
252#define PPE_PHY_PORT_RX_CNT_TBL_ADDR		0x156000
253#define PPE_PHY_PORT_RX_CNT_TBL_ENTRIES		8
254#define PPE_PHY_PORT_RX_CNT_TBL_INC		0x20
255
256/* Counters for the packet to CPU port. */
257#define PPE_DROP_CPU_CNT_TBL_ADDR		0x160000
258#define PPE_DROP_CPU_CNT_TBL_ENTRIES		1280
259#define PPE_DROP_CPU_CNT_TBL_INC		0x10
260
261/* VLAN counters. */
262#define PPE_VLAN_CNT_TBL_ADDR			0x178000
263#define PPE_VLAN_CNT_TBL_ENTRIES		64
264#define PPE_VLAN_CNT_TBL_INC			0x10
265
266/* PPE L2 counters. */
267#define PPE_PRE_L2_CNT_TBL_ADDR			0x17c000
268#define PPE_PRE_L2_CNT_TBL_ENTRIES		64
269#define PPE_PRE_L2_CNT_TBL_INC			0x20
270
271/* Port TX drop counters. */
272#define PPE_PORT_TX_DROP_CNT_TBL_ADDR		0x17d000
273#define PPE_PORT_TX_DROP_CNT_TBL_ENTRIES	8
274#define PPE_PORT_TX_DROP_CNT_TBL_INC		0x10
275
276/* Virtual port TX counters. */
277#define PPE_VPORT_TX_DROP_CNT_TBL_ADDR		0x17e000
278#define PPE_VPORT_TX_DROP_CNT_TBL_ENTRIES	256
279#define PPE_VPORT_TX_DROP_CNT_TBL_INC		0x10
280
281/* Counters for the tunnel packet. */
282#define PPE_TPR_PKT_CNT_TBL_ADDR		0x1d0080
283#define PPE_TPR_PKT_CNT_TBL_ENTRIES		8
284#define PPE_TPR_PKT_CNT_TBL_INC			4
285
286/* Counters for the all packet received. */
287#define PPE_IPR_PKT_CNT_TBL_ADDR		0x1e0080
288#define PPE_IPR_PKT_CNT_TBL_ENTRIES		8
289#define PPE_IPR_PKT_CNT_TBL_INC			4
290
291/* PPE service code configuration for the tunnel packet. */
292#define PPE_TL_SERVICE_TBL_ADDR			0x306000
293#define PPE_TL_SERVICE_TBL_ENTRIES		256
294#define PPE_TL_SERVICE_TBL_INC			4
295#define PPE_TL_SERVICE_TBL_BYPASS_BITMAP	GENMASK(31, 0)
296
297/* Port scheduler global config. */
298#define PPE_PSCH_SCH_DEPTH_CFG_ADDR		0x400000
299#define PPE_PSCH_SCH_DEPTH_CFG_INC		4
300#define PPE_PSCH_SCH_DEPTH_CFG_SCH_DEPTH	GENMASK(7, 0)
301
302/* PPE queue level scheduler configurations. */
303#define PPE_L0_FLOW_MAP_TBL_ADDR		0x402000
304#define PPE_L0_FLOW_MAP_TBL_ENTRIES		300
305#define PPE_L0_FLOW_MAP_TBL_INC			0x10
306#define PPE_L0_FLOW_MAP_TBL_FLOW_ID		GENMASK(5, 0)
307#define PPE_L0_FLOW_MAP_TBL_C_PRI		GENMASK(8, 6)
308#define PPE_L0_FLOW_MAP_TBL_E_PRI		GENMASK(11, 9)
309#define PPE_L0_FLOW_MAP_TBL_C_NODE_WT		GENMASK(21, 12)
310#define PPE_L0_FLOW_MAP_TBL_E_NODE_WT		GENMASK(31, 22)
311
312#define PPE_L0_C_FLOW_CFG_TBL_ADDR		0x404000
313#define PPE_L0_C_FLOW_CFG_TBL_ENTRIES		512
314#define PPE_L0_C_FLOW_CFG_TBL_INC		0x10
315#define PPE_L0_C_FLOW_CFG_TBL_NODE_ID		GENMASK(7, 0)
316#define PPE_L0_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT	BIT(8)
317
318#define PPE_L0_E_FLOW_CFG_TBL_ADDR		0x406000
319#define PPE_L0_E_FLOW_CFG_TBL_ENTRIES		512
320#define PPE_L0_E_FLOW_CFG_TBL_INC		0x10
321#define PPE_L0_E_FLOW_CFG_TBL_NODE_ID		GENMASK(7, 0)
322#define PPE_L0_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT	BIT(8)
323
324#define PPE_L0_FLOW_PORT_MAP_TBL_ADDR		0x408000
325#define PPE_L0_FLOW_PORT_MAP_TBL_ENTRIES	300
326#define PPE_L0_FLOW_PORT_MAP_TBL_INC		0x10
327#define PPE_L0_FLOW_PORT_MAP_TBL_PORT_NUM	GENMASK(3, 0)
328
329#define PPE_L0_COMP_CFG_TBL_ADDR		0x428000
330#define PPE_L0_COMP_CFG_TBL_ENTRIES		300
331#define PPE_L0_COMP_CFG_TBL_INC			0x10
332#define PPE_L0_COMP_CFG_TBL_SHAPER_METER_LEN	GENMASK(1, 0)
333#define PPE_L0_COMP_CFG_TBL_NODE_METER_LEN	GENMASK(3, 2)
334
335/* PPE queue to Ethernet DMA ring mapping table. */
336#define PPE_RING_Q_MAP_TBL_ADDR			0x42a000
337#define PPE_RING_Q_MAP_TBL_ENTRIES		24
338#define PPE_RING_Q_MAP_TBL_INC			0x40
339
340/* Table addresses for per-queue dequeue setting. */
341#define PPE_DEQ_OPR_TBL_ADDR			0x430000
342#define PPE_DEQ_OPR_TBL_ENTRIES			300
343#define PPE_DEQ_OPR_TBL_INC			0x10
344#define PPE_DEQ_OPR_TBL_DEQ_DISABLE		BIT(0)
345
346/* PPE flow level scheduler configurations. */
347#define PPE_L1_FLOW_MAP_TBL_ADDR		0x440000
348#define PPE_L1_FLOW_MAP_TBL_ENTRIES		64
349#define PPE_L1_FLOW_MAP_TBL_INC			0x10
350#define PPE_L1_FLOW_MAP_TBL_FLOW_ID		GENMASK(3, 0)
351#define PPE_L1_FLOW_MAP_TBL_C_PRI		GENMASK(6, 4)
352#define PPE_L1_FLOW_MAP_TBL_E_PRI		GENMASK(9, 7)
353#define PPE_L1_FLOW_MAP_TBL_C_NODE_WT		GENMASK(19, 10)
354#define PPE_L1_FLOW_MAP_TBL_E_NODE_WT		GENMASK(29, 20)
355
356#define PPE_L1_C_FLOW_CFG_TBL_ADDR		0x442000
357#define PPE_L1_C_FLOW_CFG_TBL_ENTRIES		64
358#define PPE_L1_C_FLOW_CFG_TBL_INC		0x10
359#define PPE_L1_C_FLOW_CFG_TBL_NODE_ID		GENMASK(5, 0)
360#define PPE_L1_C_FLOW_CFG_TBL_NODE_CREDIT_UNIT	BIT(6)
361
362#define PPE_L1_E_FLOW_CFG_TBL_ADDR		0x444000
363#define PPE_L1_E_FLOW_CFG_TBL_ENTRIES		64
364#define PPE_L1_E_FLOW_CFG_TBL_INC		0x10
365#define PPE_L1_E_FLOW_CFG_TBL_NODE_ID		GENMASK(5, 0)
366#define PPE_L1_E_FLOW_CFG_TBL_NODE_CREDIT_UNIT	BIT(6)
367
368#define PPE_L1_FLOW_PORT_MAP_TBL_ADDR		0x446000
369#define PPE_L1_FLOW_PORT_MAP_TBL_ENTRIES	64
370#define PPE_L1_FLOW_PORT_MAP_TBL_INC		0x10
371#define PPE_L1_FLOW_PORT_MAP_TBL_PORT_NUM	GENMASK(3, 0)
372
373#define PPE_L1_COMP_CFG_TBL_ADDR		0x46a000
374#define PPE_L1_COMP_CFG_TBL_ENTRIES		64
375#define PPE_L1_COMP_CFG_TBL_INC			0x10
376#define PPE_L1_COMP_CFG_TBL_SHAPER_METER_LEN	GENMASK(1, 0)
377#define PPE_L1_COMP_CFG_TBL_NODE_METER_LEN	GENMASK(3, 2)
378
379/* PPE port scheduler configurations for egress. */
380#define PPE_PSCH_SCH_CFG_TBL_ADDR		0x47a000
381#define PPE_PSCH_SCH_CFG_TBL_ENTRIES		128
382#define PPE_PSCH_SCH_CFG_TBL_INC		0x10
383#define PPE_PSCH_SCH_CFG_TBL_DES_PORT		GENMASK(3, 0)
384#define PPE_PSCH_SCH_CFG_TBL_ENS_PORT		GENMASK(7, 4)
385#define PPE_PSCH_SCH_CFG_TBL_ENS_PORT_BITMAP	GENMASK(15, 8)
386#define PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT_EN	BIT(16)
387#define PPE_PSCH_SCH_CFG_TBL_DES_SECOND_PORT	GENMASK(20, 17)
388
389/* There are 15 BM ports and 4 BM groups supported by PPE.
390 * BM port (0-7) is for EDMA port 0, BM port (8-13) is for
391 * PPE physical port 1-6 and BM port 14 is for EIP port.
392 */
393#define PPE_BM_PORT_FC_MODE_ADDR		0x600100
394#define PPE_BM_PORT_FC_MODE_ENTRIES		15
395#define PPE_BM_PORT_FC_MODE_INC			0x4
396#define PPE_BM_PORT_FC_MODE_EN			BIT(0)
397
398#define PPE_BM_PORT_GROUP_ID_ADDR		0x600180
399#define PPE_BM_PORT_GROUP_ID_ENTRIES		15
400#define PPE_BM_PORT_GROUP_ID_INC		0x4
401#define PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID	GENMASK(1, 0)
402
403/* Counters for PPE buffers used for packets cached. */
404#define PPE_BM_USED_CNT_TBL_ADDR		0x6001c0
405#define PPE_BM_USED_CNT_TBL_ENTRIES		15
406#define PPE_BM_USED_CNT_TBL_INC			0x4
407#define PPE_BM_USED_CNT_VAL			GENMASK(10, 0)
408
409/* Counters for PPE buffers used for packets received after pause frame sent. */
410#define PPE_BM_REACT_CNT_TBL_ADDR		0x600240
411#define PPE_BM_REACT_CNT_TBL_ENTRIES		15
412#define PPE_BM_REACT_CNT_TBL_INC		0x4
413#define PPE_BM_REACT_CNT_VAL			GENMASK(8, 0)
414
415#define PPE_BM_SHARED_GROUP_CFG_ADDR		0x600290
416#define PPE_BM_SHARED_GROUP_CFG_ENTRIES		4
417#define PPE_BM_SHARED_GROUP_CFG_INC		0x4
418#define PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT	GENMASK(10, 0)
419
420#define PPE_BM_PORT_FC_CFG_TBL_ADDR		0x601000
421#define PPE_BM_PORT_FC_CFG_TBL_ENTRIES		15
422#define PPE_BM_PORT_FC_CFG_TBL_INC		0x10
423#define PPE_BM_PORT_FC_W0_REACT_LIMIT		GENMASK(8, 0)
424#define PPE_BM_PORT_FC_W0_RESUME_THRESHOLD	GENMASK(17, 9)
425#define PPE_BM_PORT_FC_W0_RESUME_OFFSET		GENMASK(28, 18)
426#define PPE_BM_PORT_FC_W0_CEILING_LOW		GENMASK(31, 29)
427#define PPE_BM_PORT_FC_W1_CEILING_HIGH		GENMASK(7, 0)
428#define PPE_BM_PORT_FC_W1_WEIGHT		GENMASK(10, 8)
429#define PPE_BM_PORT_FC_W1_DYNAMIC		BIT(11)
430#define PPE_BM_PORT_FC_W1_PRE_ALLOC		GENMASK(22, 12)
431
432#define PPE_BM_PORT_FC_SET_REACT_LIMIT(tbl_cfg, value)	\
433	FIELD_MODIFY(PPE_BM_PORT_FC_W0_REACT_LIMIT, tbl_cfg, value)
434#define PPE_BM_PORT_FC_SET_RESUME_THRESHOLD(tbl_cfg, value)	\
435	FIELD_MODIFY(PPE_BM_PORT_FC_W0_RESUME_THRESHOLD, tbl_cfg, value)
436#define PPE_BM_PORT_FC_SET_RESUME_OFFSET(tbl_cfg, value)	\
437	FIELD_MODIFY(PPE_BM_PORT_FC_W0_RESUME_OFFSET, tbl_cfg, value)
438#define PPE_BM_PORT_FC_SET_CEILING_LOW(tbl_cfg, value)	\
439	FIELD_MODIFY(PPE_BM_PORT_FC_W0_CEILING_LOW, tbl_cfg, value)
440#define PPE_BM_PORT_FC_SET_CEILING_HIGH(tbl_cfg, value)	\
441	FIELD_MODIFY(PPE_BM_PORT_FC_W1_CEILING_HIGH, (tbl_cfg) + 0x1, value)
442#define PPE_BM_PORT_FC_SET_WEIGHT(tbl_cfg, value)	\
443	FIELD_MODIFY(PPE_BM_PORT_FC_W1_WEIGHT, (tbl_cfg) + 0x1, value)
444#define PPE_BM_PORT_FC_SET_DYNAMIC(tbl_cfg, value)	\
445	FIELD_MODIFY(PPE_BM_PORT_FC_W1_DYNAMIC, (tbl_cfg) + 0x1, value)
446#define PPE_BM_PORT_FC_SET_PRE_ALLOC(tbl_cfg, value)	\
447	FIELD_MODIFY(PPE_BM_PORT_FC_W1_PRE_ALLOC, (tbl_cfg) + 0x1, value)
448
449/* The queue base configurations based on destination port,
450 * service code or CPU code.
451 */
452#define PPE_UCAST_QUEUE_MAP_TBL_ADDR		0x810000
453#define PPE_UCAST_QUEUE_MAP_TBL_ENTRIES		3072
454#define PPE_UCAST_QUEUE_MAP_TBL_INC		0x10
455#define PPE_UCAST_QUEUE_MAP_TBL_PROFILE_ID	GENMASK(3, 0)
456#define PPE_UCAST_QUEUE_MAP_TBL_QUEUE_ID	GENMASK(11, 4)
457
458/* The queue offset configurations based on RSS hash value. */
459#define PPE_UCAST_HASH_MAP_TBL_ADDR		0x830000
460#define PPE_UCAST_HASH_MAP_TBL_ENTRIES		4096
461#define PPE_UCAST_HASH_MAP_TBL_INC		0x10
462#define PPE_UCAST_HASH_MAP_TBL_HASH		GENMASK(7, 0)
463
464/* The queue offset configurations based on PPE internal priority. */
465#define PPE_UCAST_PRIORITY_MAP_TBL_ADDR		0x842000
466#define PPE_UCAST_PRIORITY_MAP_TBL_ENTRIES	256
467#define PPE_UCAST_PRIORITY_MAP_TBL_INC		0x10
468#define PPE_UCAST_PRIORITY_MAP_TBL_CLASS	GENMASK(3, 0)
469
470/* PPE unicast queue (0-255) configurations. */
471#define PPE_AC_UNICAST_QUEUE_CFG_TBL_ADDR	0x848000
472#define PPE_AC_UNICAST_QUEUE_CFG_TBL_ENTRIES	256
473#define PPE_AC_UNICAST_QUEUE_CFG_TBL_INC	0x10
474#define PPE_AC_UNICAST_QUEUE_CFG_W0_EN		BIT(0)
475#define PPE_AC_UNICAST_QUEUE_CFG_W0_WRED_EN	BIT(1)
476#define PPE_AC_UNICAST_QUEUE_CFG_W0_FC_EN	BIT(2)
477#define PPE_AC_UNICAST_QUEUE_CFG_W0_CLR_AWARE	BIT(3)
478#define PPE_AC_UNICAST_QUEUE_CFG_W0_GRP_ID	GENMASK(5, 4)
479#define PPE_AC_UNICAST_QUEUE_CFG_W0_PRE_LIMIT	GENMASK(16, 6)
480#define PPE_AC_UNICAST_QUEUE_CFG_W0_DYNAMIC	BIT(17)
481#define PPE_AC_UNICAST_QUEUE_CFG_W0_WEIGHT	GENMASK(20, 18)
482#define PPE_AC_UNICAST_QUEUE_CFG_W0_THRESHOLD	GENMASK(31, 21)
483#define PPE_AC_UNICAST_QUEUE_CFG_W3_GRN_RESUME	GENMASK(23, 13)
484
485#define PPE_AC_UNICAST_QUEUE_SET_EN(tbl_cfg, value)	\
486	FIELD_MODIFY(PPE_AC_UNICAST_QUEUE_CFG_W0_EN, tbl_cfg, value)
487#define PPE_AC_UNICAST_QUEUE_SET_GRP_ID(tbl_cfg, value)	\
488	FIELD_MODIFY(PPE_AC_UNICAST_QUEUE_CFG_W0_GRP_ID, tbl_cfg, value)
489#define PPE_AC_UNICAST_QUEUE_SET_PRE_LIMIT(tbl_cfg, value)	\
490	FIELD_MODIFY(PPE_AC_UNICAST_QUEUE_CFG_W0_PRE_LIMIT, tbl_cfg, value)
491#define PPE_AC_UNICAST_QUEUE_SET_DYNAMIC(tbl_cfg, value)	\
492	FIELD_MODIFY(PPE_AC_UNICAST_QUEUE_CFG_W0_DYNAMIC, tbl_cfg, value)
493#define PPE_AC_UNICAST_QUEUE_SET_WEIGHT(tbl_cfg, value)	\
494	FIELD_MODIFY(PPE_AC_UNICAST_QUEUE_CFG_W0_WEIGHT, tbl_cfg, value)
495#define PPE_AC_UNICAST_QUEUE_SET_THRESHOLD(tbl_cfg, value)	\
496	FIELD_MODIFY(PPE_AC_UNICAST_QUEUE_CFG_W0_THRESHOLD, tbl_cfg, value)
497#define PPE_AC_UNICAST_QUEUE_SET_GRN_RESUME(tbl_cfg, value)	\
498	FIELD_MODIFY(PPE_AC_UNICAST_QUEUE_CFG_W3_GRN_RESUME, (tbl_cfg) + 0x3, value)
499
500/* PPE multicast queue (256-299) configurations. */
501#define PPE_AC_MULTICAST_QUEUE_CFG_TBL_ADDR	0x84a000
502#define PPE_AC_MULTICAST_QUEUE_CFG_TBL_ENTRIES	44
503#define PPE_AC_MULTICAST_QUEUE_CFG_TBL_INC	0x10
504#define PPE_AC_MULTICAST_QUEUE_CFG_W0_EN	BIT(0)
505#define PPE_AC_MULTICAST_QUEUE_CFG_W0_FC_EN	BIT(1)
506#define PPE_AC_MULTICAST_QUEUE_CFG_W0_CLR_AWARE	BIT(2)
507#define PPE_AC_MULTICAST_QUEUE_CFG_W0_GRP_ID	GENMASK(4, 3)
508#define PPE_AC_MULTICAST_QUEUE_CFG_W0_PRE_LIMIT	GENMASK(15, 5)
509#define PPE_AC_MULTICAST_QUEUE_CFG_W0_THRESHOLD	GENMASK(26, 16)
510#define PPE_AC_MULTICAST_QUEUE_CFG_W2_RESUME	GENMASK(17, 7)
511
512#define PPE_AC_MULTICAST_QUEUE_SET_EN(tbl_cfg, value)	\
513	FIELD_MODIFY(PPE_AC_MULTICAST_QUEUE_CFG_W0_EN, tbl_cfg, value)
514#define PPE_AC_MULTICAST_QUEUE_SET_GRN_GRP_ID(tbl_cfg, value)	\
515	FIELD_MODIFY(PPE_AC_MULTICAST_QUEUE_CFG_W0_GRP_ID, tbl_cfg, value)
516#define PPE_AC_MULTICAST_QUEUE_SET_GRN_PRE_LIMIT(tbl_cfg, value)	\
517	FIELD_MODIFY(PPE_AC_MULTICAST_QUEUE_CFG_W0_PRE_LIMIT, tbl_cfg, value)
518#define PPE_AC_MULTICAST_QUEUE_SET_GRN_THRESHOLD(tbl_cfg, value)	\
519	FIELD_MODIFY(PPE_AC_MULTICAST_QUEUE_CFG_W0_THRESHOLD, tbl_cfg, value)
520#define PPE_AC_MULTICAST_QUEUE_SET_GRN_RESUME(tbl_cfg, value)	\
521	FIELD_MODIFY(PPE_AC_MULTICAST_QUEUE_CFG_W2_RESUME, (tbl_cfg) + 0x2, value)
522
523/* PPE admission control group (0-3) configurations */
524#define PPE_AC_GRP_CFG_TBL_ADDR			0x84c000
525#define PPE_AC_GRP_CFG_TBL_ENTRIES		0x4
526#define PPE_AC_GRP_CFG_TBL_INC			0x10
527#define PPE_AC_GRP_W0_AC_EN			BIT(0)
528#define PPE_AC_GRP_W0_AC_FC_EN			BIT(1)
529#define PPE_AC_GRP_W0_CLR_AWARE			BIT(2)
530#define PPE_AC_GRP_W0_THRESHOLD_LOW		GENMASK(31, 25)
531#define PPE_AC_GRP_W1_THRESHOLD_HIGH		GENMASK(3, 0)
532#define PPE_AC_GRP_W1_BUF_LIMIT			GENMASK(14, 4)
533#define PPE_AC_GRP_W2_RESUME_GRN		GENMASK(15, 5)
534#define PPE_AC_GRP_W2_PRE_ALLOC			GENMASK(26, 16)
535
536#define PPE_AC_GRP_SET_BUF_LIMIT(tbl_cfg, value)	\
537	FIELD_MODIFY(PPE_AC_GRP_W1_BUF_LIMIT, (tbl_cfg) + 0x1, value)
538
539/* Counters for packets handled by unicast queues (0-255). */
540#define PPE_AC_UNICAST_QUEUE_CNT_TBL_ADDR	0x84e000
541#define PPE_AC_UNICAST_QUEUE_CNT_TBL_ENTRIES	256
542#define PPE_AC_UNICAST_QUEUE_CNT_TBL_INC	0x10
543#define PPE_AC_UNICAST_QUEUE_CNT_TBL_PEND_CNT	GENMASK(12, 0)
544
545/* Counters for packets handled by multicast queues (256-299). */
546#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_ADDR	0x852000
547#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_ENTRIES	44
548#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_INC	0x10
549#define PPE_AC_MULTICAST_QUEUE_CNT_TBL_PEND_CNT	GENMASK(12, 0)
550
551/* Table addresses for per-queue enqueue setting. */
552#define PPE_ENQ_OPR_TBL_ADDR			0x85c000
553#define PPE_ENQ_OPR_TBL_ENTRIES			300
554#define PPE_ENQ_OPR_TBL_INC			0x10
555#define PPE_ENQ_OPR_TBL_ENQ_DISABLE		BIT(0)
556
557/* Unicast drop count includes the possible drops with WRED for the green,
558 * yellow and red categories.
559 */
560#define PPE_UNICAST_DROP_CNT_TBL_ADDR		0x9e0000
561#define PPE_UNICAST_DROP_CNT_TBL_ENTRIES	1536
562#define PPE_UNICAST_DROP_CNT_TBL_INC		0x10
563#define PPE_UNICAST_DROP_TYPES			6
564#define PPE_UNICAST_DROP_FORCE_OFFSET		3
565
566/* There are 16 multicast queues dedicated to CPU port 0. Multicast drop
567 * count includes the force drop for green, yellow and red category packets.
568 */
569#define PPE_P0_MULTICAST_DROP_CNT_TBL_ADDR	0x9f0000
570#define PPE_P0_MULTICAST_DROP_CNT_TBL_ENTRIES	48
571#define PPE_P0_MULTICAST_DROP_CNT_TBL_INC	0x10
572#define PPE_P0_MULTICAST_QUEUE_NUM		16
573
574/* Each PPE physical port has four dedicated multicast queues, providing
575 * a total of 12 entries per port. The multicast drop count includes forced
576 * drops for green, yellow, and red category packets.
577 */
578#define PPE_MULTICAST_QUEUE_PORT_ADDR_INC	0x1000
579#define PPE_MULTICAST_DROP_CNT_TBL_INC		0x10
580#define PPE_MULTICAST_DROP_TYPES		3
581#define PPE_MULTICAST_QUEUE_NUM			4
582#define PPE_MULTICAST_DROP_CNT_TBL_ENTRIES	12
583
584#define PPE_CPU_PORT_MULTICAST_FORCE_DROP_CNT_TBL_ADDR(mq_offset)	\
585	(PPE_P0_MULTICAST_DROP_CNT_TBL_ADDR +				\
586	 (mq_offset) * PPE_P0_MULTICAST_DROP_CNT_TBL_INC *		\
587	 PPE_MULTICAST_DROP_TYPES)
588
589#define PPE_P1_MULTICAST_DROP_CNT_TBL_ADDR	\
590	(PPE_P0_MULTICAST_DROP_CNT_TBL_ADDR + PPE_MULTICAST_QUEUE_PORT_ADDR_INC)
591#endif