ppe_config.h

  1/* SPDX-License-Identifier: GPL-2.0-only
  2 *
  3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  4 */
  5
  6#ifndef __PPE_CONFIG_H__
  7#define __PPE_CONFIG_H__
  8
  9#include <linux/types.h>
 10
 11#include "ppe.h"
 12
 13/* There are different table index ranges for configuring queue base ID of
 14 * the destination port, CPU code and service code.
 15 */
 16#define PPE_QUEUE_BASE_DEST_PORT		0
 17#define PPE_QUEUE_BASE_CPU_CODE			1024
 18#define PPE_QUEUE_BASE_SERVICE_CODE		2048
 19
 20#define PPE_QUEUE_INTER_PRI_NUM			16
 21#define PPE_QUEUE_HASH_NUM			256
 22
 23/* The service code is used by EDMA port to transmit packet to PPE. */
 24#define PPE_EDMA_SC_BYPASS_ID			1
 25
 26/* The PPE RSS hash configured for IPv4 and IPv6 packet separately. */
 27#define PPE_RSS_HASH_MODE_IPV4			BIT(0)
 28#define PPE_RSS_HASH_MODE_IPV6			BIT(1)
 29#define PPE_RSS_HASH_IP_LENGTH			4
 30#define PPE_RSS_HASH_TUPLES			5
 31
 32/* PPE supports 300 queues, each bit presents as one queue. */
 33#define PPE_RING_TO_QUEUE_BITMAP_WORD_CNT	10
 34
 35/**
 36 * enum ppe_scheduler_frame_mode - PPE scheduler frame mode.
 37 * @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG,
 38 * preamble, Ethernet packet and CRC.
 39 * @PPE_SCH_WITH_FRAME_CRC: The scheduled frame includes Ethernet frame and CRC
 40 * excluding IPG and preamble.
 41 * @PPE_SCH_WITH_L3_PAYLOAD: The scheduled frame includes layer 3 packet data.
 42 */
 43enum ppe_scheduler_frame_mode {
 44	PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC = 0,
 45	PPE_SCH_WITH_FRAME_CRC = 1,
 46	PPE_SCH_WITH_L3_PAYLOAD = 2,
 47};
 48
 49/**
 50 * struct ppe_scheduler_cfg - PPE scheduler configuration.
 51 * @flow_id: PPE flow ID.
 52 * @pri: Scheduler priority.
 53 * @drr_node_id: Node ID for scheduled traffic.
 54 * @drr_node_wt: Weight for scheduled traffic.
 55 * @unit_is_packet: Packet based or byte based unit for scheduled traffic.
 56 * @frame_mode: Packet mode to be scheduled.
 57 *
 58 * PPE scheduler supports commit rate and exceed rate configurations.
 59 */
 60struct ppe_scheduler_cfg {
 61	int flow_id;
 62	int pri;
 63	int drr_node_id;
 64	int drr_node_wt;
 65	bool unit_is_packet;
 66	enum ppe_scheduler_frame_mode frame_mode;
 67};
 68
 69/**
 70 * enum ppe_resource_type - PPE resource type.
 71 * @PPE_RES_UCAST: Unicast queue resource.
 72 * @PPE_RES_MCAST: Multicast queue resource.
 73 * @PPE_RES_L0_NODE: Level 0 for queue based node resource.
 74 * @PPE_RES_L1_NODE: Level 1 for flow based node resource.
 75 * @PPE_RES_FLOW_ID: Flow based node resource.
 76 */
 77enum ppe_resource_type {
 78	PPE_RES_UCAST,
 79	PPE_RES_MCAST,
 80	PPE_RES_L0_NODE,
 81	PPE_RES_L1_NODE,
 82	PPE_RES_FLOW_ID,
 83};
 84
 85/**
 86 * struct ppe_queue_ucast_dest - PPE unicast queue destination.
 87 * @src_profile: Source profile.
 88 * @service_code_en: Enable service code to map the queue base ID.
 89 * @service_code: Service code.
 90 * @cpu_code_en: Enable CPU code to map the queue base ID.
 91 * @cpu_code: CPU code.
 92 * @dest_port: destination port.
 93 *
 94 * PPE egress queue ID is decided by the service code if enabled, otherwise
 95 * by the CPU code if enabled, or by destination port if both service code
 96 * and CPU code are disabled.
 97 */
 98struct ppe_queue_ucast_dest {
 99	int src_profile;
100	bool service_code_en;
101	int service_code;
102	bool cpu_code_en;
103	int cpu_code;
104	int dest_port;
105};
106
107/* Hardware bitmaps for bypassing features of the ingress packet. */
108enum ppe_sc_ingress_type {
109	PPE_SC_BYPASS_INGRESS_VLAN_TAG_FMT_CHECK = 0,
110	PPE_SC_BYPASS_INGRESS_VLAN_MEMBER_CHECK = 1,
111	PPE_SC_BYPASS_INGRESS_VLAN_TRANSLATE = 2,
112	PPE_SC_BYPASS_INGRESS_MY_MAC_CHECK = 3,
113	PPE_SC_BYPASS_INGRESS_DIP_LOOKUP = 4,
114	PPE_SC_BYPASS_INGRESS_FLOW_LOOKUP = 5,
115	PPE_SC_BYPASS_INGRESS_FLOW_ACTION = 6,
116	PPE_SC_BYPASS_INGRESS_ACL = 7,
117	PPE_SC_BYPASS_INGRESS_FAKE_MAC_HEADER = 8,
118	PPE_SC_BYPASS_INGRESS_SERVICE_CODE = 9,
119	PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L2 = 10,
120	PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV4 = 11,
121	PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV6 = 12,
122	PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L4 = 13,
123	PPE_SC_BYPASS_INGRESS_FLOW_SERVICE_CODE = 14,
124	PPE_SC_BYPASS_INGRESS_ACL_SERVICE_CODE = 15,
125	PPE_SC_BYPASS_INGRESS_FAKE_L2_PROTO = 16,
126	PPE_SC_BYPASS_INGRESS_PPPOE_TERMINATION = 17,
127	PPE_SC_BYPASS_INGRESS_DEFAULT_VLAN = 18,
128	PPE_SC_BYPASS_INGRESS_DEFAULT_PCP = 19,
129	PPE_SC_BYPASS_INGRESS_VSI_ASSIGN = 20,
130	/* Values 21-23 are not specified by hardware. */
131	PPE_SC_BYPASS_INGRESS_VLAN_ASSIGN_FAIL = 24,
132	PPE_SC_BYPASS_INGRESS_SOURCE_GUARD = 25,
133	PPE_SC_BYPASS_INGRESS_MRU_MTU_CHECK = 26,
134	PPE_SC_BYPASS_INGRESS_FLOW_SRC_CHECK = 27,
135	PPE_SC_BYPASS_INGRESS_FLOW_QOS = 28,
136	/* This must be last as it determines the size of the BITMAP. */
137	PPE_SC_BYPASS_INGRESS_SIZE,
138};
139
140/* Hardware bitmaps for bypassing features of the egress packet. */
141enum ppe_sc_egress_type {
142	PPE_SC_BYPASS_EGRESS_VLAN_MEMBER_CHECK = 0,
143	PPE_SC_BYPASS_EGRESS_VLAN_TRANSLATE = 1,
144	PPE_SC_BYPASS_EGRESS_VLAN_TAG_FMT_CTRL = 2,
145	PPE_SC_BYPASS_EGRESS_FDB_LEARN = 3,
146	PPE_SC_BYPASS_EGRESS_FDB_REFRESH = 4,
147	PPE_SC_BYPASS_EGRESS_L2_SOURCE_SECURITY = 5,
148	PPE_SC_BYPASS_EGRESS_MANAGEMENT_FWD = 6,
149	PPE_SC_BYPASS_EGRESS_BRIDGING_FWD = 7,
150	PPE_SC_BYPASS_EGRESS_IN_STP_FLTR = 8,
151	PPE_SC_BYPASS_EGRESS_EG_STP_FLTR = 9,
152	PPE_SC_BYPASS_EGRESS_SOURCE_FLTR = 10,
153	PPE_SC_BYPASS_EGRESS_POLICER = 11,
154	PPE_SC_BYPASS_EGRESS_L2_PKT_EDIT = 12,
155	PPE_SC_BYPASS_EGRESS_L3_PKT_EDIT = 13,
156	PPE_SC_BYPASS_EGRESS_ACL_POST_ROUTING_CHECK = 14,
157	PPE_SC_BYPASS_EGRESS_PORT_ISOLATION = 15,
158	PPE_SC_BYPASS_EGRESS_PRE_ACL_QOS = 16,
159	PPE_SC_BYPASS_EGRESS_POST_ACL_QOS = 17,
160	PPE_SC_BYPASS_EGRESS_DSCP_QOS = 18,
161	PPE_SC_BYPASS_EGRESS_PCP_QOS = 19,
162	PPE_SC_BYPASS_EGRESS_PREHEADER_QOS = 20,
163	PPE_SC_BYPASS_EGRESS_FAKE_MAC_DROP = 21,
164	PPE_SC_BYPASS_EGRESS_TUNL_CONTEXT = 22,
165	PPE_SC_BYPASS_EGRESS_FLOW_POLICER = 23,
166	/* This must be last as it determines the size of the BITMAP. */
167	PPE_SC_BYPASS_EGRESS_SIZE,
168};
169
170/* Hardware bitmaps for bypassing counter of packet. */
171enum ppe_sc_counter_type {
172	PPE_SC_BYPASS_COUNTER_RX_VLAN = 0,
173	PPE_SC_BYPASS_COUNTER_RX = 1,
174	PPE_SC_BYPASS_COUNTER_TX_VLAN = 2,
175	PPE_SC_BYPASS_COUNTER_TX = 3,
176	/* This must be last as it determines the size of the BITMAP. */
177	PPE_SC_BYPASS_COUNTER_SIZE,
178};
179
180/* Hardware bitmaps for bypassing features of tunnel packet. */
181enum ppe_sc_tunnel_type {
182	PPE_SC_BYPASS_TUNNEL_SERVICE_CODE = 0,
183	PPE_SC_BYPASS_TUNNEL_TUNNEL_HANDLE = 1,
184	PPE_SC_BYPASS_TUNNEL_L3_IF_CHECK = 2,
185	PPE_SC_BYPASS_TUNNEL_VLAN_CHECK = 3,
186	PPE_SC_BYPASS_TUNNEL_DMAC_CHECK = 4,
187	PPE_SC_BYPASS_TUNNEL_UDP_CSUM_0_CHECK = 5,
188	PPE_SC_BYPASS_TUNNEL_TBL_DE_ACCE_CHECK = 6,
189	PPE_SC_BYPASS_TUNNEL_PPPOE_MC_TERM_CHECK = 7,
190	PPE_SC_BYPASS_TUNNEL_TTL_EXCEED_CHECK = 8,
191	PPE_SC_BYPASS_TUNNEL_MAP_SRC_CHECK = 9,
192	PPE_SC_BYPASS_TUNNEL_MAP_DST_CHECK = 10,
193	PPE_SC_BYPASS_TUNNEL_LPM_DST_LOOKUP = 11,
194	PPE_SC_BYPASS_TUNNEL_LPM_LOOKUP = 12,
195	PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L2 = 13,
196	PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV4 = 14,
197	PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV6 = 15,
198	PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L4 = 16,
199	PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_TUNNEL = 17,
200	/* Values 18-19 are not specified by hardware. */
201	PPE_SC_BYPASS_TUNNEL_PRE_IPO = 20,
202	/* This must be last as it determines the size of the BITMAP. */
203	PPE_SC_BYPASS_TUNNEL_SIZE,
204};
205
206/**
207 * struct ppe_sc_bypass - PPE service bypass bitmaps
208 * @ingress: Bitmap of features that can be bypassed on the ingress packet.
209 * @egress: Bitmap of features that can be bypassed on the egress packet.
210 * @counter: Bitmap of features that can be bypassed on the counter type.
211 * @tunnel: Bitmap of features that can be bypassed on the tunnel packet.
212 */
213struct ppe_sc_bypass {
214	DECLARE_BITMAP(ingress, PPE_SC_BYPASS_INGRESS_SIZE);
215	DECLARE_BITMAP(egress, PPE_SC_BYPASS_EGRESS_SIZE);
216	DECLARE_BITMAP(counter, PPE_SC_BYPASS_COUNTER_SIZE);
217	DECLARE_BITMAP(tunnel, PPE_SC_BYPASS_TUNNEL_SIZE);
218};
219
220/**
221 * struct ppe_sc_cfg - PPE service code configuration.
222 * @dest_port_valid: Generate destination port or not.
223 * @dest_port: Destination port ID.
224 * @bitmaps: Bitmap of bypass features.
225 * @is_src: Destination port acts as source port, packet sent to CPU.
226 * @next_service_code: New service code generated.
227 * @eip_field_update_bitmap: Fields updated as actions taken for EIP.
228 * @eip_hw_service: Selected hardware functions for EIP.
229 * @eip_offset_sel: Packet offset selection, using packet's layer 4 offset
230 * or using packet's layer 3 offset for EIP.
231 *
232 * Service code is generated during the packet passing through PPE.
233 */
234struct ppe_sc_cfg {
235	bool dest_port_valid;
236	int dest_port;
237	struct ppe_sc_bypass bitmaps;
238	bool is_src;
239	int next_service_code;
240	int eip_field_update_bitmap;
241	int eip_hw_service;
242	int eip_offset_sel;
243};
244
245/**
246 * enum ppe_action_type - PPE action of the received packet.
247 * @PPE_ACTION_FORWARD: Packet forwarded per L2/L3 process.
248 * @PPE_ACTION_DROP: Packet dropped by PPE.
249 * @PPE_ACTION_COPY_TO_CPU: Packet copied to CPU port per multicast queue.
250 * @PPE_ACTION_REDIRECT_TO_CPU: Packet redirected to CPU port per unicast queue.
251 */
252enum ppe_action_type {
253	PPE_ACTION_FORWARD = 0,
254	PPE_ACTION_DROP = 1,
255	PPE_ACTION_COPY_TO_CPU = 2,
256	PPE_ACTION_REDIRECT_TO_CPU = 3,
257};
258
259/**
260 * struct ppe_rss_hash_cfg - PPE RSS hash configuration.
261 * @hash_mask: Mask of the generated hash value.
262 * @hash_fragment_mode: Hash generation mode for the first fragment of TCP,
263 * UDP and UDP-Lite packets, to use either 3 tuple or 5 tuple for RSS hash
264 * key computation.
265 * @hash_seed: Seed to generate RSS hash.
266 * @hash_sip_mix: Source IP selection.
267 * @hash_dip_mix: Destination IP selection.
268 * @hash_protocol_mix: Protocol selection.
269 * @hash_sport_mix: Source L4 port selection.
270 * @hash_dport_mix: Destination L4 port selection.
271 * @hash_fin_inner: RSS hash value first selection.
272 * @hash_fin_outer: RSS hash value second selection.
273 *
274 * PPE RSS hash value is generated for the packet based on the RSS hash
275 * configured.
276 */
277struct ppe_rss_hash_cfg {
278	u32 hash_mask;
279	bool hash_fragment_mode;
280	u32 hash_seed;
281	u8 hash_sip_mix[PPE_RSS_HASH_IP_LENGTH];
282	u8 hash_dip_mix[PPE_RSS_HASH_IP_LENGTH];
283	u8 hash_protocol_mix;
284	u8 hash_sport_mix;
285	u8 hash_dport_mix;
286	u8 hash_fin_inner[PPE_RSS_HASH_TUPLES];
287	u8 hash_fin_outer[PPE_RSS_HASH_TUPLES];
288};
289
290int ppe_hw_config(struct ppe_device *ppe_dev);
291int ppe_queue_scheduler_set(struct ppe_device *ppe_dev,
292			    int node_id, bool flow_level, int port,
293			    struct ppe_scheduler_cfg scheduler_cfg);
294int ppe_queue_ucast_base_set(struct ppe_device *ppe_dev,
295			     struct ppe_queue_ucast_dest queue_dst,
296			     int queue_base,
297			     int profile_id);
298int ppe_queue_ucast_offset_pri_set(struct ppe_device *ppe_dev,
299				   int profile_id,
300				   int priority,
301				   int queue_offset);
302int ppe_queue_ucast_offset_hash_set(struct ppe_device *ppe_dev,
303				    int profile_id,
304				    int rss_hash,
305				    int queue_offset);
306int ppe_port_resource_get(struct ppe_device *ppe_dev, int port,
307			  enum ppe_resource_type type,
308			  int *res_start, int *res_end);
309int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc,
310		      struct ppe_sc_cfg cfg);
311int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port);
312int ppe_rss_hash_config_set(struct ppe_device *ppe_dev, int mode,
313			    struct ppe_rss_hash_cfg hash_cfg);
314int ppe_ring_queue_map_set(struct ppe_device *ppe_dev,
315			   int ring_id,
316			   u32 *queue_map);
317#endif