qlcnic_sriov_common.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * QLogic qlcnic NIC Driver
   4 * Copyright (c) 2009-2013 QLogic Corporation
   5 */
   6
   7#include <linux/types.h>
   8
   9#include "qlcnic_sriov.h"
  10#include "qlcnic.h"
  11#include "qlcnic_83xx_hw.h"
  12
  13#define QLC_BC_COMMAND	0
  14#define QLC_BC_RESPONSE	1
  15
  16#define QLC_MBOX_RESP_TIMEOUT		(10 * HZ)
  17#define QLC_MBOX_CH_FREE_TIMEOUT	(10 * HZ)
  18
  19#define QLC_BC_MSG		0
  20#define QLC_BC_CFREE		1
  21#define QLC_BC_FLR		2
  22#define QLC_BC_HDR_SZ		16
  23#define QLC_BC_PAYLOAD_SZ	(1024 - QLC_BC_HDR_SZ)
  24
  25#define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF		2048
  26#define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF	512
  27
  28#define QLC_83XX_VF_RESET_FAIL_THRESH	8
  29#define QLC_BC_CMD_MAX_RETRY_CNT	5
  30
  31static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work);
  32static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *);
  33static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32);
  34static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *);
  35static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *);
  36static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *);
  37static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *,
  38				  struct qlcnic_cmd_args *);
  39static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8);
  40static void qlcnic_sriov_process_bc_cmd(struct work_struct *);
  41static int qlcnic_sriov_vf_shutdown(struct pci_dev *);
  42static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *);
  43static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *,
  44					struct qlcnic_cmd_args *);
  45
  46static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
  47	.read_crb			= qlcnic_83xx_read_crb,
  48	.write_crb			= qlcnic_83xx_write_crb,
  49	.read_reg			= qlcnic_83xx_rd_reg_indirect,
  50	.write_reg			= qlcnic_83xx_wrt_reg_indirect,
  51	.get_mac_address		= qlcnic_83xx_get_mac_address,
  52	.setup_intr			= qlcnic_83xx_setup_intr,
  53	.alloc_mbx_args			= qlcnic_83xx_alloc_mbx_args,
  54	.mbx_cmd			= qlcnic_sriov_issue_cmd,
  55	.get_func_no			= qlcnic_83xx_get_func_no,
  56	.api_lock			= qlcnic_83xx_cam_lock,
  57	.api_unlock			= qlcnic_83xx_cam_unlock,
  58	.process_lb_rcv_ring_diag	= qlcnic_83xx_process_rcv_ring_diag,
  59	.create_rx_ctx			= qlcnic_83xx_create_rx_ctx,
  60	.create_tx_ctx			= qlcnic_83xx_create_tx_ctx,
  61	.del_rx_ctx			= qlcnic_83xx_del_rx_ctx,
  62	.del_tx_ctx			= qlcnic_83xx_del_tx_ctx,
  63	.setup_link_event		= qlcnic_83xx_setup_link_event,
  64	.get_nic_info			= qlcnic_83xx_get_nic_info,
  65	.get_pci_info			= qlcnic_83xx_get_pci_info,
  66	.set_nic_info			= qlcnic_83xx_set_nic_info,
  67	.change_macvlan			= qlcnic_83xx_sre_macaddr_change,
  68	.napi_enable			= qlcnic_83xx_napi_enable,
  69	.napi_disable			= qlcnic_83xx_napi_disable,
  70	.config_intr_coal		= qlcnic_83xx_config_intr_coal,
  71	.config_rss			= qlcnic_83xx_config_rss,
  72	.config_hw_lro			= qlcnic_83xx_config_hw_lro,
  73	.config_promisc_mode		= qlcnic_83xx_nic_set_promisc,
  74	.change_l2_filter		= qlcnic_83xx_change_l2_filter,
  75	.get_board_info			= qlcnic_83xx_get_port_info,
  76	.free_mac_list			= qlcnic_sriov_vf_free_mac_list,
  77	.enable_sds_intr		= qlcnic_83xx_enable_sds_intr,
  78	.disable_sds_intr		= qlcnic_83xx_disable_sds_intr,
  79	.encap_rx_offload               = qlcnic_83xx_encap_rx_offload,
  80	.encap_tx_offload               = qlcnic_83xx_encap_tx_offload,
  81};
  82
  83static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
  84	.config_bridged_mode	= qlcnic_config_bridged_mode,
  85	.config_led		= qlcnic_config_led,
  86	.cancel_idc_work        = qlcnic_sriov_vf_cancel_fw_work,
  87	.napi_add		= qlcnic_83xx_napi_add,
  88	.napi_del		= qlcnic_83xx_napi_del,
  89	.shutdown		= qlcnic_sriov_vf_shutdown,
  90	.resume			= qlcnic_sriov_vf_resume,
  91	.config_ipaddr		= qlcnic_83xx_config_ipaddr,
  92	.clear_legacy_intr	= qlcnic_83xx_clear_legacy_intr,
  93};
  94
  95static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
  96	{QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
  97	{QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
  98	{QLCNIC_BC_CMD_GET_ACL, 3, 14},
  99	{QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2},
 100};
 101
 102static inline bool qlcnic_sriov_bc_msg_check(u32 val)
 103{
 104	return (val & (1 << QLC_BC_MSG)) ? true : false;
 105}
 106
 107static inline bool qlcnic_sriov_channel_free_check(u32 val)
 108{
 109	return (val & (1 << QLC_BC_CFREE)) ? true : false;
 110}
 111
 112static inline bool qlcnic_sriov_flr_check(u32 val)
 113{
 114	return (val & (1 << QLC_BC_FLR)) ? true : false;
 115}
 116
 117static inline u8 qlcnic_sriov_target_func_id(u32 val)
 118{
 119	return (val >> 4) & 0xff;
 120}
 121
 122static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
 123{
 124	struct pci_dev *dev = adapter->pdev;
 125	int pos;
 126	u16 stride, offset;
 127
 128	if (qlcnic_sriov_vf_check(adapter))
 129		return 0;
 130
 131	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
 132	if (!pos)
 133		return 0;
 134	pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
 135	pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
 136
 137	return (dev->devfn + offset + stride * vf_id) & 0xff;
 138}
 139
 140int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
 141{
 142	struct qlcnic_sriov *sriov;
 143	struct qlcnic_back_channel *bc;
 144	struct workqueue_struct *wq;
 145	struct qlcnic_vport *vp;
 146	struct qlcnic_vf_info *vf;
 147	int err, i;
 148
 149	if (!qlcnic_sriov_enable_check(adapter))
 150		return -EIO;
 151
 152	sriov  = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL);
 153	if (!sriov)
 154		return -ENOMEM;
 155
 156	adapter->ahw->sriov = sriov;
 157	sriov->num_vfs = num_vfs;
 158	bc = &sriov->bc;
 159	sriov->vf_info = kcalloc(num_vfs, sizeof(struct qlcnic_vf_info),
 160				 GFP_KERNEL);
 161	if (!sriov->vf_info) {
 162		err = -ENOMEM;
 163		goto qlcnic_free_sriov;
 164	}
 165
 166	wq = create_singlethread_workqueue("bc-trans");
 167	if (wq == NULL) {
 168		err = -ENOMEM;
 169		dev_err(&adapter->pdev->dev,
 170			"Cannot create bc-trans workqueue\n");
 171		goto qlcnic_free_vf_info;
 172	}
 173
 174	bc->bc_trans_wq = wq;
 175
 176	wq = create_singlethread_workqueue("async");
 177	if (wq == NULL) {
 178		err = -ENOMEM;
 179		dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n");
 180		goto qlcnic_destroy_trans_wq;
 181	}
 182
 183	bc->bc_async_wq =  wq;
 184	INIT_LIST_HEAD(&bc->async_cmd_list);
 185	INIT_WORK(&bc->vf_async_work, qlcnic_sriov_handle_async_issue_cmd);
 186	spin_lock_init(&bc->queue_lock);
 187	bc->adapter = adapter;
 188
 189	for (i = 0; i < num_vfs; i++) {
 190		vf = &sriov->vf_info[i];
 191		vf->adapter = adapter;
 192		vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
 193		mutex_init(&vf->send_cmd_lock);
 194		spin_lock_init(&vf->vlan_list_lock);
 195		INIT_LIST_HEAD(&vf->rcv_act.wait_list);
 196		INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
 197		spin_lock_init(&vf->rcv_act.lock);
 198		spin_lock_init(&vf->rcv_pend.lock);
 199		init_completion(&vf->ch_free_cmpl);
 200
 201		INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd);
 202
 203		if (qlcnic_sriov_pf_check(adapter)) {
 204			vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
 205			if (!vp) {
 206				err = -ENOMEM;
 207				goto qlcnic_destroy_async_wq;
 208			}
 209			sriov->vf_info[i].vp = vp;
 210			vp->vlan_mode = QLC_GUEST_VLAN_MODE;
 211			vp->max_tx_bw = MAX_BW;
 212			vp->min_tx_bw = MIN_BW;
 213			vp->spoofchk = false;
 214			eth_random_addr(vp->mac);
 215			dev_info(&adapter->pdev->dev,
 216				 "MAC Address %pM is configured for VF %d\n",
 217				 vp->mac, i);
 218		}
 219	}
 220
 221	return 0;
 222
 223qlcnic_destroy_async_wq:
 224	while (i--)
 225		kfree(sriov->vf_info[i].vp);
 226	destroy_workqueue(bc->bc_async_wq);
 227
 228qlcnic_destroy_trans_wq:
 229	destroy_workqueue(bc->bc_trans_wq);
 230
 231qlcnic_free_vf_info:
 232	kfree(sriov->vf_info);
 233
 234qlcnic_free_sriov:
 235	kfree(adapter->ahw->sriov);
 236	return err;
 237}
 238
 239void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list)
 240{
 241	struct qlcnic_bc_trans *trans;
 242	struct qlcnic_cmd_args cmd;
 243	unsigned long flags;
 244
 245	spin_lock_irqsave(&t_list->lock, flags);
 246
 247	while (!list_empty(&t_list->wait_list)) {
 248		trans = list_first_entry(&t_list->wait_list,
 249					 struct qlcnic_bc_trans, list);
 250		list_del(&trans->list);
 251		t_list->count--;
 252		cmd.req.arg = (u32 *)trans->req_pay;
 253		cmd.rsp.arg = (u32 *)trans->rsp_pay;
 254		qlcnic_free_mbx_args(&cmd);
 255		qlcnic_sriov_cleanup_transaction(trans);
 256	}
 257
 258	spin_unlock_irqrestore(&t_list->lock, flags);
 259}
 260
 261void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
 262{
 263	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
 264	struct qlcnic_back_channel *bc = &sriov->bc;
 265	struct qlcnic_vf_info *vf;
 266	int i;
 267
 268	if (!qlcnic_sriov_enable_check(adapter))
 269		return;
 270
 271	qlcnic_sriov_cleanup_async_list(bc);
 272	destroy_workqueue(bc->bc_async_wq);
 273
 274	for (i = 0; i < sriov->num_vfs; i++) {
 275		vf = &sriov->vf_info[i];
 276		qlcnic_sriov_cleanup_list(&vf->rcv_pend);
 277		cancel_work_sync(&vf->trans_work);
 278		qlcnic_sriov_cleanup_list(&vf->rcv_act);
 279	}
 280
 281	destroy_workqueue(bc->bc_trans_wq);
 282
 283	for (i = 0; i < sriov->num_vfs; i++)
 284		kfree(sriov->vf_info[i].vp);
 285
 286	kfree(sriov->vf_info);
 287	kfree(adapter->ahw->sriov);
 288}
 289
 290static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
 291{
 292	qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
 293	qlcnic_sriov_cfg_bc_intr(adapter, 0);
 294	__qlcnic_sriov_cleanup(adapter);
 295}
 296
 297void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
 298{
 299	if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
 300		return;
 301
 302	qlcnic_sriov_free_vlans(adapter);
 303
 304	if (qlcnic_sriov_pf_check(adapter))
 305		qlcnic_sriov_pf_cleanup(adapter);
 306
 307	if (qlcnic_sriov_vf_check(adapter))
 308		qlcnic_sriov_vf_cleanup(adapter);
 309}
 310
 311static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
 312				    u32 *pay, u8 pci_func, u8 size)
 313{
 314	struct qlcnic_hardware_context *ahw = adapter->ahw;
 315	struct qlcnic_mailbox *mbx = ahw->mailbox;
 316	struct qlcnic_cmd_args cmd;
 317	unsigned long timeout;
 318	int err;
 319
 320	memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
 321	cmd.hdr = hdr;
 322	cmd.pay = pay;
 323	cmd.pay_size = size;
 324	cmd.func_num = pci_func;
 325	cmd.op_type = QLC_83XX_MBX_POST_BC_OP;
 326	cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
 327
 328	err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout);
 329	if (err) {
 330		dev_err(&adapter->pdev->dev,
 331			"%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 332			__func__, cmd.cmd_op, cmd.type, ahw->pci_func,
 333			ahw->op_mode);
 334		return err;
 335	}
 336
 337	if (!wait_for_completion_timeout(&cmd.completion, timeout)) {
 338		dev_err(&adapter->pdev->dev,
 339			"%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 340			__func__, cmd.cmd_op, cmd.type, ahw->pci_func,
 341			ahw->op_mode);
 342		flush_workqueue(mbx->work_q);
 343	}
 344
 345	return cmd.rsp_opcode;
 346}
 347
 348static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter)
 349{
 350	adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF;
 351	adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
 352	adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF;
 353	adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
 354	adapter->num_txd = MAX_CMD_DESCRIPTORS;
 355	adapter->max_rds_rings = MAX_RDS_RINGS;
 356}
 357
 358int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter,
 359				   struct qlcnic_info *npar_info, u16 vport_id)
 360{
 361	struct device *dev = &adapter->pdev->dev;
 362	struct qlcnic_cmd_args cmd;
 363	int err;
 364	u32 status;
 365
 366	err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
 367	if (err)
 368		return err;
 369
 370	cmd.req.arg[1] = vport_id << 16 | 0x1;
 371	err = qlcnic_issue_cmd(adapter, &cmd);
 372	if (err) {
 373		dev_err(&adapter->pdev->dev,
 374			"Failed to get vport info, err=%d\n", err);
 375		qlcnic_free_mbx_args(&cmd);
 376		return err;
 377	}
 378
 379	status = cmd.rsp.arg[2] & 0xffff;
 380	if (status & BIT_0)
 381		npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]);
 382	if (status & BIT_1)
 383		npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]);
 384	if (status & BIT_2)
 385		npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]);
 386	if (status & BIT_3)
 387		npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]);
 388	if (status & BIT_4)
 389		npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]);
 390	if (status & BIT_5)
 391		npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]);
 392	if (status & BIT_6)
 393		npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]);
 394	if (status & BIT_7)
 395		npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]);
 396	if (status & BIT_8)
 397		npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]);
 398	if (status & BIT_9)
 399		npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]);
 400
 401	npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]);
 402	npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]);
 403	npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]);
 404	npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]);
 405
 406	dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
 407		 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
 408		 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
 409		 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
 410		 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
 411		 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
 412		 npar_info->min_tx_bw, npar_info->max_tx_bw,
 413		 npar_info->max_tx_ques, npar_info->max_tx_mac_filters,
 414		 npar_info->max_rx_mcast_mac_filters,
 415		 npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr,
 416		 npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings,
 417		 npar_info->max_rx_buf_rings, npar_info->max_rx_ques,
 418		 npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs,
 419		 npar_info->max_remote_ipv6_addrs);
 420
 421	qlcnic_free_mbx_args(&cmd);
 422	return err;
 423}
 424
 425static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter,
 426				      struct qlcnic_cmd_args *cmd)
 427{
 428	adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff;
 429	adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
 430	return 0;
 431}
 432
 433static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter,
 434					    struct qlcnic_cmd_args *cmd)
 435{
 436	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
 437	int i, num_vlans, ret;
 438	u16 *vlans;
 439
 440	if (sriov->allowed_vlans)
 441		return 0;
 442
 443	sriov->any_vlan = cmd->rsp.arg[2] & 0xf;
 444	sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16;
 445	dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n",
 446		 sriov->num_allowed_vlans);
 447
 448	ret = qlcnic_sriov_alloc_vlans(adapter);
 449	if (ret)
 450		return ret;
 451
 452	if (!sriov->any_vlan)
 453		return 0;
 454
 455	num_vlans = sriov->num_allowed_vlans;
 456	sriov->allowed_vlans = kcalloc(num_vlans, sizeof(u16), GFP_KERNEL);
 457	if (!sriov->allowed_vlans) {
 458		qlcnic_sriov_free_vlans(adapter);
 459		return -ENOMEM;
 460	}
 461
 462	vlans = (u16 *)&cmd->rsp.arg[3];
 463	for (i = 0; i < num_vlans; i++)
 464		sriov->allowed_vlans[i] = vlans[i];
 465
 466	return 0;
 467}
 468
 469static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter)
 470{
 471	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
 472	struct qlcnic_cmd_args cmd;
 473	int ret = 0;
 474
 475	memset(&cmd, 0, sizeof(cmd));
 476	ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL);
 477	if (ret)
 478		return ret;
 479
 480	ret = qlcnic_issue_cmd(adapter, &cmd);
 481	if (ret) {
 482		dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n",
 483			ret);
 484	} else {
 485		sriov->vlan_mode = cmd.rsp.arg[1] & 0x3;
 486		switch (sriov->vlan_mode) {
 487		case QLC_GUEST_VLAN_MODE:
 488			ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd);
 489			break;
 490		case QLC_PVID_MODE:
 491			ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd);
 492			break;
 493		}
 494	}
 495
 496	qlcnic_free_mbx_args(&cmd);
 497	return ret;
 498}
 499
 500static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter)
 501{
 502	struct qlcnic_hardware_context *ahw = adapter->ahw;
 503	struct qlcnic_info nic_info;
 504	int err;
 505
 506	err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0);
 507	if (err)
 508		return err;
 509
 510	ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters;
 511
 512	err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
 513	if (err)
 514		return -EIO;
 515
 516	if (qlcnic_83xx_get_port_info(adapter))
 517		return -EIO;
 518
 519	qlcnic_sriov_vf_cfg_buff_desc(adapter);
 520	adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
 521	dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
 522		 adapter->ahw->fw_hal_version);
 523
 524	ahw->physical_port = (u8) nic_info.phys_port;
 525	ahw->switch_mode = nic_info.switch_mode;
 526	ahw->max_mtu = nic_info.max_mtu;
 527	ahw->op_mode = nic_info.op_mode;
 528	ahw->capabilities = nic_info.capabilities;
 529	return 0;
 530}
 531
 532static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter)
 533{
 534	int err;
 535
 536	adapter->flags |= QLCNIC_VLAN_FILTERING;
 537	adapter->ahw->total_nic_func = 1;
 538	INIT_LIST_HEAD(&adapter->vf_mc_list);
 539	if (!qlcnic_use_msi_x && !!qlcnic_use_msi)
 540		dev_warn(&adapter->pdev->dev,
 541			 "Device does not support MSI interrupts\n");
 542
 543	/* compute and set default and max tx/sds rings */
 544	qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING);
 545	qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING);
 546
 547	err = qlcnic_setup_intr(adapter);
 548	if (err) {
 549		dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
 550		goto err_out_disable_msi;
 551	}
 552
 553	err = qlcnic_83xx_setup_mbx_intr(adapter);
 554	if (err)
 555		goto err_out_disable_msi;
 556
 557	err = qlcnic_sriov_init(adapter, 1);
 558	if (err)
 559		goto err_out_disable_mbx_intr;
 560
 561	err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
 562	if (err)
 563		goto err_out_cleanup_sriov;
 564
 565	err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
 566	if (err)
 567		goto err_out_disable_bc_intr;
 568
 569	err = qlcnic_sriov_vf_init_driver(adapter);
 570	if (err)
 571		goto err_out_send_channel_term;
 572
 573	err = qlcnic_sriov_get_vf_acl(adapter);
 574	if (err)
 575		goto err_out_send_channel_term;
 576
 577	err = qlcnic_setup_netdev(adapter, adapter->netdev);
 578	if (err)
 579		goto err_out_send_channel_term;
 580
 581	pci_set_drvdata(adapter->pdev, adapter);
 582	dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
 583		 adapter->netdev->name);
 584
 585	qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
 586			     adapter->ahw->idc.delay);
 587	return 0;
 588
 589err_out_send_channel_term:
 590	qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
 591
 592err_out_disable_bc_intr:
 593	qlcnic_sriov_cfg_bc_intr(adapter, 0);
 594
 595err_out_cleanup_sriov:
 596	__qlcnic_sriov_cleanup(adapter);
 597
 598err_out_disable_mbx_intr:
 599	qlcnic_83xx_free_mbx_intr(adapter);
 600
 601err_out_disable_msi:
 602	qlcnic_teardown_intr(adapter);
 603	return err;
 604}
 605
 606static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter)
 607{
 608	u32 state;
 609
 610	do {
 611		msleep(20);
 612		if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT)
 613			return -EIO;
 614		state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
 615	} while (state != QLC_83XX_IDC_DEV_READY);
 616
 617	return 0;
 618}
 619
 620int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter)
 621{
 622	struct qlcnic_hardware_context *ahw = adapter->ahw;
 623	int err;
 624
 625	set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status);
 626	ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 627	ahw->reset_context = 0;
 628	adapter->fw_fail_cnt = 0;
 629	ahw->msix_supported = 1;
 630	adapter->need_fw_reset = 0;
 631	adapter->flags |= QLCNIC_TX_INTR_SHARED;
 632
 633	err = qlcnic_sriov_check_dev_ready(adapter);
 634	if (err)
 635		return err;
 636
 637	err = qlcnic_sriov_setup_vf(adapter);
 638	if (err)
 639		return err;
 640
 641	if (qlcnic_read_mac_addr(adapter))
 642		dev_warn(&adapter->pdev->dev, "failed to read mac addr\n");
 643
 644	INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
 645
 646	clear_bit(__QLCNIC_RESETTING, &adapter->state);
 647	return 0;
 648}
 649
 650void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter)
 651{
 652	struct qlcnic_hardware_context *ahw = adapter->ahw;
 653
 654	ahw->op_mode = QLCNIC_SRIOV_VF_FUNC;
 655	dev_info(&adapter->pdev->dev,
 656		 "HAL Version: %d Non Privileged SRIOV function\n",
 657		 ahw->fw_hal_version);
 658	adapter->nic_ops = &qlcnic_sriov_vf_ops;
 659	set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state);
 660	return;
 661}
 662
 663void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
 664{
 665	ahw->hw_ops		= &qlcnic_sriov_vf_hw_ops;
 666	ahw->reg_tbl		= (u32 *)qlcnic_83xx_reg_tbl;
 667	ahw->ext_reg_tbl	= (u32 *)qlcnic_83xx_ext_reg_tbl;
 668}
 669
 670static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
 671{
 672	u32 pay_size;
 673
 674	pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
 675
 676	if (pay_size)
 677		pay_size = QLC_BC_PAYLOAD_SZ;
 678	else
 679		pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
 680
 681	return pay_size;
 682}
 683
 684int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
 685{
 686	struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
 687	u8 i;
 688
 689	if (qlcnic_sriov_vf_check(adapter))
 690		return 0;
 691
 692	for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
 693		if (vf_info[i].pci_func == pci_func)
 694			return i;
 695	}
 696
 697	return -EINVAL;
 698}
 699
 700static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
 701{
 702	*trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
 703	if (!*trans)
 704		return -ENOMEM;
 705
 706	init_completion(&(*trans)->resp_cmpl);
 707	return 0;
 708}
 709
 710static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
 711					    u32 size)
 712{
 713	*hdr = kcalloc(size, sizeof(struct qlcnic_bc_hdr), GFP_ATOMIC);
 714	if (!*hdr)
 715		return -ENOMEM;
 716
 717	return 0;
 718}
 719
 720static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
 721{
 722	const struct qlcnic_mailbox_metadata *mbx_tbl;
 723	int i, size;
 724
 725	mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
 726	size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
 727
 728	for (i = 0; i < size; i++) {
 729		if (type == mbx_tbl[i].cmd) {
 730			mbx->op_type = QLC_BC_CMD;
 731			mbx->req.num = mbx_tbl[i].in_args;
 732			mbx->rsp.num = mbx_tbl[i].out_args;
 733			mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 734					       GFP_ATOMIC);
 735			if (!mbx->req.arg)
 736				return -ENOMEM;
 737			mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 738					       GFP_ATOMIC);
 739			if (!mbx->rsp.arg) {
 740				kfree(mbx->req.arg);
 741				mbx->req.arg = NULL;
 742				return -ENOMEM;
 743			}
 744			mbx->req.arg[0] = (type | (mbx->req.num << 16) |
 745					   (3 << 29));
 746			mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16;
 747			return 0;
 748		}
 749	}
 750	return -EINVAL;
 751}
 752
 753static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
 754				       struct qlcnic_cmd_args *cmd,
 755				       u16 seq, u8 msg_type)
 756{
 757	struct qlcnic_bc_hdr *hdr;
 758	int i;
 759	u32 num_regs, bc_pay_sz;
 760	u16 remainder;
 761	u8 cmd_op, num_frags, t_num_frags;
 762
 763	bc_pay_sz = QLC_BC_PAYLOAD_SZ;
 764	if (msg_type == QLC_BC_COMMAND) {
 765		trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
 766		trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
 767		num_regs = cmd->req.num;
 768		trans->req_pay_size = (num_regs * 4);
 769		num_regs = cmd->rsp.num;
 770		trans->rsp_pay_size = (num_regs * 4);
 771		cmd_op = cmd->req.arg[0] & 0xff;
 772		remainder = (trans->req_pay_size) % (bc_pay_sz);
 773		num_frags = (trans->req_pay_size) / (bc_pay_sz);
 774		if (remainder)
 775			num_frags++;
 776		t_num_frags = num_frags;
 777		if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
 778			return -ENOMEM;
 779		remainder = (trans->rsp_pay_size) % (bc_pay_sz);
 780		num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
 781		if (remainder)
 782			num_frags++;
 783		if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
 784			return -ENOMEM;
 785		num_frags  = t_num_frags;
 786		hdr = trans->req_hdr;
 787	}  else {
 788		cmd->req.arg = (u32 *)trans->req_pay;
 789		cmd->rsp.arg = (u32 *)trans->rsp_pay;
 790		cmd_op = cmd->req.arg[0] & 0xff;
 791		cmd->cmd_op = cmd_op;
 792		remainder = (trans->rsp_pay_size) % (bc_pay_sz);
 793		num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
 794		if (remainder)
 795			num_frags++;
 796		cmd->req.num = trans->req_pay_size / 4;
 797		cmd->rsp.num = trans->rsp_pay_size / 4;
 798		hdr = trans->rsp_hdr;
 799		cmd->op_type = trans->req_hdr->op_type;
 800	}
 801
 802	trans->trans_id = seq;
 803	trans->cmd_id = cmd_op;
 804	for (i = 0; i < num_frags; i++) {
 805		hdr[i].version = 2;
 806		hdr[i].msg_type = msg_type;
 807		hdr[i].op_type = cmd->op_type;
 808		hdr[i].num_cmds = 1;
 809		hdr[i].num_frags = num_frags;
 810		hdr[i].frag_num = i + 1;
 811		hdr[i].cmd_op = cmd_op;
 812		hdr[i].seq_id = seq;
 813	}
 814	return 0;
 815}
 816
 817static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
 818{
 819	if (!trans)
 820		return;
 821	kfree(trans->req_hdr);
 822	kfree(trans->rsp_hdr);
 823	kfree(trans);
 824}
 825
 826static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
 827				    struct qlcnic_bc_trans *trans, u8 type)
 828{
 829	struct qlcnic_trans_list *t_list;
 830	unsigned long flags;
 831	int ret = 0;
 832
 833	if (type == QLC_BC_RESPONSE) {
 834		t_list = &vf->rcv_act;
 835		spin_lock_irqsave(&t_list->lock, flags);
 836		t_list->count--;
 837		list_del(&trans->list);
 838		if (t_list->count > 0)
 839			ret = 1;
 840		spin_unlock_irqrestore(&t_list->lock, flags);
 841	}
 842	if (type == QLC_BC_COMMAND) {
 843		while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
 844			msleep(100);
 845		vf->send_cmd = NULL;
 846		clear_bit(QLC_BC_VF_SEND, &vf->state);
 847	}
 848	return ret;
 849}
 850
 851static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
 852					 struct qlcnic_vf_info *vf,
 853					 work_func_t func)
 854{
 855	if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
 856	    vf->adapter->need_fw_reset)
 857		return;
 858
 859	queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
 860}
 861
 862static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
 863{
 864	struct completion *cmpl = &trans->resp_cmpl;
 865
 866	if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
 867		trans->trans_state = QLC_END;
 868	else
 869		trans->trans_state = QLC_ABORT;
 870
 871	return;
 872}
 873
 874static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
 875					    u8 type)
 876{
 877	if (type == QLC_BC_RESPONSE) {
 878		trans->curr_rsp_frag++;
 879		if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
 880			trans->trans_state = QLC_INIT;
 881		else
 882			trans->trans_state = QLC_END;
 883	} else {
 884		trans->curr_req_frag++;
 885		if (trans->curr_req_frag < trans->req_hdr->num_frags)
 886			trans->trans_state = QLC_INIT;
 887		else
 888			trans->trans_state = QLC_WAIT_FOR_RESP;
 889	}
 890}
 891
 892static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
 893					       u8 type)
 894{
 895	struct qlcnic_vf_info *vf = trans->vf;
 896	struct completion *cmpl = &vf->ch_free_cmpl;
 897
 898	if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
 899		trans->trans_state = QLC_ABORT;
 900		return;
 901	}
 902
 903	clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
 904	qlcnic_sriov_handle_multi_frags(trans, type);
 905}
 906
 907static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
 908				     u32 *hdr, u32 *pay, u32 size)
 909{
 910	struct qlcnic_hardware_context *ahw = adapter->ahw;
 911	u8 i, max = 2, hdr_size, j;
 912
 913	hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
 914	max = (size / sizeof(u32)) + hdr_size;
 915
 916	for (i = 2, j = 0; j < hdr_size; i++, j++)
 917		*(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
 918	for (; j < max; i++, j++)
 919		*(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
 920}
 921
 922static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
 923{
 924	int ret = -EBUSY;
 925	u32 timeout = 10000;
 926
 927	do {
 928		if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
 929			ret = 0;
 930			break;
 931		}
 932		mdelay(1);
 933	} while (--timeout);
 934
 935	return ret;
 936}
 937
 938static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
 939{
 940	struct qlcnic_vf_info *vf = trans->vf;
 941	u32 pay_size;
 942	u32 *hdr, *pay;
 943	int ret;
 944	u8 pci_func = trans->func_id;
 945
 946	if (__qlcnic_sriov_issue_bc_post(vf))
 947		return -EBUSY;
 948
 949	if (type == QLC_BC_COMMAND) {
 950		hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
 951		pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
 952		pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
 953						       trans->curr_req_frag);
 954		pay_size = (pay_size / sizeof(u32));
 955	} else {
 956		hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
 957		pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
 958		pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
 959						       trans->curr_rsp_frag);
 960		pay_size = (pay_size / sizeof(u32));
 961	}
 962
 963	ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
 964				       pci_func, pay_size);
 965	return ret;
 966}
 967
 968static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
 969				      struct qlcnic_vf_info *vf, u8 type)
 970{
 971	bool flag = true;
 972	int err = -EIO;
 973
 974	while (flag) {
 975		if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
 976		    vf->adapter->need_fw_reset)
 977			trans->trans_state = QLC_ABORT;
 978
 979		switch (trans->trans_state) {
 980		case QLC_INIT:
 981			trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
 982			if (qlcnic_sriov_issue_bc_post(trans, type))
 983				trans->trans_state = QLC_ABORT;
 984			break;
 985		case QLC_WAIT_FOR_CHANNEL_FREE:
 986			qlcnic_sriov_wait_for_channel_free(trans, type);
 987			break;
 988		case QLC_WAIT_FOR_RESP:
 989			qlcnic_sriov_wait_for_resp(trans);
 990			break;
 991		case QLC_END:
 992			err = 0;
 993			flag = false;
 994			break;
 995		case QLC_ABORT:
 996			err = -EIO;
 997			flag = false;
 998			clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
 999			break;
1000		default:
1001			err = -EIO;
1002			flag = false;
1003		}
1004	}
1005	return err;
1006}
1007
1008static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
1009				    struct qlcnic_bc_trans *trans, int pci_func)
1010{
1011	struct qlcnic_vf_info *vf;
1012	int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
1013
1014	if (index < 0)
1015		return -EIO;
1016
1017	vf = &adapter->ahw->sriov->vf_info[index];
1018	trans->vf = vf;
1019	trans->func_id = pci_func;
1020
1021	if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
1022		if (qlcnic_sriov_pf_check(adapter))
1023			return -EIO;
1024		if (qlcnic_sriov_vf_check(adapter) &&
1025		    trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
1026			return -EIO;
1027	}
1028
1029	mutex_lock(&vf->send_cmd_lock);
1030	vf->send_cmd = trans;
1031	err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
1032	qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
1033	mutex_unlock(&vf->send_cmd_lock);
1034	return err;
1035}
1036
1037static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
1038					  struct qlcnic_bc_trans *trans,
1039					  struct qlcnic_cmd_args *cmd)
1040{
1041#ifdef CONFIG_QLCNIC_SRIOV
1042	if (qlcnic_sriov_pf_check(adapter)) {
1043		qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
1044		return;
1045	}
1046#endif
1047	cmd->rsp.arg[0] |= (0x9 << 25);
1048	return;
1049}
1050
1051static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
1052{
1053	struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
1054						 trans_work);
1055	struct qlcnic_bc_trans *trans = NULL;
1056	struct qlcnic_adapter *adapter  = vf->adapter;
1057	struct qlcnic_cmd_args cmd;
1058	u8 req;
1059
1060	if (adapter->need_fw_reset)
1061		return;
1062
1063	if (test_bit(QLC_BC_VF_FLR, &vf->state))
1064		return;
1065
1066	memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1067	trans = list_first_entry(&vf->rcv_act.wait_list,
1068				 struct qlcnic_bc_trans, list);
1069	adapter = vf->adapter;
1070
1071	if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
1072					QLC_BC_RESPONSE))
1073		goto cleanup_trans;
1074
1075	__qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
1076	trans->trans_state = QLC_INIT;
1077	__qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
1078
1079cleanup_trans:
1080	qlcnic_free_mbx_args(&cmd);
1081	req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
1082	qlcnic_sriov_cleanup_transaction(trans);
1083	if (req)
1084		qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
1085					     qlcnic_sriov_process_bc_cmd);
1086}
1087
1088static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
1089					struct qlcnic_vf_info *vf)
1090{
1091	struct qlcnic_bc_trans *trans;
1092	u32 pay_size;
1093
1094	if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
1095		return;
1096
1097	trans = vf->send_cmd;
1098
1099	if (trans == NULL)
1100		goto clear_send;
1101
1102	if (trans->trans_id != hdr->seq_id)
1103		goto clear_send;
1104
1105	pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
1106					       trans->curr_rsp_frag);
1107	qlcnic_sriov_pull_bc_msg(vf->adapter,
1108				 (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
1109				 (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
1110				 pay_size);
1111	if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
1112		goto clear_send;
1113
1114	complete(&trans->resp_cmpl);
1115
1116clear_send:
1117	clear_bit(QLC_BC_VF_SEND, &vf->state);
1118}
1119
1120int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1121				struct qlcnic_vf_info *vf,
1122				struct qlcnic_bc_trans *trans)
1123{
1124	struct qlcnic_trans_list *t_list = &vf->rcv_act;
1125
1126	t_list->count++;
1127	list_add_tail(&trans->list, &t_list->wait_list);
1128	if (t_list->count == 1)
1129		qlcnic_sriov_schedule_bc_cmd(sriov, vf,
1130					     qlcnic_sriov_process_bc_cmd);
1131	return 0;
1132}
1133
1134static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1135				     struct qlcnic_vf_info *vf,
1136				     struct qlcnic_bc_trans *trans)
1137{
1138	struct qlcnic_trans_list *t_list = &vf->rcv_act;
1139
1140	spin_lock(&t_list->lock);
1141
1142	__qlcnic_sriov_add_act_list(sriov, vf, trans);
1143
1144	spin_unlock(&t_list->lock);
1145	return 0;
1146}
1147
1148static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
1149					      struct qlcnic_vf_info *vf,
1150					      struct qlcnic_bc_hdr *hdr)
1151{
1152	struct qlcnic_bc_trans *trans = NULL;
1153	struct list_head *node;
1154	u32 pay_size, curr_frag;
1155	u8 found = 0, active = 0;
1156
1157	spin_lock(&vf->rcv_pend.lock);
1158	if (vf->rcv_pend.count > 0) {
1159		list_for_each(node, &vf->rcv_pend.wait_list) {
1160			trans = list_entry(node, struct qlcnic_bc_trans, list);
1161			if (trans->trans_id == hdr->seq_id) {
1162				found = 1;
1163				break;
1164			}
1165		}
1166	}
1167
1168	if (found) {
1169		curr_frag = trans->curr_req_frag;
1170		pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1171						       curr_frag);
1172		qlcnic_sriov_pull_bc_msg(vf->adapter,
1173					 (u32 *)(trans->req_hdr + curr_frag),
1174					 (u32 *)(trans->req_pay + curr_frag),
1175					 pay_size);
1176		trans->curr_req_frag++;
1177		if (trans->curr_req_frag >= hdr->num_frags) {
1178			vf->rcv_pend.count--;
1179			list_del(&trans->list);
1180			active = 1;
1181		}
1182	}
1183	spin_unlock(&vf->rcv_pend.lock);
1184
1185	if (active)
1186		if (qlcnic_sriov_add_act_list(sriov, vf, trans))
1187			qlcnic_sriov_cleanup_transaction(trans);
1188
1189	return;
1190}
1191
1192static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
1193				       struct qlcnic_bc_hdr *hdr,
1194				       struct qlcnic_vf_info *vf)
1195{
1196	struct qlcnic_bc_trans *trans;
1197	struct qlcnic_adapter *adapter = vf->adapter;
1198	struct qlcnic_cmd_args cmd;
1199	u32 pay_size;
1200	int err;
1201	u8 cmd_op;
1202
1203	if (adapter->need_fw_reset)
1204		return;
1205
1206	if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
1207	    hdr->op_type != QLC_BC_CMD &&
1208	    hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
1209		return;
1210
1211	if (hdr->frag_num > 1) {
1212		qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
1213		return;
1214	}
1215
1216	memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1217	cmd_op = hdr->cmd_op;
1218	if (qlcnic_sriov_alloc_bc_trans(&trans))
1219		return;
1220
1221	if (hdr->op_type == QLC_BC_CMD)
1222		err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
1223	else
1224		err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
1225
1226	if (err) {
1227		qlcnic_sriov_cleanup_transaction(trans);
1228		return;
1229	}
1230
1231	cmd.op_type = hdr->op_type;
1232	if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
1233					QLC_BC_COMMAND)) {
1234		qlcnic_free_mbx_args(&cmd);
1235		qlcnic_sriov_cleanup_transaction(trans);
1236		return;
1237	}
1238
1239	pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1240					 trans->curr_req_frag);
1241	qlcnic_sriov_pull_bc_msg(vf->adapter,
1242				 (u32 *)(trans->req_hdr + trans->curr_req_frag),
1243				 (u32 *)(trans->req_pay + trans->curr_req_frag),
1244				 pay_size);
1245	trans->func_id = vf->pci_func;
1246	trans->vf = vf;
1247	trans->trans_id = hdr->seq_id;
1248	trans->curr_req_frag++;
1249
1250	if (qlcnic_sriov_soft_flr_check(adapter, trans, vf))
1251		return;
1252
1253	if (trans->curr_req_frag == trans->req_hdr->num_frags) {
1254		if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
1255			qlcnic_free_mbx_args(&cmd);
1256			qlcnic_sriov_cleanup_transaction(trans);
1257		}
1258	} else {
1259		spin_lock(&vf->rcv_pend.lock);
1260		list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
1261		vf->rcv_pend.count++;
1262		spin_unlock(&vf->rcv_pend.lock);
1263	}
1264}
1265
1266static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
1267					  struct qlcnic_vf_info *vf)
1268{
1269	struct qlcnic_bc_hdr hdr;
1270	u32 *ptr = (u32 *)&hdr;
1271	u8 msg_type, i;
1272
1273	for (i = 2; i < 6; i++)
1274		ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
1275	msg_type = hdr.msg_type;
1276
1277	switch (msg_type) {
1278	case QLC_BC_COMMAND:
1279		qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
1280		break;
1281	case QLC_BC_RESPONSE:
1282		qlcnic_sriov_handle_bc_resp(&hdr, vf);
1283		break;
1284	}
1285}
1286
1287static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov,
1288					  struct qlcnic_vf_info *vf)
1289{
1290	struct qlcnic_adapter *adapter = vf->adapter;
1291
1292	if (qlcnic_sriov_pf_check(adapter))
1293		qlcnic_sriov_pf_handle_flr(sriov, vf);
1294	else
1295		dev_err(&adapter->pdev->dev,
1296			"Invalid event to VF. VF should not get FLR event\n");
1297}
1298
1299void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
1300{
1301	struct qlcnic_vf_info *vf;
1302	struct qlcnic_sriov *sriov;
1303	int index;
1304	u8 pci_func;
1305
1306	sriov = adapter->ahw->sriov;
1307	pci_func = qlcnic_sriov_target_func_id(event);
1308	index = qlcnic_sriov_func_to_index(adapter, pci_func);
1309
1310	if (index < 0)
1311		return;
1312
1313	vf = &sriov->vf_info[index];
1314	vf->pci_func = pci_func;
1315
1316	if (qlcnic_sriov_channel_free_check(event))
1317		complete(&vf->ch_free_cmpl);
1318
1319	if (qlcnic_sriov_flr_check(event)) {
1320		qlcnic_sriov_handle_flr_event(sriov, vf);
1321		return;
1322	}
1323
1324	if (qlcnic_sriov_bc_msg_check(event))
1325		qlcnic_sriov_handle_msg_event(sriov, vf);
1326}
1327
1328int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
1329{
1330	struct qlcnic_cmd_args cmd;
1331	int err;
1332
1333	if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
1334		return 0;
1335
1336	if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
1337		return -ENOMEM;
1338
1339	if (enable)
1340		cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1341
1342	err = qlcnic_83xx_issue_cmd(adapter, &cmd);
1343
1344	if (err != QLCNIC_RCODE_SUCCESS) {
1345		dev_err(&adapter->pdev->dev,
1346			"Failed to %s bc events, err=%d\n",
1347			(enable ? "enable" : "disable"), err);
1348	}
1349
1350	qlcnic_free_mbx_args(&cmd);
1351	return err;
1352}
1353
1354static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter,
1355				     struct qlcnic_bc_trans *trans)
1356{
1357	u8 max = QLC_BC_CMD_MAX_RETRY_CNT;
1358	u32 state;
1359
1360	state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1361	if (state == QLC_83XX_IDC_DEV_READY) {
1362		msleep(20);
1363		clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state);
1364		trans->trans_state = QLC_INIT;
1365		if (++adapter->fw_fail_cnt > max)
1366			return -EIO;
1367		else
1368			return 0;
1369	}
1370
1371	return -EIO;
1372}
1373
1374static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1375				  struct qlcnic_cmd_args *cmd)
1376{
1377	struct qlcnic_hardware_context *ahw = adapter->ahw;
1378	struct qlcnic_mailbox *mbx = ahw->mailbox;
1379	struct device *dev = &adapter->pdev->dev;
1380	struct qlcnic_bc_trans *trans;
1381	int err;
1382	u32 rsp_data, opcode, mbx_err_code, rsp;
1383	u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
1384	u8 func = ahw->pci_func;
1385
1386	rsp = qlcnic_sriov_alloc_bc_trans(&trans);
1387	if (rsp)
1388		goto free_cmd;
1389
1390	rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND);
1391	if (rsp)
1392		goto cleanup_transaction;
1393
1394retry:
1395	if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
1396		rsp = -EIO;
1397		QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
1398		      QLCNIC_MBX_RSP(cmd->req.arg[0]), func);
1399		goto err_out;
1400	}
1401
1402	err = qlcnic_sriov_send_bc_cmd(adapter, trans, func);
1403	if (err) {
1404		dev_err(dev, "MBX command 0x%x timed out for VF %d\n",
1405			(cmd->req.arg[0] & 0xffff), func);
1406		rsp = QLCNIC_RCODE_TIMEOUT;
1407
1408		/* After adapter reset PF driver may take some time to
1409		 * respond to VF's request. Retry request till maximum retries.
1410		 */
1411		if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) &&
1412		    !qlcnic_sriov_retry_bc_cmd(adapter, trans))
1413			goto retry;
1414
1415		goto err_out;
1416	}
1417
1418	rsp_data = cmd->rsp.arg[0];
1419	mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
1420	opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
1421
1422	if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
1423	    (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
1424		rsp = QLCNIC_RCODE_SUCCESS;
1425	} else {
1426		if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1427			rsp = QLCNIC_RCODE_SUCCESS;
1428		} else {
1429			rsp = mbx_err_code;
1430			if (!rsp)
1431				rsp = 1;
1432
1433			dev_err(dev,
1434				"MBX command 0x%x failed with err:0x%x for VF %d\n",
1435				opcode, mbx_err_code, func);
1436		}
1437	}
1438
1439err_out:
1440	if (rsp == QLCNIC_RCODE_TIMEOUT) {
1441		ahw->reset_context = 1;
1442		adapter->need_fw_reset = 1;
1443		clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1444	}
1445
1446cleanup_transaction:
1447	qlcnic_sriov_cleanup_transaction(trans);
1448
1449free_cmd:
1450	if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1451		qlcnic_free_mbx_args(cmd);
1452		kfree(cmd);
1453	}
1454
1455	return rsp;
1456}
1457
1458
1459static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1460				  struct qlcnic_cmd_args *cmd)
1461{
1462	if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT)
1463		return qlcnic_sriov_async_issue_cmd(adapter, cmd);
1464	else
1465		return __qlcnic_sriov_issue_cmd(adapter, cmd);
1466}
1467
1468static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
1469{
1470	struct qlcnic_cmd_args cmd;
1471	struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
1472	int ret;
1473
1474	memset(&cmd, 0, sizeof(cmd));
1475	if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
1476		return -ENOMEM;
1477
1478	ret = qlcnic_issue_cmd(adapter, &cmd);
1479	if (ret) {
1480		dev_err(&adapter->pdev->dev,
1481			"Failed bc channel %s %d\n", cmd_op ? "term" : "init",
1482			ret);
1483		goto out;
1484	}
1485
1486	cmd_op = (cmd.rsp.arg[0] & 0xff);
1487	if (cmd.rsp.arg[0] >> 25 == 2) {
1488		ret = 2;
1489		goto out;
1490	}
1491
1492	if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
1493		set_bit(QLC_BC_VF_STATE, &vf->state);
1494	else
1495		clear_bit(QLC_BC_VF_STATE, &vf->state);
1496
1497out:
1498	qlcnic_free_mbx_args(&cmd);
1499	return ret;
1500}
1501
1502static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac,
1503				  enum qlcnic_mac_type mac_type)
1504{
1505	struct qlcnic_adapter *adapter = netdev_priv(netdev);
1506	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1507	struct qlcnic_vf_info *vf;
1508	u16 vlan_id;
1509	int i;
1510
1511	vf = &adapter->ahw->sriov->vf_info[0];
1512
1513	if (!qlcnic_sriov_check_any_vlan(vf)) {
1514		qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1515	} else {
1516		spin_lock(&vf->vlan_list_lock);
1517		for (i = 0; i < sriov->num_allowed_vlans; i++) {
1518			vlan_id = vf->sriov_vlans[i];
1519			if (vlan_id)
1520				qlcnic_nic_add_mac(adapter, mac, vlan_id,
1521						   mac_type);
1522		}
1523		spin_unlock(&vf->vlan_list_lock);
1524		if (qlcnic_84xx_check(adapter))
1525			qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1526	}
1527}
1528
1529void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc)
1530{
1531	struct list_head *head = &bc->async_cmd_list;
1532	struct qlcnic_async_cmd *entry;
1533
1534	flush_workqueue(bc->bc_async_wq);
1535	cancel_work_sync(&bc->vf_async_work);
1536
1537	spin_lock(&bc->queue_lock);
1538	while (!list_empty(head)) {
1539		entry = list_entry(head->next, struct qlcnic_async_cmd,
1540				   list);
1541		list_del(&entry->list);
1542		kfree(entry->cmd);
1543		kfree(entry);
1544	}
1545	spin_unlock(&bc->queue_lock);
1546}
1547
1548void qlcnic_sriov_vf_set_multi(struct net_device *netdev)
1549{
1550	struct qlcnic_adapter *adapter = netdev_priv(netdev);
1551	struct qlcnic_hardware_context *ahw = adapter->ahw;
1552	static const u8 bcast_addr[ETH_ALEN] = {
1553		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1554	};
1555	struct netdev_hw_addr *ha;
1556	u32 mode = VPORT_MISS_MODE_DROP;
1557
1558	if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
1559		return;
1560
1561	if (netdev->flags & IFF_PROMISC) {
1562		if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
1563			mode = VPORT_MISS_MODE_ACCEPT_ALL;
1564	} else if ((netdev->flags & IFF_ALLMULTI) ||
1565		   (netdev_mc_count(netdev) > ahw->max_mc_count)) {
1566		mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1567	} else {
1568		qlcnic_vf_add_mc_list(netdev, bcast_addr, QLCNIC_BROADCAST_MAC);
1569		if (!netdev_mc_empty(netdev)) {
1570			qlcnic_flush_mcast_mac(adapter);
1571			netdev_for_each_mc_addr(ha, netdev)
1572				qlcnic_vf_add_mc_list(netdev, ha->addr,
1573						      QLCNIC_MULTICAST_MAC);
1574		}
1575	}
1576
1577	/* configure unicast MAC address, if there is not sufficient space
1578	 * to store all the unicast addresses then enable promiscuous mode
1579	 */
1580	if (netdev_uc_count(netdev) > ahw->max_uc_count) {
1581		mode = VPORT_MISS_MODE_ACCEPT_ALL;
1582	} else if (!netdev_uc_empty(netdev)) {
1583		netdev_for_each_uc_addr(ha, netdev)
1584			qlcnic_vf_add_mc_list(netdev, ha->addr,
1585					      QLCNIC_UNICAST_MAC);
1586	}
1587
1588	if (adapter->pdev->is_virtfn) {
1589		if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
1590		    !adapter->fdb_mac_learn) {
1591			qlcnic_alloc_lb_filters_mem(adapter);
1592			adapter->drv_mac_learn = true;
1593			adapter->rx_mac_learn = true;
1594		} else {
1595			adapter->drv_mac_learn = false;
1596			adapter->rx_mac_learn = false;
1597		}
1598	}
1599
1600	qlcnic_nic_set_promisc(adapter, mode);
1601}
1602
1603static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work)
1604{
1605	struct qlcnic_async_cmd *entry, *tmp;
1606	struct qlcnic_back_channel *bc;
1607	struct qlcnic_cmd_args *cmd;
1608	struct list_head *head;
1609	LIST_HEAD(del_list);
1610
1611	bc = container_of(work, struct qlcnic_back_channel, vf_async_work);
1612	head = &bc->async_cmd_list;
1613
1614	spin_lock(&bc->queue_lock);
1615	list_splice_init(head, &del_list);
1616	spin_unlock(&bc->queue_lock);
1617
1618	list_for_each_entry_safe(entry, tmp, &del_list, list) {
1619		list_del(&entry->list);
1620		cmd = entry->cmd;
1621		__qlcnic_sriov_issue_cmd(bc->adapter, cmd);
1622		kfree(entry);
1623	}
1624
1625	if (!list_empty(head))
1626		queue_work(bc->bc_async_wq, &bc->vf_async_work);
1627
1628	return;
1629}
1630
1631static struct qlcnic_async_cmd *
1632qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel *bc,
1633			     struct qlcnic_cmd_args *cmd)
1634{
1635	struct qlcnic_async_cmd *entry = NULL;
1636
1637	entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
1638	if (!entry)
1639		return NULL;
1640
1641	entry->cmd = cmd;
1642
1643	spin_lock(&bc->queue_lock);
1644	list_add_tail(&entry->list, &bc->async_cmd_list);
1645	spin_unlock(&bc->queue_lock);
1646
1647	return entry;
1648}
1649
1650static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc,
1651					    struct qlcnic_cmd_args *cmd)
1652{
1653	struct qlcnic_async_cmd *entry = NULL;
1654
1655	entry = qlcnic_sriov_alloc_async_cmd(bc, cmd);
1656	if (!entry) {
1657		qlcnic_free_mbx_args(cmd);
1658		kfree(cmd);
1659		return;
1660	}
1661
1662	queue_work(bc->bc_async_wq, &bc->vf_async_work);
1663}
1664
1665static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter,
1666					struct qlcnic_cmd_args *cmd)
1667{
1668
1669	struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc;
1670
1671	if (adapter->need_fw_reset)
1672		return -EIO;
1673
1674	qlcnic_sriov_schedule_async_cmd(bc, cmd);
1675
1676	return 0;
1677}
1678
1679static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter)
1680{
1681	int err;
1682
1683	adapter->need_fw_reset = 0;
1684	qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
1685	qlcnic_83xx_enable_mbx_interrupt(adapter);
1686
1687	err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
1688	if (err)
1689		return err;
1690
1691	err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
1692	if (err)
1693		goto err_out_cleanup_bc_intr;
1694
1695	err = qlcnic_sriov_vf_init_driver(adapter);
1696	if (err)
1697		goto err_out_term_channel;
1698
1699	return 0;
1700
1701err_out_term_channel:
1702	qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
1703
1704err_out_cleanup_bc_intr:
1705	qlcnic_sriov_cfg_bc_intr(adapter, 0);
1706	return err;
1707}
1708
1709static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter)
1710{
1711	struct net_device *netdev = adapter->netdev;
1712
1713	if (netif_running(netdev)) {
1714		if (!qlcnic_up(adapter, netdev))
1715			qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1716	}
1717
1718	netif_device_attach(netdev);
1719}
1720
1721static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter)
1722{
1723	struct qlcnic_hardware_context *ahw = adapter->ahw;
1724	struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl;
1725	struct net_device *netdev = adapter->netdev;
1726	u8 i, max_ints = ahw->num_msix - 1;
1727
1728	netif_device_detach(netdev);
1729	qlcnic_83xx_detach_mailbox_work(adapter);
1730	qlcnic_83xx_disable_mbx_intr(adapter);
1731
1732	if (netif_running(netdev))
1733		qlcnic_down(adapter, netdev);
1734
1735	for (i = 0; i < max_ints; i++) {
1736		intr_tbl[i].id = i;
1737		intr_tbl[i].enabled = 0;
1738		intr_tbl[i].src = 0;
1739	}
1740	ahw->reset_context = 0;
1741}
1742
1743static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter)
1744{
1745	struct qlcnic_hardware_context *ahw = adapter->ahw;
1746	struct device *dev = &adapter->pdev->dev;
1747	struct qlc_83xx_idc *idc = &ahw->idc;
1748	u8 func = ahw->pci_func;
1749	u32 state;
1750
1751	if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
1752	    (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) {
1753		if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1754			qlcnic_sriov_vf_attach(adapter);
1755			adapter->fw_fail_cnt = 0;
1756			dev_info(dev,
1757				 "%s: Reinitialization of VF 0x%x done after FW reset\n",
1758				 __func__, func);
1759		} else {
1760			dev_err(dev,
1761				"%s: Reinitialization of VF 0x%x failed after FW reset\n",
1762				__func__, func);
1763			state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1764			dev_info(dev, "Current state 0x%x after FW reset\n",
1765				 state);
1766		}
1767	}
1768
1769	return 0;
1770}
1771
1772static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter)
1773{
1774	struct qlcnic_hardware_context *ahw = adapter->ahw;
1775	struct qlcnic_mailbox *mbx = ahw->mailbox;
1776	struct device *dev = &adapter->pdev->dev;
1777	struct qlc_83xx_idc *idc = &ahw->idc;
1778	u8 func = ahw->pci_func;
1779	u32 state;
1780
1781	adapter->reset_ctx_cnt++;
1782
1783	/* Skip the context reset and check if FW is hung */
1784	if (adapter->reset_ctx_cnt < 3) {
1785		adapter->need_fw_reset = 1;
1786		clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1787		dev_info(dev,
1788			 "Resetting context, wait here to check if FW is in failed state\n");
1789		return 0;
1790	}
1791
1792	/* Check if number of resets exceed the threshold.
1793	 * If it exceeds the threshold just fail the VF.
1794	 */
1795	if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) {
1796		clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1797		adapter->tx_timeo_cnt = 0;
1798		adapter->fw_fail_cnt = 0;
1799		adapter->reset_ctx_cnt = 0;
1800		qlcnic_sriov_vf_detach(adapter);
1801		dev_err(dev,
1802			"Device context resets have exceeded the threshold, device interface will be shutdown\n");
1803		return -EIO;
1804	}
1805
1806	dev_info(dev, "Resetting context of VF 0x%x\n", func);
1807	dev_info(dev, "%s: Context reset count %d for VF 0x%x\n",
1808		 __func__, adapter->reset_ctx_cnt, func);
1809	set_bit(__QLCNIC_RESETTING, &adapter->state);
1810	adapter->need_fw_reset = 1;
1811	clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1812	qlcnic_sriov_vf_detach(adapter);
1813	adapter->need_fw_reset = 0;
1814
1815	if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1816		qlcnic_sriov_vf_attach(adapter);
1817		adapter->tx_timeo_cnt = 0;
1818		adapter->reset_ctx_cnt = 0;
1819		adapter->fw_fail_cnt = 0;
1820		dev_info(dev, "Done resetting context for VF 0x%x\n", func);
1821	} else {
1822		dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n",
1823			__func__, func);
1824		state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1825		dev_info(dev, "%s: Current state 0x%x\n", __func__, state);
1826	}
1827
1828	return 0;
1829}
1830
1831static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter)
1832{
1833	struct qlcnic_hardware_context *ahw = adapter->ahw;
1834	int ret = 0;
1835
1836	if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY)
1837		ret = qlcnic_sriov_vf_handle_dev_ready(adapter);
1838	else if (ahw->reset_context)
1839		ret = qlcnic_sriov_vf_handle_context_reset(adapter);
1840
1841	clear_bit(__QLCNIC_RESETTING, &adapter->state);
1842	return ret;
1843}
1844
1845static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter)
1846{
1847	struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1848
1849	dev_err(&adapter->pdev->dev, "Device is in failed state\n");
1850	if (idc->prev_state == QLC_83XX_IDC_DEV_READY)
1851		qlcnic_sriov_vf_detach(adapter);
1852
1853	clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1854	clear_bit(__QLCNIC_RESETTING, &adapter->state);
1855	return -EIO;
1856}
1857
1858static int
1859qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter)
1860{
1861	struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1862	struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1863
1864	dev_info(&adapter->pdev->dev, "Device is in quiescent state\n");
1865	if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1866		set_bit(__QLCNIC_RESETTING, &adapter->state);
1867		adapter->tx_timeo_cnt = 0;
1868		adapter->reset_ctx_cnt = 0;
1869		clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1870		qlcnic_sriov_vf_detach(adapter);
1871	}
1872
1873	return 0;
1874}
1875
1876static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter)
1877{
1878	struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1879	struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1880	u8 func = adapter->ahw->pci_func;
1881
1882	if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1883		dev_err(&adapter->pdev->dev,
1884			"Firmware hang detected by VF 0x%x\n", func);
1885		set_bit(__QLCNIC_RESETTING, &adapter->state);
1886		adapter->tx_timeo_cnt = 0;
1887		adapter->reset_ctx_cnt = 0;
1888		clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1889		qlcnic_sriov_vf_detach(adapter);
1890	}
1891	return 0;
1892}
1893
1894static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter)
1895{
1896	dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__);
1897	return 0;
1898}
1899
1900static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter)
1901{
1902	if (adapter->fhash.fnum)
1903		qlcnic_prune_lb_filters(adapter);
1904}
1905
1906static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work)
1907{
1908	struct qlcnic_adapter *adapter;
1909	struct qlc_83xx_idc *idc;
1910	int ret = 0;
1911
1912	adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1913	idc = &adapter->ahw->idc;
1914	idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1915
1916	switch (idc->curr_state) {
1917	case QLC_83XX_IDC_DEV_READY:
1918		ret = qlcnic_sriov_vf_idc_ready_state(adapter);
1919		break;
1920	case QLC_83XX_IDC_DEV_NEED_RESET:
1921	case QLC_83XX_IDC_DEV_INIT:
1922		ret = qlcnic_sriov_vf_idc_init_reset_state(adapter);
1923		break;
1924	case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1925		ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter);
1926		break;
1927	case QLC_83XX_IDC_DEV_FAILED:
1928		ret = qlcnic_sriov_vf_idc_failed_state(adapter);
1929		break;
1930	case QLC_83XX_IDC_DEV_QUISCENT:
1931		break;
1932	default:
1933		ret = qlcnic_sriov_vf_idc_unknown_state(adapter);
1934	}
1935
1936	idc->prev_state = idc->curr_state;
1937	qlcnic_sriov_vf_periodic_tasks(adapter);
1938
1939	if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status))
1940		qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
1941				     idc->delay);
1942}
1943
1944static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter)
1945{
1946	while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1947		msleep(20);
1948
1949	clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1950	clear_bit(__QLCNIC_RESETTING, &adapter->state);
1951	cancel_delayed_work_sync(&adapter->fw_work);
1952}
1953
1954static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov,
1955				      struct qlcnic_vf_info *vf, u16 vlan_id)
1956{
1957	int i, err = -EINVAL;
1958
1959	if (!vf->sriov_vlans)
1960		return err;
1961
1962	spin_lock_bh(&vf->vlan_list_lock);
1963
1964	for (i = 0; i < sriov->num_allowed_vlans; i++) {
1965		if (vf->sriov_vlans[i] == vlan_id) {
1966			err = 0;
1967			break;
1968		}
1969	}
1970
1971	spin_unlock_bh(&vf->vlan_list_lock);
1972	return err;
1973}
1974
1975static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov,
1976					   struct qlcnic_vf_info *vf)
1977{
1978	int err = 0;
1979
1980	spin_lock_bh(&vf->vlan_list_lock);
1981
1982	if (vf->num_vlan >= sriov->num_allowed_vlans)
1983		err = -EINVAL;
1984
1985	spin_unlock_bh(&vf->vlan_list_lock);
1986	return err;
1987}
1988
1989static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter,
1990					  u16 vid, u8 enable)
1991{
1992	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1993	struct qlcnic_vf_info *vf;
1994	bool vlan_exist;
1995	u8 allowed = 0;
1996	int i;
1997
1998	vf = &adapter->ahw->sriov->vf_info[0];
1999	vlan_exist = qlcnic_sriov_check_any_vlan(vf);
2000	if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE)
2001		return -EINVAL;
2002
2003	if (enable) {
2004		if (qlcnic_83xx_vf_check(adapter) && vlan_exist)
2005			return -EINVAL;
2006
2007		if (qlcnic_sriov_validate_num_vlans(sriov, vf))
2008			return -EINVAL;
2009
2010		if (sriov->any_vlan) {
2011			for (i = 0; i < sriov->num_allowed_vlans; i++) {
2012				if (sriov->allowed_vlans[i] == vid)
2013					allowed = 1;
2014			}
2015
2016			if (!allowed)
2017				return -EINVAL;
2018		}
2019	} else {
2020		if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid))
2021			return -EINVAL;
2022	}
2023
2024	return 0;
2025}
2026
2027static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id,
2028					enum qlcnic_vlan_operations opcode)
2029{
2030	struct qlcnic_adapter *adapter = vf->adapter;
2031	struct qlcnic_sriov *sriov;
2032
2033	sriov = adapter->ahw->sriov;
2034
2035	if (!vf->sriov_vlans)
2036		return;
2037
2038	spin_lock_bh(&vf->vlan_list_lock);
2039
2040	switch (opcode) {
2041	case QLC_VLAN_ADD:
2042		qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id);
2043		break;
2044	case QLC_VLAN_DELETE:
2045		qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id);
2046		break;
2047	default:
2048		netdev_err(adapter->netdev, "Invalid VLAN operation\n");
2049	}
2050
2051	spin_unlock_bh(&vf->vlan_list_lock);
2052	return;
2053}
2054
2055int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter,
2056				   u16 vid, u8 enable)
2057{
2058	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2059	struct net_device *netdev = adapter->netdev;
2060	struct qlcnic_vf_info *vf;
2061	struct qlcnic_cmd_args cmd;
2062	int ret;
2063
2064	memset(&cmd, 0, sizeof(cmd));
2065	if (vid == 0)
2066		return 0;
2067
2068	vf = &adapter->ahw->sriov->vf_info[0];
2069	ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable);
2070	if (ret)
2071		return ret;
2072
2073	ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd,
2074					     QLCNIC_BC_CMD_CFG_GUEST_VLAN);
2075	if (ret)
2076		return ret;
2077
2078	cmd.req.arg[1] = (enable & 1) | vid << 16;
2079
2080	qlcnic_sriov_cleanup_async_list(&sriov->bc);
2081	ret = qlcnic_issue_cmd(adapter, &cmd);
2082	if (ret) {
2083		dev_err(&adapter->pdev->dev,
2084			"Failed to configure guest VLAN, err=%d\n", ret);
2085	} else {
2086		netif_addr_lock_bh(netdev);
2087		qlcnic_free_mac_list(adapter);
2088		netif_addr_unlock_bh(netdev);
2089
2090		if (enable)
2091			qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD);
2092		else
2093			qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE);
2094
2095		netif_addr_lock_bh(netdev);
2096		qlcnic_set_multi(netdev);
2097		netif_addr_unlock_bh(netdev);
2098	}
2099
2100	qlcnic_free_mbx_args(&cmd);
2101	return ret;
2102}
2103
2104static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter)
2105{
2106	struct list_head *head = &adapter->mac_list;
2107	struct qlcnic_mac_vlan_list *cur;
2108
2109	while (!list_empty(head)) {
2110		cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
2111		qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id,
2112					  QLCNIC_MAC_DEL);
2113		list_del(&cur->list);
2114		kfree(cur);
2115	}
2116}
2117
2118
2119static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev)
2120{
2121	struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2122	struct net_device *netdev = adapter->netdev;
2123
2124	netif_device_detach(netdev);
2125	qlcnic_cancel_idc_work(adapter);
2126
2127	if (netif_running(netdev))
2128		qlcnic_down(adapter, netdev);
2129
2130	qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
2131	qlcnic_sriov_cfg_bc_intr(adapter, 0);
2132	qlcnic_83xx_disable_mbx_intr(adapter);
2133	cancel_delayed_work_sync(&adapter->idc_aen_work);
2134
2135	return pci_save_state(pdev);
2136}
2137
2138static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter)
2139{
2140	struct qlc_83xx_idc *idc = &adapter->ahw->idc;
2141	struct net_device *netdev = adapter->netdev;
2142	int err;
2143
2144	set_bit(QLC_83XX_MODULE_LOADED, &idc->status);
2145	qlcnic_83xx_enable_mbx_interrupt(adapter);
2146	err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
2147	if (err)
2148		return err;
2149
2150	err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
2151	if (!err) {
2152		if (netif_running(netdev)) {
2153			err = qlcnic_up(adapter, netdev);
2154			if (!err)
2155				qlcnic_restore_indev_addr(netdev, NETDEV_UP);
2156		}
2157	}
2158
2159	netif_device_attach(netdev);
2160	qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
2161			     idc->delay);
2162	return err;
2163}
2164
2165int qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter)
2166{
2167	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2168	struct qlcnic_vf_info *vf;
2169	int i;
2170
2171	for (i = 0; i < sriov->num_vfs; i++) {
2172		vf = &sriov->vf_info[i];
2173		vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans,
2174					  sizeof(*vf->sriov_vlans), GFP_KERNEL);
2175		if (!vf->sriov_vlans) {
2176			qlcnic_sriov_free_vlans(adapter);
2177			return -ENOMEM;
2178		}
2179	}
2180
2181	return 0;
2182}
2183
2184void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter)
2185{
2186	struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2187	struct qlcnic_vf_info *vf;
2188	int i;
2189
2190	for (i = 0; i < sriov->num_vfs; i++) {
2191		vf = &sriov->vf_info[i];
2192		kfree(vf->sriov_vlans);
2193		vf->sriov_vlans = NULL;
2194	}
2195}
2196
2197void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov,
2198			      struct qlcnic_vf_info *vf, u16 vlan_id)
2199{
2200	int i;
2201
2202	for (i = 0; i < sriov->num_allowed_vlans; i++) {
2203		if (!vf->sriov_vlans[i]) {
2204			vf->sriov_vlans[i] = vlan_id;
2205			vf->num_vlan++;
2206			return;
2207		}
2208	}
2209}
2210
2211void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov,
2212			      struct qlcnic_vf_info *vf, u16 vlan_id)
2213{
2214	int i;
2215
2216	for (i = 0; i < sriov->num_allowed_vlans; i++) {
2217		if (vf->sriov_vlans[i] == vlan_id) {
2218			vf->sriov_vlans[i] = 0;
2219			vf->num_vlan--;
2220			return;
2221		}
2222	}
2223}
2224
2225bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf)
2226{
2227	bool err = false;
2228
2229	spin_lock_bh(&vf->vlan_list_lock);
2230
2231	if (vf->num_vlan)
2232		err = true;
2233
2234	spin_unlock_bh(&vf->vlan_list_lock);
2235	return err;
2236}