qede_ptp.c

  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2/* QLogic qede NIC Driver
  3 * Copyright (c) 2015-2017  QLogic Corporation
  4 * Copyright (c) 2019-2020 Marvell International Ltd.
  5 */
  6
  7#include "qede_ptp.h"
  8#define QEDE_PTP_TX_TIMEOUT (2 * HZ)
  9
 10struct qede_ptp {
 11	const struct qed_eth_ptp_ops	*ops;
 12	struct ptp_clock_info		clock_info;
 13	struct cyclecounter		cc;
 14	struct timecounter		tc;
 15	struct ptp_clock		*clock;
 16	struct work_struct		work;
 17	unsigned long			ptp_tx_start;
 18	struct qede_dev			*edev;
 19	struct sk_buff			*tx_skb;
 20
 21	/* ptp spinlock is used for protecting the cycle/time counter fields
 22	 * and, also for serializing the qed PTP API invocations.
 23	 */
 24	spinlock_t			lock;
 25	bool				hw_ts_ioctl_called;
 26	u16				tx_type;
 27	u16				rx_filter;
 28};
 29
 30/**
 31 * qede_ptp_adjfine() - Adjust the frequency of the PTP cycle counter.
 32 *
 33 * @info: The PTP clock info structure.
 34 * @scaled_ppm: Scaled parts per million adjustment from base.
 35 *
 36 * Scaled parts per million is ppm with a 16-bit binary fractional field.
 37 *
 38 * Return: Zero on success, negative errno otherwise.
 39 */
 40static int qede_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
 41{
 42	struct qede_ptp *ptp = container_of(info, struct qede_ptp, clock_info);
 43	s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
 44	struct qede_dev *edev = ptp->edev;
 45	int rc;
 46
 47	__qede_lock(edev);
 48	if (edev->state == QEDE_STATE_OPEN) {
 49		spin_lock_bh(&ptp->lock);
 50		rc = ptp->ops->adjfreq(edev->cdev, ppb);
 51		spin_unlock_bh(&ptp->lock);
 52	} else {
 53		DP_ERR(edev, "PTP adjfine called while interface is down\n");
 54		rc = -EFAULT;
 55	}
 56	__qede_unlock(edev);
 57
 58	return rc;
 59}
 60
 61static int qede_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
 62{
 63	struct qede_dev *edev;
 64	struct qede_ptp *ptp;
 65
 66	ptp = container_of(info, struct qede_ptp, clock_info);
 67	edev = ptp->edev;
 68
 69	DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP adjtime called, delta = %llx\n",
 70		   delta);
 71
 72	spin_lock_bh(&ptp->lock);
 73	timecounter_adjtime(&ptp->tc, delta);
 74	spin_unlock_bh(&ptp->lock);
 75
 76	return 0;
 77}
 78
 79static int qede_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
 80{
 81	struct qede_dev *edev;
 82	struct qede_ptp *ptp;
 83	u64 ns;
 84
 85	ptp = container_of(info, struct qede_ptp, clock_info);
 86	edev = ptp->edev;
 87
 88	spin_lock_bh(&ptp->lock);
 89	ns = timecounter_read(&ptp->tc);
 90	spin_unlock_bh(&ptp->lock);
 91
 92	DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP gettime called, ns = %llu\n", ns);
 93
 94	*ts = ns_to_timespec64(ns);
 95
 96	return 0;
 97}
 98
 99static int qede_ptp_settime(struct ptp_clock_info *info,
100			    const struct timespec64 *ts)
101{
102	struct qede_dev *edev;
103	struct qede_ptp *ptp;
104	u64 ns;
105
106	ptp = container_of(info, struct qede_ptp, clock_info);
107	edev = ptp->edev;
108
109	ns = timespec64_to_ns(ts);
110
111	DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP settime called, ns = %llu\n", ns);
112
113	/* Re-init the timecounter */
114	spin_lock_bh(&ptp->lock);
115	timecounter_init(&ptp->tc, &ptp->cc, ns);
116	spin_unlock_bh(&ptp->lock);
117
118	return 0;
119}
120
121/* Enable (or disable) ancillary features of the phc subsystem */
122static int qede_ptp_ancillary_feature_enable(struct ptp_clock_info *info,
123					     struct ptp_clock_request *rq,
124					     int on)
125{
126	struct qede_dev *edev;
127	struct qede_ptp *ptp;
128
129	ptp = container_of(info, struct qede_ptp, clock_info);
130	edev = ptp->edev;
131
132	DP_ERR(edev, "PHC ancillary features are not supported\n");
133
134	return -ENOTSUPP;
135}
136
137static void qede_ptp_task(struct work_struct *work)
138{
139	struct skb_shared_hwtstamps shhwtstamps;
140	struct qede_dev *edev;
141	struct qede_ptp *ptp;
142	u64 timestamp, ns;
143	bool timedout;
144	int rc;
145
146	ptp = container_of(work, struct qede_ptp, work);
147	edev = ptp->edev;
148	timedout = time_is_before_jiffies(ptp->ptp_tx_start +
149					  QEDE_PTP_TX_TIMEOUT);
150
151	/* Read Tx timestamp registers */
152	spin_lock_bh(&ptp->lock);
153	rc = ptp->ops->read_tx_ts(edev->cdev, &timestamp);
154	spin_unlock_bh(&ptp->lock);
155	if (rc) {
156		if (unlikely(timedout)) {
157			DP_INFO(edev, "Tx timestamp is not recorded\n");
158			dev_kfree_skb_any(ptp->tx_skb);
159			ptp->tx_skb = NULL;
160			clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
161					 &edev->flags);
162			edev->ptp_skip_txts++;
163		} else {
164			/* Reschedule to keep checking for a valid TS value */
165			schedule_work(&ptp->work);
166		}
167		return;
168	}
169
170	ns = timecounter_cyc2time(&ptp->tc, timestamp);
171	memset(&shhwtstamps, 0, sizeof(shhwtstamps));
172	shhwtstamps.hwtstamp = ns_to_ktime(ns);
173	skb_tstamp_tx(ptp->tx_skb, &shhwtstamps);
174	dev_kfree_skb_any(ptp->tx_skb);
175	ptp->tx_skb = NULL;
176	clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
177
178	DP_VERBOSE(edev, QED_MSG_DEBUG,
179		   "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
180		   timestamp, ns);
181}
182
183/* Read the PHC. This API is invoked with ptp_lock held. */
184static u64 qede_ptp_read_cc(struct cyclecounter *cc)
185{
186	struct qede_dev *edev;
187	struct qede_ptp *ptp;
188	u64 phc_cycles;
189	int rc;
190
191	ptp = container_of(cc, struct qede_ptp, cc);
192	edev = ptp->edev;
193	rc = ptp->ops->read_cc(edev->cdev, &phc_cycles);
194	if (rc)
195		WARN_ONCE(1, "PHC read err %d\n", rc);
196
197	DP_VERBOSE(edev, QED_MSG_DEBUG, "PHC read cycles = %llu\n", phc_cycles);
198
199	return phc_cycles;
200}
201
202static void qede_ptp_cfg_filters(struct qede_dev *edev)
203{
204	enum qed_ptp_hwtstamp_tx_type tx_type = QED_PTP_HWTSTAMP_TX_ON;
205	enum qed_ptp_filter_type rx_filter = QED_PTP_FILTER_NONE;
206	struct qede_ptp *ptp = edev->ptp;
207
208	if (!ptp->hw_ts_ioctl_called) {
209		DP_INFO(edev, "TS IOCTL not called\n");
210		return;
211	}
212
213	switch (ptp->tx_type) {
214	case HWTSTAMP_TX_ON:
215		set_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
216		tx_type = QED_PTP_HWTSTAMP_TX_ON;
217		break;
218
219	case HWTSTAMP_TX_OFF:
220		clear_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
221		tx_type = QED_PTP_HWTSTAMP_TX_OFF;
222		break;
223	}
224
225	spin_lock_bh(&ptp->lock);
226	switch (ptp->rx_filter) {
227	case HWTSTAMP_FILTER_NONE:
228		rx_filter = QED_PTP_FILTER_NONE;
229		break;
230	case HWTSTAMP_FILTER_ALL:
231	case HWTSTAMP_FILTER_SOME:
232	case HWTSTAMP_FILTER_NTP_ALL:
233		ptp->rx_filter = HWTSTAMP_FILTER_NONE;
234		rx_filter = QED_PTP_FILTER_ALL;
235		break;
236	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
237		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
238		rx_filter = QED_PTP_FILTER_V1_L4_EVENT;
239		break;
240	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
241	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
242		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
243		/* Initialize PTP detection for UDP/IPv4 events */
244		rx_filter = QED_PTP_FILTER_V1_L4_GEN;
245		break;
246	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
247		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
248		rx_filter = QED_PTP_FILTER_V2_L4_EVENT;
249		break;
250	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
251	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
252		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
253		/* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
254		rx_filter = QED_PTP_FILTER_V2_L4_GEN;
255		break;
256	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
257		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
258		rx_filter = QED_PTP_FILTER_V2_L2_EVENT;
259		break;
260	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
261	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
262		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
263		/* Initialize PTP detection L2 events */
264		rx_filter = QED_PTP_FILTER_V2_L2_GEN;
265		break;
266	case HWTSTAMP_FILTER_PTP_V2_EVENT:
267		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
268		rx_filter = QED_PTP_FILTER_V2_EVENT;
269		break;
270	case HWTSTAMP_FILTER_PTP_V2_SYNC:
271	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
272		ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
273		/* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
274		rx_filter = QED_PTP_FILTER_V2_GEN;
275		break;
276	}
277
278	ptp->ops->cfg_filters(edev->cdev, rx_filter, tx_type);
279
280	spin_unlock_bh(&ptp->lock);
281}
282
283int qede_hwtstamp_set(struct net_device *netdev,
284		      struct kernel_hwtstamp_config *config,
285		      struct netlink_ext_ack *extack)
286{
287	struct qede_dev *edev = netdev_priv(netdev);
288	struct qede_ptp *ptp;
289
290	if (!netif_running(netdev)) {
291		NL_SET_ERR_MSG_MOD(extack, "Device is down");
292		return -EAGAIN;
293	}
294
295	ptp = edev->ptp;
296	if (!ptp) {
297		NL_SET_ERR_MSG_MOD(extack, "HW timestamping is not supported");
298		return -EIO;
299	}
300
301	DP_VERBOSE(edev, QED_MSG_DEBUG,
302		   "HWTSTAMP SET: Requested tx_type = %d, requested rx_filters = %d\n",
303		   config->tx_type, config->rx_filter);
304
305	switch (config->tx_type) {
306	case HWTSTAMP_TX_ON:
307	case HWTSTAMP_TX_OFF:
308		break;
309	default:
310		NL_SET_ERR_MSG_MOD(extack,
311				   "One-step timestamping is not supported");
312		return -ERANGE;
313	}
314
315	ptp->hw_ts_ioctl_called = 1;
316	ptp->tx_type = config->tx_type;
317	ptp->rx_filter = config->rx_filter;
318
319	qede_ptp_cfg_filters(edev);
320
321	config->rx_filter = ptp->rx_filter;
322
323	return 0;
324}
325
326int qede_hwtstamp_get(struct net_device *netdev,
327		      struct kernel_hwtstamp_config *config)
328{
329	struct qede_dev *edev = netdev_priv(netdev);
330	struct qede_ptp *ptp;
331
332	ptp = edev->ptp;
333	if (!ptp)
334		return -EIO;
335
336	config->tx_type = ptp->tx_type;
337	config->rx_filter = ptp->rx_filter;
338
339	return 0;
340}
341
342int qede_ptp_get_ts_info(struct qede_dev *edev, struct kernel_ethtool_ts_info *info)
343{
344	struct qede_ptp *ptp = edev->ptp;
345
346	if (!ptp) {
347		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
348
349		return 0;
350	}
351
352	info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
353				SOF_TIMESTAMPING_TX_HARDWARE |
354				SOF_TIMESTAMPING_RX_HARDWARE |
355				SOF_TIMESTAMPING_RAW_HARDWARE;
356
357	if (ptp->clock)
358		info->phc_index = ptp_clock_index(ptp->clock);
359
360	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
361			   BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
362			   BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
363			   BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
364			   BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
365			   BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
366			   BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
367			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
368			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
369			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
370			   BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
371			   BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
372			   BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
373
374	info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
375
376	return 0;
377}
378
379void qede_ptp_disable(struct qede_dev *edev)
380{
381	struct qede_ptp *ptp;
382
383	ptp = edev->ptp;
384	if (!ptp)
385		return;
386
387	if (ptp->clock) {
388		ptp_clock_unregister(ptp->clock);
389		ptp->clock = NULL;
390	}
391
392	/* Cancel PTP work queue. Should be done after the Tx queues are
393	 * drained to prevent additional scheduling.
394	 */
395	cancel_work_sync(&ptp->work);
396	if (ptp->tx_skb) {
397		dev_kfree_skb_any(ptp->tx_skb);
398		ptp->tx_skb = NULL;
399		clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
400	}
401
402	/* Disable PTP in HW */
403	spin_lock_bh(&ptp->lock);
404	ptp->ops->disable(edev->cdev);
405	spin_unlock_bh(&ptp->lock);
406
407	kfree(ptp);
408	edev->ptp = NULL;
409}
410
411static int qede_ptp_init(struct qede_dev *edev)
412{
413	struct qede_ptp *ptp;
414	int rc;
415
416	ptp = edev->ptp;
417	if (!ptp)
418		return -EINVAL;
419
420	spin_lock_init(&ptp->lock);
421
422	/* Configure PTP in HW */
423	rc = ptp->ops->enable(edev->cdev);
424	if (rc) {
425		DP_INFO(edev, "PTP HW enable failed\n");
426		return rc;
427	}
428
429	/* Init work queue for Tx timestamping */
430	INIT_WORK(&ptp->work, qede_ptp_task);
431
432	/* Init cyclecounter and timecounter */
433	memset(&ptp->cc, 0, sizeof(ptp->cc));
434	ptp->cc.read = qede_ptp_read_cc;
435	ptp->cc.mask = CYCLECOUNTER_MASK(64);
436	ptp->cc.shift = 0;
437	ptp->cc.mult = 1;
438
439	timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
440
441	return 0;
442}
443
444int qede_ptp_enable(struct qede_dev *edev)
445{
446	struct qede_ptp *ptp;
447	int rc;
448
449	ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
450	if (!ptp) {
451		DP_INFO(edev, "Failed to allocate struct for PTP\n");
452		return -ENOMEM;
453	}
454
455	ptp->edev = edev;
456	ptp->ops = edev->ops->ptp;
457	if (!ptp->ops) {
458		DP_INFO(edev, "PTP enable failed\n");
459		rc = -EIO;
460		goto err1;
461	}
462
463	edev->ptp = ptp;
464
465	rc = qede_ptp_init(edev);
466	if (rc)
467		goto err1;
468
469	qede_ptp_cfg_filters(edev);
470
471	/* Fill the ptp_clock_info struct and register PTP clock */
472	ptp->clock_info.owner = THIS_MODULE;
473	snprintf(ptp->clock_info.name, 16, "%s", edev->ndev->name);
474	ptp->clock_info.max_adj = QED_MAX_PHC_DRIFT_PPB;
475	ptp->clock_info.n_alarm = 0;
476	ptp->clock_info.n_ext_ts = 0;
477	ptp->clock_info.n_per_out = 0;
478	ptp->clock_info.pps = 0;
479	ptp->clock_info.adjfine = qede_ptp_adjfine;
480	ptp->clock_info.adjtime = qede_ptp_adjtime;
481	ptp->clock_info.gettime64 = qede_ptp_gettime;
482	ptp->clock_info.settime64 = qede_ptp_settime;
483	ptp->clock_info.enable = qede_ptp_ancillary_feature_enable;
484
485	ptp->clock = ptp_clock_register(&ptp->clock_info, &edev->pdev->dev);
486	if (IS_ERR(ptp->clock)) {
487		DP_ERR(edev, "PTP clock registration failed\n");
488		qede_ptp_disable(edev);
489		rc = -EINVAL;
490		goto err2;
491	}
492
493	return 0;
494
495err1:
496	kfree(ptp);
497err2:
498	edev->ptp = NULL;
499
500	return rc;
501}
502
503void qede_ptp_tx_ts(struct qede_dev *edev, struct sk_buff *skb)
504{
505	struct qede_ptp *ptp;
506
507	ptp = edev->ptp;
508	if (!ptp)
509		return;
510
511	if (test_and_set_bit_lock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
512				  &edev->flags)) {
513		DP_VERBOSE(edev, QED_MSG_DEBUG, "Timestamping in progress\n");
514		edev->ptp_skip_txts++;
515		return;
516	}
517
518	if (unlikely(!test_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags))) {
519		DP_VERBOSE(edev, QED_MSG_DEBUG,
520			   "Tx timestamping was not enabled, this pkt will not be timestamped\n");
521		clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
522		edev->ptp_skip_txts++;
523	} else if (unlikely(ptp->tx_skb)) {
524		DP_VERBOSE(edev, QED_MSG_DEBUG,
525			   "Device supports a single outstanding pkt to ts, It will not be ts\n");
526		clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
527		edev->ptp_skip_txts++;
528	} else {
529		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
530		/* schedule check for Tx timestamp */
531		ptp->tx_skb = skb_get(skb);
532		ptp->ptp_tx_start = jiffies;
533		schedule_work(&ptp->work);
534	}
535}
536
537void qede_ptp_rx_ts(struct qede_dev *edev, struct sk_buff *skb)
538{
539	struct qede_ptp *ptp;
540	u64 timestamp, ns;
541	int rc;
542
543	ptp = edev->ptp;
544	if (!ptp)
545		return;
546
547	spin_lock_bh(&ptp->lock);
548	rc = ptp->ops->read_rx_ts(edev->cdev, &timestamp);
549	if (rc) {
550		spin_unlock_bh(&ptp->lock);
551		DP_INFO(edev, "Invalid Rx timestamp\n");
552		return;
553	}
554
555	ns = timecounter_cyc2time(&ptp->tc, timestamp);
556	spin_unlock_bh(&ptp->lock);
557	skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
558	DP_VERBOSE(edev, QED_MSG_DEBUG,
559		   "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
560		   timestamp, ns);
561}