ionic_lif.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
  3
  4#ifndef _IONIC_LIF_H_
  5#define _IONIC_LIF_H_
  6
  7#include <linux/ptp_clock_kernel.h>
  8#include <linux/timecounter.h>
  9#include <linux/net_tstamp.h>
 10#include <linux/dim.h>
 11#include <linux/pci.h>
 12#include "ionic_rx_filter.h"
 13#include "ionic_api.h"
 14
 15#define IONIC_ADMINQ_LENGTH	16	/* must be a power of two */
 16#define IONIC_NOTIFYQ_LENGTH	64	/* must be a power of two */
 17
 18#define ADD_ADDR	true
 19#define DEL_ADDR	false
 20#define CAN_SLEEP	true
 21#define CAN_NOT_SLEEP	false
 22
 23#define IONIC_RX_COPYBREAK_DEFAULT	256
 24#define IONIC_TX_BUDGET_DEFAULT		256
 25
 26struct ionic_tx_stats {
 27	u64 pkts;
 28	u64 bytes;
 29	u64 csum_none;
 30	u64 csum;
 31	u64 tso;
 32	u64 tso_bytes;
 33	u64 frags;
 34	u64 vlan_inserted;
 35	u64 clean;
 36	u64 linearize;
 37	u64 crc32_csum;
 38	u64 dma_map_err;
 39	u64 hwstamp_valid;
 40	u64 hwstamp_invalid;
 41	u64 xdp_frames;
 42};
 43
 44struct ionic_rx_stats {
 45	u64 pkts;
 46	u64 bytes;
 47	u64 csum_none;
 48	u64 csum_complete;
 49	u64 dropped;
 50	u64 vlan_stripped;
 51	u64 csum_error;
 52	u64 dma_map_err;
 53	u64 alloc_err;
 54	u64 hwstamp_valid;
 55	u64 hwstamp_invalid;
 56	u64 xdp_drop;
 57	u64 xdp_aborted;
 58	u64 xdp_pass;
 59	u64 xdp_tx;
 60	u64 xdp_redirect;
 61};
 62
 63#define IONIC_QCQ_F_INITED		BIT(0)
 64#define IONIC_QCQ_F_SG			BIT(1)
 65#define IONIC_QCQ_F_INTR		BIT(2)
 66#define IONIC_QCQ_F_TX_STATS		BIT(3)
 67#define IONIC_QCQ_F_RX_STATS		BIT(4)
 68#define IONIC_QCQ_F_NOTIFYQ		BIT(5)
 69#define IONIC_QCQ_F_CMB_RINGS		BIT(6)
 70
 71struct ionic_qcq {
 72	void *q_base;
 73	dma_addr_t q_base_pa;
 74	u32 q_size;
 75	u32 cq_size;
 76	void *cq_base;
 77	dma_addr_t cq_base_pa;
 78	void *sg_base;
 79	dma_addr_t sg_base_pa;
 80	u32 sg_size;
 81	unsigned int flags;
 82	void __iomem *cmb_q_base;
 83	phys_addr_t cmb_q_base_pa;
 84	u32 cmb_q_size;
 85	u32 cmb_pgid;
 86	u32 cmb_order;
 87	struct dim dim;
 88	struct ionic_queue q;
 89	struct ionic_cq cq;
 90	struct napi_struct napi;
 91	struct ionic_intr_info intr;
 92	struct work_struct doorbell_napi_work;
 93	struct dentry *dentry;
 94};
 95
 96#define q_to_qcq(q)		container_of(q, struct ionic_qcq, q)
 97#define q_to_tx_stats(q)	(&(q)->lif->txqstats[(q)->index])
 98#define q_to_rx_stats(q)	(&(q)->lif->rxqstats[(q)->index])
 99#define napi_to_qcq(napi)	container_of(napi, struct ionic_qcq, napi)
100#define napi_to_cq(napi)	(&napi_to_qcq(napi)->cq)
101
102enum ionic_deferred_work_type {
103	IONIC_DW_TYPE_RX_MODE,
104	IONIC_DW_TYPE_LINK_STATUS,
105	IONIC_DW_TYPE_LIF_RESET,
106};
107
108struct ionic_deferred_work {
109	struct list_head list;
110	enum ionic_deferred_work_type type;
111	union {
112		u8 addr[ETH_ALEN];
113		u8 fw_status;
114	};
115};
116
117struct ionic_deferred {
118	spinlock_t lock;		/* lock for deferred work list */
119	struct list_head list;
120	struct work_struct work;
121};
122
123struct ionic_lif_sw_stats {
124	u64 tx_packets;
125	u64 tx_bytes;
126	u64 rx_packets;
127	u64 rx_bytes;
128	u64 tx_tso;
129	u64 tx_tso_bytes;
130	u64 tx_csum_none;
131	u64 tx_csum;
132	u64 rx_csum_none;
133	u64 rx_csum_complete;
134	u64 rx_csum_error;
135	u64 tx_hwstamp_valid;
136	u64 tx_hwstamp_invalid;
137	u64 rx_hwstamp_valid;
138	u64 rx_hwstamp_invalid;
139	u64 hw_tx_dropped;
140	u64 hw_rx_dropped;
141	u64 hw_rx_over_errors;
142	u64 hw_rx_missed_errors;
143	u64 hw_tx_aborted_errors;
144	u64 xdp_drop;
145	u64 xdp_aborted;
146	u64 xdp_pass;
147	u64 xdp_tx;
148	u64 xdp_redirect;
149	u64 xdp_frames;
150};
151
152enum ionic_lif_state_flags {
153	IONIC_LIF_F_INITED,
154	IONIC_LIF_F_UP,
155	IONIC_LIF_F_LINK_CHECK_REQUESTED,
156	IONIC_LIF_F_FILTER_SYNC_NEEDED,
157	IONIC_LIF_F_FW_RESET,
158	IONIC_LIF_F_FW_STOPPING,
159	IONIC_LIF_F_SPLIT_INTR,
160	IONIC_LIF_F_BROKEN,
161	IONIC_LIF_F_TX_DIM_INTR,
162	IONIC_LIF_F_RX_DIM_INTR,
163	IONIC_LIF_F_CMB_TX_RINGS,
164	IONIC_LIF_F_CMB_RX_RINGS,
165
166	/* leave this as last */
167	IONIC_LIF_F_STATE_SIZE
168};
169
170struct ionic_qtype_info {
171	u8  version;
172	u8  supported;
173	u64 features;
174	u16 desc_sz;
175	u16 comp_sz;
176	u16 sg_desc_sz;
177	u16 max_sg_elems;
178	u16 sg_desc_stride;
179};
180
181struct ionic_phc;
182
183#define IONIC_LIF_NAME_MAX_SZ		32
184struct ionic_lif {
185	struct net_device *netdev;
186	DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE);
187	struct ionic *ionic;
188	unsigned int index;
189	unsigned int hw_index;
190	struct mutex queue_lock;	/* lock for queue structures */
191	struct mutex config_lock;	/* lock for config actions */
192	spinlock_t adminq_lock;		/* lock for AdminQ operations */
193	struct ionic_qcq *adminqcq;
194	struct ionic_qcq *notifyqcq;
195	struct ionic_qcq **txqcqs;
196	struct ionic_qcq *hwstamp_txq;
197	struct ionic_tx_stats *txqstats;
198	struct ionic_qcq **rxqcqs;
199	struct ionic_qcq *hwstamp_rxq;
200	struct ionic_rx_stats *rxqstats;
201	struct ionic_deferred deferred;
202	struct work_struct tx_timeout_work;
203	u64 last_eid;
204	unsigned int kern_pid;
205	u64 __iomem *kern_dbpage;
206	unsigned int neqs;
207	unsigned int nxqs;
208	unsigned int ntxq_descs;
209	unsigned int nrxq_descs;
210	u64 rxq_features;
211	u64 hw_features;
212	u16 rx_copybreak;
213	u16 rx_mode;
214	bool registered;
215	bool doorbell_wa;
216	u16 lif_type;
217	unsigned int link_down_count;
218	unsigned int nmcast;
219	unsigned int nucast;
220	unsigned int nvlans;
221	unsigned int max_vlans;
222	char name[IONIC_LIF_NAME_MAX_SZ];
223
224	union ionic_lif_identity *identity;
225	struct ionic_lif_info *info;
226	dma_addr_t info_pa;
227	u32 info_sz;
228	struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX];
229	struct ionic_aux_dev *ionic_adev;
230	struct mutex adev_lock;	/* lock for aux_dev actions */
231
232	u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE];
233	u8 *rss_ind_tbl;
234	dma_addr_t rss_ind_tbl_pa;
235	u32 rss_ind_tbl_sz;
236	u16 rss_types;
237
238	struct ionic_rx_filters rx_filters;
239	u32 rx_coalesce_usecs;		/* what the user asked for */
240	u32 rx_coalesce_hw;		/* what the hw is using */
241	u32 tx_coalesce_usecs;		/* what the user asked for */
242	u32 tx_coalesce_hw;		/* what the hw is using */
243	unsigned int dbid_count;
244
245	struct ionic_phc *phc;
246
247	struct dentry *dentry;
248	struct bpf_prog *xdp_prog;
249};
250
251struct ionic_phc {
252	spinlock_t lock; /* lock for cc and tc */
253	struct cyclecounter cc;
254	struct timecounter tc;
255
256	struct mutex config_lock; /* lock for ts_config */
257	struct kernel_hwtstamp_config ts_config;
258	u64 ts_config_rx_filt;
259	u32 ts_config_tx_mode;
260
261	u32 init_cc_mult;
262	long aux_work_delay;
263
264	struct ptp_clock_info ptp_info;
265	struct ptp_clock *ptp;
266	struct ionic_lif *lif;
267};
268
269struct ionic_queue_params {
270	unsigned int nxqs;
271	unsigned int ntxq_descs;
272	unsigned int nrxq_descs;
273	u64 rxq_features;
274	struct bpf_prog *xdp_prog;
275	bool intr_split;
276	bool cmb_tx;
277	bool cmb_rx;
278};
279
280static inline void ionic_init_queue_params(struct ionic_lif *lif,
281					   struct ionic_queue_params *qparam)
282{
283	qparam->nxqs = lif->nxqs;
284	qparam->ntxq_descs = lif->ntxq_descs;
285	qparam->nrxq_descs = lif->nrxq_descs;
286	qparam->rxq_features = lif->rxq_features;
287	qparam->xdp_prog = lif->xdp_prog;
288	qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
289	qparam->cmb_tx = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state);
290	qparam->cmb_rx = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state);
291}
292
293static inline void ionic_set_queue_params(struct ionic_lif *lif,
294					  struct ionic_queue_params *qparam)
295{
296	lif->nxqs = qparam->nxqs;
297	lif->ntxq_descs = qparam->ntxq_descs;
298	lif->nrxq_descs = qparam->nrxq_descs;
299	lif->rxq_features = qparam->rxq_features;
300
301	if (qparam->intr_split)
302		set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
303	else
304		clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
305
306	if (qparam->cmb_tx)
307		set_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state);
308	else
309		clear_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state);
310
311	if (qparam->cmb_rx)
312		set_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state);
313	else
314		clear_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state);
315}
316
317static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs)
318{
319	u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult);
320	u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div);
321
322	/* Div-by-zero should never be an issue, but check anyway */
323	if (!div || !mult)
324		return 0;
325
326	/* Round up in case usecs is close to the next hw unit */
327	usecs += (div / mult) >> 1;
328
329	/* Convert from usecs to device units */
330	return (usecs * mult) / div;
331}
332
333static inline bool ionic_txq_hwstamp_enabled(struct ionic_queue *q)
334{
335	return q->features & IONIC_TXQ_F_HWSTAMP;
336}
337
338void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep);
339void ionic_get_stats64(struct net_device *netdev,
340		       struct rtnl_link_stats64 *ns);
341void ionic_lif_deferred_enqueue(struct ionic_lif *lif,
342				struct ionic_deferred_work *work);
343int ionic_lif_alloc(struct ionic *ionic);
344int ionic_lif_init(struct ionic_lif *lif);
345void ionic_lif_free(struct ionic_lif *lif);
346void ionic_lif_deinit(struct ionic_lif *lif);
347
348int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr);
349int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr);
350
351void ionic_stop_queues_reconfig(struct ionic_lif *lif);
352void ionic_txrx_free(struct ionic_lif *lif);
353void ionic_qcqs_free(struct ionic_lif *lif);
354int ionic_restart_lif(struct ionic_lif *lif);
355
356int ionic_lif_register(struct ionic_lif *lif);
357void ionic_lif_unregister(struct ionic_lif *lif);
358int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
359		       union ionic_lif_identity *lif_ident);
360int ionic_lif_size(struct ionic *ionic);
361
362#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
363void ionic_lif_hwstamp_replay(struct ionic_lif *lif);
364void ionic_lif_hwstamp_recreate_queues(struct ionic_lif *lif);
365int ionic_hwstamp_set(struct net_device *netdev,
366		      struct kernel_hwtstamp_config *config,
367		      struct netlink_ext_ack *extack);
368int ionic_hwstamp_get(struct net_device *netdev,
369		      struct kernel_hwtstamp_config *config);
370ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 counter);
371void ionic_lif_register_phc(struct ionic_lif *lif);
372void ionic_lif_unregister_phc(struct ionic_lif *lif);
373void ionic_lif_alloc_phc(struct ionic_lif *lif);
374void ionic_lif_free_phc(struct ionic_lif *lif);
375#else
376static inline void ionic_lif_hwstamp_replay(struct ionic_lif *lif) {}
377static inline void ionic_lif_hwstamp_recreate_queues(struct ionic_lif *lif) {}
378
379static inline int ionic_hwstamp_set(struct net_device *netdev,
380				    struct kernel_hwtstamp_config *config,
381				    struct netlink_ext_ack *extack)
382{
383	return -EOPNOTSUPP;
384}
385
386static inline int ionic_hwstamp_get(struct net_device *netdev,
387				    struct kernel_hwtstamp_config *config)
388{
389	return -EOPNOTSUPP;
390}
391
392static inline ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 counter)
393{
394	return ns_to_ktime(0);
395}
396
397static inline void ionic_lif_register_phc(struct ionic_lif *lif) {}
398static inline void ionic_lif_unregister_phc(struct ionic_lif *lif) {}
399static inline void ionic_lif_alloc_phc(struct ionic_lif *lif) {}
400static inline void ionic_lif_free_phc(struct ionic_lif *lif) {}
401#endif
402
403int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif);
404int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif);
405int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all);
406int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode);
407int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class);
408
409int ionic_lif_rss_config(struct ionic_lif *lif, u16 types,
410			 const u8 *key, const u32 *indir);
411void ionic_lif_rx_mode(struct ionic_lif *lif);
412int ionic_reconfigure_queues(struct ionic_lif *lif,
413			     struct ionic_queue_params *qparam);
414#endif /* _IONIC_LIF_H_ */