ionic_lif.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
   3
   4#include <linux/ethtool.h>
   5#include <linux/printk.h>
   6#include <linux/dynamic_debug.h>
   7#include <linux/netdevice.h>
   8#include <linux/etherdevice.h>
   9#include <linux/if_vlan.h>
  10#include <linux/rtnetlink.h>
  11#include <linux/interrupt.h>
  12#include <linux/pci.h>
  13#include <linux/cpumask.h>
  14#include <linux/crash_dump.h>
  15#include <linux/vmalloc.h>
  16#include <net/page_pool/helpers.h>
  17
  18#include "ionic.h"
  19#include "ionic_bus.h"
  20#include "ionic_dev.h"
  21#include "ionic_lif.h"
  22#include "ionic_aux.h"
  23#include "ionic_txrx.h"
  24#include "ionic_ethtool.h"
  25#include "ionic_debugfs.h"
  26
  27/* queuetype support level */
  28static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = {
  29	[IONIC_QTYPE_ADMINQ]  = 0,   /* 0 = Base version with CQ support */
  30	[IONIC_QTYPE_NOTIFYQ] = 0,   /* 0 = Base version */
  31	[IONIC_QTYPE_RXQ]     = 2,   /* 0 = Base version with CQ+SG support
  32				      * 2 =       ... with CMB rings
  33				      */
  34	[IONIC_QTYPE_TXQ]     = 3,   /* 0 = Base version with CQ+SG support
  35				      * 1 =       ... with Tx SG version 1
  36				      * 3 =       ... with CMB rings
  37				      */
  38};
  39
  40static void ionic_link_status_check(struct ionic_lif *lif);
  41static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
  42static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
  43static void ionic_lif_set_netdev_info(struct ionic_lif *lif);
  44
  45static void ionic_txrx_deinit(struct ionic_lif *lif);
  46static int ionic_txrx_init(struct ionic_lif *lif);
  47static int ionic_start_queues(struct ionic_lif *lif);
  48static void ionic_stop_queues(struct ionic_lif *lif);
  49static void ionic_lif_queue_identify(struct ionic_lif *lif);
  50
  51static void ionic_xdp_rxqs_prog_update(struct ionic_lif *lif);
  52static void ionic_unregister_rxq_info(struct ionic_queue *q);
  53static int ionic_register_rxq_info(struct ionic_queue *q, unsigned int napi_id);
  54
  55static void ionic_dim_work(struct work_struct *work)
  56{
  57	struct dim *dim = container_of(work, struct dim, work);
  58	struct dim_cq_moder cur_moder;
  59	struct ionic_intr_info *intr;
  60	struct ionic_qcq *qcq;
  61	struct ionic_lif *lif;
  62	struct ionic_queue *q;
  63	u32 new_coal;
  64
  65	qcq = container_of(dim, struct ionic_qcq, dim);
  66	q = &qcq->q;
  67	if (q->type == IONIC_QTYPE_RXQ)
  68		cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
  69	else
  70		cur_moder = net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
  71	lif = q->lif;
  72	new_coal = ionic_coal_usec_to_hw(lif->ionic, cur_moder.usec);
  73	new_coal = new_coal ? new_coal : 1;
  74
  75	intr = &qcq->intr;
  76	if (intr->dim_coal_hw != new_coal) {
  77		intr->dim_coal_hw = new_coal;
  78
  79		ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
  80				     intr->index, intr->dim_coal_hw);
  81	}
  82
  83	dim->state = DIM_START_MEASURE;
  84}
  85
  86static void ionic_lif_deferred_work(struct work_struct *work)
  87{
  88	struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
  89	struct ionic_deferred *def = &lif->deferred;
  90	struct ionic_deferred_work *w = NULL;
  91
  92	do {
  93		spin_lock_bh(&def->lock);
  94		if (!list_empty(&def->list)) {
  95			w = list_first_entry(&def->list,
  96					     struct ionic_deferred_work, list);
  97			list_del(&w->list);
  98		}
  99		spin_unlock_bh(&def->lock);
 100
 101		if (!w)
 102			break;
 103
 104		switch (w->type) {
 105		case IONIC_DW_TYPE_RX_MODE:
 106			ionic_lif_rx_mode(lif);
 107			break;
 108		case IONIC_DW_TYPE_LINK_STATUS:
 109			ionic_link_status_check(lif);
 110			break;
 111		case IONIC_DW_TYPE_LIF_RESET:
 112			if (w->fw_status) {
 113				ionic_lif_handle_fw_up(lif);
 114			} else {
 115				ionic_lif_handle_fw_down(lif);
 116
 117				/* Fire off another watchdog to see
 118				 * if the FW is already back rather than
 119				 * waiting another whole cycle
 120				 */
 121				mod_timer(&lif->ionic->watchdog_timer, jiffies + 1);
 122			}
 123			break;
 124		default:
 125			break;
 126		}
 127		kfree(w);
 128		w = NULL;
 129	} while (true);
 130}
 131
 132void ionic_lif_deferred_enqueue(struct ionic_lif *lif,
 133				struct ionic_deferred_work *work)
 134{
 135	spin_lock_bh(&lif->deferred.lock);
 136	list_add_tail(&work->list, &lif->deferred.list);
 137	spin_unlock_bh(&lif->deferred.lock);
 138	queue_work(lif->ionic->wq, &lif->deferred.work);
 139}
 140
 141static void ionic_link_status_check(struct ionic_lif *lif)
 142{
 143	struct net_device *netdev = lif->netdev;
 144	u16 link_status;
 145	bool link_up;
 146
 147	if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
 148		return;
 149
 150	/* Don't put carrier back up if we're in a broken state */
 151	if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) {
 152		clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
 153		return;
 154	}
 155
 156	link_status = le16_to_cpu(lif->info->status.link_status);
 157	link_up = link_status == IONIC_PORT_OPER_STATUS_UP;
 158
 159	if (link_up) {
 160		int err = 0;
 161
 162		if (netdev->flags & IFF_UP && netif_running(netdev)) {
 163			mutex_lock(&lif->queue_lock);
 164			err = ionic_start_queues(lif);
 165			if (err && err != -EBUSY) {
 166				netdev_err(netdev,
 167					   "Failed to start queues: %d\n", err);
 168				set_bit(IONIC_LIF_F_BROKEN, lif->state);
 169				netif_carrier_off(lif->netdev);
 170			}
 171			mutex_unlock(&lif->queue_lock);
 172		}
 173
 174		if (!err && !netif_carrier_ok(netdev)) {
 175			ionic_port_identify(lif->ionic);
 176			netdev_info(netdev, "Link up - %d Gbps\n",
 177				    le32_to_cpu(lif->info->status.link_speed) / 1000);
 178			netif_carrier_on(netdev);
 179		}
 180	} else {
 181		if (netif_carrier_ok(netdev)) {
 182			lif->link_down_count++;
 183			netdev_info(netdev, "Link down\n");
 184			netif_carrier_off(netdev);
 185		}
 186
 187		if (netdev->flags & IFF_UP && netif_running(netdev)) {
 188			mutex_lock(&lif->queue_lock);
 189			ionic_stop_queues(lif);
 190			mutex_unlock(&lif->queue_lock);
 191		}
 192	}
 193
 194	clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
 195}
 196
 197void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep)
 198{
 199	struct ionic_deferred_work *work;
 200
 201	/* we only need one request outstanding at a time */
 202	if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
 203		return;
 204
 205	if (!can_sleep) {
 206		work = kzalloc(sizeof(*work), GFP_ATOMIC);
 207		if (!work) {
 208			clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
 209			return;
 210		}
 211
 212		work->type = IONIC_DW_TYPE_LINK_STATUS;
 213		ionic_lif_deferred_enqueue(lif, work);
 214	} else {
 215		ionic_link_status_check(lif);
 216	}
 217}
 218
 219static irqreturn_t ionic_isr(int irq, void *data)
 220{
 221	struct napi_struct *napi = data;
 222
 223	napi_schedule_irqoff(napi);
 224
 225	return IRQ_HANDLED;
 226}
 227
 228static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
 229{
 230	struct ionic_intr_info *intr = &qcq->intr;
 231	struct device *dev = lif->ionic->dev;
 232	struct ionic_queue *q = &qcq->q;
 233	const char *name;
 234
 235	if (lif->registered)
 236		name = netdev_name(lif->netdev);
 237	else
 238		name = dev_name(dev);
 239
 240	snprintf(intr->name, sizeof(intr->name),
 241		 "%.5s-%.16s-%.8s", IONIC_DRV_NAME, name, q->name);
 242
 243	return devm_request_irq(dev, intr->vector, ionic_isr,
 244				0, intr->name, &qcq->napi);
 245}
 246
 247int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 248{
 249	struct ionic *ionic = lif->ionic;
 250	int index, err;
 251
 252	index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
 253	if (index == ionic->nintrs)
 254		return -ENOSPC;
 255
 256	set_bit(index, ionic->intrs);
 257	ionic_intr_init(&ionic->idev, intr, index);
 258
 259	err = ionic_bus_get_irq(ionic, intr->index);
 260	if (err < 0) {
 261		clear_bit(index, ionic->intrs);
 262		return err;
 263	}
 264
 265	intr->vector = err;
 266
 267	return 0;
 268}
 269EXPORT_SYMBOL_NS(ionic_intr_alloc, "NET_IONIC");
 270
 271void ionic_intr_free(struct ionic_lif *lif, int index)
 272{
 273	if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < lif->ionic->nintrs)
 274		clear_bit(index, lif->ionic->intrs);
 275}
 276EXPORT_SYMBOL_NS(ionic_intr_free, "NET_IONIC");
 277
 278static void ionic_irq_aff_notify(struct irq_affinity_notify *notify,
 279				 const cpumask_t *mask)
 280{
 281	struct ionic_intr_info *intr = container_of(notify, struct ionic_intr_info, aff_notify);
 282
 283	cpumask_copy(*intr->affinity_mask, mask);
 284}
 285
 286static void ionic_irq_aff_release(struct kref __always_unused *ref)
 287{
 288}
 289
 290static int ionic_qcq_enable(struct ionic_qcq *qcq)
 291{
 292	struct ionic_queue *q = &qcq->q;
 293	struct ionic_lif *lif = q->lif;
 294	struct ionic_dev *idev;
 295	struct device *dev;
 296
 297	struct ionic_admin_ctx ctx = {
 298		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 299		.cmd.q_control = {
 300			.opcode = IONIC_CMD_Q_CONTROL,
 301			.lif_index = cpu_to_le16(lif->index),
 302			.type = q->type,
 303			.index = cpu_to_le32(q->index),
 304			.oper = IONIC_Q_ENABLE,
 305		},
 306	};
 307	int ret;
 308
 309	idev = &lif->ionic->idev;
 310	dev = lif->ionic->dev;
 311
 312	dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
 313		ctx.cmd.q_control.index, ctx.cmd.q_control.type);
 314
 315	if (qcq->flags & IONIC_QCQ_F_INTR)
 316		ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
 317
 318	ret = ionic_adminq_post_wait(lif, &ctx);
 319	if (ret)
 320		return ret;
 321
 322	if (qcq->flags & IONIC_QCQ_F_INTR) {
 323		napi_enable(&qcq->napi);
 324		irq_set_affinity_notifier(qcq->intr.vector,
 325					  &qcq->intr.aff_notify);
 326		irq_set_affinity_hint(qcq->intr.vector,
 327				      *qcq->intr.affinity_mask);
 328		ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 329				IONIC_INTR_MASK_CLEAR);
 330	}
 331
 332	return 0;
 333}
 334
 335static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err)
 336{
 337	struct ionic_queue *q;
 338
 339	struct ionic_admin_ctx ctx = {
 340		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 341		.cmd.q_control = {
 342			.opcode = IONIC_CMD_Q_CONTROL,
 343			.oper = IONIC_Q_DISABLE,
 344		},
 345	};
 346
 347	if (!qcq) {
 348		netdev_err(lif->netdev, "%s: bad qcq\n", __func__);
 349		return -ENXIO;
 350	}
 351
 352	q = &qcq->q;
 353
 354	if (qcq->flags & IONIC_QCQ_F_INTR) {
 355		struct ionic_dev *idev = &lif->ionic->idev;
 356
 357		if (lif->doorbell_wa)
 358			cancel_work_sync(&qcq->doorbell_napi_work);
 359		cancel_work_sync(&qcq->dim.work);
 360		ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 361				IONIC_INTR_MASK_SET);
 362		synchronize_irq(qcq->intr.vector);
 363		irq_set_affinity_notifier(qcq->intr.vector, NULL);
 364		irq_set_affinity_hint(qcq->intr.vector, NULL);
 365		napi_disable(&qcq->napi);
 366	}
 367
 368	/* If there was a previous fw communcation error, don't bother with
 369	 * sending the adminq command and just return the same error value.
 370	 */
 371	if (fw_err == -ETIMEDOUT || fw_err == -ENXIO)
 372		return fw_err;
 373
 374	ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index);
 375	ctx.cmd.q_control.type = q->type;
 376	ctx.cmd.q_control.index = cpu_to_le32(q->index);
 377	dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n",
 378		ctx.cmd.q_control.index, ctx.cmd.q_control.type);
 379
 380	return ionic_adminq_post_wait(lif, &ctx);
 381}
 382
 383static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 384{
 385	struct ionic_dev *idev = &lif->ionic->idev;
 386
 387	if (!qcq)
 388		return;
 389
 390	if (!(qcq->flags & IONIC_QCQ_F_INITED))
 391		return;
 392
 393	ionic_unregister_rxq_info(&qcq->q);
 394	if (qcq->flags & IONIC_QCQ_F_INTR) {
 395		ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 396				IONIC_INTR_MASK_SET);
 397		netif_napi_del(&qcq->napi);
 398	}
 399
 400	qcq->flags &= ~IONIC_QCQ_F_INITED;
 401}
 402
 403static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
 404{
 405	if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0)
 406		return;
 407
 408	irq_set_affinity_hint(qcq->intr.vector, NULL);
 409	devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi);
 410	qcq->intr.vector = 0;
 411	ionic_intr_free(lif, qcq->intr.index);
 412	qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 413}
 414
 415static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
 416{
 417	struct device *dev = lif->ionic->dev;
 418
 419	if (!qcq)
 420		return;
 421
 422	ionic_debugfs_del_qcq(qcq);
 423
 424	if (qcq->q_base) {
 425		dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa);
 426		qcq->q_base = NULL;
 427		qcq->q_base_pa = 0;
 428	}
 429
 430	if (qcq->cmb_q_base) {
 431		iounmap(qcq->cmb_q_base);
 432		ionic_put_cmb(lif, qcq->cmb_pgid, qcq->cmb_order);
 433		qcq->cmb_pgid = 0;
 434		qcq->cmb_order = 0;
 435		qcq->cmb_q_base = NULL;
 436		qcq->cmb_q_base_pa = 0;
 437	}
 438
 439	if (qcq->cq_base) {
 440		dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa);
 441		qcq->cq_base = NULL;
 442		qcq->cq_base_pa = 0;
 443	}
 444
 445	if (qcq->sg_base) {
 446		dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa);
 447		qcq->sg_base = NULL;
 448		qcq->sg_base_pa = 0;
 449	}
 450
 451	page_pool_destroy(qcq->q.page_pool);
 452	qcq->q.page_pool = NULL;
 453
 454	ionic_qcq_intr_free(lif, qcq);
 455	vfree(qcq->q.info);
 456	qcq->q.info = NULL;
 457}
 458
 459void ionic_qcqs_free(struct ionic_lif *lif)
 460{
 461	struct device *dev = lif->ionic->dev;
 462	struct ionic_qcq *adminqcq;
 463	unsigned long irqflags;
 464
 465	if (lif->notifyqcq) {
 466		ionic_qcq_free(lif, lif->notifyqcq);
 467		devm_kfree(dev, lif->notifyqcq);
 468		lif->notifyqcq = NULL;
 469	}
 470
 471	if (lif->adminqcq) {
 472		spin_lock_irqsave(&lif->adminq_lock, irqflags);
 473		adminqcq = READ_ONCE(lif->adminqcq);
 474		lif->adminqcq = NULL;
 475		spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
 476		if (adminqcq) {
 477			ionic_qcq_free(lif, adminqcq);
 478			devm_kfree(dev, adminqcq);
 479		}
 480	}
 481
 482	if (lif->rxqcqs) {
 483		devm_kfree(dev, lif->rxqstats);
 484		lif->rxqstats = NULL;
 485		devm_kfree(dev, lif->rxqcqs);
 486		lif->rxqcqs = NULL;
 487	}
 488
 489	if (lif->txqcqs) {
 490		devm_kfree(dev, lif->txqstats);
 491		lif->txqstats = NULL;
 492		devm_kfree(dev, lif->txqcqs);
 493		lif->txqcqs = NULL;
 494	}
 495}
 496
 497static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
 498				      struct ionic_qcq *n_qcq)
 499{
 500	n_qcq->intr.vector = src_qcq->intr.vector;
 501	n_qcq->intr.index = src_qcq->intr.index;
 502}
 503
 504static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
 505{
 506	cpumask_var_t *affinity_mask;
 507	int err;
 508
 509	if (!(qcq->flags & IONIC_QCQ_F_INTR)) {
 510		qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 511		return 0;
 512	}
 513
 514	err = ionic_intr_alloc(lif, &qcq->intr);
 515	if (err) {
 516		netdev_warn(lif->netdev, "no intr for %s: %d\n",
 517			    qcq->q.name, err);
 518		goto err_out;
 519	}
 520
 521	ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index,
 522			       IONIC_INTR_MASK_SET);
 523
 524	err = ionic_request_irq(lif, qcq);
 525	if (err) {
 526		netdev_warn(lif->netdev, "irq request failed %d\n", err);
 527		goto err_out_free_intr;
 528	}
 529
 530	/* try to get the irq on the local numa node first */
 531	affinity_mask = &lif->ionic->affinity_masks[qcq->intr.index];
 532	if (cpumask_empty(*affinity_mask)) {
 533		unsigned int cpu;
 534
 535		cpu = cpumask_local_spread(qcq->intr.index,
 536					   dev_to_node(lif->ionic->dev));
 537		if (cpu != -1)
 538			cpumask_set_cpu(cpu, *affinity_mask);
 539	}
 540
 541	qcq->intr.affinity_mask = affinity_mask;
 542	qcq->intr.aff_notify.notify = ionic_irq_aff_notify;
 543	qcq->intr.aff_notify.release = ionic_irq_aff_release;
 544
 545	netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
 546	return 0;
 547
 548err_out_free_intr:
 549	ionic_intr_free(lif, qcq->intr.index);
 550err_out:
 551	return err;
 552}
 553
 554static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
 555			   unsigned int index,
 556			   const char *name, unsigned int flags,
 557			   unsigned int num_descs, unsigned int desc_size,
 558			   unsigned int cq_desc_size,
 559			   unsigned int sg_desc_size,
 560			   unsigned int desc_info_size,
 561			   unsigned int pid, struct bpf_prog *xdp_prog,
 562			   struct ionic_qcq **qcq)
 563{
 564	struct ionic_dev *idev = &lif->ionic->idev;
 565	struct device *dev = lif->ionic->dev;
 566	struct ionic_qcq *new;
 567	int err;
 568
 569	*qcq = NULL;
 570
 571	new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
 572	if (!new) {
 573		netdev_err(lif->netdev, "Cannot allocate queue structure\n");
 574		err = -ENOMEM;
 575		goto err_out;
 576	}
 577
 578	new->q.dev = dev;
 579	new->flags = flags;
 580
 581	new->q.info = vcalloc(num_descs, desc_info_size);
 582	if (!new->q.info) {
 583		netdev_err(lif->netdev, "Cannot allocate queue info\n");
 584		err = -ENOMEM;
 585		goto err_out_free_qcq;
 586	}
 587
 588	if (type == IONIC_QTYPE_RXQ) {
 589		struct page_pool_params pp_params = {
 590			.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
 591			.order = 0,
 592			.pool_size = num_descs,
 593			.nid = NUMA_NO_NODE,
 594			.dev = lif->ionic->dev,
 595			.napi = &new->napi,
 596			.dma_dir = DMA_FROM_DEVICE,
 597			.max_len = PAGE_SIZE,
 598			.netdev = lif->netdev,
 599		};
 600
 601		if (xdp_prog)
 602			pp_params.dma_dir = DMA_BIDIRECTIONAL;
 603
 604		new->q.page_pool = page_pool_create(&pp_params);
 605		if (IS_ERR(new->q.page_pool)) {
 606			netdev_err(lif->netdev, "Cannot create page_pool\n");
 607			err = PTR_ERR(new->q.page_pool);
 608			new->q.page_pool = NULL;
 609			goto err_out_free_q_info;
 610		}
 611	}
 612
 613	new->q.type = type;
 614	new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems;
 615
 616	err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
 617			   desc_size, sg_desc_size, pid);
 618	if (err) {
 619		netdev_err(lif->netdev, "Cannot initialize queue\n");
 620		goto err_out_free_page_pool;
 621	}
 622
 623	err = ionic_alloc_qcq_interrupt(lif, new);
 624	if (err)
 625		goto err_out_free_page_pool;
 626
 627	err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
 628	if (err) {
 629		netdev_err(lif->netdev, "Cannot initialize completion queue\n");
 630		goto err_out_free_irq;
 631	}
 632
 633	if (flags & IONIC_QCQ_F_NOTIFYQ) {
 634		int q_size;
 635
 636		/* q & cq need to be contiguous in NotifyQ, so alloc it all in q
 637		 * and don't alloc qc.  We leave new->qc_size and new->qc_base
 638		 * as 0 to be sure we don't try to free it later.
 639		 */
 640		q_size = ALIGN(num_descs * desc_size, PAGE_SIZE);
 641		new->q_size = PAGE_SIZE + q_size +
 642			      ALIGN(num_descs * cq_desc_size, PAGE_SIZE);
 643		new->q_base = dma_alloc_coherent(dev, new->q_size,
 644						 &new->q_base_pa, GFP_KERNEL);
 645		if (!new->q_base) {
 646			netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n");
 647			err = -ENOMEM;
 648			goto err_out_free_irq;
 649		}
 650		new->q.base = PTR_ALIGN(new->q_base, PAGE_SIZE);
 651		new->q.base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
 652
 653		/* Base the NotifyQ cq.base off of the ALIGNed q.base */
 654		new->cq.base = PTR_ALIGN(new->q.base + q_size, PAGE_SIZE);
 655		new->cq.base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE);
 656		new->cq.bound_q = &new->q;
 657	} else {
 658		/* regular DMA q descriptors */
 659		new->q_size = PAGE_SIZE + (num_descs * desc_size);
 660		new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa,
 661						 GFP_KERNEL);
 662		if (!new->q_base) {
 663			netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
 664			err = -ENOMEM;
 665			goto err_out_free_irq;
 666		}
 667		new->q.base = PTR_ALIGN(new->q_base, PAGE_SIZE);
 668		new->q.base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
 669
 670		if (flags & IONIC_QCQ_F_CMB_RINGS) {
 671			/* on-chip CMB q descriptors */
 672			new->cmb_q_size = num_descs * desc_size;
 673			new->cmb_order = order_base_2(new->cmb_q_size / PAGE_SIZE);
 674
 675			err = ionic_get_cmb(lif, &new->cmb_pgid, &new->cmb_q_base_pa,
 676					    new->cmb_order, 0, NULL);
 677			if (err) {
 678				netdev_err(lif->netdev,
 679					   "Cannot allocate queue order %d from cmb: err %d\n",
 680					   new->cmb_order, err);
 681				goto err_out_free_q;
 682			}
 683
 684			new->cmb_q_base = ioremap_wc(new->cmb_q_base_pa, new->cmb_q_size);
 685			if (!new->cmb_q_base) {
 686				netdev_err(lif->netdev, "Cannot map queue from cmb\n");
 687				ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order);
 688				err = -ENOMEM;
 689				goto err_out_free_q;
 690			}
 691
 692			new->cmb_q_base_pa -= idev->phy_cmb_pages;
 693			new->q.cmb_base = new->cmb_q_base;
 694			new->q.cmb_base_pa = new->cmb_q_base_pa;
 695		}
 696
 697		/* cq DMA descriptors */
 698		new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size);
 699		new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa,
 700						  GFP_KERNEL);
 701		if (!new->cq_base) {
 702			netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n");
 703			err = -ENOMEM;
 704			goto err_out_free_q;
 705		}
 706		new->cq.base = PTR_ALIGN(new->cq_base, PAGE_SIZE);
 707		new->cq.base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE);
 708		new->cq.bound_q = &new->q;
 709	}
 710
 711	if (flags & IONIC_QCQ_F_SG) {
 712		new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size);
 713		new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa,
 714						  GFP_KERNEL);
 715		if (!new->sg_base) {
 716			netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n");
 717			err = -ENOMEM;
 718			goto err_out_free_cq;
 719		}
 720		new->q.sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE);
 721		new->q.sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE);
 722	}
 723
 724	INIT_WORK(&new->dim.work, ionic_dim_work);
 725	new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 726	if (lif->doorbell_wa)
 727		INIT_WORK(&new->doorbell_napi_work, ionic_doorbell_napi_work);
 728
 729	*qcq = new;
 730
 731	return 0;
 732
 733err_out_free_cq:
 734	dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa);
 735err_out_free_q:
 736	if (new->cmb_q_base) {
 737		iounmap(new->cmb_q_base);
 738		ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order);
 739	}
 740	dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa);
 741err_out_free_irq:
 742	if (flags & IONIC_QCQ_F_INTR) {
 743		devm_free_irq(dev, new->intr.vector, &new->napi);
 744		ionic_intr_free(lif, new->intr.index);
 745	}
 746err_out_free_page_pool:
 747	page_pool_destroy(new->q.page_pool);
 748err_out_free_q_info:
 749	vfree(new->q.info);
 750err_out_free_qcq:
 751	devm_kfree(dev, new);
 752err_out:
 753	dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
 754	return err;
 755}
 756
 757static int ionic_qcqs_alloc(struct ionic_lif *lif)
 758{
 759	struct device *dev = lif->ionic->dev;
 760	unsigned int flags;
 761	int err;
 762
 763	flags = IONIC_QCQ_F_INTR;
 764	err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 765			      IONIC_ADMINQ_LENGTH,
 766			      sizeof(struct ionic_admin_cmd),
 767			      sizeof(struct ionic_admin_comp),
 768			      0,
 769			      sizeof(struct ionic_admin_desc_info),
 770			      lif->kern_pid, NULL, &lif->adminqcq);
 771	if (err)
 772		return err;
 773	ionic_debugfs_add_qcq(lif, lif->adminqcq);
 774
 775	if (lif->ionic->nnqs_per_lif) {
 776		flags = IONIC_QCQ_F_NOTIFYQ;
 777		err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
 778				      flags, IONIC_NOTIFYQ_LENGTH,
 779				      sizeof(struct ionic_notifyq_cmd),
 780				      sizeof(union ionic_notifyq_comp),
 781				      0,
 782				      sizeof(struct ionic_admin_desc_info),
 783				      lif->kern_pid, NULL, &lif->notifyqcq);
 784		if (err)
 785			goto err_out;
 786		ionic_debugfs_add_qcq(lif, lif->notifyqcq);
 787
 788		/* Let the notifyq ride on the adminq interrupt */
 789		ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
 790	}
 791
 792	err = -ENOMEM;
 793	lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
 794				   sizeof(*lif->txqcqs), GFP_KERNEL);
 795	if (!lif->txqcqs)
 796		goto err_out;
 797	lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
 798				   sizeof(*lif->rxqcqs), GFP_KERNEL);
 799	if (!lif->rxqcqs)
 800		goto err_out;
 801
 802	lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1,
 803				     sizeof(*lif->txqstats), GFP_KERNEL);
 804	if (!lif->txqstats)
 805		goto err_out;
 806	lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1,
 807				     sizeof(*lif->rxqstats), GFP_KERNEL);
 808	if (!lif->rxqstats)
 809		goto err_out;
 810
 811	return 0;
 812
 813err_out:
 814	ionic_qcqs_free(lif);
 815	return err;
 816}
 817
 818static void ionic_qcq_sanitize(struct ionic_qcq *qcq)
 819{
 820	qcq->q.tail_idx = 0;
 821	qcq->q.head_idx = 0;
 822	qcq->cq.tail_idx = 0;
 823	qcq->cq.done_color = 1;
 824	memset(qcq->q_base, 0, qcq->q_size);
 825	if (qcq->cmb_q_base)
 826		memset_io(qcq->cmb_q_base, 0, qcq->cmb_q_size);
 827	memset(qcq->cq_base, 0, qcq->cq_size);
 828	memset(qcq->sg_base, 0, qcq->sg_size);
 829}
 830
 831static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
 832{
 833	struct device *dev = lif->ionic->dev;
 834	struct ionic_queue *q = &qcq->q;
 835	struct ionic_cq *cq = &qcq->cq;
 836	struct ionic_admin_ctx ctx = {
 837		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 838		.cmd.q_init = {
 839			.opcode = IONIC_CMD_Q_INIT,
 840			.lif_index = cpu_to_le16(lif->index),
 841			.type = q->type,
 842			.ver = lif->qtype_info[q->type].version,
 843			.index = cpu_to_le32(q->index),
 844			.flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
 845					     IONIC_QINIT_F_SG),
 846			.intr_index = cpu_to_le16(qcq->intr.index),
 847			.pid = cpu_to_le16(q->pid),
 848			.ring_size = ilog2(q->num_descs),
 849			.ring_base = cpu_to_le64(q->base_pa),
 850			.cq_ring_base = cpu_to_le64(cq->base_pa),
 851			.sg_ring_base = cpu_to_le64(q->sg_base_pa),
 852			.features = cpu_to_le64(q->features),
 853		},
 854	};
 855	int err;
 856
 857	if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) {
 858		ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB);
 859		ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa);
 860	}
 861
 862	dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
 863	dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
 864	dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
 865	dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
 866	dev_dbg(dev, "txq_init.cq_ring_base 0x%llx\n", ctx.cmd.q_init.cq_ring_base);
 867	dev_dbg(dev, "txq_init.sg_ring_base 0x%llx\n", ctx.cmd.q_init.sg_ring_base);
 868	dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
 869	dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver);
 870	dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
 871
 872	ionic_qcq_sanitize(qcq);
 873
 874	err = ionic_adminq_post_wait(lif, &ctx);
 875	if (err)
 876		return err;
 877
 878	q->hw_type = ctx.comp.q_init.hw_type;
 879	q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
 880	q->dbval = IONIC_DBELL_QID(q->hw_index);
 881
 882	dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
 883	dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
 884
 885	q->dbell_deadline = IONIC_TX_DOORBELL_DEADLINE;
 886	q->dbell_jiffies = jiffies;
 887
 888	if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
 889		netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi);
 890
 891	qcq->flags |= IONIC_QCQ_F_INITED;
 892
 893	return 0;
 894}
 895
 896static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
 897{
 898	struct device *dev = lif->ionic->dev;
 899	struct ionic_queue *q = &qcq->q;
 900	struct ionic_cq *cq = &qcq->cq;
 901	struct ionic_admin_ctx ctx = {
 902		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 903		.cmd.q_init = {
 904			.opcode = IONIC_CMD_Q_INIT,
 905			.lif_index = cpu_to_le16(lif->index),
 906			.type = q->type,
 907			.ver = lif->qtype_info[q->type].version,
 908			.index = cpu_to_le32(q->index),
 909			.flags = cpu_to_le16(IONIC_QINIT_F_IRQ),
 910			.intr_index = cpu_to_le16(cq->bound_intr->index),
 911			.pid = cpu_to_le16(q->pid),
 912			.ring_size = ilog2(q->num_descs),
 913			.ring_base = cpu_to_le64(q->base_pa),
 914			.cq_ring_base = cpu_to_le64(cq->base_pa),
 915			.sg_ring_base = cpu_to_le64(q->sg_base_pa),
 916			.features = cpu_to_le64(q->features),
 917		},
 918	};
 919	int err;
 920
 921	q->partner = &lif->txqcqs[q->index]->q;
 922	q->partner->partner = q;
 923
 924	if (!lif->xdp_prog ||
 925	    (lif->xdp_prog->aux && lif->xdp_prog->aux->xdp_has_frags))
 926		ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_SG);
 927
 928	if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) {
 929		ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB);
 930		ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa);
 931	}
 932
 933	dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
 934	dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
 935	dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
 936	dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
 937	dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
 938	dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver);
 939	dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
 940
 941	ionic_qcq_sanitize(qcq);
 942
 943	err = ionic_adminq_post_wait(lif, &ctx);
 944	if (err)
 945		return err;
 946
 947	q->hw_type = ctx.comp.q_init.hw_type;
 948	q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
 949	q->dbval = IONIC_DBELL_QID(q->hw_index);
 950
 951	dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
 952	dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
 953
 954	q->dbell_deadline = IONIC_RX_MIN_DOORBELL_DEADLINE;
 955	q->dbell_jiffies = jiffies;
 956
 957	if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
 958		netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi);
 959	else
 960		netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi);
 961	err = ionic_register_rxq_info(q, qcq->napi.napi_id);
 962	if (err) {
 963		netif_napi_del(&qcq->napi);
 964		return err;
 965	}
 966
 967	qcq->flags |= IONIC_QCQ_F_INITED;
 968
 969	return 0;
 970}
 971
 972int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif)
 973{
 974	unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
 975	unsigned int txq_i, flags;
 976	struct ionic_qcq *txq;
 977	u64 features;
 978	int err;
 979
 980	if (lif->hwstamp_txq)
 981		return 0;
 982
 983	features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP;
 984
 985	num_desc = IONIC_MIN_TXRX_DESC;
 986	desc_sz = sizeof(struct ionic_txq_desc);
 987	comp_sz = 2 * sizeof(struct ionic_txq_comp);
 988
 989	if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
 990	    lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1))
 991		sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
 992	else
 993		sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
 994
 995	txq_i = lif->ionic->ntxqs_per_lif;
 996	flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
 997
 998	err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags,
 999			      num_desc, desc_sz, comp_sz, sg_desc_sz,
1000			      sizeof(struct ionic_tx_desc_info),
1001			      lif->kern_pid, NULL, &txq);
1002	if (err)
1003		goto err_qcq_alloc;
1004
1005	txq->q.features = features;
1006
1007	ionic_link_qcq_interrupts(lif->adminqcq, txq);
1008	ionic_debugfs_add_qcq(lif, txq);
1009
1010	lif->hwstamp_txq = txq;
1011
1012	if (netif_running(lif->netdev)) {
1013		err = ionic_lif_txq_init(lif, txq);
1014		if (err)
1015			goto err_qcq_init;
1016
1017		if (test_bit(IONIC_LIF_F_UP, lif->state)) {
1018			err = ionic_qcq_enable(txq);
1019			if (err)
1020				goto err_qcq_enable;
1021		}
1022	}
1023
1024	return 0;
1025
1026err_qcq_enable:
1027	ionic_lif_qcq_deinit(lif, txq);
1028err_qcq_init:
1029	lif->hwstamp_txq = NULL;
1030	ionic_debugfs_del_qcq(txq);
1031	ionic_qcq_free(lif, txq);
1032	devm_kfree(lif->ionic->dev, txq);
1033err_qcq_alloc:
1034	return err;
1035}
1036
1037int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif)
1038{
1039	unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
1040	unsigned int rxq_i, flags;
1041	struct ionic_qcq *rxq;
1042	u64 features;
1043	int err;
1044
1045	if (lif->hwstamp_rxq)
1046		return 0;
1047
1048	features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
1049
1050	num_desc = IONIC_MIN_TXRX_DESC;
1051	desc_sz = sizeof(struct ionic_rxq_desc);
1052	comp_sz = 2 * sizeof(struct ionic_rxq_comp);
1053	sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
1054
1055	rxq_i = lif->ionic->nrxqs_per_lif;
1056	flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG;
1057
1058	err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags,
1059			      num_desc, desc_sz, comp_sz, sg_desc_sz,
1060			      sizeof(struct ionic_rx_desc_info),
1061			      lif->kern_pid, NULL, &rxq);
1062	if (err)
1063		goto err_qcq_alloc;
1064
1065	rxq->q.features = features;
1066
1067	ionic_link_qcq_interrupts(lif->adminqcq, rxq);
1068	ionic_debugfs_add_qcq(lif, rxq);
1069
1070	lif->hwstamp_rxq = rxq;
1071
1072	if (netif_running(lif->netdev)) {
1073		err = ionic_lif_rxq_init(lif, rxq);
1074		if (err)
1075			goto err_qcq_init;
1076
1077		if (test_bit(IONIC_LIF_F_UP, lif->state)) {
1078			ionic_rx_fill(&rxq->q, NULL);
1079			err = ionic_qcq_enable(rxq);
1080			if (err)
1081				goto err_qcq_enable;
1082		}
1083	}
1084
1085	return 0;
1086
1087err_qcq_enable:
1088	ionic_lif_qcq_deinit(lif, rxq);
1089err_qcq_init:
1090	lif->hwstamp_rxq = NULL;
1091	ionic_debugfs_del_qcq(rxq);
1092	ionic_qcq_free(lif, rxq);
1093	devm_kfree(lif->ionic->dev, rxq);
1094err_qcq_alloc:
1095	return err;
1096}
1097
1098int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all)
1099{
1100	struct ionic_queue_params qparam;
1101
1102	ionic_init_queue_params(lif, &qparam);
1103
1104	if (rx_all)
1105		qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
1106	else
1107		qparam.rxq_features = 0;
1108
1109	/* if we're not running, just set the values and return */
1110	if (!netif_running(lif->netdev)) {
1111		lif->rxq_features = qparam.rxq_features;
1112		return 0;
1113	}
1114
1115	return ionic_reconfigure_queues(lif, &qparam);
1116}
1117
1118int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode)
1119{
1120	struct ionic_admin_ctx ctx = {
1121		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1122		.cmd.lif_setattr = {
1123			.opcode = IONIC_CMD_LIF_SETATTR,
1124			.index = cpu_to_le16(lif->index),
1125			.attr = IONIC_LIF_ATTR_TXSTAMP,
1126			.txstamp_mode = cpu_to_le16(txstamp_mode),
1127		},
1128	};
1129
1130	return ionic_adminq_post_wait(lif, &ctx);
1131}
1132
1133static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif)
1134{
1135	struct ionic_admin_ctx ctx = {
1136		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1137		.cmd.rx_filter_del = {
1138			.opcode = IONIC_CMD_RX_FILTER_DEL,
1139			.lif_index = cpu_to_le16(lif->index),
1140		},
1141	};
1142	struct ionic_rx_filter *f;
1143	u32 filter_id;
1144	int err;
1145
1146	spin_lock_bh(&lif->rx_filters.lock);
1147
1148	f = ionic_rx_filter_rxsteer(lif);
1149	if (!f) {
1150		spin_unlock_bh(&lif->rx_filters.lock);
1151		return;
1152	}
1153
1154	filter_id = f->filter_id;
1155	ionic_rx_filter_free(lif, f);
1156
1157	spin_unlock_bh(&lif->rx_filters.lock);
1158
1159	netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id);
1160
1161	ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id);
1162
1163	err = ionic_adminq_post_wait(lif, &ctx);
1164	if (err && err != -EEXIST)
1165		netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id);
1166}
1167
1168static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1169{
1170	struct ionic_admin_ctx ctx = {
1171		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1172		.cmd.rx_filter_add = {
1173			.opcode = IONIC_CMD_RX_FILTER_ADD,
1174			.lif_index = cpu_to_le16(lif->index),
1175			.match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS),
1176			.pkt_class = cpu_to_le64(pkt_class),
1177		},
1178	};
1179	u8 qtype;
1180	u32 qid;
1181	int err;
1182
1183	if (!lif->hwstamp_rxq)
1184		return -EINVAL;
1185
1186	qtype = lif->hwstamp_rxq->q.type;
1187	ctx.cmd.rx_filter_add.qtype = qtype;
1188
1189	qid = lif->hwstamp_rxq->q.index;
1190	ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid);
1191
1192	netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n");
1193	err = ionic_adminq_post_wait(lif, &ctx);
1194	if (err && err != -EEXIST)
1195		return err;
1196
1197	spin_lock_bh(&lif->rx_filters.lock);
1198	err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED);
1199	spin_unlock_bh(&lif->rx_filters.lock);
1200
1201	return err;
1202}
1203
1204int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1205{
1206	ionic_lif_del_hwstamp_rxfilt(lif);
1207
1208	if (!pkt_class)
1209		return 0;
1210
1211	return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class);
1212}
1213
1214static int ionic_adminq_napi(struct napi_struct *napi, int budget)
1215{
1216	struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr;
1217	struct ionic_lif *lif = napi_to_cq(napi)->lif;
1218	struct ionic_dev *idev = &lif->ionic->idev;
1219	unsigned long irqflags;
1220	unsigned int flags = 0;
1221	int rx_work = 0;
1222	int tx_work = 0;
1223	int n_work = 0;
1224	int a_work = 0;
1225	int work_done;
1226	int credits;
1227
1228	if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)
1229		n_work = ionic_cq_service(&lif->notifyqcq->cq, budget,
1230					  ionic_notifyq_service, NULL, NULL);
1231
1232	spin_lock_irqsave(&lif->adminq_lock, irqflags);
1233	if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED)
1234		a_work = ionic_cq_service(&lif->adminqcq->cq, budget,
1235					  ionic_adminq_service, NULL, NULL);
1236
1237	spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
1238
1239	if (lif->hwstamp_rxq)
1240		rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget,
1241					   ionic_rx_service, NULL, NULL);
1242
1243	if (lif->hwstamp_txq)
1244		tx_work = ionic_tx_cq_service(&lif->hwstamp_txq->cq, budget, !!budget);
1245
1246	work_done = max(max(n_work, a_work), max(rx_work, tx_work));
1247	if (work_done < budget && napi_complete_done(napi, work_done)) {
1248		flags |= IONIC_INTR_CRED_UNMASK;
1249		intr->rearm_count++;
1250	}
1251
1252	if (work_done || flags) {
1253		flags |= IONIC_INTR_CRED_RESET_COALESCE;
1254		credits = n_work + a_work + rx_work + tx_work;
1255		ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags);
1256	}
1257
1258	if (lif->doorbell_wa) {
1259		if (!a_work)
1260			ionic_adminq_poke_doorbell(&lif->adminqcq->q);
1261		if (lif->hwstamp_rxq && !rx_work)
1262			ionic_rxq_poke_doorbell(&lif->hwstamp_rxq->q);
1263		if (lif->hwstamp_txq && !tx_work)
1264			ionic_txq_poke_doorbell(&lif->hwstamp_txq->q);
1265	}
1266
1267	return work_done;
1268}
1269
1270void ionic_get_stats64(struct net_device *netdev,
1271		       struct rtnl_link_stats64 *ns)
1272{
1273	struct ionic_lif *lif = netdev_priv(netdev);
1274	struct ionic_lif_stats *ls;
1275
1276	memset(ns, 0, sizeof(*ns));
1277	ls = &lif->info->stats;
1278
1279	ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
1280			 le64_to_cpu(ls->rx_mcast_packets) +
1281			 le64_to_cpu(ls->rx_bcast_packets);
1282
1283	ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
1284			 le64_to_cpu(ls->tx_mcast_packets) +
1285			 le64_to_cpu(ls->tx_bcast_packets);
1286
1287	ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
1288		       le64_to_cpu(ls->rx_mcast_bytes) +
1289		       le64_to_cpu(ls->rx_bcast_bytes);
1290
1291	ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
1292		       le64_to_cpu(ls->tx_mcast_bytes) +
1293		       le64_to_cpu(ls->tx_bcast_bytes);
1294
1295	ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
1296			 le64_to_cpu(ls->rx_mcast_drop_packets) +
1297			 le64_to_cpu(ls->rx_bcast_drop_packets);
1298
1299	ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
1300			 le64_to_cpu(ls->tx_mcast_drop_packets) +
1301			 le64_to_cpu(ls->tx_bcast_drop_packets);
1302
1303	ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
1304
1305	ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
1306
1307	ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
1308			       le64_to_cpu(ls->rx_queue_disabled) +
1309			       le64_to_cpu(ls->rx_desc_fetch_error) +
1310			       le64_to_cpu(ls->rx_desc_data_error);
1311
1312	ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
1313				le64_to_cpu(ls->tx_queue_disabled) +
1314				le64_to_cpu(ls->tx_desc_fetch_error) +
1315				le64_to_cpu(ls->tx_desc_data_error);
1316
1317	ns->rx_errors = ns->rx_over_errors +
1318			ns->rx_missed_errors;
1319
1320	ns->tx_errors = ns->tx_aborted_errors;
1321}
1322
1323static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
1324{
1325	return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR);
1326}
1327
1328static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
1329{
1330	/* Don't delete our own address from the uc list */
1331	if (ether_addr_equal(addr, netdev->dev_addr))
1332		return 0;
1333
1334	return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR);
1335}
1336
1337void ionic_lif_rx_mode(struct ionic_lif *lif)
1338{
1339	struct net_device *netdev = lif->netdev;
1340	unsigned int nfilters;
1341	unsigned int nd_flags;
1342	char buf[128];
1343	u16 rx_mode;
1344	int i;
1345#define REMAIN(__x) (sizeof(buf) - (__x))
1346
1347	mutex_lock(&lif->config_lock);
1348
1349	/* grab the flags once for local use */
1350	nd_flags = netdev->flags;
1351
1352	rx_mode = IONIC_RX_MODE_F_UNICAST;
1353	rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
1354	rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
1355	rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
1356	rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;
1357
1358	/* sync the filters */
1359	ionic_rx_filter_sync(lif);
1360
1361	/* check for overflow state
1362	 *    if so, we track that we overflowed and enable NIC PROMISC
1363	 *    else if the overflow is set and not needed
1364	 *       we remove our overflow flag and check the netdev flags
1365	 *       to see if we can disable NIC PROMISC
1366	 */
1367	nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
1368
1369	if (((lif->nucast + lif->nmcast) >= nfilters) ||
1370	    (lif->max_vlans && lif->nvlans >= lif->max_vlans)) {
1371		rx_mode |= IONIC_RX_MODE_F_PROMISC;
1372		rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
1373	} else {
1374		if (!(nd_flags & IFF_PROMISC))
1375			rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
1376		if (!(nd_flags & IFF_ALLMULTI))
1377			rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
1378	}
1379
1380	i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
1381		      lif->rx_mode, rx_mode);
1382	if (rx_mode & IONIC_RX_MODE_F_UNICAST)
1383		i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
1384	if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
1385		i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
1386	if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
1387		i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
1388	if (rx_mode & IONIC_RX_MODE_F_PROMISC)
1389		i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
1390	if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
1391		i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
1392	if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER)
1393		i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER");
1394	netdev_dbg(netdev, "lif%d %s\n", lif->index, buf);
1395
1396	if (lif->rx_mode != rx_mode) {
1397		struct ionic_admin_ctx ctx = {
1398			.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1399			.cmd.rx_mode_set = {
1400				.opcode = IONIC_CMD_RX_MODE_SET,
1401				.lif_index = cpu_to_le16(lif->index),
1402			},
1403		};
1404		int err;
1405
1406		ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode);
1407		err = ionic_adminq_post_wait(lif, &ctx);
1408		if (err)
1409			netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n",
1410				    rx_mode, err);
1411		else
1412			lif->rx_mode = rx_mode;
1413	}
1414
1415	mutex_unlock(&lif->config_lock);
1416}
1417
1418static void ionic_ndo_set_rx_mode(struct net_device *netdev)
1419{
1420	struct ionic_lif *lif = netdev_priv(netdev);
1421	struct ionic_deferred_work *work;
1422
1423	/* Sync the kernel filter list with the driver filter list */
1424	__dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
1425	__dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
1426
1427	/* Shove off the rest of the rxmode work to the work task
1428	 * which will include syncing the filters to the firmware.
1429	 */
1430	work = kzalloc(sizeof(*work), GFP_ATOMIC);
1431	if (!work) {
1432		netdev_err(lif->netdev, "rxmode change dropped\n");
1433		return;
1434	}
1435	work->type = IONIC_DW_TYPE_RX_MODE;
1436	netdev_dbg(lif->netdev, "deferred: rx_mode\n");
1437	ionic_lif_deferred_enqueue(lif, work);
1438}
1439
1440static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
1441{
1442	u64 wanted = 0;
1443
1444	if (features & NETIF_F_HW_VLAN_CTAG_TX)
1445		wanted |= IONIC_ETH_HW_VLAN_TX_TAG;
1446	if (features & NETIF_F_HW_VLAN_CTAG_RX)
1447		wanted |= IONIC_ETH_HW_VLAN_RX_STRIP;
1448	if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1449		wanted |= IONIC_ETH_HW_VLAN_RX_FILTER;
1450	if (features & NETIF_F_RXHASH)
1451		wanted |= IONIC_ETH_HW_RX_HASH;
1452	if (features & NETIF_F_RXCSUM)
1453		wanted |= IONIC_ETH_HW_RX_CSUM;
1454	if (features & NETIF_F_SG)
1455		wanted |= IONIC_ETH_HW_TX_SG;
1456	if (features & NETIF_F_HW_CSUM)
1457		wanted |= IONIC_ETH_HW_TX_CSUM;
1458	if (features & NETIF_F_TSO)
1459		wanted |= IONIC_ETH_HW_TSO;
1460	if (features & NETIF_F_TSO6)
1461		wanted |= IONIC_ETH_HW_TSO_IPV6;
1462	if (features & NETIF_F_TSO_ECN)
1463		wanted |= IONIC_ETH_HW_TSO_ECN;
1464	if (features & NETIF_F_GSO_GRE)
1465		wanted |= IONIC_ETH_HW_TSO_GRE;
1466	if (features & NETIF_F_GSO_GRE_CSUM)
1467		wanted |= IONIC_ETH_HW_TSO_GRE_CSUM;
1468	if (features & NETIF_F_GSO_IPXIP4)
1469		wanted |= IONIC_ETH_HW_TSO_IPXIP4;
1470	if (features & NETIF_F_GSO_IPXIP6)
1471		wanted |= IONIC_ETH_HW_TSO_IPXIP6;
1472	if (features & NETIF_F_GSO_UDP_TUNNEL)
1473		wanted |= IONIC_ETH_HW_TSO_UDP;
1474	if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
1475		wanted |= IONIC_ETH_HW_TSO_UDP_CSUM;
1476
1477	return cpu_to_le64(wanted);
1478}
1479
1480static int ionic_set_nic_features(struct ionic_lif *lif,
1481				  netdev_features_t features)
1482{
1483	struct device *dev = lif->ionic->dev;
1484	struct ionic_admin_ctx ctx = {
1485		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1486		.cmd.lif_setattr = {
1487			.opcode = IONIC_CMD_LIF_SETATTR,
1488			.index = cpu_to_le16(lif->index),
1489			.attr = IONIC_LIF_ATTR_FEATURES,
1490		},
1491	};
1492	u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG |
1493			 IONIC_ETH_HW_VLAN_RX_STRIP |
1494			 IONIC_ETH_HW_VLAN_RX_FILTER;
1495	u64 old_hw_features;
1496	int err;
1497
1498	ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
1499
1500	if (lif->phc)
1501		ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP);
1502
1503	err = ionic_adminq_post_wait(lif, &ctx);
1504	if (err)
1505		return err;
1506
1507	old_hw_features = lif->hw_features;
1508	lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
1509				       ctx.comp.lif_setattr.features);
1510
1511	if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
1512		ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1513
1514	if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) &&
1515	    !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
1516		dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
1517
1518	if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1519		dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
1520	if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1521		dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
1522	if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1523		dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
1524	if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1525		dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
1526	if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1527		dev_dbg(dev, "feature ETH_HW_TX_SG\n");
1528	if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1529		dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
1530	if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1531		dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
1532	if (lif->hw_features & IONIC_ETH_HW_TSO)
1533		dev_dbg(dev, "feature ETH_HW_TSO\n");
1534	if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1535		dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
1536	if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1537		dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
1538	if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1539		dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
1540	if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1541		dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
1542	if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1543		dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
1544	if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1545		dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
1546	if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1547		dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
1548	if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1549		dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
1550	if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP)
1551		dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n");
1552
1553	return 0;
1554}
1555
1556static int ionic_init_nic_features(struct ionic_lif *lif)
1557{
1558	struct net_device *netdev = lif->netdev;
1559	netdev_features_t features;
1560	int err;
1561
1562	/* set up what we expect to support by default */
1563	features = NETIF_F_HW_VLAN_CTAG_TX |
1564		   NETIF_F_HW_VLAN_CTAG_RX |
1565		   NETIF_F_HW_VLAN_CTAG_FILTER |
1566		   NETIF_F_SG |
1567		   NETIF_F_HW_CSUM |
1568		   NETIF_F_RXCSUM |
1569		   NETIF_F_TSO |
1570		   NETIF_F_TSO6 |
1571		   NETIF_F_TSO_ECN |
1572		   NETIF_F_GSO_GRE |
1573		   NETIF_F_GSO_GRE_CSUM |
1574		   NETIF_F_GSO_IPXIP4 |
1575		   NETIF_F_GSO_IPXIP6 |
1576		   NETIF_F_GSO_UDP_TUNNEL |
1577		   NETIF_F_GSO_UDP_TUNNEL_CSUM;
1578
1579	if (lif->nxqs > 1)
1580		features |= NETIF_F_RXHASH;
1581
1582	err = ionic_set_nic_features(lif, features);
1583	if (err)
1584		return err;
1585
1586	/* tell the netdev what we actually can support */
1587	netdev->features |= NETIF_F_HIGHDMA;
1588
1589	if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1590		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
1591	if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1592		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1593	if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1594		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1595	if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1596		netdev->hw_features |= NETIF_F_RXHASH;
1597	if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1598		netdev->hw_features |= NETIF_F_SG;
1599
1600	if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1601		netdev->hw_enc_features |= NETIF_F_HW_CSUM;
1602	if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1603		netdev->hw_enc_features |= NETIF_F_RXCSUM;
1604	if (lif->hw_features & IONIC_ETH_HW_TSO)
1605		netdev->hw_enc_features |= NETIF_F_TSO;
1606	if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1607		netdev->hw_enc_features |= NETIF_F_TSO6;
1608	if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1609		netdev->hw_enc_features |= NETIF_F_TSO_ECN;
1610	if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1611		netdev->hw_enc_features |= NETIF_F_GSO_GRE;
1612	if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1613		netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
1614	if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1615		netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
1616	if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1617		netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
1618	if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1619		netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
1620	if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1621		netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1622
1623	netdev->hw_features |= netdev->hw_enc_features;
1624	netdev->features |= netdev->hw_features;
1625	netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES;
1626
1627	netdev->priv_flags |= IFF_UNICAST_FLT |
1628			      IFF_LIVE_ADDR_CHANGE;
1629
1630	netdev->xdp_features = NETDEV_XDP_ACT_BASIC    |
1631			       NETDEV_XDP_ACT_REDIRECT |
1632			       NETDEV_XDP_ACT_RX_SG    |
1633			       NETDEV_XDP_ACT_NDO_XMIT |
1634			       NETDEV_XDP_ACT_NDO_XMIT_SG;
1635
1636	return 0;
1637}
1638
1639static int ionic_set_features(struct net_device *netdev,
1640			      netdev_features_t features)
1641{
1642	struct ionic_lif *lif = netdev_priv(netdev);
1643	int err;
1644
1645	netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
1646		   __func__, (u64)lif->netdev->features, (u64)features);
1647
1648	err = ionic_set_nic_features(lif, features);
1649
1650	return err;
1651}
1652
1653static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac)
1654{
1655	struct ionic_admin_ctx ctx = {
1656		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1657		.cmd.lif_setattr = {
1658			.opcode = IONIC_CMD_LIF_SETATTR,
1659			.index = cpu_to_le16(lif->index),
1660			.attr = IONIC_LIF_ATTR_MAC,
1661		},
1662	};
1663
1664	ether_addr_copy(ctx.cmd.lif_setattr.mac, mac);
1665	return ionic_adminq_post_wait(lif, &ctx);
1666}
1667
1668static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr)
1669{
1670	struct ionic_admin_ctx ctx = {
1671		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1672		.cmd.lif_getattr = {
1673			.opcode = IONIC_CMD_LIF_GETATTR,
1674			.index = cpu_to_le16(lif->index),
1675			.attr = IONIC_LIF_ATTR_MAC,
1676		},
1677	};
1678	int err;
1679
1680	err = ionic_adminq_post_wait(lif, &ctx);
1681	if (err)
1682		return err;
1683
1684	ether_addr_copy(mac_addr, ctx.comp.lif_getattr.mac);
1685	return 0;
1686}
1687
1688static int ionic_program_mac(struct ionic_lif *lif, u8 *mac)
1689{
1690	u8  get_mac[ETH_ALEN];
1691	int err;
1692
1693	err = ionic_set_attr_mac(lif, mac);
1694	if (err)
1695		return err;
1696
1697	err = ionic_get_attr_mac(lif, get_mac);
1698	if (err)
1699		return err;
1700
1701	/* To deal with older firmware that silently ignores the set attr mac:
1702	 * doesn't actually change the mac and doesn't return an error, so we
1703	 * do the get attr to verify whether or not the set actually happened
1704	 */
1705	if (!ether_addr_equal(get_mac, mac))
1706		return 1;
1707
1708	return 0;
1709}
1710
1711static int ionic_set_mac_address(struct net_device *netdev, void *sa)
1712{
1713	struct ionic_lif *lif = netdev_priv(netdev);
1714	struct sockaddr *addr = sa;
1715	u8 *mac;
1716	int err;
1717
1718	mac = (u8 *)addr->sa_data;
1719	if (ether_addr_equal(netdev->dev_addr, mac))
1720		return 0;
1721
1722	/* Only program macs for virtual functions to avoid losing the permanent
1723	 * Mac across warm reset/reboot.
1724	 */
1725	if (lif->ionic->pdev->is_virtfn) {
1726		err = ionic_program_mac(lif, mac);
1727		if (err < 0)
1728			return err;
1729
1730		if (err > 0)
1731			netdev_dbg(netdev, "%s: SET and GET ATTR Mac are not equal-due to old FW running\n",
1732				   __func__);
1733	}
1734
1735	err = eth_prepare_mac_addr_change(netdev, addr);
1736	if (err)
1737		return err;
1738
1739	if (!is_zero_ether_addr(netdev->dev_addr)) {
1740		netdev_info(netdev, "deleting mac addr %pM\n",
1741			    netdev->dev_addr);
1742		ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr);
1743	}
1744
1745	eth_commit_mac_addr_change(netdev, addr);
1746	netdev_info(netdev, "updating mac addr %pM\n", mac);
1747
1748	return ionic_lif_addr_add(netdev_priv(netdev), mac);
1749}
1750
1751void ionic_stop_queues_reconfig(struct ionic_lif *lif)
1752{
1753	/* Stop and clean the queues before reconfiguration */
1754	netif_device_detach(lif->netdev);
1755	ionic_stop_queues(lif);
1756	ionic_txrx_deinit(lif);
1757}
1758
1759static int ionic_start_queues_reconfig(struct ionic_lif *lif)
1760{
1761	int err;
1762
1763	/* Re-init the queues after reconfiguration */
1764
1765	/* The only way txrx_init can fail here is if communication
1766	 * with FW is suddenly broken.  There's not much we can do
1767	 * at this point - error messages have already been printed,
1768	 * so we can continue on and the user can eventually do a
1769	 * DOWN and UP to try to reset and clear the issue.
1770	 */
1771	err = ionic_txrx_init(lif);
1772	ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
1773	netif_device_attach(lif->netdev);
1774
1775	return err;
1776}
1777
1778static bool ionic_xdp_is_valid_mtu(struct ionic_lif *lif, u32 mtu,
1779				   struct bpf_prog *xdp_prog)
1780{
1781	if (!xdp_prog)
1782		return true;
1783
1784	if (mtu <= IONIC_XDP_MAX_LINEAR_MTU)
1785		return true;
1786
1787	if (xdp_prog->aux && xdp_prog->aux->xdp_has_frags)
1788		return true;
1789
1790	return false;
1791}
1792
1793static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
1794{
1795	struct ionic_lif *lif = netdev_priv(netdev);
1796	struct ionic_admin_ctx ctx = {
1797		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1798		.cmd.lif_setattr = {
1799			.opcode = IONIC_CMD_LIF_SETATTR,
1800			.index = cpu_to_le16(lif->index),
1801			.attr = IONIC_LIF_ATTR_MTU,
1802			.mtu = cpu_to_le32(new_mtu),
1803		},
1804	};
1805	struct bpf_prog *xdp_prog;
1806	int err;
1807
1808	xdp_prog = READ_ONCE(lif->xdp_prog);
1809	if (!ionic_xdp_is_valid_mtu(lif, new_mtu, xdp_prog))
1810		return -EINVAL;
1811
1812	err = ionic_adminq_post_wait(lif, &ctx);
1813	if (err)
1814		return err;
1815
1816	/* if we're not running, nothing more to do */
1817	if (!netif_running(netdev)) {
1818		WRITE_ONCE(netdev->mtu, new_mtu);
1819		return 0;
1820	}
1821
1822	mutex_lock(&lif->queue_lock);
1823	ionic_stop_queues_reconfig(lif);
1824	WRITE_ONCE(netdev->mtu, new_mtu);
1825	err = ionic_start_queues_reconfig(lif);
1826	mutex_unlock(&lif->queue_lock);
1827
1828	return err;
1829}
1830
1831static void ionic_tx_timeout_work(struct work_struct *ws)
1832{
1833	struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);
1834	int err;
1835
1836	if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
1837		return;
1838
1839	/* if we were stopped before this scheduled job was launched,
1840	 * don't bother the queues as they are already stopped.
1841	 */
1842	if (!netif_running(lif->netdev))
1843		return;
1844
1845	mutex_lock(&lif->queue_lock);
1846	ionic_stop_queues_reconfig(lif);
1847	err = ionic_start_queues_reconfig(lif);
1848	mutex_unlock(&lif->queue_lock);
1849
1850	if (err)
1851		dev_err(lif->ionic->dev, "%s: Restarting queues failed\n", __func__);
1852}
1853
1854static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1855{
1856	struct ionic_lif *lif = netdev_priv(netdev);
1857
1858	netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue);
1859	schedule_work(&lif->tx_timeout_work);
1860}
1861
1862static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1863				 u16 vid)
1864{
1865	struct ionic_lif *lif = netdev_priv(netdev);
1866	int err;
1867
1868	err = ionic_lif_vlan_add(lif, vid);
1869	if (err)
1870		return err;
1871
1872	ionic_lif_rx_mode(lif);
1873
1874	return 0;
1875}
1876
1877static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1878				  u16 vid)
1879{
1880	struct ionic_lif *lif = netdev_priv(netdev);
1881	int err;
1882
1883	err = ionic_lif_vlan_del(lif, vid);
1884	if (err)
1885		return err;
1886
1887	ionic_lif_rx_mode(lif);
1888
1889	return 0;
1890}
1891
1892int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
1893			 const u8 *key, const u32 *indir)
1894{
1895	struct ionic_admin_ctx ctx = {
1896		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1897		.cmd.lif_setattr = {
1898			.opcode = IONIC_CMD_LIF_SETATTR,
1899			.attr = IONIC_LIF_ATTR_RSS,
1900			.rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
1901		},
1902	};
1903	unsigned int i, tbl_sz;
1904
1905	if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
1906		lif->rss_types = types;
1907		ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types);
1908	}
1909
1910	if (key)
1911		memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1912
1913	if (indir) {
1914		tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1915		for (i = 0; i < tbl_sz; i++)
1916			lif->rss_ind_tbl[i] = indir[i];
1917	}
1918
1919	memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1920	       IONIC_RSS_HASH_KEY_SIZE);
1921
1922	return ionic_adminq_post_wait(lif, &ctx);
1923}
1924
1925static int ionic_lif_rss_init(struct ionic_lif *lif)
1926{
1927	unsigned int tbl_sz;
1928	unsigned int i;
1929
1930	lif->rss_types = IONIC_RSS_TYPE_IPV4     |
1931			 IONIC_RSS_TYPE_IPV4_TCP |
1932			 IONIC_RSS_TYPE_IPV4_UDP |
1933			 IONIC_RSS_TYPE_IPV6     |
1934			 IONIC_RSS_TYPE_IPV6_TCP |
1935			 IONIC_RSS_TYPE_IPV6_UDP;
1936
1937	/* Fill indirection table with 'default' values */
1938	tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1939	for (i = 0; i < tbl_sz; i++)
1940		lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
1941
1942	return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1943}
1944
1945static void ionic_lif_rss_deinit(struct ionic_lif *lif)
1946{
1947	int tbl_sz;
1948
1949	tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1950	memset(lif->rss_ind_tbl, 0, tbl_sz);
1951	memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);
1952
1953	ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1954}
1955
1956static void ionic_lif_quiesce(struct ionic_lif *lif)
1957{
1958	struct ionic_admin_ctx ctx = {
1959		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1960		.cmd.lif_setattr = {
1961			.opcode = IONIC_CMD_LIF_SETATTR,
1962			.index = cpu_to_le16(lif->index),
1963			.attr = IONIC_LIF_ATTR_STATE,
1964			.state = IONIC_LIF_QUIESCE,
1965		},
1966	};
1967	int err;
1968
1969	err = ionic_adminq_post_wait(lif, &ctx);
1970	if (err)
1971		netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err);
1972}
1973
1974static void ionic_txrx_disable(struct ionic_lif *lif)
1975{
1976	unsigned int i;
1977	int err = 0;
1978
1979	if (lif->txqcqs) {
1980		for (i = 0; i < lif->nxqs; i++)
1981			err = ionic_qcq_disable(lif, lif->txqcqs[i], err);
1982	}
1983
1984	if (lif->hwstamp_txq)
1985		err = ionic_qcq_disable(lif, lif->hwstamp_txq, err);
1986
1987	if (lif->rxqcqs) {
1988		for (i = 0; i < lif->nxqs; i++)
1989			err = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
1990	}
1991
1992	if (lif->hwstamp_rxq)
1993		err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err);
1994
1995	ionic_lif_quiesce(lif);
1996}
1997
1998static void ionic_txrx_deinit(struct ionic_lif *lif)
1999{
2000	unsigned int i;
2001
2002	if (lif->txqcqs) {
2003		for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) {
2004			ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2005			ionic_tx_flush(&lif->txqcqs[i]->cq);
2006			ionic_tx_empty(&lif->txqcqs[i]->q);
2007		}
2008	}
2009
2010	if (lif->rxqcqs) {
2011		for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) {
2012			ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
2013			ionic_rx_empty(&lif->rxqcqs[i]->q);
2014		}
2015	}
2016	lif->rx_mode = 0;
2017
2018	if (lif->hwstamp_txq) {
2019		ionic_lif_qcq_deinit(lif, lif->hwstamp_txq);
2020		ionic_tx_flush(&lif->hwstamp_txq->cq);
2021		ionic_tx_empty(&lif->hwstamp_txq->q);
2022	}
2023
2024	if (lif->hwstamp_rxq) {
2025		ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq);
2026		ionic_rx_empty(&lif->hwstamp_rxq->q);
2027	}
2028}
2029
2030void ionic_txrx_free(struct ionic_lif *lif)
2031{
2032	unsigned int i;
2033
2034	if (lif->txqcqs) {
2035		for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) {
2036			ionic_qcq_free(lif, lif->txqcqs[i]);
2037			devm_kfree(lif->ionic->dev, lif->txqcqs[i]);
2038			lif->txqcqs[i] = NULL;
2039		}
2040	}
2041
2042	if (lif->rxqcqs) {
2043		for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
2044			ionic_qcq_free(lif, lif->rxqcqs[i]);
2045			devm_kfree(lif->ionic->dev, lif->rxqcqs[i]);
2046			lif->rxqcqs[i] = NULL;
2047		}
2048	}
2049
2050	if (lif->hwstamp_txq) {
2051		ionic_qcq_free(lif, lif->hwstamp_txq);
2052		devm_kfree(lif->ionic->dev, lif->hwstamp_txq);
2053		lif->hwstamp_txq = NULL;
2054	}
2055
2056	if (lif->hwstamp_rxq) {
2057		ionic_qcq_free(lif, lif->hwstamp_rxq);
2058		devm_kfree(lif->ionic->dev, lif->hwstamp_rxq);
2059		lif->hwstamp_rxq = NULL;
2060	}
2061}
2062
2063static int ionic_txrx_alloc(struct ionic_lif *lif)
2064{
2065	unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
2066	unsigned int flags, i;
2067	int err = 0;
2068
2069	num_desc = lif->ntxq_descs;
2070	desc_sz = sizeof(struct ionic_txq_desc);
2071	comp_sz = sizeof(struct ionic_txq_comp);
2072
2073	if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2074	    lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2075					  sizeof(struct ionic_txq_sg_desc_v1))
2076		sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
2077	else
2078		sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
2079
2080	flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
2081
2082	if (test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state))
2083		flags |= IONIC_QCQ_F_CMB_RINGS;
2084
2085	if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
2086		flags |= IONIC_QCQ_F_INTR;
2087
2088	for (i = 0; i < lif->nxqs; i++) {
2089		err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2090				      num_desc, desc_sz, comp_sz, sg_desc_sz,
2091				      sizeof(struct ionic_tx_desc_info),
2092				      lif->kern_pid, NULL, &lif->txqcqs[i]);
2093		if (err)
2094			goto err_out;
2095
2096		if (flags & IONIC_QCQ_F_INTR) {
2097			ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2098					     lif->txqcqs[i]->intr.index,
2099					     lif->tx_coalesce_hw);
2100			if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
2101				lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
2102		}
2103
2104		ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
2105	}
2106
2107	flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR;
2108
2109	if (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state))
2110		flags |= IONIC_QCQ_F_CMB_RINGS;
2111
2112	num_desc = lif->nrxq_descs;
2113	desc_sz = sizeof(struct ionic_rxq_desc);
2114	comp_sz = sizeof(struct ionic_rxq_comp);
2115	sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
2116
2117	if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC)
2118		comp_sz *= 2;
2119
2120	for (i = 0; i < lif->nxqs; i++) {
2121		err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
2122				      num_desc, desc_sz, comp_sz, sg_desc_sz,
2123				      sizeof(struct ionic_rx_desc_info),
2124				      lif->kern_pid, lif->xdp_prog,
2125				      &lif->rxqcqs[i]);
2126		if (err)
2127			goto err_out;
2128
2129		lif->rxqcqs[i]->q.features = lif->rxq_features;
2130
2131		ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2132				     lif->rxqcqs[i]->intr.index,
2133				     lif->rx_coalesce_hw);
2134		if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state))
2135			lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw;
2136
2137		if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
2138			ionic_link_qcq_interrupts(lif->rxqcqs[i],
2139						  lif->txqcqs[i]);
2140
2141		ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
2142	}
2143
2144	return 0;
2145
2146err_out:
2147	ionic_txrx_free(lif);
2148
2149	return err;
2150}
2151
2152static int ionic_txrx_init(struct ionic_lif *lif)
2153{
2154	unsigned int i;
2155	int err;
2156
2157	for (i = 0; i < lif->nxqs; i++) {
2158		err = ionic_lif_txq_init(lif, lif->txqcqs[i]);
2159		if (err)
2160			goto err_out;
2161
2162		err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]);
2163		if (err) {
2164			ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2165			goto err_out;
2166		}
2167	}
2168
2169	if (lif->netdev->features & NETIF_F_RXHASH)
2170		ionic_lif_rss_init(lif);
2171
2172	ionic_lif_rx_mode(lif);
2173
2174	return 0;
2175
2176err_out:
2177	while (i--) {
2178		ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2179		ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
2180	}
2181
2182	return err;
2183}
2184
2185static int ionic_txrx_enable(struct ionic_lif *lif)
2186{
2187	int derr = 0;
2188	int i, err;
2189
2190	ionic_xdp_rxqs_prog_update(lif);
2191
2192	for (i = 0; i < lif->nxqs; i++) {
2193		if (!(lif->rxqcqs[i] && lif->txqcqs[i])) {
2194			dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i);
2195			err = -ENXIO;
2196			goto err_out;
2197		}
2198
2199		ionic_rx_fill(&lif->rxqcqs[i]->q,
2200			      READ_ONCE(lif->rxqcqs[i]->q.xdp_prog));
2201		err = ionic_qcq_enable(lif->rxqcqs[i]);
2202		if (err)
2203			goto err_out;
2204
2205		err = ionic_qcq_enable(lif->txqcqs[i]);
2206		if (err) {
2207			derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
2208			goto err_out;
2209		}
2210	}
2211
2212	if (lif->hwstamp_rxq) {
2213		ionic_rx_fill(&lif->hwstamp_rxq->q, NULL);
2214		err = ionic_qcq_enable(lif->hwstamp_rxq);
2215		if (err)
2216			goto err_out_hwstamp_rx;
2217	}
2218
2219	if (lif->hwstamp_txq) {
2220		err = ionic_qcq_enable(lif->hwstamp_txq);
2221		if (err)
2222			goto err_out_hwstamp_tx;
2223	}
2224
2225	return 0;
2226
2227err_out_hwstamp_tx:
2228	if (lif->hwstamp_rxq)
2229		derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr);
2230err_out_hwstamp_rx:
2231	i = lif->nxqs;
2232err_out:
2233	while (i--) {
2234		derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr);
2235		derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr);
2236	}
2237
2238	ionic_xdp_rxqs_prog_update(lif);
2239
2240	return err;
2241}
2242
2243static int ionic_start_queues(struct ionic_lif *lif)
2244{
2245	int err;
2246
2247	if (test_bit(IONIC_LIF_F_BROKEN, lif->state))
2248		return -EIO;
2249
2250	if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2251		return -EBUSY;
2252
2253	if (test_and_set_bit(IONIC_LIF_F_UP, lif->state))
2254		return 0;
2255
2256	err = ionic_txrx_enable(lif);
2257	if (err) {
2258		clear_bit(IONIC_LIF_F_UP, lif->state);
2259		return err;
2260	}
2261	netif_tx_wake_all_queues(lif->netdev);
2262
2263	return 0;
2264}
2265
2266static int ionic_open(struct net_device *netdev)
2267{
2268	struct ionic_lif *lif = netdev_priv(netdev);
2269	int err;
2270
2271	/* If recovering from a broken state, clear the bit and we'll try again */
2272	if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
2273		netdev_info(netdev, "clearing broken state\n");
2274
2275	mutex_lock(&lif->queue_lock);
2276
2277	err = ionic_txrx_alloc(lif);
2278	if (err)
2279		goto err_unlock;
2280
2281	err = ionic_txrx_init(lif);
2282	if (err)
2283		goto err_txrx_free;
2284
2285	err = netif_set_real_num_tx_queues(netdev, lif->nxqs);
2286	if (err)
2287		goto err_txrx_deinit;
2288
2289	err = netif_set_real_num_rx_queues(netdev, lif->nxqs);
2290	if (err)
2291		goto err_txrx_deinit;
2292
2293	/* don't start the queues until we have link */
2294	if (netif_carrier_ok(netdev)) {
2295		err = ionic_start_queues(lif);
2296		if (err)
2297			goto err_txrx_deinit;
2298	}
2299
2300	/* If hardware timestamping is enabled, but the queues were freed by
2301	 * ionic_stop, those need to be reallocated and initialized, too.
2302	 */
2303	ionic_lif_hwstamp_recreate_queues(lif);
2304
2305	mutex_unlock(&lif->queue_lock);
2306
2307	return 0;
2308
2309err_txrx_deinit:
2310	ionic_txrx_deinit(lif);
2311err_txrx_free:
2312	ionic_txrx_free(lif);
2313err_unlock:
2314	mutex_unlock(&lif->queue_lock);
2315	return err;
2316}
2317
2318static void ionic_stop_queues(struct ionic_lif *lif)
2319{
2320	if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state))
2321		return;
2322
2323	netif_tx_disable(lif->netdev);
2324	ionic_txrx_disable(lif);
2325}
2326
2327static int ionic_stop(struct net_device *netdev)
2328{
2329	struct ionic_lif *lif = netdev_priv(netdev);
2330
2331	if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2332		return 0;
2333
2334	mutex_lock(&lif->queue_lock);
2335	ionic_stop_queues(lif);
2336	ionic_txrx_deinit(lif);
2337	ionic_txrx_free(lif);
2338	mutex_unlock(&lif->queue_lock);
2339
2340	return 0;
2341}
2342
2343static int ionic_get_vf_config(struct net_device *netdev,
2344			       int vf, struct ifla_vf_info *ivf)
2345{
2346	struct ionic_lif *lif = netdev_priv(netdev);
2347	struct ionic *ionic = lif->ionic;
2348	int ret = 0;
2349
2350	if (!netif_device_present(netdev))
2351		return -EBUSY;
2352
2353	down_read(&ionic->vf_op_lock);
2354
2355	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2356		ret = -EINVAL;
2357	} else {
2358		struct ionic_vf *vfdata = &ionic->vfs[vf];
2359
2360		ivf->vf		  = vf;
2361		ivf->qos	  = 0;
2362		ivf->vlan         = le16_to_cpu(vfdata->vlanid);
2363		ivf->spoofchk     = vfdata->spoofchk;
2364		ivf->linkstate    = vfdata->linkstate;
2365		ivf->max_tx_rate  = le32_to_cpu(vfdata->maxrate);
2366		ivf->trusted      = vfdata->trusted;
2367		ether_addr_copy(ivf->mac, vfdata->macaddr);
2368	}
2369
2370	up_read(&ionic->vf_op_lock);
2371	return ret;
2372}
2373
2374static int ionic_get_vf_stats(struct net_device *netdev, int vf,
2375			      struct ifla_vf_stats *vf_stats)
2376{
2377	struct ionic_lif *lif = netdev_priv(netdev);
2378	struct ionic *ionic = lif->ionic;
2379	struct ionic_lif_stats *vs;
2380	int ret = 0;
2381
2382	if (!netif_device_present(netdev))
2383		return -EBUSY;
2384
2385	down_read(&ionic->vf_op_lock);
2386
2387	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2388		ret = -EINVAL;
2389	} else {
2390		memset(vf_stats, 0, sizeof(*vf_stats));
2391		vs = &ionic->vfs[vf].stats;
2392
2393		vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets);
2394		vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets);
2395		vf_stats->rx_bytes   = le64_to_cpu(vs->rx_ucast_bytes);
2396		vf_stats->tx_bytes   = le64_to_cpu(vs->tx_ucast_bytes);
2397		vf_stats->broadcast  = le64_to_cpu(vs->rx_bcast_packets);
2398		vf_stats->multicast  = le64_to_cpu(vs->rx_mcast_packets);
2399		vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) +
2400				       le64_to_cpu(vs->rx_mcast_drop_packets) +
2401				       le64_to_cpu(vs->rx_bcast_drop_packets);
2402		vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) +
2403				       le64_to_cpu(vs->tx_mcast_drop_packets) +
2404				       le64_to_cpu(vs->tx_bcast_drop_packets);
2405	}
2406
2407	up_read(&ionic->vf_op_lock);
2408	return ret;
2409}
2410
2411static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2412{
2413	struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_MAC };
2414	struct ionic_lif *lif = netdev_priv(netdev);
2415	struct ionic *ionic = lif->ionic;
2416	int ret;
2417
2418	if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac)))
2419		return -EINVAL;
2420
2421	if (!netif_device_present(netdev))
2422		return -EBUSY;
2423
2424	down_write(&ionic->vf_op_lock);
2425
2426	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2427		ret = -EINVAL;
2428	} else {
2429		ether_addr_copy(vfc.macaddr, mac);
2430		dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n",
2431			__func__, vf, vfc.macaddr);
2432
2433		ret = ionic_set_vf_config(ionic, vf, &vfc);
2434		if (!ret)
2435			ether_addr_copy(ionic->vfs[vf].macaddr, mac);
2436	}
2437
2438	up_write(&ionic->vf_op_lock);
2439	return ret;
2440}
2441
2442static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2443			     u8 qos, __be16 proto)
2444{
2445	struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_VLAN };
2446	struct ionic_lif *lif = netdev_priv(netdev);
2447	struct ionic *ionic = lif->ionic;
2448	int ret;
2449
2450	/* until someday when we support qos */
2451	if (qos)
2452		return -EINVAL;
2453
2454	if (vlan > 4095)
2455		return -EINVAL;
2456
2457	if (proto != htons(ETH_P_8021Q))
2458		return -EPROTONOSUPPORT;
2459
2460	if (!netif_device_present(netdev))
2461		return -EBUSY;
2462
2463	down_write(&ionic->vf_op_lock);
2464
2465	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2466		ret = -EINVAL;
2467	} else {
2468		vfc.vlanid = cpu_to_le16(vlan);
2469		dev_dbg(ionic->dev, "%s: vf %d vlan %d\n",
2470			__func__, vf, le16_to_cpu(vfc.vlanid));
2471
2472		ret = ionic_set_vf_config(ionic, vf, &vfc);
2473		if (!ret)
2474			ionic->vfs[vf].vlanid = cpu_to_le16(vlan);
2475	}
2476
2477	up_write(&ionic->vf_op_lock);
2478	return ret;
2479}
2480
2481static int ionic_set_vf_rate(struct net_device *netdev, int vf,
2482			     int tx_min, int tx_max)
2483{
2484	struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_RATE };
2485	struct ionic_lif *lif = netdev_priv(netdev);
2486	struct ionic *ionic = lif->ionic;
2487	int ret;
2488
2489	/* setting the min just seems silly */
2490	if (tx_min)
2491		return -EINVAL;
2492
2493	if (!netif_device_present(netdev))
2494		return -EBUSY;
2495
2496	down_write(&ionic->vf_op_lock);
2497
2498	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2499		ret = -EINVAL;
2500	} else {
2501		vfc.maxrate = cpu_to_le32(tx_max);
2502		dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n",
2503			__func__, vf, le32_to_cpu(vfc.maxrate));
2504
2505		ret = ionic_set_vf_config(ionic, vf, &vfc);
2506		if (!ret)
2507			ionic->vfs[vf].maxrate = cpu_to_le32(tx_max);
2508	}
2509
2510	up_write(&ionic->vf_op_lock);
2511	return ret;
2512}
2513
2514static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set)
2515{
2516	struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_SPOOFCHK };
2517	struct ionic_lif *lif = netdev_priv(netdev);
2518	struct ionic *ionic = lif->ionic;
2519	int ret;
2520
2521	if (!netif_device_present(netdev))
2522		return -EBUSY;
2523
2524	down_write(&ionic->vf_op_lock);
2525
2526	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2527		ret = -EINVAL;
2528	} else {
2529		vfc.spoofchk = set;
2530		dev_dbg(ionic->dev, "%s: vf %d spoof %d\n",
2531			__func__, vf, vfc.spoofchk);
2532
2533		ret = ionic_set_vf_config(ionic, vf, &vfc);
2534		if (!ret)
2535			ionic->vfs[vf].spoofchk = set;
2536	}
2537
2538	up_write(&ionic->vf_op_lock);
2539	return ret;
2540}
2541
2542static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set)
2543{
2544	struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_TRUST };
2545	struct ionic_lif *lif = netdev_priv(netdev);
2546	struct ionic *ionic = lif->ionic;
2547	int ret;
2548
2549	if (!netif_device_present(netdev))
2550		return -EBUSY;
2551
2552	down_write(&ionic->vf_op_lock);
2553
2554	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2555		ret = -EINVAL;
2556	} else {
2557		vfc.trust = set;
2558		dev_dbg(ionic->dev, "%s: vf %d trust %d\n",
2559			__func__, vf, vfc.trust);
2560
2561		ret = ionic_set_vf_config(ionic, vf, &vfc);
2562		if (!ret)
2563			ionic->vfs[vf].trusted = set;
2564	}
2565
2566	up_write(&ionic->vf_op_lock);
2567	return ret;
2568}
2569
2570static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set)
2571{
2572	struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_LINKSTATE };
2573	struct ionic_lif *lif = netdev_priv(netdev);
2574	struct ionic *ionic = lif->ionic;
2575	u8 vfls;
2576	int ret;
2577
2578	switch (set) {
2579	case IFLA_VF_LINK_STATE_ENABLE:
2580		vfls = IONIC_VF_LINK_STATUS_UP;
2581		break;
2582	case IFLA_VF_LINK_STATE_DISABLE:
2583		vfls = IONIC_VF_LINK_STATUS_DOWN;
2584		break;
2585	case IFLA_VF_LINK_STATE_AUTO:
2586		vfls = IONIC_VF_LINK_STATUS_AUTO;
2587		break;
2588	default:
2589		return -EINVAL;
2590	}
2591
2592	if (!netif_device_present(netdev))
2593		return -EBUSY;
2594
2595	down_write(&ionic->vf_op_lock);
2596
2597	if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2598		ret = -EINVAL;
2599	} else {
2600		vfc.linkstate = vfls;
2601		dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n",
2602			__func__, vf, vfc.linkstate);
2603
2604		ret = ionic_set_vf_config(ionic, vf, &vfc);
2605		if (!ret)
2606			ionic->vfs[vf].linkstate = set;
2607	}
2608
2609	up_write(&ionic->vf_op_lock);
2610	return ret;
2611}
2612
2613static void ionic_vf_attr_replay(struct ionic_lif *lif)
2614{
2615	struct ionic_vf_setattr_cmd vfc = { };
2616	struct ionic *ionic = lif->ionic;
2617	struct ionic_vf *v;
2618	int i;
2619
2620	if (!ionic->vfs)
2621		return;
2622
2623	down_read(&ionic->vf_op_lock);
2624
2625	for (i = 0; i < ionic->num_vfs; i++) {
2626		v = &ionic->vfs[i];
2627
2628		if (v->stats_pa) {
2629			vfc.attr = IONIC_VF_ATTR_STATSADDR;
2630			vfc.stats_pa = cpu_to_le64(v->stats_pa);
2631			ionic_set_vf_config(ionic, i, &vfc);
2632			vfc.stats_pa = 0;
2633		}
2634
2635		if (!is_zero_ether_addr(v->macaddr)) {
2636			vfc.attr = IONIC_VF_ATTR_MAC;
2637			ether_addr_copy(vfc.macaddr, v->macaddr);
2638			ionic_set_vf_config(ionic, i, &vfc);
2639			eth_zero_addr(vfc.macaddr);
2640		}
2641
2642		if (v->vlanid) {
2643			vfc.attr = IONIC_VF_ATTR_VLAN;
2644			vfc.vlanid = v->vlanid;
2645			ionic_set_vf_config(ionic, i, &vfc);
2646			vfc.vlanid = 0;
2647		}
2648
2649		if (v->maxrate) {
2650			vfc.attr = IONIC_VF_ATTR_RATE;
2651			vfc.maxrate = v->maxrate;
2652			ionic_set_vf_config(ionic, i, &vfc);
2653			vfc.maxrate = 0;
2654		}
2655
2656		if (v->spoofchk) {
2657			vfc.attr = IONIC_VF_ATTR_SPOOFCHK;
2658			vfc.spoofchk = v->spoofchk;
2659			ionic_set_vf_config(ionic, i, &vfc);
2660			vfc.spoofchk = 0;
2661		}
2662
2663		if (v->trusted) {
2664			vfc.attr = IONIC_VF_ATTR_TRUST;
2665			vfc.trust = v->trusted;
2666			ionic_set_vf_config(ionic, i, &vfc);
2667			vfc.trust = 0;
2668		}
2669
2670		if (v->linkstate) {
2671			vfc.attr = IONIC_VF_ATTR_LINKSTATE;
2672			vfc.linkstate = v->linkstate;
2673			ionic_set_vf_config(ionic, i, &vfc);
2674			vfc.linkstate = 0;
2675		}
2676	}
2677
2678	up_read(&ionic->vf_op_lock);
2679
2680	ionic_vf_start(ionic);
2681}
2682
2683static void ionic_unregister_rxq_info(struct ionic_queue *q)
2684{
2685	struct xdp_rxq_info *xi;
2686
2687	if (!q->xdp_rxq_info)
2688		return;
2689
2690	xi = q->xdp_rxq_info;
2691	q->xdp_rxq_info = NULL;
2692
2693	xdp_rxq_info_unreg(xi);
2694	kfree(xi);
2695}
2696
2697static int ionic_register_rxq_info(struct ionic_queue *q, unsigned int napi_id)
2698{
2699	struct xdp_rxq_info *rxq_info;
2700	int err;
2701
2702	rxq_info = kzalloc(sizeof(*rxq_info), GFP_KERNEL);
2703	if (!rxq_info)
2704		return -ENOMEM;
2705
2706	err = xdp_rxq_info_reg(rxq_info, q->lif->netdev, q->index, napi_id);
2707	if (err) {
2708		netdev_err(q->lif->netdev, "q%d xdp_rxq_info_reg failed, err %d\n",
2709			   q->index, err);
2710		goto err_out;
2711	}
2712
2713	err = xdp_rxq_info_reg_mem_model(rxq_info, MEM_TYPE_PAGE_POOL, q->page_pool);
2714	if (err) {
2715		netdev_err(q->lif->netdev, "q%d xdp_rxq_info_reg_mem_model failed, err %d\n",
2716			   q->index, err);
2717		xdp_rxq_info_unreg(rxq_info);
2718		goto err_out;
2719	}
2720
2721	q->xdp_rxq_info = rxq_info;
2722
2723	return 0;
2724
2725err_out:
2726	kfree(rxq_info);
2727	return err;
2728}
2729
2730static void ionic_xdp_rxqs_prog_update(struct ionic_lif *lif)
2731{
2732	struct bpf_prog *xdp_prog;
2733	unsigned int i;
2734
2735	if (!lif->rxqcqs)
2736		return;
2737
2738	xdp_prog = READ_ONCE(lif->xdp_prog);
2739	for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
2740		struct ionic_queue *q = &lif->rxqcqs[i]->q;
2741
2742		WRITE_ONCE(q->xdp_prog, xdp_prog);
2743	}
2744}
2745
2746static int ionic_xdp_config(struct net_device *netdev, struct netdev_bpf *bpf)
2747{
2748	struct ionic_lif *lif = netdev_priv(netdev);
2749	struct bpf_prog *old_prog;
2750	u32 maxfs;
2751
2752	if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) {
2753#define XDP_ERR_SPLIT "XDP not available with split Tx/Rx interrupts"
2754		NL_SET_ERR_MSG_MOD(bpf->extack, XDP_ERR_SPLIT);
2755		netdev_info(lif->netdev, XDP_ERR_SPLIT);
2756		return -EOPNOTSUPP;
2757	}
2758
2759	if (!ionic_xdp_is_valid_mtu(lif, netdev->mtu, bpf->prog)) {
2760#define XDP_ERR_MTU "MTU is too large for XDP without frags support"
2761		NL_SET_ERR_MSG_MOD(bpf->extack, XDP_ERR_MTU);
2762		netdev_info(lif->netdev, XDP_ERR_MTU);
2763		return -EINVAL;
2764	}
2765
2766	maxfs = __le32_to_cpu(lif->identity->eth.max_frame_size) - VLAN_ETH_HLEN;
2767	if (bpf->prog && !(bpf->prog->aux && bpf->prog->aux->xdp_has_frags))
2768		maxfs = min_t(u32, maxfs, IONIC_XDP_MAX_LINEAR_MTU);
2769	netdev->max_mtu = maxfs;
2770
2771	if (!netif_running(netdev)) {
2772		old_prog = xchg(&lif->xdp_prog, bpf->prog);
2773	} else if (lif->xdp_prog && bpf->prog) {
2774		old_prog = xchg(&lif->xdp_prog, bpf->prog);
2775		ionic_xdp_rxqs_prog_update(lif);
2776	} else {
2777		struct ionic_queue_params qparams;
2778
2779		ionic_init_queue_params(lif, &qparams);
2780		qparams.xdp_prog = bpf->prog;
2781		mutex_lock(&lif->queue_lock);
2782		ionic_reconfigure_queues(lif, &qparams);
2783		old_prog = xchg(&lif->xdp_prog, bpf->prog);
2784		mutex_unlock(&lif->queue_lock);
2785	}
2786
2787	if (old_prog)
2788		bpf_prog_put(old_prog);
2789
2790	return 0;
2791}
2792
2793static int ionic_xdp(struct net_device *netdev, struct netdev_bpf *bpf)
2794{
2795	switch (bpf->command) {
2796	case XDP_SETUP_PROG:
2797		return ionic_xdp_config(netdev, bpf);
2798	default:
2799		return -EINVAL;
2800	}
2801}
2802
2803static const struct net_device_ops ionic_netdev_ops = {
2804	.ndo_open               = ionic_open,
2805	.ndo_stop               = ionic_stop,
2806	.ndo_start_xmit		= ionic_start_xmit,
2807	.ndo_bpf		= ionic_xdp,
2808	.ndo_xdp_xmit		= ionic_xdp_xmit,
2809	.ndo_get_stats64	= ionic_get_stats64,
2810	.ndo_set_rx_mode	= ionic_ndo_set_rx_mode,
2811	.ndo_set_features	= ionic_set_features,
2812	.ndo_set_mac_address	= ionic_set_mac_address,
2813	.ndo_validate_addr	= eth_validate_addr,
2814	.ndo_tx_timeout         = ionic_tx_timeout,
2815	.ndo_change_mtu         = ionic_change_mtu,
2816	.ndo_vlan_rx_add_vid    = ionic_vlan_rx_add_vid,
2817	.ndo_vlan_rx_kill_vid   = ionic_vlan_rx_kill_vid,
2818	.ndo_set_vf_vlan	= ionic_set_vf_vlan,
2819	.ndo_set_vf_trust	= ionic_set_vf_trust,
2820	.ndo_set_vf_mac		= ionic_set_vf_mac,
2821	.ndo_set_vf_rate	= ionic_set_vf_rate,
2822	.ndo_set_vf_spoofchk	= ionic_set_vf_spoofchk,
2823	.ndo_get_vf_config	= ionic_get_vf_config,
2824	.ndo_set_vf_link_state	= ionic_set_vf_link_state,
2825	.ndo_get_vf_stats       = ionic_get_vf_stats,
2826	.ndo_hwtstamp_get	= ionic_hwstamp_get,
2827	.ndo_hwtstamp_set	= ionic_hwstamp_set,
2828};
2829
2830static int ionic_cmb_reconfig(struct ionic_lif *lif,
2831			      struct ionic_queue_params *qparam)
2832{
2833	struct ionic_queue_params start_qparams;
2834	int err = 0;
2835
2836	/* When changing CMB queue parameters, we're using limited
2837	 * on-device memory and don't have extra memory to use for
2838	 * duplicate allocations, so we free it all first then
2839	 * re-allocate with the new parameters.
2840	 */
2841
2842	/* Checkpoint for possible unwind */
2843	ionic_init_queue_params(lif, &start_qparams);
2844
2845	/* Stop and free the queues */
2846	ionic_stop_queues_reconfig(lif);
2847	ionic_txrx_free(lif);
2848
2849	/* Set up new qparams */
2850	ionic_set_queue_params(lif, qparam);
2851
2852	if (netif_running(lif->netdev)) {
2853		/* Alloc and start the new configuration */
2854		err = ionic_txrx_alloc(lif);
2855		if (err) {
2856			dev_warn(lif->ionic->dev,
2857				 "CMB reconfig failed, restoring values: %d\n", err);
2858
2859			/* Back out the changes */
2860			ionic_set_queue_params(lif, &start_qparams);
2861			err = ionic_txrx_alloc(lif);
2862			if (err) {
2863				dev_err(lif->ionic->dev,
2864					"CMB restore failed: %d\n", err);
2865				goto err_out;
2866			}
2867		}
2868
2869		err = ionic_start_queues_reconfig(lif);
2870		if (err) {
2871			dev_err(lif->ionic->dev,
2872				"CMB reconfig failed: %d\n", err);
2873			goto err_out;
2874		}
2875	}
2876
2877err_out:
2878	/* This was detached in ionic_stop_queues_reconfig() */
2879	netif_device_attach(lif->netdev);
2880
2881	return err;
2882}
2883
2884static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b)
2885{
2886	/* only swapping the queues and napi, not flags or other stuff */
2887	swap(a->napi,         b->napi);
2888
2889	if (a->q.type == IONIC_QTYPE_RXQ) {
2890		swap(a->q.page_pool, b->q.page_pool);
2891		a->q.page_pool->p.napi = &a->napi;
2892		if (b->q.page_pool)  /* is NULL when increasing queue count */
2893			b->q.page_pool->p.napi = &b->napi;
2894	}
2895
2896	swap(a->q.features,   b->q.features);
2897	swap(a->q.num_descs,  b->q.num_descs);
2898	swap(a->q.desc_size,  b->q.desc_size);
2899	swap(a->q.base,       b->q.base);
2900	swap(a->q.base_pa,    b->q.base_pa);
2901	swap(a->q.info,       b->q.info);
2902	swap(a->q.xdp_prog,   b->q.xdp_prog);
2903	swap(a->q.xdp_rxq_info, b->q.xdp_rxq_info);
2904	swap(a->q.partner,    b->q.partner);
2905	swap(a->q_base,       b->q_base);
2906	swap(a->q_base_pa,    b->q_base_pa);
2907	swap(a->q_size,       b->q_size);
2908
2909	swap(a->q.sg_desc_size, b->q.sg_desc_size);
2910	swap(a->q.sg_base,    b->q.sg_base);
2911	swap(a->q.sg_base_pa, b->q.sg_base_pa);
2912	swap(a->sg_base,      b->sg_base);
2913	swap(a->sg_base_pa,   b->sg_base_pa);
2914	swap(a->sg_size,      b->sg_size);
2915
2916	swap(a->cq.num_descs, b->cq.num_descs);
2917	swap(a->cq.desc_size, b->cq.desc_size);
2918	swap(a->cq.base,      b->cq.base);
2919	swap(a->cq.base_pa,   b->cq.base_pa);
2920	swap(a->cq_base,      b->cq_base);
2921	swap(a->cq_base_pa,   b->cq_base_pa);
2922	swap(a->cq_size,      b->cq_size);
2923
2924	ionic_debugfs_del_qcq(a);
2925	ionic_debugfs_add_qcq(a->q.lif, a);
2926}
2927
2928int ionic_reconfigure_queues(struct ionic_lif *lif,
2929			     struct ionic_queue_params *qparam)
2930{
2931	unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
2932	struct ionic_qcq **tx_qcqs = NULL;
2933	struct ionic_qcq **rx_qcqs = NULL;
2934	unsigned int flags, i;
2935	int err = 0;
2936
2937	/* Are we changing q params while CMB is on */
2938	if ((test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && qparam->cmb_tx) ||
2939	    (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state) && qparam->cmb_rx))
2940		return ionic_cmb_reconfig(lif, qparam);
2941
2942	/* allocate temporary qcq arrays to hold new queue structs */
2943	if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) {
2944		tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif,
2945				       sizeof(struct ionic_qcq *), GFP_KERNEL);
2946		if (!tx_qcqs) {
2947			err = -ENOMEM;
2948			goto err_out;
2949		}
2950	}
2951	if (qparam->nxqs != lif->nxqs ||
2952	    qparam->nrxq_descs != lif->nrxq_descs ||
2953	    qparam->rxq_features != lif->rxq_features ||
2954	    qparam->xdp_prog != lif->xdp_prog) {
2955		rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif,
2956				       sizeof(struct ionic_qcq *), GFP_KERNEL);
2957		if (!rx_qcqs) {
2958			err = -ENOMEM;
2959			goto err_out;
2960		}
2961	}
2962
2963	/* allocate new desc_info and rings, but leave the interrupt setup
2964	 * until later so as to not mess with the still-running queues
2965	 */
2966	if (tx_qcqs) {
2967		num_desc = qparam->ntxq_descs;
2968		desc_sz = sizeof(struct ionic_txq_desc);
2969		comp_sz = sizeof(struct ionic_txq_comp);
2970
2971		if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2972		    lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2973		    sizeof(struct ionic_txq_sg_desc_v1))
2974			sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
2975		else
2976			sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
2977
2978		for (i = 0; i < qparam->nxqs; i++) {
2979			/* If missing, short placeholder qcq needed for swap */
2980			if (!lif->txqcqs[i]) {
2981				flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
2982				err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2983						      4, desc_sz, comp_sz, sg_desc_sz,
2984						      sizeof(struct ionic_tx_desc_info),
2985						      lif->kern_pid, NULL, &lif->txqcqs[i]);
2986				if (err)
2987					goto err_out;
2988			}
2989
2990			flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2991			err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2992					      num_desc, desc_sz, comp_sz, sg_desc_sz,
2993					      sizeof(struct ionic_tx_desc_info),
2994					      lif->kern_pid, NULL, &tx_qcqs[i]);
2995			if (err)
2996				goto err_out;
2997		}
2998	}
2999
3000	if (rx_qcqs) {
3001		num_desc = qparam->nrxq_descs;
3002		desc_sz = sizeof(struct ionic_rxq_desc);
3003		comp_sz = sizeof(struct ionic_rxq_comp);
3004		sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
3005
3006		if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC)
3007			comp_sz *= 2;
3008
3009		for (i = 0; i < qparam->nxqs; i++) {
3010			/* If missing, short placeholder qcq needed for swap */
3011			if (!lif->rxqcqs[i]) {
3012				flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG;
3013				err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
3014						      4, desc_sz, comp_sz, sg_desc_sz,
3015						      sizeof(struct ionic_rx_desc_info),
3016						      lif->kern_pid, NULL, &lif->rxqcqs[i]);
3017				if (err)
3018					goto err_out;
3019			}
3020
3021			flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
3022			err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
3023					      num_desc, desc_sz, comp_sz, sg_desc_sz,
3024					      sizeof(struct ionic_rx_desc_info),
3025					      lif->kern_pid, qparam->xdp_prog, &rx_qcqs[i]);
3026			if (err)
3027				goto err_out;
3028
3029			rx_qcqs[i]->q.features = qparam->rxq_features;
3030			rx_qcqs[i]->q.xdp_prog = qparam->xdp_prog;
3031		}
3032	}
3033
3034	/* stop and clean the queues */
3035	ionic_stop_queues_reconfig(lif);
3036
3037	if (qparam->nxqs != lif->nxqs) {
3038		err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs);
3039		if (err)
3040			goto err_out_reinit_unlock;
3041		err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs);
3042		if (err) {
3043			netif_set_real_num_tx_queues(lif->netdev, lif->nxqs);
3044			goto err_out_reinit_unlock;
3045		}
3046	}
3047
3048	/* swap new desc_info and rings, keeping existing interrupt config */
3049	if (tx_qcqs) {
3050		lif->ntxq_descs = qparam->ntxq_descs;
3051		for (i = 0; i < qparam->nxqs; i++)
3052			ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]);
3053	}
3054
3055	if (rx_qcqs) {
3056		lif->nrxq_descs = qparam->nrxq_descs;
3057		for (i = 0; i < qparam->nxqs; i++)
3058			ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]);
3059	}
3060
3061	/* if we need to change the interrupt layout, this is the time */
3062	if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) ||
3063	    qparam->nxqs != lif->nxqs) {
3064		if (qparam->intr_split) {
3065			set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
3066		} else {
3067			clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
3068			lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
3069			lif->tx_coalesce_hw = lif->rx_coalesce_hw;
3070		}
3071
3072		/* Clear existing interrupt assignments.  We check for NULL here
3073		 * because we're checking the whole array for potential qcqs, not
3074		 * just those qcqs that have just been set up.
3075		 */
3076		for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) {
3077			if (lif->txqcqs[i])
3078				ionic_qcq_intr_free(lif, lif->txqcqs[i]);
3079			if (lif->rxqcqs[i])
3080				ionic_qcq_intr_free(lif, lif->rxqcqs[i]);
3081		}
3082
3083		/* re-assign the interrupts */
3084		for (i = 0; i < qparam->nxqs; i++) {
3085			lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR;
3086			err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]);
3087			ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
3088					     lif->rxqcqs[i]->intr.index,
3089					     lif->rx_coalesce_hw);
3090
3091			if (qparam->intr_split) {
3092				lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR;
3093				err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]);
3094				ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
3095						     lif->txqcqs[i]->intr.index,
3096						     lif->tx_coalesce_hw);
3097				if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
3098					lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
3099			} else {
3100				lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3101				ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]);
3102			}
3103		}
3104	}
3105
3106	/* now we can rework the debugfs mappings */
3107	if (tx_qcqs) {
3108		for (i = 0; i < qparam->nxqs; i++) {
3109			ionic_debugfs_del_qcq(lif->txqcqs[i]);
3110			ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
3111		}
3112	}
3113
3114	if (rx_qcqs) {
3115		for (i = 0; i < qparam->nxqs; i++) {
3116			ionic_debugfs_del_qcq(lif->rxqcqs[i]);
3117			ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
3118		}
3119	}
3120
3121	swap(lif->nxqs, qparam->nxqs);
3122	swap(lif->rxq_features, qparam->rxq_features);
3123
3124err_out_reinit_unlock:
3125	/* re-init the queues, but don't lose an error code */
3126	if (err)
3127		ionic_start_queues_reconfig(lif);
3128	else
3129		err = ionic_start_queues_reconfig(lif);
3130
3131err_out:
3132	/* free old allocs without cleaning intr */
3133	for (i = 0; i < qparam->nxqs; i++) {
3134		if (tx_qcqs && tx_qcqs[i]) {
3135			tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3136			ionic_qcq_free(lif, tx_qcqs[i]);
3137			devm_kfree(lif->ionic->dev, tx_qcqs[i]);
3138			tx_qcqs[i] = NULL;
3139		}
3140		if (rx_qcqs && rx_qcqs[i]) {
3141			rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3142			ionic_qcq_free(lif, rx_qcqs[i]);
3143			devm_kfree(lif->ionic->dev, rx_qcqs[i]);
3144			rx_qcqs[i] = NULL;
3145		}
3146	}
3147
3148	/* free q array */
3149	if (rx_qcqs) {
3150		devm_kfree(lif->ionic->dev, rx_qcqs);
3151		rx_qcqs = NULL;
3152	}
3153	if (tx_qcqs) {
3154		devm_kfree(lif->ionic->dev, tx_qcqs);
3155		tx_qcqs = NULL;
3156	}
3157
3158	/* clean the unused dma and info allocations when new set is smaller
3159	 * than the full array, but leave the qcq shells in place
3160	 */
3161	for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) {
3162		if (lif->txqcqs && lif->txqcqs[i]) {
3163			lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3164			ionic_qcq_free(lif, lif->txqcqs[i]);
3165		}
3166
3167		if (lif->rxqcqs && lif->rxqcqs[i]) {
3168			lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
3169			ionic_qcq_free(lif, lif->rxqcqs[i]);
3170		}
3171	}
3172
3173	if (err)
3174		netdev_info(lif->netdev, "%s: failed %d\n", __func__, err);
3175
3176	return err;
3177}
3178
3179static int ionic_affinity_masks_alloc(struct ionic *ionic)
3180{
3181	cpumask_var_t *affinity_masks;
3182	int nintrs = ionic->nintrs;
3183	int i;
3184
3185	affinity_masks = kcalloc(nintrs, sizeof(cpumask_var_t), GFP_KERNEL);
3186	if (!affinity_masks)
3187		return -ENOMEM;
3188
3189	for (i = 0; i < nintrs; i++) {
3190		if (!zalloc_cpumask_var_node(&affinity_masks[i], GFP_KERNEL,
3191					     dev_to_node(ionic->dev)))
3192			goto err_out;
3193	}
3194
3195	ionic->affinity_masks = affinity_masks;
3196
3197	return 0;
3198
3199err_out:
3200	for (--i; i >= 0; i--)
3201		free_cpumask_var(affinity_masks[i]);
3202	kfree(affinity_masks);
3203
3204	return -ENOMEM;
3205}
3206
3207static void ionic_affinity_masks_free(struct ionic *ionic)
3208{
3209	int i;
3210
3211	for (i = 0; i < ionic->nintrs; i++)
3212		free_cpumask_var(ionic->affinity_masks[i]);
3213	kfree(ionic->affinity_masks);
3214	ionic->affinity_masks = NULL;
3215}
3216
3217int ionic_lif_alloc(struct ionic *ionic)
3218{
3219	struct device *dev = ionic->dev;
3220	union ionic_lif_identity *lid;
3221	struct net_device *netdev;
3222	struct ionic_lif *lif;
3223	int tbl_sz;
3224	int err;
3225
3226	lid = kzalloc(sizeof(*lid), GFP_KERNEL);
3227	if (!lid)
3228		return -ENOMEM;
3229
3230	netdev = alloc_etherdev_mqs(sizeof(*lif),
3231				    ionic->ntxqs_per_lif, ionic->ntxqs_per_lif);
3232	if (!netdev) {
3233		dev_err(dev, "Cannot allocate netdev, aborting\n");
3234		err = -ENOMEM;
3235		goto err_out_free_lid;
3236	}
3237
3238	SET_NETDEV_DEV(netdev, dev);
3239
3240	lif = netdev_priv(netdev);
3241	lif->netdev = netdev;
3242	ionic->lif = lif;
3243	lif->ionic = ionic;
3244	netdev->netdev_ops = &ionic_netdev_ops;
3245	ionic_ethtool_set_ops(netdev);
3246
3247	netdev->watchdog_timeo = 5 * HZ;
3248	netif_carrier_off(netdev);
3249
3250	lif->identity = lid;
3251	lif->lif_type = IONIC_LIF_TYPE_CLASSIC;
3252	err = ionic_lif_identify(ionic, lif->lif_type, lif->identity);
3253	if (err) {
3254		dev_err(ionic->dev, "Cannot identify type %d: %d\n",
3255			lif->lif_type, err);
3256		goto err_out_free_netdev;
3257	}
3258	lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU,
3259				     le32_to_cpu(lif->identity->eth.min_frame_size));
3260	lif->netdev->max_mtu =
3261		le32_to_cpu(lif->identity->eth.max_frame_size) - VLAN_ETH_HLEN;
3262
3263	lif->neqs = ionic->neqs_per_lif;
3264	lif->nxqs = ionic->ntxqs_per_lif;
3265
3266	lif->index = 0;
3267
3268	if (is_kdump_kernel()) {
3269		lif->ntxq_descs = IONIC_MIN_TXRX_DESC;
3270		lif->nrxq_descs = IONIC_MIN_TXRX_DESC;
3271	} else {
3272		lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
3273		lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
3274	}
3275
3276	/* Convert the default coalesce value to actual hw resolution */
3277	lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT;
3278	lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic,
3279						    lif->rx_coalesce_usecs);
3280	lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
3281	lif->tx_coalesce_hw = lif->rx_coalesce_hw;
3282	set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
3283	set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
3284
3285	snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
3286
3287	mutex_init(&lif->queue_lock);
3288	mutex_init(&lif->config_lock);
3289	mutex_init(&lif->adev_lock);
3290
3291	spin_lock_init(&lif->adminq_lock);
3292
3293	spin_lock_init(&lif->deferred.lock);
3294	INIT_LIST_HEAD(&lif->deferred.list);
3295	INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
3296
3297	/* allocate lif info */
3298	lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
3299	lif->info = dma_alloc_coherent(dev, lif->info_sz,
3300				       &lif->info_pa, GFP_KERNEL);
3301	if (!lif->info) {
3302		dev_err(dev, "Failed to allocate lif info, aborting\n");
3303		err = -ENOMEM;
3304		goto err_out_free_mutex;
3305	}
3306
3307	ionic_debugfs_add_lif(lif);
3308
3309	err = ionic_affinity_masks_alloc(ionic);
3310	if (err)
3311		goto err_out_free_lif_info;
3312
3313	/* allocate control queues and txrx queue arrays */
3314	ionic_lif_queue_identify(lif);
3315	err = ionic_qcqs_alloc(lif);
3316	if (err)
3317		goto err_out_free_affinity_masks;
3318
3319	/* allocate rss indirection table */
3320	tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
3321	lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
3322	lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
3323					      &lif->rss_ind_tbl_pa,
3324					      GFP_KERNEL);
3325
3326	if (!lif->rss_ind_tbl) {
3327		err = -ENOMEM;
3328		dev_err(dev, "Failed to allocate rss indirection table, aborting\n");
3329		goto err_out_free_qcqs;
3330	}
3331	netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
3332
3333	ionic_lif_alloc_phc(lif);
3334
3335	return 0;
3336
3337err_out_free_qcqs:
3338	ionic_qcqs_free(lif);
3339err_out_free_affinity_masks:
3340	ionic_affinity_masks_free(lif->ionic);
3341err_out_free_lif_info:
3342	dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
3343	lif->info = NULL;
3344	lif->info_pa = 0;
3345err_out_free_mutex:
3346	mutex_destroy(&lif->adev_lock);
3347	mutex_destroy(&lif->config_lock);
3348	mutex_destroy(&lif->queue_lock);
3349err_out_free_netdev:
3350	free_netdev(lif->netdev);
3351	lif = NULL;
3352err_out_free_lid:
3353	kfree(lid);
3354
3355	return err;
3356}
3357
3358static void ionic_lif_reset(struct ionic_lif *lif)
3359{
3360	struct ionic_dev *idev = &lif->ionic->idev;
3361
3362	if (!ionic_is_fw_running(idev))
3363		return;
3364
3365	mutex_lock(&lif->ionic->dev_cmd_lock);
3366	ionic_dev_cmd_lif_reset(idev, lif->index);
3367	ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3368	mutex_unlock(&lif->ionic->dev_cmd_lock);
3369}
3370
3371static void ionic_lif_handle_fw_down(struct ionic_lif *lif)
3372{
3373	struct ionic *ionic = lif->ionic;
3374
3375	if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state))
3376		return;
3377
3378	dev_info(ionic->dev, "FW Down: Stopping LIFs\n");
3379
3380	netif_device_detach(lif->netdev);
3381
3382	ionic_auxbus_unregister(ionic->lif);
3383	mutex_lock(&lif->queue_lock);
3384	if (test_bit(IONIC_LIF_F_UP, lif->state)) {
3385		dev_info(ionic->dev, "Surprise FW stop, stopping queues\n");
3386		ionic_stop_queues(lif);
3387	}
3388
3389	if (netif_running(lif->netdev)) {
3390		ionic_txrx_deinit(lif);
3391		ionic_txrx_free(lif);
3392	}
3393	ionic_lif_deinit(lif);
3394	ionic_reset(ionic);
3395	ionic_qcqs_free(lif);
3396
3397	mutex_unlock(&lif->queue_lock);
3398
3399	clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state);
3400	dev_info(ionic->dev, "FW Down: LIFs stopped\n");
3401}
3402
3403int ionic_restart_lif(struct ionic_lif *lif)
3404{
3405	struct ionic *ionic = lif->ionic;
3406	int err;
3407
3408	mutex_lock(&lif->queue_lock);
3409
3410	if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
3411		dev_info(ionic->dev, "FW Up: clearing broken state\n");
3412
3413	err = ionic_qcqs_alloc(lif);
3414	if (err)
3415		goto err_unlock;
3416
3417	err = ionic_lif_init(lif);
3418	if (err)
3419		goto err_qcqs_free;
3420
3421	ionic_vf_attr_replay(lif);
3422
3423	if (lif->registered)
3424		ionic_lif_set_netdev_info(lif);
3425
3426	ionic_rx_filter_replay(lif);
3427
3428	if (netif_running(lif->netdev)) {
3429		err = ionic_txrx_alloc(lif);
3430		if (err)
3431			goto err_lifs_deinit;
3432
3433		err = ionic_txrx_init(lif);
3434		if (err)
3435			goto err_txrx_free;
3436	}
3437
3438	mutex_unlock(&lif->queue_lock);
3439
3440	clear_bit(IONIC_LIF_F_FW_RESET, lif->state);
3441	ionic_link_status_check_request(lif, CAN_SLEEP);
3442	netif_device_attach(lif->netdev);
3443	ionic_queue_doorbell_check(ionic, IONIC_NAPI_DEADLINE);
3444
3445	ionic_auxbus_register(ionic->lif);
3446
3447	return 0;
3448
3449err_txrx_free:
3450	ionic_txrx_free(lif);
3451err_lifs_deinit:
3452	ionic_lif_deinit(lif);
3453err_qcqs_free:
3454	ionic_qcqs_free(lif);
3455err_unlock:
3456	mutex_unlock(&lif->queue_lock);
3457
3458	return err;
3459}
3460
3461static void ionic_lif_handle_fw_up(struct ionic_lif *lif)
3462{
3463	struct ionic *ionic = lif->ionic;
3464	int err;
3465
3466	if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3467		return;
3468
3469	dev_info(ionic->dev, "FW Up: restarting LIFs\n");
3470
3471	/* This is a little different from what happens at
3472	 * probe time because the LIF already exists so we
3473	 * just need to reanimate it.
3474	 */
3475	ionic_init_devinfo(ionic);
3476	ionic_reset(ionic);
3477	err = ionic_identify(ionic);
3478	if (err)
3479		goto err_out;
3480	err = ionic_port_identify(ionic);
3481	if (err)
3482		goto err_out;
3483	err = ionic_port_init(ionic);
3484	if (err)
3485		goto err_out;
3486
3487	err = ionic_restart_lif(lif);
3488	if (err)
3489		goto err_out;
3490
3491	dev_info(ionic->dev, "FW Up: LIFs restarted\n");
3492
3493	/* restore the hardware timestamping queues */
3494	ionic_lif_hwstamp_replay(lif);
3495
3496	return;
3497
3498err_out:
3499	dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err);
3500}
3501
3502void ionic_lif_free(struct ionic_lif *lif)
3503{
3504	struct device *dev = lif->ionic->dev;
3505
3506	ionic_lif_free_phc(lif);
3507
3508	/* free rss indirection table */
3509	dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
3510			  lif->rss_ind_tbl_pa);
3511	lif->rss_ind_tbl = NULL;
3512	lif->rss_ind_tbl_pa = 0;
3513
3514	/* free queues */
3515	ionic_qcqs_free(lif);
3516	if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3517		ionic_lif_reset(lif);
3518
3519	ionic_affinity_masks_free(lif->ionic);
3520
3521	/* free lif info */
3522	kfree(lif->identity);
3523	dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
3524	lif->info = NULL;
3525	lif->info_pa = 0;
3526
3527	mutex_destroy(&lif->config_lock);
3528	mutex_destroy(&lif->queue_lock);
3529	mutex_destroy(&lif->adev_lock);
3530
3531	/* free netdev & lif */
3532	ionic_debugfs_del_lif(lif);
3533	free_netdev(lif->netdev);
3534}
3535
3536void ionic_lif_deinit(struct ionic_lif *lif)
3537{
3538	if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state))
3539		return;
3540
3541	if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3542		cancel_work_sync(&lif->deferred.work);
3543		cancel_work_sync(&lif->tx_timeout_work);
3544		ionic_rx_filters_deinit(lif);
3545		if (lif->netdev->features & NETIF_F_RXHASH)
3546			ionic_lif_rss_deinit(lif);
3547	}
3548
3549	napi_disable(&lif->adminqcq->napi);
3550	ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3551	ionic_lif_qcq_deinit(lif, lif->adminqcq);
3552
3553	ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3554	lif->kern_dbpage = NULL;
3555
3556	ionic_lif_reset(lif);
3557}
3558
3559static int ionic_lif_adminq_init(struct ionic_lif *lif)
3560{
3561	struct device *dev = lif->ionic->dev;
3562	struct ionic_q_init_comp comp;
3563	struct ionic_dev *idev;
3564	struct ionic_qcq *qcq;
3565	struct ionic_queue *q;
3566	int err;
3567
3568	idev = &lif->ionic->idev;
3569	qcq = lif->adminqcq;
3570	q = &qcq->q;
3571
3572	mutex_lock(&lif->ionic->dev_cmd_lock);
3573	ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
3574	err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3575	ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3576	mutex_unlock(&lif->ionic->dev_cmd_lock);
3577	if (err) {
3578		netdev_err(lif->netdev, "adminq init failed %d\n", err);
3579		return err;
3580	}
3581
3582	q->hw_type = comp.hw_type;
3583	q->hw_index = le32_to_cpu(comp.hw_index);
3584	q->dbval = IONIC_DBELL_QID(q->hw_index);
3585
3586	dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type);
3587	dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index);
3588
3589	q->dbell_deadline = IONIC_ADMIN_DOORBELL_DEADLINE;
3590	q->dbell_jiffies = jiffies;
3591
3592	netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi);
3593
3594	napi_enable(&qcq->napi);
3595
3596	if (qcq->flags & IONIC_QCQ_F_INTR) {
3597		irq_set_affinity_hint(qcq->intr.vector,
3598				      *qcq->intr.affinity_mask);
3599		ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
3600				IONIC_INTR_MASK_CLEAR);
3601	}
3602
3603	qcq->flags |= IONIC_QCQ_F_INITED;
3604
3605	return 0;
3606}
3607
3608static int ionic_lif_notifyq_init(struct ionic_lif *lif)
3609{
3610	struct ionic_qcq *qcq = lif->notifyqcq;
3611	struct device *dev = lif->ionic->dev;
3612	struct ionic_queue *q = &qcq->q;
3613	int err;
3614
3615	struct ionic_admin_ctx ctx = {
3616		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3617		.cmd.q_init = {
3618			.opcode = IONIC_CMD_Q_INIT,
3619			.lif_index = cpu_to_le16(lif->index),
3620			.type = q->type,
3621			.ver = lif->qtype_info[q->type].version,
3622			.index = cpu_to_le32(q->index),
3623			.flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
3624					     IONIC_QINIT_F_ENA),
3625			.intr_index = cpu_to_le16(lif->adminqcq->intr.index),
3626			.pid = cpu_to_le16(q->pid),
3627			.ring_size = ilog2(q->num_descs),
3628			.ring_base = cpu_to_le64(q->base_pa),
3629		}
3630	};
3631
3632	dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
3633	dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
3634	dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
3635	dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
3636
3637	err = ionic_adminq_post_wait(lif, &ctx);
3638	if (err)
3639		return err;
3640
3641	lif->last_eid = 0;
3642	q->hw_type = ctx.comp.q_init.hw_type;
3643	q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
3644	q->dbval = IONIC_DBELL_QID(q->hw_index);
3645
3646	dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
3647	dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
3648
3649	/* preset the callback info */
3650	q->admin_info[0].ctx = lif;
3651
3652	qcq->flags |= IONIC_QCQ_F_INITED;
3653
3654	return 0;
3655}
3656
3657static int ionic_station_set(struct ionic_lif *lif)
3658{
3659	struct net_device *netdev = lif->netdev;
3660	struct ionic_admin_ctx ctx = {
3661		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3662		.cmd.lif_getattr = {
3663			.opcode = IONIC_CMD_LIF_GETATTR,
3664			.index = cpu_to_le16(lif->index),
3665			.attr = IONIC_LIF_ATTR_MAC,
3666		},
3667	};
3668	u8 mac_address[ETH_ALEN];
3669	struct sockaddr addr;
3670	int err;
3671
3672	err = ionic_adminq_post_wait(lif, &ctx);
3673	if (err)
3674		return err;
3675	netdev_dbg(lif->netdev, "found initial MAC addr %pM\n",
3676		   ctx.comp.lif_getattr.mac);
3677	ether_addr_copy(mac_address, ctx.comp.lif_getattr.mac);
3678
3679	if (is_zero_ether_addr(mac_address)) {
3680		eth_hw_addr_random(netdev);
3681		netdev_dbg(netdev, "Random Mac generated: %pM\n", netdev->dev_addr);
3682		ether_addr_copy(mac_address, netdev->dev_addr);
3683
3684		err = ionic_program_mac(lif, mac_address);
3685		if (err < 0)
3686			return err;
3687
3688		if (err > 0) {
3689			netdev_dbg(netdev, "%s:SET/GET ATTR Mac are not same-due to old FW running\n",
3690				   __func__);
3691			return 0;
3692		}
3693	}
3694
3695	if (!is_zero_ether_addr(netdev->dev_addr)) {
3696		/* If the netdev mac is non-zero and doesn't match the default
3697		 * device address, it was set by something earlier and we're
3698		 * likely here again after a fw-upgrade reset.  We need to be
3699		 * sure the netdev mac is in our filter list.
3700		 */
3701		if (!ether_addr_equal(mac_address, netdev->dev_addr))
3702			ionic_lif_addr_add(lif, netdev->dev_addr);
3703	} else {
3704		/* Update the netdev mac with the device's mac */
3705		ether_addr_copy(addr.sa_data, mac_address);
3706		addr.sa_family = AF_INET;
3707		err = eth_prepare_mac_addr_change(netdev, &addr);
3708		if (err) {
3709			netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n",
3710				    addr.sa_data, err);
3711			return 0;
3712		}
3713
3714		eth_commit_mac_addr_change(netdev, &addr);
3715	}
3716
3717	netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
3718		   netdev->dev_addr);
3719	ionic_lif_addr_add(lif, netdev->dev_addr);
3720
3721	return 0;
3722}
3723
3724int ionic_lif_init(struct ionic_lif *lif)
3725{
3726	struct ionic_dev *idev = &lif->ionic->idev;
3727	struct device *dev = lif->ionic->dev;
3728	struct ionic_lif_init_comp comp;
3729	int dbpage_num;
3730	int err;
3731
3732	mutex_lock(&lif->ionic->dev_cmd_lock);
3733	ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
3734	err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3735	ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3736	mutex_unlock(&lif->ionic->dev_cmd_lock);
3737	if (err)
3738		return err;
3739
3740	lif->hw_index = le16_to_cpu(comp.hw_index);
3741
3742	/* now that we have the hw_index we can figure out our doorbell page */
3743	lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
3744	if (!lif->dbid_count) {
3745		dev_err(dev, "No doorbell pages, aborting\n");
3746		return -EINVAL;
3747	}
3748
3749	lif->kern_pid = 0;
3750	dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
3751	lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
3752	if (!lif->kern_dbpage) {
3753		dev_err(dev, "Cannot map dbpage, aborting\n");
3754		return -ENOMEM;
3755	}
3756
3757	err = ionic_lif_adminq_init(lif);
3758	if (err)
3759		goto err_out_adminq_deinit;
3760
3761	if (lif->ionic->nnqs_per_lif) {
3762		err = ionic_lif_notifyq_init(lif);
3763		if (err)
3764			goto err_out_notifyq_deinit;
3765	}
3766
3767	if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3768		err = ionic_set_nic_features(lif, lif->netdev->features);
3769	else
3770		err = ionic_init_nic_features(lif);
3771	if (err)
3772		goto err_out_notifyq_deinit;
3773
3774	if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3775		err = ionic_rx_filters_init(lif);
3776		if (err)
3777			goto err_out_notifyq_deinit;
3778	}
3779
3780	err = ionic_station_set(lif);
3781	if (err)
3782		goto err_out_notifyq_deinit;
3783
3784	lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
3785	lif->doorbell_wa = ionic_doorbell_wa(lif->ionic);
3786
3787	set_bit(IONIC_LIF_F_INITED, lif->state);
3788
3789	INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
3790
3791	return 0;
3792
3793err_out_notifyq_deinit:
3794	napi_disable(&lif->adminqcq->napi);
3795	ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3796err_out_adminq_deinit:
3797	ionic_lif_qcq_deinit(lif, lif->adminqcq);
3798	ionic_lif_reset(lif);
3799	ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3800	lif->kern_dbpage = NULL;
3801
3802	return err;
3803}
3804
3805static void ionic_lif_set_netdev_info(struct ionic_lif *lif)
3806{
3807	struct ionic_admin_ctx ctx = {
3808		.work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3809		.cmd.lif_setattr = {
3810			.opcode = IONIC_CMD_LIF_SETATTR,
3811			.index = cpu_to_le16(lif->index),
3812			.attr = IONIC_LIF_ATTR_NAME,
3813		},
3814	};
3815
3816	strscpy(ctx.cmd.lif_setattr.name, netdev_name(lif->netdev),
3817		sizeof(ctx.cmd.lif_setattr.name));
3818
3819	ionic_adminq_post_wait(lif, &ctx);
3820}
3821
3822static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev)
3823{
3824	if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit)
3825		return NULL;
3826
3827	return netdev_priv(netdev);
3828}
3829
3830static int ionic_lif_notify(struct notifier_block *nb,
3831			    unsigned long event, void *info)
3832{
3833	struct net_device *ndev = netdev_notifier_info_to_dev(info);
3834	struct ionic *ionic = container_of(nb, struct ionic, nb);
3835	struct ionic_lif *lif = ionic_netdev_lif(ndev);
3836
3837	if (!lif || lif->ionic != ionic)
3838		return NOTIFY_DONE;
3839
3840	switch (event) {
3841	case NETDEV_CHANGENAME:
3842		ionic_lif_set_netdev_info(lif);
3843		break;
3844	}
3845
3846	return NOTIFY_DONE;
3847}
3848
3849int ionic_lif_register(struct ionic_lif *lif)
3850{
3851	int err;
3852
3853	ionic_lif_register_phc(lif);
3854
3855	lif->ionic->nb.notifier_call = ionic_lif_notify;
3856
3857	err = register_netdevice_notifier(&lif->ionic->nb);
3858	if (err)
3859		lif->ionic->nb.notifier_call = NULL;
3860
3861	/* only register LIF0 for now */
3862	err = register_netdev(lif->netdev);
3863	if (err) {
3864		dev_err(lif->ionic->dev, "Cannot register net device: %d, aborting\n", err);
3865		ionic_lif_unregister(lif);
3866		return err;
3867	}
3868
3869	ionic_link_status_check_request(lif, CAN_SLEEP);
3870	lif->registered = true;
3871	ionic_lif_set_netdev_info(lif);
3872
3873	return 0;
3874}
3875
3876void ionic_lif_unregister(struct ionic_lif *lif)
3877{
3878	if (lif->ionic->nb.notifier_call) {
3879		unregister_netdevice_notifier(&lif->ionic->nb);
3880		lif->ionic->nb.notifier_call = NULL;
3881	}
3882
3883	if (lif->netdev->reg_state == NETREG_REGISTERED)
3884		unregister_netdev(lif->netdev);
3885
3886	ionic_lif_unregister_phc(lif);
3887
3888	lif->registered = false;
3889}
3890
3891static void ionic_lif_queue_identify(struct ionic_lif *lif)
3892{
3893	union ionic_q_identity __iomem *q_ident;
3894	struct ionic *ionic = lif->ionic;
3895	struct ionic_dev *idev;
3896	u16 max_frags;
3897	int qtype;
3898	int err;
3899
3900	idev = &lif->ionic->idev;
3901	q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data;
3902
3903	for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) {
3904		struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
3905
3906		/* filter out the ones we know about */
3907		switch (qtype) {
3908		case IONIC_QTYPE_ADMINQ:
3909		case IONIC_QTYPE_NOTIFYQ:
3910		case IONIC_QTYPE_RXQ:
3911		case IONIC_QTYPE_TXQ:
3912			break;
3913		default:
3914			continue;
3915		}
3916
3917		memset(qti, 0, sizeof(*qti));
3918
3919		mutex_lock(&ionic->dev_cmd_lock);
3920		ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype,
3921					     ionic_qtype_versions[qtype]);
3922		err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3923		if (!err) {
3924			qti->version   = readb(&q_ident->version);
3925			qti->supported = readb(&q_ident->supported);
3926			qti->features  = readq(&q_ident->features);
3927			qti->desc_sz   = readw(&q_ident->desc_sz);
3928			qti->comp_sz   = readw(&q_ident->comp_sz);
3929			qti->sg_desc_sz   = readw(&q_ident->sg_desc_sz);
3930			qti->max_sg_elems = readw(&q_ident->max_sg_elems);
3931			qti->sg_desc_stride = readw(&q_ident->sg_desc_stride);
3932		}
3933		mutex_unlock(&ionic->dev_cmd_lock);
3934
3935		if (err == -EINVAL) {
3936			dev_err(ionic->dev, "qtype %d not supported\n", qtype);
3937			continue;
3938		} else if (err == -EIO) {
3939			dev_err(ionic->dev, "q_ident failed, not supported on older FW\n");
3940			return;
3941		} else if (err) {
3942			dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n",
3943				qtype, err);
3944			return;
3945		}
3946
3947		dev_dbg(ionic->dev, " qtype[%d].version = %d\n",
3948			qtype, qti->version);
3949		dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n",
3950			qtype, qti->supported);
3951		dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n",
3952			qtype, qti->features);
3953		dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n",
3954			qtype, qti->desc_sz);
3955		dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n",
3956			qtype, qti->comp_sz);
3957		dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n",
3958			qtype, qti->sg_desc_sz);
3959		dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n",
3960			qtype, qti->max_sg_elems);
3961		dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n",
3962			qtype, qti->sg_desc_stride);
3963
3964		if (qtype == IONIC_QTYPE_TXQ)
3965			max_frags = IONIC_TX_MAX_FRAGS;
3966		else if (qtype == IONIC_QTYPE_RXQ)
3967			max_frags = IONIC_RX_MAX_FRAGS;
3968		else
3969			max_frags = 1;
3970
3971		qti->max_sg_elems = min_t(u16, max_frags - 1, MAX_SKB_FRAGS);
3972		dev_dbg(ionic->dev, "qtype %d max_sg_elems %d\n",
3973			qtype, qti->max_sg_elems);
3974	}
3975}
3976
3977int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
3978		       union ionic_lif_identity *lid)
3979{
3980	struct ionic_dev *idev = &ionic->idev;
3981	size_t sz;
3982	int err;
3983
3984	sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data));
3985
3986	mutex_lock(&ionic->dev_cmd_lock);
3987	ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1);
3988	err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3989	memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz);
3990	mutex_unlock(&ionic->dev_cmd_lock);
3991	if (err)
3992		return (err);
3993
3994	dev_dbg(ionic->dev, "capabilities 0x%llx\n",
3995		le64_to_cpu(lid->capabilities));
3996
3997	dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n",
3998		le32_to_cpu(lid->eth.max_ucast_filters));
3999	dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n",
4000		le32_to_cpu(lid->eth.max_mcast_filters));
4001	dev_dbg(ionic->dev, "eth.features 0x%llx\n",
4002		le64_to_cpu(lid->eth.config.features));
4003	dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n",
4004		le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ]));
4005	dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n",
4006		le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]));
4007	dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n",
4008		le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ]));
4009	dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n",
4010		le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ]));
4011	dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name);
4012	dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac);
4013	dev_dbg(ionic->dev, "eth.config.mtu %d\n",
4014		le32_to_cpu(lid->eth.config.mtu));
4015
4016	return 0;
4017}
4018
4019int ionic_lif_size(struct ionic *ionic)
4020{
4021	struct ionic_identity *ident = &ionic->ident;
4022	unsigned int nintrs, dev_nintrs;
4023	union ionic_lif_config *lc;
4024	unsigned int ntxqs_per_lif;
4025	unsigned int nrxqs_per_lif;
4026	unsigned int neqs_per_lif;
4027	unsigned int nnqs_per_lif;
4028	unsigned int nxqs, neqs;
4029	unsigned int min_intrs;
4030	int err;
4031
4032	/* retrieve basic values from FW */
4033	lc = &ident->lif.eth.config;
4034	dev_nintrs = le32_to_cpu(ident->dev.nintrs);
4035	neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
4036	nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]);
4037	ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]);
4038	nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]);
4039
4040	/* limit values to play nice with kdump */
4041	if (is_kdump_kernel()) {
4042		dev_nintrs = 2;
4043		neqs_per_lif = 0;
4044		nnqs_per_lif = 0;
4045		ntxqs_per_lif = 1;
4046		nrxqs_per_lif = 1;
4047	}
4048
4049	/* reserve last queue id for hardware timestamping */
4050	if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) {
4051		if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) {
4052			lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP);
4053		} else {
4054			ntxqs_per_lif -= 1;
4055			nrxqs_per_lif -= 1;
4056		}
4057	}
4058
4059	nxqs = min(ntxqs_per_lif, nrxqs_per_lif);
4060	nxqs = min(nxqs, num_online_cpus());
4061	neqs = min(neqs_per_lif, num_online_cpus());
4062
4063try_again:
4064	/* interrupt usage:
4065	 *    1 for master lif adminq/notifyq
4066	 *    1 for each CPU for master lif TxRx queue pairs
4067	 *    whatever's left is for RDMA queues
4068	 */
4069	nintrs = 1 + nxqs + neqs;
4070	min_intrs = 2;  /* adminq + 1 TxRx queue pair */
4071
4072	if (nintrs > dev_nintrs)
4073		goto try_fewer;
4074
4075	err = ionic_bus_alloc_irq_vectors(ionic, nintrs);
4076	if (err < 0 && err != -ENOSPC) {
4077		dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err);
4078		return err;
4079	}
4080	if (err == -ENOSPC)
4081		goto try_fewer;
4082
4083	if (err != nintrs) {
4084		ionic_bus_free_irq_vectors(ionic);
4085		goto try_fewer;
4086	}
4087
4088	ionic->nnqs_per_lif = nnqs_per_lif;
4089	ionic->neqs_per_lif = neqs;
4090	ionic->ntxqs_per_lif = nxqs;
4091	ionic->nrxqs_per_lif = nxqs;
4092	ionic->nintrs = nintrs;
4093
4094	ionic_debugfs_add_sizes(ionic);
4095
4096	return 0;
4097
4098try_fewer:
4099	if (nnqs_per_lif > 1) {
4100		nnqs_per_lif >>= 1;
4101		goto try_again;
4102	}
4103	if (neqs > 1) {
4104		neqs >>= 1;
4105		goto try_again;
4106	}
4107	if (nxqs > 1) {
4108		nxqs >>= 1;
4109		goto try_again;
4110	}
4111	dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs);
4112	return -ENOSPC;
4113}