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ionic_if.h
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linux-6.19.14/drivers/net/ethernet/pensando/ionic/ionic_if.h
1/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2/* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4#ifndef _IONIC_IF_H_ 5#define _IONIC_IF_H_ 6 7#define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8#define IONIC_DEV_INFO_VERSION 1 9#define IONIC_IFNAMSIZ 16 10 11/* 12 * enum ionic_cmd_opcode - Device commands 13 */ 14enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 IONIC_CMD_LIF_SETPHC = 25, 38 39 IONIC_CMD_RX_MODE_SET = 30, 40 IONIC_CMD_RX_FILTER_ADD = 31, 41 IONIC_CMD_RX_FILTER_DEL = 32, 42 43 /* Queue commands */ 44 IONIC_CMD_Q_IDENTIFY = 39, 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* SR/IOV commands */ 55 IONIC_CMD_VF_GETATTR = 60, 56 IONIC_CMD_VF_SETATTR = 61, 57 IONIC_CMD_VF_CTRL = 62, 58 59 /* CMB command */ 60 IONIC_CMD_DISCOVER_CMB = 80, 61 62 /* QoS commands */ 63 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 64 IONIC_CMD_QOS_CLASS_INIT = 241, 65 IONIC_CMD_QOS_CLASS_RESET = 242, 66 IONIC_CMD_QOS_CLASS_UPDATE = 243, 67 IONIC_CMD_QOS_CLEAR_STATS = 244, 68 IONIC_CMD_QOS_RESET = 245, 69 70 /* Firmware commands */ 71 IONIC_CMD_FW_DOWNLOAD = 252, 72 IONIC_CMD_FW_CONTROL = 253, 73 IONIC_CMD_FW_DOWNLOAD_V1 = 254, 74 IONIC_CMD_FW_CONTROL_V1 = 255, 75}; 76 77/* 78 * enum ionic_status_code - Device command return codes 79 */ 80enum ionic_status_code { 81 IONIC_RC_SUCCESS = 0, /* Success */ 82 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 83 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 84 IONIC_RC_EIO = 3, /* I/O error */ 85 IONIC_RC_EPERM = 4, /* Permission denied */ 86 IONIC_RC_EQID = 5, /* Bad qid */ 87 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 88 IONIC_RC_ENOENT = 7, /* No such element */ 89 IONIC_RC_EINTR = 8, /* operation interrupted */ 90 IONIC_RC_EAGAIN = 9, /* Try again */ 91 IONIC_RC_ENOMEM = 10, /* Out of memory */ 92 IONIC_RC_EFAULT = 11, /* Bad address */ 93 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 94 IONIC_RC_EEXIST = 13, /* object already exists */ 95 IONIC_RC_EINVAL = 14, /* Invalid argument */ 96 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 97 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 98 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 99 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 100 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 101 IONIC_RC_ERROR = 29, /* Generic error */ 102 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 103 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 104 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ 105}; 106 107enum ionic_notifyq_opcode { 108 IONIC_EVENT_LINK_CHANGE = 1, 109 IONIC_EVENT_RESET = 2, 110 IONIC_EVENT_HEARTBEAT = 3, 111 IONIC_EVENT_LOG = 4, 112 IONIC_EVENT_XCVR = 5, 113}; 114 115/** 116 * struct ionic_admin_cmd - General admin command format 117 * @opcode: Opcode for the command 118 * @rsvd: reserved byte(s) 119 * @lif_index: LIF index 120 * @cmd_data: Opcode-specific command bytes 121 */ 122struct ionic_admin_cmd { 123 u8 opcode; 124 u8 rsvd; 125 __le16 lif_index; 126 u8 cmd_data[60]; 127}; 128 129/** 130 * struct ionic_admin_comp - General admin command completion format 131 * @status: Status of the command (enum ionic_status_code) 132 * @rsvd: reserved byte(s) 133 * @comp_index: Index in the descriptor ring for which this is the completion 134 * @cmd_data: Command-specific bytes 135 * @color: Color bit (Always 0 for commands issued to the 136 * Device Cmd Registers) 137 */ 138struct ionic_admin_comp { 139 u8 status; 140 u8 rsvd; 141 __le16 comp_index; 142 u8 cmd_data[11]; 143 u8 color; 144#define IONIC_COMP_COLOR_MASK 0x80 145}; 146 147static inline u8 color_match(u8 color, u8 done_color) 148{ 149 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 150} 151 152/** 153 * struct ionic_nop_cmd - NOP command 154 * @opcode: opcode 155 * @rsvd: reserved byte(s) 156 */ 157struct ionic_nop_cmd { 158 u8 opcode; 159 u8 rsvd[63]; 160}; 161 162/** 163 * struct ionic_nop_comp - NOP command completion 164 * @status: Status of the command (enum ionic_status_code) 165 * @rsvd: reserved byte(s) 166 */ 167struct ionic_nop_comp { 168 u8 status; 169 u8 rsvd[15]; 170}; 171 172/** 173 * struct ionic_dev_init_cmd - Device init command 174 * @opcode: opcode 175 * @type: Device type 176 * @rsvd: reserved byte(s) 177 */ 178struct ionic_dev_init_cmd { 179 u8 opcode; 180 u8 type; 181 u8 rsvd[62]; 182}; 183 184/** 185 * struct ionic_dev_init_comp - Device init command completion 186 * @status: Status of the command (enum ionic_status_code) 187 * @rsvd: reserved byte(s) 188 */ 189struct ionic_dev_init_comp { 190 u8 status; 191 u8 rsvd[15]; 192}; 193 194/** 195 * struct ionic_dev_reset_cmd - Device reset command 196 * @opcode: opcode 197 * @rsvd: reserved byte(s) 198 */ 199struct ionic_dev_reset_cmd { 200 u8 opcode; 201 u8 rsvd[63]; 202}; 203 204/** 205 * struct ionic_dev_reset_comp - Reset command completion 206 * @status: Status of the command (enum ionic_status_code) 207 * @rsvd: reserved byte(s) 208 */ 209struct ionic_dev_reset_comp { 210 u8 status; 211 u8 rsvd[15]; 212}; 213 214#define IONIC_IDENTITY_VERSION_1 1 215#define IONIC_DEV_IDENTITY_VERSION_2 2 216 217/** 218 * struct ionic_dev_identify_cmd - Driver/device identify command 219 * @opcode: opcode 220 * @ver: Highest version of identify supported by driver 221 * @rsvd: reserved byte(s) 222 */ 223struct ionic_dev_identify_cmd { 224 u8 opcode; 225 u8 ver; 226 u8 rsvd[62]; 227}; 228 229/** 230 * struct ionic_dev_identify_comp - Driver/device identify command completion 231 * @status: Status of the command (enum ionic_status_code) 232 * @ver: Version of identify returned by device 233 * @rsvd: reserved byte(s) 234 */ 235struct ionic_dev_identify_comp { 236 u8 status; 237 u8 ver; 238 u8 rsvd[14]; 239}; 240 241enum ionic_os_type { 242 IONIC_OS_TYPE_LINUX = 1, 243 IONIC_OS_TYPE_WIN = 2, 244 IONIC_OS_TYPE_DPDK = 3, 245 IONIC_OS_TYPE_FREEBSD = 4, 246 IONIC_OS_TYPE_IPXE = 5, 247 IONIC_OS_TYPE_ESXI = 6, 248}; 249 250/** 251 * union ionic_drv_identity - driver identity information 252 * @os_type: OS type (see enum ionic_os_type) 253 * @os_dist: OS distribution, numeric format 254 * @os_dist_str: OS distribution, string format 255 * @kernel_ver: Kernel version, numeric format 256 * @kernel_ver_str: Kernel version, string format 257 * @driver_ver_str: Driver version, string format 258 * @words: word access to struct contents 259 */ 260union ionic_drv_identity { 261 struct { 262 __le32 os_type; 263 __le32 os_dist; 264 char os_dist_str[128]; 265 __le32 kernel_ver; 266 char kernel_ver_str[32]; 267 char driver_ver_str[32]; 268 }; 269 __le32 words[478]; 270}; 271 272/** 273 * enum ionic_dev_capability - Device capabilities 274 * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations 275 * @IONIC_DEV_CAP_DISC_CMB: Device supports CMB discovery operations 276 */ 277enum ionic_dev_capability { 278 IONIC_DEV_CAP_VF_CTRL = BIT(0), 279 IONIC_DEV_CAP_DISC_CMB = BIT(1), 280}; 281 282/** 283 * union ionic_dev_identity - device identity information 284 * @version: Version of device identify 285 * @type: Identify type (0 for now) 286 * @rsvd: reserved byte(s) 287 * @nports: Number of ports provisioned 288 * @rsvd2: reserved byte(s) 289 * @nlifs: Number of LIFs provisioned 290 * @nintrs: Number of interrupts provisioned 291 * @ndbpgs_per_lif: Number of doorbell pages per LIF 292 * @intr_coal_mult: Interrupt coalescing multiplication factor 293 * Scale user-supplied interrupt coalescing 294 * value in usecs to device units using: 295 * device units = usecs * mult / div 296 * @intr_coal_div: Interrupt coalescing division factor 297 * Scale user-supplied interrupt coalescing 298 * value in usecs to device units using: 299 * device units = usecs * mult / div 300 * @eq_count: Number of shared event queues 301 * @hwstamp_mask: Bitmask for subtraction of hardware tick values. 302 * @hwstamp_mult: Hardware tick to nanosecond multiplier. 303 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 304 * @capabilities: Device capabilities 305 * @words: word access to struct contents 306 */ 307union ionic_dev_identity { 308 struct { 309 u8 version; 310 u8 type; 311 u8 rsvd[2]; 312 u8 nports; 313 u8 rsvd2[3]; 314 __le32 nlifs; 315 __le32 nintrs; 316 __le32 ndbpgs_per_lif; 317 __le32 intr_coal_mult; 318 __le32 intr_coal_div; 319 __le32 eq_count; 320 __le64 hwstamp_mask; 321 __le32 hwstamp_mult; 322 __le32 hwstamp_shift; 323 __le64 capabilities; 324 }; 325 __le32 words[478]; 326}; 327 328enum ionic_lif_type { 329 IONIC_LIF_TYPE_CLASSIC = 0, 330 IONIC_LIF_TYPE_MACVLAN = 1, 331 IONIC_LIF_TYPE_NETQUEUE = 2, 332}; 333 334/** 335 * struct ionic_lif_identify_cmd - LIF identify command 336 * @opcode: opcode 337 * @type: LIF type (enum ionic_lif_type) 338 * @ver: Version of identify returned by device 339 * @rsvd: reserved byte(s) 340 */ 341struct ionic_lif_identify_cmd { 342 u8 opcode; 343 u8 type; 344 u8 ver; 345 u8 rsvd[61]; 346}; 347 348/** 349 * struct ionic_lif_identify_comp - LIF identify command completion 350 * @status: Status of the command (enum ionic_status_code) 351 * @ver: Version of identify returned by device 352 * @rsvd2: reserved byte(s) 353 */ 354struct ionic_lif_identify_comp { 355 u8 status; 356 u8 ver; 357 u8 rsvd2[14]; 358}; 359 360/** 361 * enum ionic_lif_capability - LIF capabilities 362 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 363 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA 364 */ 365enum ionic_lif_capability { 366 IONIC_LIF_CAP_ETH = BIT(0), 367 IONIC_LIF_CAP_RDMA = BIT(1), 368}; 369 370/** 371 * enum ionic_logical_qtype - Logical Queue Types 372 * @IONIC_QTYPE_ADMINQ: Administrative Queue 373 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 374 * @IONIC_QTYPE_RXQ: Receive Queue 375 * @IONIC_QTYPE_TXQ: Transmit Queue 376 * @IONIC_QTYPE_EQ: Event Queue 377 * @IONIC_QTYPE_MAX: Max queue type supported 378 */ 379enum ionic_logical_qtype { 380 IONIC_QTYPE_ADMINQ = 0, 381 IONIC_QTYPE_NOTIFYQ = 1, 382 IONIC_QTYPE_RXQ = 2, 383 IONIC_QTYPE_TXQ = 3, 384 IONIC_QTYPE_EQ = 4, 385 IONIC_QTYPE_MAX = 16, 386}; 387 388/** 389 * enum ionic_q_feature - Common Features for most queue types 390 * 391 * Common features use bits 0-15. Per-queue-type features use higher bits. 392 * 393 * @IONIC_QIDENT_F_CQ: Queue has completion ring 394 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring 395 * @IONIC_QIDENT_F_EQ: Queue can use event queue 396 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar 397 * @IONIC_Q_F_2X_DESC: Double main descriptor size 398 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size 399 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size 400 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size 401 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size 402 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size 403 * @IONIC_QIDENT_F_EXPDB: Queue supports express doorbell 404 */ 405enum ionic_q_feature { 406 IONIC_QIDENT_F_CQ = BIT_ULL(0), 407 IONIC_QIDENT_F_SG = BIT_ULL(1), 408 IONIC_QIDENT_F_EQ = BIT_ULL(2), 409 IONIC_QIDENT_F_CMB = BIT_ULL(3), 410 IONIC_Q_F_2X_DESC = BIT_ULL(4), 411 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), 412 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), 413 IONIC_Q_F_4X_DESC = BIT_ULL(7), 414 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), 415 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), 416 IONIC_QIDENT_F_EXPDB = BIT_ULL(10), 417}; 418 419/** 420 * enum ionic_rxq_feature - RXQ-specific Features 421 * 422 * Per-queue-type features use bits 16 and higher. 423 * 424 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping 425 */ 426enum ionic_rxq_feature { 427 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), 428}; 429 430/** 431 * enum ionic_txq_feature - TXQ-specific Features 432 * 433 * Per-queue-type features use bits 16 and higher. 434 * 435 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping 436 */ 437enum ionic_txq_feature { 438 IONIC_TXQ_F_HWSTAMP = BIT(16), 439}; 440 441/** 442 * enum ionic_hwstamp_bits - Hardware timestamp decoding bits 443 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 444 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 445 * from the base cq descriptor. 446 */ 447enum ionic_hwstamp_bits { 448 IONIC_HWSTAMP_INVALID = ~0ull, 449 IONIC_HWSTAMP_CQ_NEGOFFSET = 8, 450}; 451 452/** 453 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 454 * @qtype: Hardware Queue Type 455 * @rsvd: reserved byte(s) 456 * @qid_count: Number of Queue IDs of the logical type 457 * @qid_base: Minimum Queue ID of the logical type 458 */ 459struct ionic_lif_logical_qtype { 460 u8 qtype; 461 u8 rsvd[3]; 462 __le32 qid_count; 463 __le32 qid_base; 464}; 465 466/** 467 * enum ionic_lif_state - LIF state 468 * @IONIC_LIF_DISABLE: LIF disabled 469 * @IONIC_LIF_ENABLE: LIF enabled 470 * @IONIC_LIF_QUIESCE: LIF Quiesced 471 */ 472enum ionic_lif_state { 473 IONIC_LIF_QUIESCE = 0, 474 IONIC_LIF_ENABLE = 1, 475 IONIC_LIF_DISABLE = 2, 476}; 477 478/** 479 * union ionic_lif_config - LIF configuration 480 * @state: LIF state (enum ionic_lif_state) 481 * @rsvd: reserved byte(s) 482 * @name: LIF name 483 * @mtu: MTU 484 * @mac: Station MAC address 485 * @vlan: Default Vlan ID 486 * @features: Features (enum ionic_eth_hw_features) 487 * @queue_count: Queue counts per queue-type 488 * @words: word access to struct contents 489 */ 490union ionic_lif_config { 491 struct { 492 u8 state; 493 u8 rsvd[3]; 494 char name[IONIC_IFNAMSIZ]; 495 __le32 mtu; 496 u8 mac[6]; 497 __le16 vlan; 498 __le64 features; 499 __le32 queue_count[IONIC_QTYPE_MAX]; 500 } __packed; 501 __le32 words[64]; 502}; 503 504/** 505 * enum ionic_lif_rdma_cap_stats - LIF stat type 506 * @IONIC_LIF_RDMA_STAT_GLOBAL: Global stats 507 * @IONIC_LIF_RDMA_STAT_QP: Queue pair stats 508 */ 509enum ionic_lif_rdma_cap_stats { 510 IONIC_LIF_RDMA_STAT_GLOBAL = BIT(0), 511 IONIC_LIF_RDMA_STAT_QP = BIT(1), 512}; 513 514/** 515 * struct ionic_lif_identity - LIF identity information (type-specific) 516 * 517 * @capabilities: LIF capabilities 518 * 519 * @eth: Ethernet identify structure 520 * @eth.version: Ethernet identify structure version 521 * @eth.rsvd: reserved byte(s) 522 * @eth.max_ucast_filters: Number of perfect unicast addresses supported 523 * @eth.max_mcast_filters: Number of perfect multicast addresses supported 524 * @eth.min_frame_size: Minimum size of frames to be sent 525 * @eth.max_frame_size: Maximum size of frames to be sent 526 * @eth.rsvd2: reserved byte(s) 527 * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 528 * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 529 * @eth.rsvd3: reserved byte(s) 530 * @eth.config: LIF config struct with features, mtu, mac, q counts 531 * 532 * @rdma: RDMA identify structure 533 * @rdma.version: RDMA capability version 534 * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported 535 * @rdma.admin_opcodes: Number of RDMA admin opcodes supported 536 * @rdma.minor_version: RDMA capability minor version 537 * @rdma.npts_per_lif: Page table size per LIF 538 * @rdma.nmrs_per_lif: Number of memory regions per LIF 539 * @rdma.nahs_per_lif: Number of address handles per LIF 540 * @rdma.max_stride: Max work request stride 541 * @rdma.cl_stride: Cache line stride 542 * @rdma.pte_stride: Page table entry stride 543 * @rdma.rrq_stride: Remote RQ work request stride 544 * @rdma.rsq_stride: Remote SQ work request stride 545 * @rdma.dcqcn_profiles: Number of DCQCN profiles 546 * @rdma.udma_shift: Log2 number of queues per queue group 547 * @rdma.rsvd_dimensions: Reserved byte 548 * @rdma.page_size_cap: Supported page sizes 549 * @rdma.aq_qtype: RDMA Admin Qtype 550 * @rdma.sq_qtype: RDMA Send Qtype 551 * @rdma.rq_qtype: RDMA Receive Qtype 552 * @rdma.cq_qtype: RDMA Completion Qtype 553 * @rdma.eq_qtype: RDMA Event Qtype 554 * @rdma.stats_type: Supported statistics type 555 * (enum ionic_lif_rdma_cap_stats) 556 * @rdma.rsvd1: Reserved byte(s) 557 * @words: word access to struct contents 558 */ 559union ionic_lif_identity { 560 struct { 561 __le64 capabilities; 562 563 struct { 564 u8 version; 565 u8 rsvd[3]; 566 __le32 max_ucast_filters; 567 __le32 max_mcast_filters; 568 __le16 rss_ind_tbl_sz; 569 __le32 min_frame_size; 570 __le32 max_frame_size; 571 u8 rsvd2[2]; 572 __le64 hwstamp_tx_modes; 573 __le64 hwstamp_rx_filters; 574 u8 rsvd3[88]; 575 union ionic_lif_config config; 576 } __packed eth; 577 578 struct { 579 u8 version; 580 u8 qp_opcodes; 581 u8 admin_opcodes; 582 u8 minor_version; 583 __le32 npts_per_lif; 584 __le32 nmrs_per_lif; 585 __le32 nahs_per_lif; 586 u8 max_stride; 587 u8 cl_stride; 588 u8 pte_stride; 589 u8 rrq_stride; 590 u8 rsq_stride; 591 u8 dcqcn_profiles; 592 u8 udma_shift; 593 u8 rsvd_dimensions; 594 __le64 page_size_cap; 595 struct ionic_lif_logical_qtype aq_qtype; 596 struct ionic_lif_logical_qtype sq_qtype; 597 struct ionic_lif_logical_qtype rq_qtype; 598 struct ionic_lif_logical_qtype cq_qtype; 599 struct ionic_lif_logical_qtype eq_qtype; 600 __le16 stats_type; 601 u8 rsvd1[162]; 602 } __packed rdma; 603 } __packed; 604 __le32 words[478]; 605}; 606 607/** 608 * struct ionic_lif_init_cmd - LIF init command 609 * @opcode: Opcode 610 * @type: LIF type (enum ionic_lif_type) 611 * @index: LIF index 612 * @rsvd: reserved byte(s) 613 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 614 * @rsvd2: reserved byte(s) 615 */ 616struct ionic_lif_init_cmd { 617 u8 opcode; 618 u8 type; 619 __le16 index; 620 __le32 rsvd; 621 __le64 info_pa; 622 u8 rsvd2[48]; 623}; 624 625/** 626 * struct ionic_lif_init_comp - LIF init command completion 627 * @status: Status of the command (enum ionic_status_code) 628 * @rsvd: reserved byte(s) 629 * @hw_index: Hardware index of the initialized LIF 630 * @rsvd2: reserved byte(s) 631 */ 632struct ionic_lif_init_comp { 633 u8 status; 634 u8 rsvd; 635 __le16 hw_index; 636 u8 rsvd2[12]; 637}; 638 639/** 640 * struct ionic_q_identify_cmd - queue identify command 641 * @opcode: opcode 642 * @rsvd: reserved byte(s) 643 * @lif_type: LIF type (enum ionic_lif_type) 644 * @type: Logical queue type (enum ionic_logical_qtype) 645 * @ver: Highest queue type version that the driver supports 646 * @rsvd2: reserved byte(s) 647 */ 648struct ionic_q_identify_cmd { 649 u8 opcode; 650 u8 rsvd; 651 __le16 lif_type; 652 u8 type; 653 u8 ver; 654 u8 rsvd2[58]; 655}; 656 657/** 658 * struct ionic_q_identify_comp - queue identify command completion 659 * @status: Status of the command (enum ionic_status_code) 660 * @rsvd: reserved byte(s) 661 * @comp_index: Index in the descriptor ring for which this is the completion 662 * @ver: Queue type version that can be used with FW 663 * @rsvd2: reserved byte(s) 664 */ 665struct ionic_q_identify_comp { 666 u8 status; 667 u8 rsvd; 668 __le16 comp_index; 669 u8 ver; 670 u8 rsvd2[11]; 671}; 672 673/** 674 * union ionic_q_identity - queue identity information 675 * @version: Queue type version that can be used with FW 676 * @supported: Bitfield of queue versions, first bit = ver 0 677 * @rsvd: reserved byte(s) 678 * @features: Queue features (enum ionic_q_feature, etc) 679 * @desc_sz: Descriptor size 680 * @comp_sz: Completion descriptor size 681 * @sg_desc_sz: Scatter/Gather descriptor size 682 * @max_sg_elems: Maximum number of Scatter/Gather elements 683 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 684 * @words: word access to struct contents 685 */ 686union ionic_q_identity { 687 struct { 688 u8 version; 689 u8 supported; 690 u8 rsvd[6]; 691 __le64 features; 692 __le16 desc_sz; 693 __le16 comp_sz; 694 __le16 sg_desc_sz; 695 __le16 max_sg_elems; 696 __le16 sg_desc_stride; 697 }; 698 __le32 words[478]; 699}; 700 701/** 702 * struct ionic_q_init_cmd - Queue init command 703 * @opcode: opcode 704 * @rsvd: reserved byte(s) 705 * @type: Logical queue type 706 * @ver: Queue type version 707 * @rsvd1: reserved byte(s) 708 * @lif_index: LIF index 709 * @index: (LIF, qtype) relative admin queue index 710 * @intr_index: Interrupt control register index, or Event queue index 711 * @pid: Process ID 712 * @flags: 713 * IRQ: Interrupt requested on completion 714 * ENA: Enable the queue. If ENA=0 the queue is initialized 715 * but remains disabled, to be later enabled with the 716 * Queue Enable command. If ENA=1, then queue is 717 * initialized and then enabled. 718 * SG: Enable Scatter-Gather on the queue. 719 * in number of descs. The actual ring size is 720 * (1 << ring_size). For example, to 721 * select a ring size of 64 descriptors write 722 * ring_size = 6. The minimum ring_size value is 2 723 * for a ring size of 4 descriptors. The maximum 724 * ring_size value is 16 for a ring size of 64k 725 * descriptors. Values of ring_size <2 and >16 are 726 * reserved. 727 * EQ: Enable the Event Queue 728 * @cos: Class of service for this queue 729 * @ring_size: Queue ring size, encoded as a log2(size) 730 * @ring_base: Queue ring base address 731 * @cq_ring_base: Completion queue ring base address 732 * @sg_ring_base: Scatter/Gather ring base address 733 * @rsvd2: reserved byte(s) 734 * @features: Mask of queue features to enable, if not in the flags above. 735 */ 736struct ionic_q_init_cmd { 737 u8 opcode; 738 u8 rsvd; 739 __le16 lif_index; 740 u8 type; 741 u8 ver; 742 u8 rsvd1[2]; 743 __le32 index; 744 __le16 pid; 745 __le16 intr_index; 746 __le16 flags; 747#define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 748#define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 749#define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 750#define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 751#define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 752#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 753 u8 cos; 754 u8 ring_size; 755 __le64 ring_base; 756 __le64 cq_ring_base; 757 __le64 sg_ring_base; 758 u8 rsvd2[12]; 759 __le64 features; 760} __packed; 761 762/** 763 * struct ionic_q_init_comp - Queue init command completion 764 * @status: Status of the command (enum ionic_status_code) 765 * @rsvd: reserved byte(s) 766 * @comp_index: Index in the descriptor ring for which this is the completion 767 * @hw_index: Hardware Queue ID 768 * @hw_type: Hardware Queue type 769 * @rsvd2: reserved byte(s) 770 * @color: Color 771 */ 772struct ionic_q_init_comp { 773 u8 status; 774 u8 rsvd; 775 __le16 comp_index; 776 __le32 hw_index; 777 u8 hw_type; 778 u8 rsvd2[6]; 779 u8 color; 780}; 781 782/* the device's internal addressing uses up to 52 bits */ 783#define IONIC_ADDR_LEN 52 784#define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 785 786enum ionic_txq_desc_opcode { 787 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 788 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 789 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 790 IONIC_TXQ_DESC_OPCODE_TSO = 3, 791}; 792 793/** 794 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 795 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 796 * 797 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 798 * Non-offload send. No segmentation, 799 * fragmentation or checksum calc/insertion is 800 * performed by device; packet is prepared 801 * to send by software stack and requires 802 * no further manipulation from device. 803 * 804 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 805 * Offload 16-bit L4 checksum 806 * calculation/insertion. The device will 807 * calculate the L4 checksum value and 808 * insert the result in the packet's L4 809 * header checksum field. The L4 checksum 810 * is calculated starting at @csum_start bytes 811 * into the packet to the end of the packet. 812 * The checksum insertion position is given 813 * in @csum_offset, which is the offset from 814 * @csum_start to the checksum field in the L4 815 * header. This feature is only applicable to 816 * protocols such as TCP, UDP and ICMP where a 817 * standard (i.e. the 'IP-style' checksum) 818 * one's complement 16-bit checksum is used, 819 * using an IP pseudo-header to seed the 820 * calculation. Software will preload the L4 821 * checksum field with the IP pseudo-header 822 * checksum. 823 * 824 * For tunnel encapsulation, @csum_start and 825 * @csum_offset refer to the inner L4 826 * header. Supported tunnels encapsulations 827 * are: IPIP, GRE, and UDP. If the @encap 828 * is clear, no further processing by the 829 * device is required; software will 830 * calculate the outer header checksums. If 831 * the @encap is set, the device will 832 * offload the outer header checksums using 833 * LCO (local checksum offload) (see 834 * Documentation/networking/checksum-offloads.rst 835 * for more info). 836 * 837 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 838 * Offload 16-bit checksum computation to hardware. 839 * If @csum_l3 is set then the packet's L3 checksum is 840 * updated. Similarly, if @csum_l4 is set the L4 841 * checksum is updated. If @encap is set then encap header 842 * checksums are also updated. 843 * 844 * IONIC_TXQ_DESC_OPCODE_TSO: 845 * Device performs TCP segmentation offload 846 * (TSO). @hdr_len is the number of bytes 847 * to the end of TCP header (the offset to 848 * the TCP payload). @mss is the desired 849 * MSS, the TCP payload length for each 850 * segment. The device will calculate/ 851 * insert IP (IPv4 only) and TCP checksums 852 * for each segment. In the first data 853 * buffer containing the header template, 854 * the driver will set IPv4 checksum to 0 855 * and preload TCP checksum with the IP 856 * pseudo header calculated with IP length = 0. 857 * 858 * Supported tunnel encapsulations are IPIP, 859 * layer-3 GRE, and UDP. @hdr_len includes 860 * both outer and inner headers. The driver 861 * will set IPv4 checksum to zero and 862 * preload TCP checksum with IP pseudo 863 * header on the inner header. 864 * 865 * TCP ECN offload is supported. The device 866 * will set CWR flag in the first segment if 867 * CWR is set in the template header, and 868 * clear CWR in remaining segments. 869 * flags: 870 * vlan: 871 * Insert an L2 VLAN header using @vlan_tci 872 * encap: 873 * Calculate encap header checksum 874 * csum_l3: 875 * Compute L3 header checksum 876 * csum_l4: 877 * Compute L4 header checksum 878 * tso_sot: 879 * TSO start 880 * tso_eot: 881 * TSO end 882 * num_sg_elems: Number of scatter-gather elements in SG 883 * descriptor 884 * addr: First data buffer's DMA address 885 * (Subsequent data buffers are on txq_sg_desc) 886 * @len: First data buffer's length, in bytes 887 * @vlan_tci: VLAN tag to insert in the packet (if requested 888 * by @V-bit). Includes .1p and .1q tags 889 * @hword0: half word padding 890 * @hdr_len: Length of packet headers, including 891 * encapsulating outer header, if applicable 892 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 893 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 894 * all other modes. For 895 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 896 * of headers up to inner-most L4 header. For 897 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 898 * inner-most L4 payload, so inclusive of 899 * inner-most L4 header. 900 * @hword1: half word padding 901 * @mss: Desired MSS value for TSO; only applicable for 902 * IONIC_TXQ_DESC_OPCODE_TSO 903 * @csum_start: Offset from packet to first byte checked in L4 checksum 904 * @csum_offset: Offset from csum_start to L4 checksum field 905 * @hword2: half word padding 906 */ 907struct ionic_txq_desc { 908 __le64 cmd; 909#define IONIC_TXQ_DESC_OPCODE_MASK 0xf 910#define IONIC_TXQ_DESC_OPCODE_SHIFT 4 911#define IONIC_TXQ_DESC_FLAGS_MASK 0xf 912#define IONIC_TXQ_DESC_FLAGS_SHIFT 0 913#define IONIC_TXQ_DESC_NSGE_MASK 0xf 914#define IONIC_TXQ_DESC_NSGE_SHIFT 8 915#define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 916#define IONIC_TXQ_DESC_ADDR_SHIFT 12 917 918/* common flags */ 919#define IONIC_TXQ_DESC_FLAG_VLAN 0x1 920#define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 921 922/* flags for csum_hw opcode */ 923#define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 924#define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 925 926/* flags for tso opcode */ 927#define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 928#define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 929 930 __le16 len; 931 union { 932 __le16 vlan_tci; 933 __le16 hword0; 934 }; 935 union { 936 __le16 csum_start; 937 __le16 hdr_len; 938 __le16 hword1; 939 }; 940 union { 941 __le16 csum_offset; 942 __le16 mss; 943 __le16 hword2; 944 }; 945}; 946 947static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 948 u8 nsge, u64 addr) 949{ 950 u64 cmd; 951 952 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 953 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 954 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 955 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 956 957 return cmd; 958}; 959 960static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 961 u8 *nsge, u64 *addr) 962{ 963 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 964 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 965 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 966 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 967}; 968 969/** 970 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 971 * @addr: DMA address of SG element data buffer 972 * @len: Length of SG element data buffer, in bytes 973 * @rsvd: reserved byte(s) 974 */ 975struct ionic_txq_sg_elem { 976 __le64 addr; 977 __le16 len; 978 __le16 rsvd[3]; 979}; 980 981/** 982 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 983 * @elems: Scatter-gather elements 984 */ 985struct ionic_txq_sg_desc { 986#define IONIC_TX_MAX_SG_ELEMS 8 987#define IONIC_TX_SG_DESC_STRIDE 8 988 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 989}; 990 991struct ionic_txq_sg_desc_v1 { 992#define IONIC_TX_MAX_SG_ELEMS_V1 15 993#define IONIC_TX_SG_DESC_STRIDE_V1 16 994 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 995}; 996 997/** 998 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 999 * @status: Status of the command (enum ionic_status_code) 1000 * @rsvd: reserved byte(s) 1001 * @comp_index: Index in the descriptor ring for which this is the completion 1002 * @rsvd2: reserved byte(s) 1003 * @color: Color bit 1004 */ 1005struct ionic_txq_comp { 1006 u8 status; 1007 u8 rsvd; 1008 __le16 comp_index; 1009 u8 rsvd2[11]; 1010 u8 color; 1011}; 1012 1013enum ionic_rxq_desc_opcode { 1014 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 1015 IONIC_RXQ_DESC_OPCODE_SG = 1, 1016}; 1017 1018/** 1019 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 1020 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 1021 * 1022 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 1023 * Receive full packet into data buffer 1024 * starting at @addr. Results of 1025 * receive, including actual bytes received, 1026 * are recorded in Rx completion descriptor. 1027 * 1028 * @rsvd: reserved byte(s) 1029 * @len: Data buffer's length, in bytes 1030 * @addr: Data buffer's DMA address 1031 */ 1032struct ionic_rxq_desc { 1033 u8 opcode; 1034 u8 rsvd[5]; 1035 __le16 len; 1036 __le64 addr; 1037}; 1038 1039/** 1040 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 1041 * @addr: DMA address of SG element data buffer 1042 * @len: Length of SG element data buffer, in bytes 1043 * @rsvd: reserved byte(s) 1044 */ 1045struct ionic_rxq_sg_elem { 1046 __le64 addr; 1047 __le16 len; 1048 __le16 rsvd[3]; 1049}; 1050 1051/** 1052 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 1053 * @elems: Scatter-gather elements 1054 */ 1055struct ionic_rxq_sg_desc { 1056#define IONIC_RX_MAX_SG_ELEMS 8 1057#define IONIC_RX_SG_DESC_STRIDE 8 1058 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 1059}; 1060 1061/** 1062 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 1063 * @status: Status of the command (enum ionic_status_code) 1064 * @num_sg_elems: Number of SG elements used by this descriptor 1065 * @comp_index: Index in the descriptor ring for which this is the completion 1066 * @rss_hash: 32-bit RSS hash 1067 * @csum: 16-bit sum of the packet's L2 payload 1068 * If the packet's L2 payload is odd length, an extra 1069 * zero-value byte is included in the @csum calculation but 1070 * not included in @len. 1071 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 1072 * set. Includes .1p and .1q tags. 1073 * @len: Received packet length, in bytes. Excludes FCS. 1074 * @csum_calc L2 payload checksum is computed or not 1075 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 1076 * 1077 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 1078 * The TCP checksum calculated by the device 1079 * matched the checksum in the receive packet's 1080 * TCP header. 1081 * 1082 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 1083 * The TCP checksum calculated by the device did 1084 * not match the checksum in the receive packet's 1085 * TCP header. 1086 * 1087 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 1088 * The UDP checksum calculated by the device 1089 * matched the checksum in the receive packet's 1090 * UDP header 1091 * 1092 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 1093 * The UDP checksum calculated by the device did 1094 * not match the checksum in the receive packet's 1095 * UDP header. 1096 * 1097 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 1098 * The IPv4 checksum calculated by the device 1099 * matched the checksum in the receive packet's 1100 * first IPv4 header. If the receive packet 1101 * contains both a tunnel IPv4 header and a 1102 * transport IPv4 header, the device validates the 1103 * checksum for both IPv4 headers. 1104 * 1105 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 1106 * The IPv4 checksum calculated by the device did 1107 * not match the checksum in the receive packet's 1108 * first IPv4 header. If the receive packet 1109 * contains both a tunnel IPv4 header and a 1110 * transport IPv4 header, the device validates the 1111 * checksum for both IP headers. 1112 * 1113 * IONIC_RXQ_COMP_CSUM_F_VLAN: 1114 * The VLAN header was stripped and placed in @vlan_tci. 1115 * 1116 * IONIC_RXQ_COMP_CSUM_F_CALC: 1117 * The checksum was calculated by the device. 1118 * 1119 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 1120 */ 1121struct ionic_rxq_comp { 1122 u8 status; 1123 u8 num_sg_elems; 1124 __le16 comp_index; 1125 __le32 rss_hash; 1126 __le16 csum; 1127 __le16 vlan_tci; 1128 __le16 len; 1129 u8 csum_flags; 1130#define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 1131#define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 1132#define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 1133#define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 1134#define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 1135#define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 1136#define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 1137#define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 1138 u8 pkt_type_color; 1139#define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 1140}; 1141 1142enum ionic_pkt_type { 1143 IONIC_PKT_TYPE_NON_IP = 0x00, 1144 IONIC_PKT_TYPE_IPV4 = 0x01, 1145 IONIC_PKT_TYPE_IPV4_TCP = 0x03, 1146 IONIC_PKT_TYPE_IPV4_UDP = 0x05, 1147 IONIC_PKT_TYPE_IPV6 = 0x08, 1148 IONIC_PKT_TYPE_IPV6_TCP = 0x18, 1149 IONIC_PKT_TYPE_IPV6_UDP = 0x28, 1150 /* below types are only used if encap offloads are enabled on lif */ 1151 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 1152 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 1153 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 1154 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 1155 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 1156 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 1157 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1158}; 1159 1160enum ionic_eth_hw_features { 1161 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1162 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1163 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1164 IONIC_ETH_HW_RX_HASH = BIT(3), 1165 IONIC_ETH_HW_RX_CSUM = BIT(4), 1166 IONIC_ETH_HW_TX_SG = BIT(5), 1167 IONIC_ETH_HW_RX_SG = BIT(6), 1168 IONIC_ETH_HW_TX_CSUM = BIT(7), 1169 IONIC_ETH_HW_TSO = BIT(8), 1170 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1171 IONIC_ETH_HW_TSO_ECN = BIT(10), 1172 IONIC_ETH_HW_TSO_GRE = BIT(11), 1173 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1174 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1175 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1176 IONIC_ETH_HW_TSO_UDP = BIT(15), 1177 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1178 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1179 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1180 IONIC_ETH_HW_TSO_GENEVE = BIT(19), 1181 IONIC_ETH_HW_TIMESTAMP = BIT(20), 1182}; 1183 1184/** 1185 * enum ionic_pkt_class - Packet classification mask. 1186 * 1187 * Used with rx steering filter, packets indicated by the mask can be steered 1188 * toward a specific receive queue. 1189 * 1190 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. 1191 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync 1192 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request 1193 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets 1194 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync 1195 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request 1196 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets 1197 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync 1198 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request 1199 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets 1200 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync 1201 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request 1202 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets 1203 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync 1204 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request 1205 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets 1206 */ 1207enum ionic_pkt_class { 1208 IONIC_PKT_CLS_NTP_ALL = BIT(0), 1209 1210 IONIC_PKT_CLS_PTP1_SYNC = BIT(1), 1211 IONIC_PKT_CLS_PTP1_DREQ = BIT(2), 1212 IONIC_PKT_CLS_PTP1_ALL = BIT(3) | 1213 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, 1214 1215 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), 1216 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), 1217 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | 1218 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, 1219 1220 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), 1221 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), 1222 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | 1223 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, 1224 1225 IONIC_PKT_CLS_PTP2_SYNC = 1226 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, 1227 IONIC_PKT_CLS_PTP2_DREQ = 1228 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, 1229 IONIC_PKT_CLS_PTP2_ALL = 1230 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, 1231 1232 IONIC_PKT_CLS_PTP_SYNC = 1233 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, 1234 IONIC_PKT_CLS_PTP_DREQ = 1235 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, 1236 IONIC_PKT_CLS_PTP_ALL = 1237 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, 1238}; 1239 1240/** 1241 * struct ionic_q_control_cmd - Queue control command 1242 * @opcode: opcode 1243 * @type: Queue type 1244 * @lif_index: LIF index 1245 * @index: Queue index 1246 * @oper: Operation (enum ionic_q_control_oper) 1247 * @rsvd: reserved byte(s) 1248 */ 1249struct ionic_q_control_cmd { 1250 u8 opcode; 1251 u8 type; 1252 __le16 lif_index; 1253 __le32 index; 1254 u8 oper; 1255 u8 rsvd[55]; 1256}; 1257 1258typedef struct ionic_admin_comp ionic_q_control_comp; 1259 1260enum ionic_q_control_oper { 1261 IONIC_Q_DISABLE = 0, 1262 IONIC_Q_ENABLE = 1, 1263 IONIC_Q_HANG_RESET = 2, 1264}; 1265 1266/** 1267 * enum ionic_phy_type - Physical connection type 1268 * @IONIC_PHY_TYPE_NONE: No PHY installed 1269 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1270 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1271 */ 1272enum ionic_phy_type { 1273 IONIC_PHY_TYPE_NONE = 0, 1274 IONIC_PHY_TYPE_COPPER = 1, 1275 IONIC_PHY_TYPE_FIBER = 2, 1276}; 1277 1278/** 1279 * enum ionic_xcvr_state - Transceiver status 1280 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1281 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1282 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1283 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1284 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1285 */ 1286enum ionic_xcvr_state { 1287 IONIC_XCVR_STATE_REMOVED = 0, 1288 IONIC_XCVR_STATE_INSERTED = 1, 1289 IONIC_XCVR_STATE_PENDING = 2, 1290 IONIC_XCVR_STATE_SPROM_READ = 3, 1291 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1292}; 1293 1294/* 1295 * enum ionic_xcvr_pid - Supported link modes 1296 */ 1297enum ionic_xcvr_pid { 1298 IONIC_XCVR_PID_UNKNOWN = 0, 1299 1300 /* CU */ 1301 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1302 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1303 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1304 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1305 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1306 IONIC_XCVR_PID_QSFP_50G_CR2_FC = 6, 1307 IONIC_XCVR_PID_QSFP_50G_CR2 = 7, 1308 IONIC_XCVR_PID_QSFP_200G_CR4 = 8, 1309 IONIC_XCVR_PID_QSFP_400G_CR4 = 9, 1310 /* Fiber */ 1311 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1312 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1313 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1314 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1315 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1316 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1317 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1318 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1319 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1320 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1321 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1322 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1323 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1324 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1325 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1326 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1327 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1328 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1329 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1330 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1331 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1332 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1333 IONIC_XCVR_PID_SFP_10GBASE_T = 72, 1334 IONIC_XCVR_PID_SFP_1000BASE_T = 73, 1335 IONIC_XCVR_PID_QSFP_200G_AOC = 74, 1336 IONIC_XCVR_PID_QSFP_200G_FR4 = 75, 1337 IONIC_XCVR_PID_QSFP_200G_DR4 = 76, 1338 IONIC_XCVR_PID_QSFP_200G_SR4 = 77, 1339 IONIC_XCVR_PID_QSFP_200G_ACC = 78, 1340 IONIC_XCVR_PID_QSFP_400G_FR4 = 79, 1341 IONIC_XCVR_PID_QSFP_400G_DR4 = 80, 1342 IONIC_XCVR_PID_QSFP_400G_SR4 = 81, 1343 IONIC_XCVR_PID_QSFP_400G_VR4 = 82, 1344}; 1345 1346/** 1347 * enum ionic_port_type - Port types 1348 * @IONIC_PORT_TYPE_NONE: Port type not configured 1349 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1350 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1351 */ 1352enum ionic_port_type { 1353 IONIC_PORT_TYPE_NONE = 0, 1354 IONIC_PORT_TYPE_ETH = 1, 1355 IONIC_PORT_TYPE_MGMT = 2, 1356}; 1357 1358/** 1359 * enum ionic_port_admin_state - Port config state 1360 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1361 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1362 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1363 */ 1364enum ionic_port_admin_state { 1365 IONIC_PORT_ADMIN_STATE_NONE = 0, 1366 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1367 IONIC_PORT_ADMIN_STATE_UP = 2, 1368}; 1369 1370/** 1371 * enum ionic_port_oper_status - Port operational status 1372 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1373 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1374 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1375 */ 1376enum ionic_port_oper_status { 1377 IONIC_PORT_OPER_STATUS_NONE = 0, 1378 IONIC_PORT_OPER_STATUS_UP = 1, 1379 IONIC_PORT_OPER_STATUS_DOWN = 2, 1380}; 1381 1382/** 1383 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1384 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1385 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1386 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1387 */ 1388enum ionic_port_fec_type { 1389 IONIC_PORT_FEC_TYPE_NONE = 0, 1390 IONIC_PORT_FEC_TYPE_FC = 1, 1391 IONIC_PORT_FEC_TYPE_RS = 2, 1392}; 1393 1394/** 1395 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1396 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1397 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1398 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1399 */ 1400enum ionic_port_pause_type { 1401 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1402 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1403 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1404}; 1405 1406/** 1407 * enum ionic_port_loopback_mode - Loopback modes 1408 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1409 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1410 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1411 */ 1412enum ionic_port_loopback_mode { 1413 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1414 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1415 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1416}; 1417 1418/** 1419 * struct ionic_xcvr_status - Transceiver Status information 1420 * @state: Transceiver status (enum ionic_xcvr_state) 1421 * @phy: Physical connection type (enum ionic_phy_type) 1422 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1423 * @sprom: Transceiver sprom contents 1424 */ 1425struct ionic_xcvr_status { 1426 u8 state; 1427 u8 phy; 1428 __le16 pid; 1429 u8 sprom[256]; 1430}; 1431 1432/** 1433 * union ionic_port_config - Port configuration 1434 * @speed: port speed (in Mbps) 1435 * @mtu: mtu 1436 * @state: port admin state (enum ionic_port_admin_state) 1437 * @an_enable: autoneg enable 1438 * @fec_type: fec type (enum ionic_port_fec_type) 1439 * @pause_type: pause type (enum ionic_port_pause_type) 1440 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1441 * @words: word access to struct contents 1442 */ 1443union ionic_port_config { 1444 struct { 1445#define IONIC_SPEED_400G 400000 /* 400G in Mbps */ 1446#define IONIC_SPEED_200G 200000 /* 200G in Mbps */ 1447#define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1448#define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1449#define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1450#define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1451#define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1452#define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1453 __le32 speed; 1454 __le32 mtu; 1455 u8 state; 1456 u8 an_enable; 1457 u8 fec_type; 1458#define IONIC_PAUSE_TYPE_MASK 0x0f 1459#define IONIC_PAUSE_FLAGS_MASK 0xf0 1460#define IONIC_PAUSE_F_TX 0x10 1461#define IONIC_PAUSE_F_RX 0x20 1462 u8 pause_type; 1463 u8 loopback_mode; 1464 }; 1465 __le32 words[64]; 1466}; 1467 1468/** 1469 * struct ionic_port_status - Port Status information 1470 * @status: link status (enum ionic_port_oper_status) 1471 * @id: port id 1472 * @speed: link speed (in Mbps) 1473 * @link_down_count: number of times link went from up to down 1474 * @fec_type: fec type (enum ionic_port_fec_type) 1475 * @rsvd: reserved byte(s) 1476 * @xcvr: transceiver status 1477 */ 1478struct ionic_port_status { 1479 __le32 id; 1480 __le32 speed; 1481 u8 status; 1482 __le16 link_down_count; 1483 u8 fec_type; 1484 u8 rsvd[48]; 1485 struct ionic_xcvr_status xcvr; 1486} __packed; 1487 1488/** 1489 * struct ionic_port_identify_cmd - Port identify command 1490 * @opcode: opcode 1491 * @index: port index 1492 * @ver: Highest version of identify supported by driver 1493 * @rsvd: reserved byte(s) 1494 */ 1495struct ionic_port_identify_cmd { 1496 u8 opcode; 1497 u8 index; 1498 u8 ver; 1499 u8 rsvd[61]; 1500}; 1501 1502/** 1503 * struct ionic_port_identify_comp - Port identify command completion 1504 * @status: Status of the command (enum ionic_status_code) 1505 * @ver: Version of identify returned by device 1506 * @rsvd: reserved byte(s) 1507 */ 1508struct ionic_port_identify_comp { 1509 u8 status; 1510 u8 ver; 1511 u8 rsvd[14]; 1512}; 1513 1514/** 1515 * struct ionic_port_init_cmd - Port initialization command 1516 * @opcode: opcode 1517 * @index: port index 1518 * @rsvd: reserved byte(s) 1519 * @info_pa: destination address for port info (struct ionic_port_info) 1520 * @rsvd2: reserved byte(s) 1521 */ 1522struct ionic_port_init_cmd { 1523 u8 opcode; 1524 u8 index; 1525 u8 rsvd[6]; 1526 __le64 info_pa; 1527 u8 rsvd2[48]; 1528}; 1529 1530/** 1531 * struct ionic_port_init_comp - Port initialization command completion 1532 * @status: Status of the command (enum ionic_status_code) 1533 * @rsvd: reserved byte(s) 1534 */ 1535struct ionic_port_init_comp { 1536 u8 status; 1537 u8 rsvd[15]; 1538}; 1539 1540/** 1541 * struct ionic_port_reset_cmd - Port reset command 1542 * @opcode: opcode 1543 * @index: port index 1544 * @rsvd: reserved byte(s) 1545 */ 1546struct ionic_port_reset_cmd { 1547 u8 opcode; 1548 u8 index; 1549 u8 rsvd[62]; 1550}; 1551 1552/** 1553 * struct ionic_port_reset_comp - Port reset command completion 1554 * @status: Status of the command (enum ionic_status_code) 1555 * @rsvd: reserved byte(s) 1556 */ 1557struct ionic_port_reset_comp { 1558 u8 status; 1559 u8 rsvd[15]; 1560}; 1561 1562/** 1563 * enum ionic_stats_ctl_cmd - List of commands for stats control 1564 * @IONIC_STATS_CTL_RESET: Reset statistics 1565 */ 1566enum ionic_stats_ctl_cmd { 1567 IONIC_STATS_CTL_RESET = 0, 1568}; 1569 1570/** 1571 * enum ionic_txstamp_mode - List of TX Timestamping Modes 1572 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. 1573 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. 1574 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. 1575 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. 1576 */ 1577enum ionic_txstamp_mode { 1578 IONIC_TXSTAMP_OFF = 0, 1579 IONIC_TXSTAMP_ON = 1, 1580 IONIC_TXSTAMP_ONESTEP_SYNC = 2, 1581 IONIC_TXSTAMP_ONESTEP_P2P = 3, 1582}; 1583 1584/** 1585 * enum ionic_port_attr - List of device attributes 1586 * @IONIC_PORT_ATTR_STATE: Port state attribute 1587 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1588 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1589 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1590 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1591 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1592 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1593 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1594 */ 1595enum ionic_port_attr { 1596 IONIC_PORT_ATTR_STATE = 0, 1597 IONIC_PORT_ATTR_SPEED = 1, 1598 IONIC_PORT_ATTR_MTU = 2, 1599 IONIC_PORT_ATTR_AUTONEG = 3, 1600 IONIC_PORT_ATTR_FEC = 4, 1601 IONIC_PORT_ATTR_PAUSE = 5, 1602 IONIC_PORT_ATTR_LOOPBACK = 6, 1603 IONIC_PORT_ATTR_STATS_CTRL = 7, 1604}; 1605 1606/** 1607 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1608 * @opcode: Opcode 1609 * @index: Port index 1610 * @attr: Attribute type (enum ionic_port_attr) 1611 * @rsvd: reserved byte(s) 1612 * @state: Port state 1613 * @speed: Port speed 1614 * @mtu: Port MTU 1615 * @an_enable: Port autonegotiation setting 1616 * @fec_type: Port FEC type setting 1617 * @pause_type: Port pause type setting 1618 * @loopback_mode: Port loopback mode 1619 * @stats_ctl: Port stats setting 1620 * @rsvd2: reserved byte(s) 1621 */ 1622struct ionic_port_setattr_cmd { 1623 u8 opcode; 1624 u8 index; 1625 u8 attr; 1626 u8 rsvd; 1627 union { 1628 u8 state; 1629 __le32 speed; 1630 __le32 mtu; 1631 u8 an_enable; 1632 u8 fec_type; 1633 u8 pause_type; 1634 u8 loopback_mode; 1635 u8 stats_ctl; 1636 u8 rsvd2[60]; 1637 }; 1638}; 1639 1640/** 1641 * struct ionic_port_setattr_comp - Port set attr command completion 1642 * @status: Status of the command (enum ionic_status_code) 1643 * @rsvd: reserved byte(s) 1644 * @color: Color bit 1645 */ 1646struct ionic_port_setattr_comp { 1647 u8 status; 1648 u8 rsvd[14]; 1649 u8 color; 1650}; 1651 1652/** 1653 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1654 * @opcode: Opcode 1655 * @index: port index 1656 * @attr: Attribute type (enum ionic_port_attr) 1657 * @rsvd: reserved byte(s) 1658 */ 1659struct ionic_port_getattr_cmd { 1660 u8 opcode; 1661 u8 index; 1662 u8 attr; 1663 u8 rsvd[61]; 1664}; 1665 1666/** 1667 * struct ionic_port_getattr_comp - Port get attr command completion 1668 * @status: Status of the command (enum ionic_status_code) 1669 * @rsvd: reserved byte(s) 1670 * @state: Port state 1671 * @speed: Port speed 1672 * @mtu: Port MTU 1673 * @an_enable: Port autonegotiation setting 1674 * @fec_type: Port FEC type setting 1675 * @pause_type: Port pause type setting 1676 * @loopback_mode: Port loopback mode 1677 * @rsvd2: reserved byte(s) 1678 * @color: Color bit 1679 */ 1680struct ionic_port_getattr_comp { 1681 u8 status; 1682 u8 rsvd[3]; 1683 union { 1684 u8 state; 1685 __le32 speed; 1686 __le32 mtu; 1687 u8 an_enable; 1688 u8 fec_type; 1689 u8 pause_type; 1690 u8 loopback_mode; 1691 u8 rsvd2[11]; 1692 } __packed; 1693 u8 color; 1694}; 1695 1696/** 1697 * struct ionic_lif_status - LIF status register 1698 * @eid: most recent NotifyQ event id 1699 * @port_num: port the LIF is connected to 1700 * @rsvd: reserved byte(s) 1701 * @link_status: port status (enum ionic_port_oper_status) 1702 * @link_speed: speed of link in Mbps 1703 * @link_down_count: number of times link went from up to down 1704 * @rsvd2: reserved byte(s) 1705 */ 1706struct ionic_lif_status { 1707 __le64 eid; 1708 u8 port_num; 1709 u8 rsvd; 1710 __le16 link_status; 1711 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1712 __le16 link_down_count; 1713 u8 rsvd2[46]; 1714}; 1715 1716/** 1717 * struct ionic_lif_reset_cmd - LIF reset command 1718 * @opcode: opcode 1719 * @rsvd: reserved byte(s) 1720 * @index: LIF index 1721 * @rsvd2: reserved byte(s) 1722 */ 1723struct ionic_lif_reset_cmd { 1724 u8 opcode; 1725 u8 rsvd; 1726 __le16 index; 1727 __le32 rsvd2[15]; 1728}; 1729 1730typedef struct ionic_admin_comp ionic_lif_reset_comp; 1731 1732enum ionic_dev_state { 1733 IONIC_DEV_DISABLE = 0, 1734 IONIC_DEV_ENABLE = 1, 1735 IONIC_DEV_HANG_RESET = 2, 1736}; 1737 1738/** 1739 * enum ionic_dev_attr - List of device attributes 1740 * @IONIC_DEV_ATTR_STATE: Device state attribute 1741 * @IONIC_DEV_ATTR_NAME: Device name attribute 1742 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1743 */ 1744enum ionic_dev_attr { 1745 IONIC_DEV_ATTR_STATE = 0, 1746 IONIC_DEV_ATTR_NAME = 1, 1747 IONIC_DEV_ATTR_FEATURES = 2, 1748}; 1749 1750/** 1751 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1752 * @opcode: Opcode 1753 * @attr: Attribute type (enum ionic_dev_attr) 1754 * @rsvd: reserved byte(s) 1755 * @state: Device state (enum ionic_dev_state) 1756 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1757 * @features: Device features 1758 * @rsvd2: reserved byte(s) 1759 */ 1760struct ionic_dev_setattr_cmd { 1761 u8 opcode; 1762 u8 attr; 1763 __le16 rsvd; 1764 union { 1765 u8 state; 1766 char name[IONIC_IFNAMSIZ]; 1767 __le64 features; 1768 u8 rsvd2[60]; 1769 } __packed; 1770}; 1771 1772/** 1773 * struct ionic_dev_setattr_comp - Device set attr command completion 1774 * @status: Status of the command (enum ionic_status_code) 1775 * @rsvd: reserved byte(s) 1776 * @features: Device features 1777 * @rsvd2: reserved byte(s) 1778 * @color: Color bit 1779 */ 1780struct ionic_dev_setattr_comp { 1781 u8 status; 1782 u8 rsvd[3]; 1783 union { 1784 __le64 features; 1785 u8 rsvd2[11]; 1786 } __packed; 1787 u8 color; 1788}; 1789 1790/** 1791 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1792 * @opcode: opcode 1793 * @attr: Attribute type (enum ionic_dev_attr) 1794 * @rsvd: reserved byte(s) 1795 */ 1796struct ionic_dev_getattr_cmd { 1797 u8 opcode; 1798 u8 attr; 1799 u8 rsvd[62]; 1800}; 1801 1802/** 1803 * struct ionic_dev_getattr_comp - Device set attr command completion 1804 * @status: Status of the command (enum ionic_status_code) 1805 * @rsvd: reserved byte(s) 1806 * @features: Device features 1807 * @rsvd2: reserved byte(s) 1808 * @color: Color bit 1809 */ 1810struct ionic_dev_getattr_comp { 1811 u8 status; 1812 u8 rsvd[3]; 1813 union { 1814 __le64 features; 1815 u8 rsvd2[11]; 1816 } __packed; 1817 u8 color; 1818}; 1819 1820/* 1821 * RSS parameters 1822 */ 1823#define IONIC_RSS_HASH_KEY_SIZE 40 1824 1825enum ionic_rss_hash_types { 1826 IONIC_RSS_TYPE_IPV4 = BIT(0), 1827 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1828 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1829 IONIC_RSS_TYPE_IPV6 = BIT(3), 1830 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1831 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1832}; 1833 1834/** 1835 * enum ionic_lif_attr - List of LIF attributes 1836 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1837 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1838 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1839 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1840 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1841 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1842 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1843 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1844 * @IONIC_LIF_ATTR_MAX: maximum attribute value 1845 */ 1846enum ionic_lif_attr { 1847 IONIC_LIF_ATTR_STATE = 0, 1848 IONIC_LIF_ATTR_NAME = 1, 1849 IONIC_LIF_ATTR_MTU = 2, 1850 IONIC_LIF_ATTR_MAC = 3, 1851 IONIC_LIF_ATTR_FEATURES = 4, 1852 IONIC_LIF_ATTR_RSS = 5, 1853 IONIC_LIF_ATTR_STATS_CTRL = 6, 1854 IONIC_LIF_ATTR_TXSTAMP = 7, 1855 IONIC_LIF_ATTR_MAX = 255, 1856}; 1857 1858/** 1859 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1860 * @opcode: Opcode 1861 * @attr: Attribute type (enum ionic_lif_attr) 1862 * @index: LIF index 1863 * @state: LIF state (enum ionic_lif_state) 1864 * @name: The netdev name string, 0 terminated 1865 * @mtu: Mtu 1866 * @mac: Station mac 1867 * @features: Features (enum ionic_eth_hw_features) 1868 * @rss: RSS properties 1869 * @rss.types: The hash types to enable (see rss_hash_types) 1870 * @rss.key: The hash secret key 1871 * @rss.rsvd: reserved byte(s) 1872 * @rss.addr: Address for the indirection table shared memory 1873 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1874 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1875 * @rsvd: reserved byte(s) 1876 */ 1877struct ionic_lif_setattr_cmd { 1878 u8 opcode; 1879 u8 attr; 1880 __le16 index; 1881 union { 1882 u8 state; 1883 char name[IONIC_IFNAMSIZ]; 1884 __le32 mtu; 1885 u8 mac[6]; 1886 __le64 features; 1887 struct { 1888 __le16 types; 1889 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1890 u8 rsvd[6]; 1891 __le64 addr; 1892 } rss; 1893 u8 stats_ctl; 1894 __le16 txstamp_mode; 1895 u8 rsvd[60]; 1896 } __packed; 1897}; 1898 1899/** 1900 * struct ionic_lif_setattr_comp - LIF set attr command completion 1901 * @status: Status of the command (enum ionic_status_code) 1902 * @rsvd: reserved byte(s) 1903 * @comp_index: Index in the descriptor ring for which this is the completion 1904 * @features: features (enum ionic_eth_hw_features) 1905 * @rsvd2: reserved byte(s) 1906 * @color: Color bit 1907 */ 1908struct ionic_lif_setattr_comp { 1909 u8 status; 1910 u8 rsvd; 1911 __le16 comp_index; 1912 union { 1913 __le64 features; 1914 u8 rsvd2[11]; 1915 } __packed; 1916 u8 color; 1917}; 1918 1919/** 1920 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1921 * @opcode: Opcode 1922 * @attr: Attribute type (enum ionic_lif_attr) 1923 * @index: LIF index 1924 * @rsvd: reserved byte(s) 1925 */ 1926struct ionic_lif_getattr_cmd { 1927 u8 opcode; 1928 u8 attr; 1929 __le16 index; 1930 u8 rsvd[60]; 1931}; 1932 1933/** 1934 * struct ionic_lif_getattr_comp - LIF get attr command completion 1935 * @status: Status of the command (enum ionic_status_code) 1936 * @rsvd: reserved byte(s) 1937 * @comp_index: Index in the descriptor ring for which this is the completion 1938 * @state: LIF state (enum ionic_lif_state) 1939 * @mtu: Mtu 1940 * @mac: Station mac 1941 * @features: Features (enum ionic_eth_hw_features) 1942 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1943 * @rsvd2: reserved byte(s) 1944 * @color: Color bit 1945 */ 1946struct ionic_lif_getattr_comp { 1947 u8 status; 1948 u8 rsvd; 1949 __le16 comp_index; 1950 union { 1951 u8 state; 1952 __le32 mtu; 1953 u8 mac[6]; 1954 __le64 features; 1955 __le16 txstamp_mode; 1956 u8 rsvd2[11]; 1957 } __packed; 1958 u8 color; 1959}; 1960 1961/** 1962 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 1963 * @opcode: Opcode 1964 * @rsvd1: reserved byte(s) 1965 * @lif_index: LIF index 1966 * @rsvd2: reserved byte(s) 1967 * @tick: Hardware stamp tick of an instant in time. 1968 * @nsec: Nanosecond stamp of the same instant. 1969 * @frac: Fractional nanoseconds at the same instant. 1970 * @mult: Cycle to nanosecond multiplier. 1971 * @shift: Cycle to nanosecond divisor (power of two). 1972 * @rsvd3: reserved byte(s) 1973 */ 1974struct ionic_lif_setphc_cmd { 1975 u8 opcode; 1976 u8 rsvd1; 1977 __le16 lif_index; 1978 u8 rsvd2[4]; 1979 __le64 tick; 1980 __le64 nsec; 1981 __le64 frac; 1982 __le32 mult; 1983 __le32 shift; 1984 u8 rsvd3[24]; 1985}; 1986 1987enum ionic_rx_mode { 1988 IONIC_RX_MODE_F_UNICAST = BIT(0), 1989 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1990 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1991 IONIC_RX_MODE_F_PROMISC = BIT(3), 1992 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1993 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1994}; 1995 1996/** 1997 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1998 * @opcode: opcode 1999 * @rsvd: reserved byte(s) 2000 * @lif_index: LIF index 2001 * @rx_mode: Rx mode flags: 2002 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 2003 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 2004 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 2005 * IONIC_RX_MODE_F_PROMISC: Accept any packets 2006 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 2007 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 2008 * @rsvd2: reserved byte(s) 2009 */ 2010struct ionic_rx_mode_set_cmd { 2011 u8 opcode; 2012 u8 rsvd; 2013 __le16 lif_index; 2014 __le16 rx_mode; 2015 __le16 rsvd2[29]; 2016}; 2017 2018typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 2019 2020enum ionic_rx_filter_match_type { 2021 IONIC_RX_FILTER_MATCH_VLAN = 0x0, 2022 IONIC_RX_FILTER_MATCH_MAC = 0x1, 2023 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, 2024 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, 2025}; 2026 2027/** 2028 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 2029 * @opcode: opcode 2030 * @qtype: Queue type 2031 * @lif_index: LIF index 2032 * @qid: Queue ID 2033 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 2034 * @vlan: VLAN filter 2035 * @vlan.vlan: VLAN ID 2036 * @mac: MAC filter 2037 * @mac.addr: MAC address (network-byte order) 2038 * @mac_vlan: MACVLAN filter 2039 * @mac_vlan.vlan: VLAN ID 2040 * @mac_vlan.addr: MAC address (network-byte order) 2041 * @pkt_class: Packet classification filter 2042 * @rsvd: reserved byte(s) 2043 */ 2044struct ionic_rx_filter_add_cmd { 2045 u8 opcode; 2046 u8 qtype; 2047 __le16 lif_index; 2048 __le32 qid; 2049 __le16 match; 2050 union { 2051 struct { 2052 __le16 vlan; 2053 } vlan; 2054 struct { 2055 u8 addr[6]; 2056 } mac; 2057 struct { 2058 __le16 vlan; 2059 u8 addr[6]; 2060 } mac_vlan; 2061 __le64 pkt_class; 2062 u8 rsvd[54]; 2063 } __packed; 2064}; 2065 2066/** 2067 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 2068 * @status: Status of the command (enum ionic_status_code) 2069 * @rsvd: reserved byte(s) 2070 * @comp_index: Index in the descriptor ring for which this is the completion 2071 * @filter_id: Filter ID 2072 * @rsvd2: reserved byte(s) 2073 * @color: Color bit 2074 */ 2075struct ionic_rx_filter_add_comp { 2076 u8 status; 2077 u8 rsvd; 2078 __le16 comp_index; 2079 __le32 filter_id; 2080 u8 rsvd2[7]; 2081 u8 color; 2082}; 2083 2084/** 2085 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 2086 * @opcode: opcode 2087 * @rsvd: reserved byte(s) 2088 * @lif_index: LIF index 2089 * @filter_id: Filter ID 2090 * @rsvd2: reserved byte(s) 2091 */ 2092struct ionic_rx_filter_del_cmd { 2093 u8 opcode; 2094 u8 rsvd; 2095 __le16 lif_index; 2096 __le32 filter_id; 2097 u8 rsvd2[56]; 2098}; 2099 2100typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 2101 2102enum ionic_vf_attr { 2103 IONIC_VF_ATTR_SPOOFCHK = 1, 2104 IONIC_VF_ATTR_TRUST = 2, 2105 IONIC_VF_ATTR_MAC = 3, 2106 IONIC_VF_ATTR_LINKSTATE = 4, 2107 IONIC_VF_ATTR_VLAN = 5, 2108 IONIC_VF_ATTR_RATE = 6, 2109 IONIC_VF_ATTR_STATSADDR = 7, 2110}; 2111 2112/** 2113 * enum ionic_vf_link_status - Virtual Function link status 2114 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 2115 * @IONIC_VF_LINK_STATUS_UP: Link always up 2116 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 2117 */ 2118enum ionic_vf_link_status { 2119 IONIC_VF_LINK_STATUS_AUTO = 0, 2120 IONIC_VF_LINK_STATUS_UP = 1, 2121 IONIC_VF_LINK_STATUS_DOWN = 2, 2122}; 2123 2124/** 2125 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 2126 * @opcode: Opcode 2127 * @attr: Attribute type (enum ionic_vf_attr) 2128 * @vf_index: VF index 2129 * @macaddr: mac address 2130 * @vlanid: vlan ID 2131 * @maxrate: max Tx rate in Mbps 2132 * @spoofchk: enable address spoof checking 2133 * @trust: enable VF trust 2134 * @linkstate: set link up or down 2135 * @stats_pa: set DMA address for VF stats 2136 * @pad: reserved byte(s) 2137 */ 2138struct ionic_vf_setattr_cmd { 2139 u8 opcode; 2140 u8 attr; 2141 __le16 vf_index; 2142 union { 2143 u8 macaddr[6]; 2144 __le16 vlanid; 2145 __le32 maxrate; 2146 u8 spoofchk; 2147 u8 trust; 2148 u8 linkstate; 2149 __le64 stats_pa; 2150 u8 pad[60]; 2151 } __packed; 2152}; 2153 2154struct ionic_vf_setattr_comp { 2155 u8 status; 2156 u8 attr; 2157 __le16 vf_index; 2158 __le16 comp_index; 2159 u8 rsvd[9]; 2160 u8 color; 2161}; 2162 2163/** 2164 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 2165 * @opcode: Opcode 2166 * @attr: Attribute type (enum ionic_vf_attr) 2167 * @vf_index: VF index 2168 * @rsvd: reserved byte(s) 2169 */ 2170struct ionic_vf_getattr_cmd { 2171 u8 opcode; 2172 u8 attr; 2173 __le16 vf_index; 2174 u8 rsvd[60]; 2175}; 2176 2177struct ionic_vf_getattr_comp { 2178 u8 status; 2179 u8 attr; 2180 __le16 vf_index; 2181 union { 2182 u8 macaddr[6]; 2183 __le16 vlanid; 2184 __le32 maxrate; 2185 u8 spoofchk; 2186 u8 trust; 2187 u8 linkstate; 2188 __le64 stats_pa; 2189 u8 pad[11]; 2190 } __packed; 2191 u8 color; 2192}; 2193 2194enum ionic_vf_ctrl_opcode { 2195 IONIC_VF_CTRL_START_ALL = 0, 2196 IONIC_VF_CTRL_START = 1, 2197}; 2198 2199/** 2200 * struct ionic_vf_ctrl_cmd - VF control command 2201 * @opcode: Opcode for the command 2202 * @ctrl_opcode: VF control operation type 2203 * @vf_index: VF Index. It is unused if op START_ALL is used. 2204 */ 2205struct ionic_vf_ctrl_cmd { 2206 u8 opcode; 2207 u8 ctrl_opcode; 2208 __le16 vf_index; 2209 /* private: */ 2210 u8 rsvd1[60]; 2211}; 2212 2213/** 2214 * struct ionic_vf_ctrl_comp - VF_CTRL command completion. 2215 * @status: Status of the command (enum ionic_status_code) 2216 */ 2217struct ionic_vf_ctrl_comp { 2218 u8 status; 2219 /* private: */ 2220 u8 rsvd[15]; 2221}; 2222 2223/** 2224 * struct ionic_discover_cmb_cmd - CMB discovery command 2225 * @opcode: Opcode for the command 2226 * @rsvd: Reserved bytes 2227 */ 2228struct ionic_discover_cmb_cmd { 2229 u8 opcode; 2230 u8 rsvd[63]; 2231}; 2232 2233/** 2234 * struct ionic_discover_cmb_comp - CMB discover command completion. 2235 * @status: Status of the command (enum ionic_status_code) 2236 * @rsvd: Reserved bytes 2237 */ 2238struct ionic_discover_cmb_comp { 2239 u8 status; 2240 u8 rsvd[15]; 2241}; 2242 2243#define IONIC_MAX_CMB_REGIONS 16 2244#define IONIC_CMB_SHIFT_64K 16 2245 2246enum ionic_cmb_type { 2247 IONIC_CMB_TYPE_DEVMEM = 0, 2248 IONIC_CMB_TYPE_EXPDB64 = 1, 2249 IONIC_CMB_TYPE_EXPDB128 = 2, 2250 IONIC_CMB_TYPE_EXPDB256 = 3, 2251 IONIC_CMB_TYPE_EXPDB512 = 4, 2252}; 2253 2254/** 2255 * union ionic_cmb_region - Configuration for CMB region 2256 * @bar_num: CMB mapping number from FW 2257 * @cmb_type: Type of CMB this region describes (enum ionic_cmb_type) 2258 * @rsvd: Reserved 2259 * @offset: Offset within BAR in 64KB pages 2260 * @length: Length of the CMB region 2261 * @words: 32-bit words for direct access to the entire region 2262 */ 2263union ionic_cmb_region { 2264 struct { 2265 u8 bar_num; 2266 u8 cmb_type; 2267 u8 rsvd[6]; 2268 __le32 offset; 2269 __le32 length; 2270 } __packed; 2271 __le32 words[4]; 2272}; 2273 2274/** 2275 * union ionic_discover_cmb_identity - CMB layout identity structure 2276 * @num_regions: Number of CMB regions, up to 16 2277 * @flags: Feature and capability bits (0 for express 2278 * doorbell, 1 for 4K alignment indicator, 2279 * 31-24 for version information) 2280 * @region: CMB mappings region, entry 0 for regular 2281 * mapping, entries 1-7 for WQE sizes 64, 2282 * 128, 256, 512, 1024, 2048 and 4096 bytes 2283 * @words: Full union buffer size 2284 */ 2285union ionic_discover_cmb_identity { 2286 struct { 2287 __le32 num_regions; 2288#define IONIC_CMB_FLAG_EXPDB BIT(0) 2289#define IONIC_CMB_FLAG_4KALIGN BIT(1) 2290#define IONIC_CMB_FLAG_VERSION 0xff000000 2291 __le32 flags; 2292 union ionic_cmb_region region[IONIC_MAX_CMB_REGIONS]; 2293 }; 2294 __le32 words[478]; 2295}; 2296 2297/** 2298 * struct ionic_qos_identify_cmd - QoS identify command 2299 * @opcode: opcode 2300 * @ver: Highest version of identify supported by driver 2301 * @rsvd: reserved byte(s) 2302 */ 2303struct ionic_qos_identify_cmd { 2304 u8 opcode; 2305 u8 ver; 2306 u8 rsvd[62]; 2307}; 2308 2309/** 2310 * struct ionic_qos_identify_comp - QoS identify command completion 2311 * @status: Status of the command (enum ionic_status_code) 2312 * @ver: Version of identify returned by device 2313 * @rsvd: reserved byte(s) 2314 */ 2315struct ionic_qos_identify_comp { 2316 u8 status; 2317 u8 ver; 2318 u8 rsvd[14]; 2319}; 2320 2321#define IONIC_QOS_TC_MAX 8 2322#define IONIC_QOS_ALL_TC 0xFF 2323/* Capri max supported, should be renamed. */ 2324#define IONIC_QOS_CLASS_MAX 7 2325#define IONIC_QOS_PCP_MAX 8 2326#define IONIC_QOS_CLASS_NAME_SZ 32 2327#define IONIC_QOS_DSCP_MAX 64 2328#define IONIC_QOS_ALL_PCP 0xFF 2329#define IONIC_DSCP_BLOCK_SIZE 8 2330 2331/* 2332 * enum ionic_qos_class 2333 */ 2334enum ionic_qos_class { 2335 IONIC_QOS_CLASS_DEFAULT = 0, 2336 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 2337 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 2338 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 2339 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 2340 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 2341 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 2342}; 2343 2344/** 2345 * enum ionic_qos_class_type - Traffic classification criteria 2346 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 2347 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 2348 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 2349 */ 2350enum ionic_qos_class_type { 2351 IONIC_QOS_CLASS_TYPE_NONE = 0, 2352 IONIC_QOS_CLASS_TYPE_PCP = 1, 2353 IONIC_QOS_CLASS_TYPE_DSCP = 2, 2354}; 2355 2356/** 2357 * enum ionic_qos_sched_type - QoS class scheduling type 2358 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 2359 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 2360 */ 2361enum ionic_qos_sched_type { 2362 IONIC_QOS_SCHED_TYPE_STRICT = 0, 2363 IONIC_QOS_SCHED_TYPE_DWRR = 1, 2364}; 2365 2366/** 2367 * union ionic_qos_config - QoS configuration structure 2368 * @flags: Configuration flags 2369 * IONIC_QOS_CONFIG_F_ENABLE enable 2370 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 2371 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 2372 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 2373 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 2374 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 2375 * @class_type: QoS class type (enum ionic_qos_class_type) 2376 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 2377 * @name: QoS class name 2378 * @mtu: MTU of the class 2379 * @pfc_cos: Priority-Flow Control class of service 2380 * @dwrr_weight: QoS class scheduling weight 2381 * @strict_rlmt: Rate limit for strict priority scheduling 2382 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 2383 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 2384 * @dot1q_pcp: Dot1q pcp value 2385 * @ndscp: Number of valid dscp values in the ip_dscp field 2386 * @ip_dscp: IP dscp values 2387 * @words: word access to struct contents 2388 */ 2389union ionic_qos_config { 2390 struct { 2391#define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 2392#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 2393/* Used to rewrite PCP or DSCP value. */ 2394#define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 2395#define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 2396/* Non-disruptive TC update */ 2397#define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 2398 u8 flags; 2399 u8 sched_type; 2400 u8 class_type; 2401 u8 pause_type; 2402 char name[IONIC_QOS_CLASS_NAME_SZ]; 2403 __le32 mtu; 2404 /* flow control */ 2405 u8 pfc_cos; 2406 /* scheduler */ 2407 union { 2408 u8 dwrr_weight; 2409 __le64 strict_rlmt; 2410 }; 2411 /* marking */ 2412 /* Used to rewrite PCP or DSCP value. */ 2413 union { 2414 u8 rw_dot1q_pcp; 2415 u8 rw_ip_dscp; 2416 }; 2417 /* classification */ 2418 union { 2419 u8 dot1q_pcp; 2420 struct { 2421 u8 ndscp; 2422 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 2423 }; 2424 }; 2425 }; 2426 __le32 words[64]; 2427}; 2428 2429/** 2430 * union ionic_qos_identity - QoS identity structure 2431 * @version: Version of the identify structure 2432 * @type: QoS system type 2433 * @rsvd: reserved byte(s) 2434 * @config: Current configuration of classes 2435 * @words: word access to struct contents 2436 */ 2437union ionic_qos_identity { 2438 struct { 2439 u8 version; 2440 u8 type; 2441 u8 rsvd[62]; 2442 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2443 }; 2444 __le32 words[478]; 2445}; 2446 2447/** 2448 * struct ionic_qos_init_cmd - QoS config init command 2449 * @opcode: Opcode 2450 * @group: QoS class id 2451 * @rsvd: reserved byte(s) 2452 * @info_pa: destination address for qos info 2453 * @rsvd1: reserved byte(s) 2454 */ 2455struct ionic_qos_init_cmd { 2456 u8 opcode; 2457 u8 group; 2458 u8 rsvd[6]; 2459 __le64 info_pa; 2460 u8 rsvd1[48]; 2461}; 2462 2463typedef struct ionic_admin_comp ionic_qos_init_comp; 2464 2465/** 2466 * struct ionic_qos_reset_cmd - QoS config reset command 2467 * @opcode: Opcode 2468 * @group: QoS class id 2469 * @rsvd: reserved byte(s) 2470 */ 2471struct ionic_qos_reset_cmd { 2472 u8 opcode; 2473 u8 group; 2474 u8 rsvd[62]; 2475}; 2476 2477/** 2478 * struct ionic_qos_clear_stats_cmd - Qos config reset command 2479 * @opcode: Opcode 2480 * @group_bitmap: bitmap of groups to be cleared 2481 * @rsvd: reserved byte(s) 2482 */ 2483struct ionic_qos_clear_stats_cmd { 2484 u8 opcode; 2485 u8 group_bitmap; 2486 u8 rsvd[62]; 2487}; 2488 2489typedef struct ionic_admin_comp ionic_qos_reset_comp; 2490 2491/** 2492 * struct ionic_fw_download_cmd - Firmware download command 2493 * @opcode: opcode 2494 * @rsvd: reserved byte(s) 2495 * @addr: dma address of the firmware buffer 2496 * @offset: offset of the firmware buffer within the full image 2497 * @length: number of valid bytes in the firmware buffer 2498 */ 2499struct ionic_fw_download_cmd { 2500 u8 opcode; 2501 u8 rsvd[3]; 2502 __le32 offset; 2503 __le64 addr; 2504 __le32 length; 2505}; 2506 2507typedef struct ionic_admin_comp ionic_fw_download_comp; 2508 2509/** 2510 * enum ionic_fw_control_oper - FW control operations 2511 * @IONIC_FW_RESET: Reset firmware 2512 * @IONIC_FW_INSTALL: Install firmware 2513 * @IONIC_FW_ACTIVATE: Activate firmware 2514 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 2515 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2516 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2517 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2518 * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update 2519 */ 2520enum ionic_fw_control_oper { 2521 IONIC_FW_RESET = 0, 2522 IONIC_FW_INSTALL = 1, 2523 IONIC_FW_ACTIVATE = 2, 2524 IONIC_FW_INSTALL_ASYNC = 3, 2525 IONIC_FW_INSTALL_STATUS = 4, 2526 IONIC_FW_ACTIVATE_ASYNC = 5, 2527 IONIC_FW_ACTIVATE_STATUS = 6, 2528 IONIC_FW_UPDATE_CLEANUP = 7, 2529}; 2530 2531/** 2532 * struct ionic_fw_control_cmd - Firmware control command 2533 * @opcode: opcode 2534 * @rsvd: reserved byte(s) 2535 * @oper: firmware control operation (enum ionic_fw_control_oper) 2536 * @slot: slot to activate 2537 * @rsvd1: reserved byte(s) 2538 */ 2539struct ionic_fw_control_cmd { 2540 u8 opcode; 2541 u8 rsvd[3]; 2542 u8 oper; 2543 u8 slot; 2544 u8 rsvd1[58]; 2545}; 2546 2547/** 2548 * struct ionic_fw_control_comp - Firmware control copletion 2549 * @status: Status of the command (enum ionic_status_code) 2550 * @rsvd: reserved byte(s) 2551 * @comp_index: Index in the descriptor ring for which this is the completion 2552 * @slot: Slot where the firmware was installed 2553 * @rsvd1: reserved byte(s) 2554 * @color: Color bit 2555 */ 2556struct ionic_fw_control_comp { 2557 u8 status; 2558 u8 rsvd; 2559 __le16 comp_index; 2560 u8 slot; 2561 u8 rsvd1[10]; 2562 u8 color; 2563}; 2564 2565/****************************************************************** 2566 ******************* RDMA Commands ******************************** 2567 ******************************************************************/ 2568 2569/** 2570 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2571 * @opcode: opcode 2572 * @rsvd: reserved byte(s) 2573 * @lif_index: LIF index 2574 * @rsvd2: reserved byte(s) 2575 * 2576 * There is no RDMA specific dev command completion struct. Completion uses 2577 * the common struct ionic_admin_comp. Only the status is indicated. 2578 * Nonzero status means the LIF does not support RDMA. 2579 **/ 2580struct ionic_rdma_reset_cmd { 2581 u8 opcode; 2582 u8 rsvd; 2583 __le16 lif_index; 2584 u8 rsvd2[60]; 2585}; 2586 2587/** 2588 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2589 * @opcode: opcode, 52, 53 2590 * @rsvd: reserved byte(s) 2591 * @lif_index: LIF index 2592 * @qid_ver: (qid | (RDMA version << 24)) 2593 * @cid: intr, eq_id, or cq_id 2594 * @dbid: doorbell page id 2595 * @depth_log2: log base two of queue depth 2596 * @stride_log2: log base two of queue stride 2597 * @dma_addr: address of the queue memory 2598 * @rsvd2: reserved byte(s) 2599 * 2600 * The same command struct is used to create an RDMA event queue, completion 2601 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2602 * queue, an event queue id for a completion queue, or a completion queue id 2603 * for an RDMA admin queue. 2604 * 2605 * The queue created via a dev command must be contiguous in dma space. 2606 * 2607 * The dev commands are intended only to be used during driver initialization, 2608 * to create queues supporting the RDMA admin queue. Other queues, and other 2609 * types of RDMA resources like memory regions, will be created and registered 2610 * via the RDMA admin queue, and will support a more complete interface 2611 * providing scatter gather lists for larger, scattered queue buffers and 2612 * memory registration. 2613 * 2614 * There is no RDMA specific dev command completion struct. Completion uses 2615 * the common struct ionic_admin_comp. Only the status is indicated. 2616 **/ 2617struct ionic_rdma_queue_cmd { 2618 u8 opcode; 2619 u8 rsvd; 2620 __le16 lif_index; 2621 __le32 qid_ver; 2622 __le32 cid; 2623 __le16 dbid; 2624 u8 depth_log2; 2625 u8 stride_log2; 2626 __le64 dma_addr; 2627 u8 rsvd2[40]; 2628}; 2629 2630/****************************************************************** 2631 ******************* Notify Events ******************************** 2632 ******************************************************************/ 2633 2634/** 2635 * struct ionic_notifyq_event - Generic event reporting structure 2636 * @eid: event number 2637 * @ecode: event code 2638 * @data: unspecified data about the event 2639 * 2640 * This is the generic event report struct from which the other 2641 * actual events will be formed. 2642 */ 2643struct ionic_notifyq_event { 2644 __le64 eid; 2645 __le16 ecode; 2646 u8 data[54]; 2647}; 2648 2649/** 2650 * struct ionic_link_change_event - Link change event notification 2651 * @eid: event number 2652 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2653 * @link_status: link up/down, with error bits (enum ionic_port_status) 2654 * @link_speed: speed of the network link 2655 * @rsvd: reserved byte(s) 2656 * 2657 * Sent when the network link state changes between UP and DOWN 2658 */ 2659struct ionic_link_change_event { 2660 __le64 eid; 2661 __le16 ecode; 2662 __le16 link_status; 2663 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2664 u8 rsvd[48]; 2665}; 2666 2667/** 2668 * struct ionic_reset_event - Reset event notification 2669 * @eid: event number 2670 * @ecode: event code = IONIC_EVENT_RESET 2671 * @reset_code: reset type 2672 * @state: 0=pending, 1=complete, 2=error 2673 * @rsvd: reserved byte(s) 2674 * 2675 * Sent when the NIC or some subsystem is going to be or 2676 * has been reset. 2677 */ 2678struct ionic_reset_event { 2679 __le64 eid; 2680 __le16 ecode; 2681 u8 reset_code; 2682 u8 state; 2683 u8 rsvd[52]; 2684}; 2685 2686/** 2687 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2688 * @eid: event number 2689 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2690 * @rsvd: reserved byte(s) 2691 */ 2692struct ionic_heartbeat_event { 2693 __le64 eid; 2694 __le16 ecode; 2695 u8 rsvd[54]; 2696}; 2697 2698/** 2699 * struct ionic_log_event - Sent to notify the driver of an internal error 2700 * @eid: event number 2701 * @ecode: event code = IONIC_EVENT_LOG 2702 * @data: log data 2703 */ 2704struct ionic_log_event { 2705 __le64 eid; 2706 __le16 ecode; 2707 u8 data[54]; 2708}; 2709 2710/** 2711 * struct ionic_xcvr_event - Transceiver change event 2712 * @eid: event number 2713 * @ecode: event code = IONIC_EVENT_XCVR 2714 * @rsvd: reserved byte(s) 2715 */ 2716struct ionic_xcvr_event { 2717 __le64 eid; 2718 __le16 ecode; 2719 u8 rsvd[54]; 2720}; 2721 2722/* 2723 * struct ionic_port_stats - Port statistics structure 2724 */ 2725struct ionic_port_stats { 2726 __le64 frames_rx_ok; 2727 __le64 frames_rx_all; 2728 __le64 frames_rx_bad_fcs; 2729 __le64 frames_rx_bad_all; 2730 __le64 octets_rx_ok; 2731 __le64 octets_rx_all; 2732 __le64 frames_rx_unicast; 2733 __le64 frames_rx_multicast; 2734 __le64 frames_rx_broadcast; 2735 __le64 frames_rx_pause; 2736 __le64 frames_rx_bad_length; 2737 __le64 frames_rx_undersized; 2738 __le64 frames_rx_oversized; 2739 __le64 frames_rx_fragments; 2740 __le64 frames_rx_jabber; 2741 __le64 frames_rx_pripause; 2742 __le64 frames_rx_stomped_crc; 2743 __le64 frames_rx_too_long; 2744 __le64 frames_rx_vlan_good; 2745 __le64 frames_rx_dropped; 2746 __le64 frames_rx_less_than_64b; 2747 __le64 frames_rx_64b; 2748 __le64 frames_rx_65b_127b; 2749 __le64 frames_rx_128b_255b; 2750 __le64 frames_rx_256b_511b; 2751 __le64 frames_rx_512b_1023b; 2752 __le64 frames_rx_1024b_1518b; 2753 __le64 frames_rx_1519b_2047b; 2754 __le64 frames_rx_2048b_4095b; 2755 __le64 frames_rx_4096b_8191b; 2756 __le64 frames_rx_8192b_9215b; 2757 __le64 frames_rx_other; 2758 __le64 frames_tx_ok; 2759 __le64 frames_tx_all; 2760 __le64 frames_tx_bad; 2761 __le64 octets_tx_ok; 2762 __le64 octets_tx_total; 2763 __le64 frames_tx_unicast; 2764 __le64 frames_tx_multicast; 2765 __le64 frames_tx_broadcast; 2766 __le64 frames_tx_pause; 2767 __le64 frames_tx_pripause; 2768 __le64 frames_tx_vlan; 2769 __le64 frames_tx_less_than_64b; 2770 __le64 frames_tx_64b; 2771 __le64 frames_tx_65b_127b; 2772 __le64 frames_tx_128b_255b; 2773 __le64 frames_tx_256b_511b; 2774 __le64 frames_tx_512b_1023b; 2775 __le64 frames_tx_1024b_1518b; 2776 __le64 frames_tx_1519b_2047b; 2777 __le64 frames_tx_2048b_4095b; 2778 __le64 frames_tx_4096b_8191b; 2779 __le64 frames_tx_8192b_9215b; 2780 __le64 frames_tx_other; 2781 __le64 frames_tx_pri_0; 2782 __le64 frames_tx_pri_1; 2783 __le64 frames_tx_pri_2; 2784 __le64 frames_tx_pri_3; 2785 __le64 frames_tx_pri_4; 2786 __le64 frames_tx_pri_5; 2787 __le64 frames_tx_pri_6; 2788 __le64 frames_tx_pri_7; 2789 __le64 frames_rx_pri_0; 2790 __le64 frames_rx_pri_1; 2791 __le64 frames_rx_pri_2; 2792 __le64 frames_rx_pri_3; 2793 __le64 frames_rx_pri_4; 2794 __le64 frames_rx_pri_5; 2795 __le64 frames_rx_pri_6; 2796 __le64 frames_rx_pri_7; 2797 __le64 tx_pripause_0_1us_count; 2798 __le64 tx_pripause_1_1us_count; 2799 __le64 tx_pripause_2_1us_count; 2800 __le64 tx_pripause_3_1us_count; 2801 __le64 tx_pripause_4_1us_count; 2802 __le64 tx_pripause_5_1us_count; 2803 __le64 tx_pripause_6_1us_count; 2804 __le64 tx_pripause_7_1us_count; 2805 __le64 rx_pripause_0_1us_count; 2806 __le64 rx_pripause_1_1us_count; 2807 __le64 rx_pripause_2_1us_count; 2808 __le64 rx_pripause_3_1us_count; 2809 __le64 rx_pripause_4_1us_count; 2810 __le64 rx_pripause_5_1us_count; 2811 __le64 rx_pripause_6_1us_count; 2812 __le64 rx_pripause_7_1us_count; 2813 __le64 rx_pause_1us_count; 2814 __le64 frames_tx_truncated; 2815}; 2816 2817struct ionic_mgmt_port_stats { 2818 __le64 frames_rx_ok; 2819 __le64 frames_rx_all; 2820 __le64 frames_rx_bad_fcs; 2821 __le64 frames_rx_bad_all; 2822 __le64 octets_rx_ok; 2823 __le64 octets_rx_all; 2824 __le64 frames_rx_unicast; 2825 __le64 frames_rx_multicast; 2826 __le64 frames_rx_broadcast; 2827 __le64 frames_rx_pause; 2828 __le64 frames_rx_bad_length; 2829 __le64 frames_rx_undersized; 2830 __le64 frames_rx_oversized; 2831 __le64 frames_rx_fragments; 2832 __le64 frames_rx_jabber; 2833 __le64 frames_rx_64b; 2834 __le64 frames_rx_65b_127b; 2835 __le64 frames_rx_128b_255b; 2836 __le64 frames_rx_256b_511b; 2837 __le64 frames_rx_512b_1023b; 2838 __le64 frames_rx_1024b_1518b; 2839 __le64 frames_rx_gt_1518b; 2840 __le64 frames_rx_fifo_full; 2841 __le64 frames_tx_ok; 2842 __le64 frames_tx_all; 2843 __le64 frames_tx_bad; 2844 __le64 octets_tx_ok; 2845 __le64 octets_tx_total; 2846 __le64 frames_tx_unicast; 2847 __le64 frames_tx_multicast; 2848 __le64 frames_tx_broadcast; 2849 __le64 frames_tx_pause; 2850}; 2851 2852enum ionic_pb_buffer_drop_stats { 2853 IONIC_BUFFER_INTRINSIC_DROP = 0, 2854 IONIC_BUFFER_DISCARDED, 2855 IONIC_BUFFER_ADMITTED, 2856 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2857 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2858 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2859 IONIC_BUFFER_TRUNCATION_DROP, 2860 IONIC_BUFFER_PORT_DISABLED_DROP, 2861 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2862 IONIC_BUFFER_SPAN_TAIL_DROP, 2863 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2864 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2865 IONIC_BUFFER_INVALID_PORT_DROP, 2866 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2867 IONIC_BUFFER_DROP_MAX, 2868}; 2869 2870enum ionic_oflow_drop_stats { 2871 IONIC_OFLOW_OCCUPANCY_DROP, 2872 IONIC_OFLOW_EMERGENCY_STOP_DROP, 2873 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 2874 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 2875 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 2876 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 2877 IONIC_OFLOW_DROP_MAX, 2878}; 2879 2880/* struct ionic_port_pb_stats - packet buffers system stats 2881 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2882 */ 2883struct ionic_port_pb_stats { 2884 __le64 sop_count_in; 2885 __le64 eop_count_in; 2886 __le64 sop_count_out; 2887 __le64 eop_count_out; 2888 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2889 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2890 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2891 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2892 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 2893 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 2894 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 2895 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 2896 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 2897 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 2898 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 2899 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2900}; 2901 2902/** 2903 * struct ionic_port_identity - port identity structure 2904 * @version: identity structure version 2905 * @type: type of port (enum ionic_port_type) 2906 * @num_lanes: number of lanes for the port 2907 * @autoneg: autoneg supported 2908 * @min_frame_size: minimum frame size supported 2909 * @max_frame_size: maximum frame size supported 2910 * @fec_type: supported fec types 2911 * @pause_type: supported pause types 2912 * @loopback_mode: supported loopback mode 2913 * @speeds: supported speeds 2914 * @rsvd2: reserved byte(s) 2915 * @config: current port configuration 2916 * @words: word access to struct contents 2917 */ 2918union ionic_port_identity { 2919 struct { 2920 u8 version; 2921 u8 type; 2922 u8 num_lanes; 2923 u8 autoneg; 2924 __le32 min_frame_size; 2925 __le32 max_frame_size; 2926 u8 fec_type[4]; 2927 u8 pause_type[2]; 2928 u8 loopback_mode[2]; 2929 __le32 speeds[16]; 2930 u8 rsvd2[44]; 2931 union ionic_port_config config; 2932 }; 2933 __le32 words[478]; 2934}; 2935 2936/** 2937 * struct ionic_port_info - port info structure 2938 * @config: Port configuration data 2939 * @status: Port status data 2940 * @stats: Port statistics data 2941 * @mgmt_stats: Port management statistics data 2942 * @sprom_epage: Extended Transceiver sprom 2943 * @sprom_page1: Extended Transceiver sprom, page 1 2944 * @sprom_page2: Extended Transceiver sprom, page 2 2945 * @sprom_page17: Extended Transceiver sprom, page 17 2946 * @rsvd: reserved byte(s) 2947 * @pb_stats: uplink pb drop stats 2948 */ 2949struct ionic_port_info { 2950 union ionic_port_config config; 2951 struct ionic_port_status status; 2952 union { 2953 struct ionic_port_stats stats; 2954 struct ionic_mgmt_port_stats mgmt_stats; 2955 }; 2956 union { 2957 u8 sprom_epage[384]; 2958 struct { 2959 u8 sprom_page1[128]; 2960 u8 sprom_page2[128]; 2961 u8 sprom_page17[128]; 2962 }; 2963 }; 2964 u8 rsvd[376]; 2965 2966 /* pb_stats must start at 2k offset */ 2967 struct ionic_port_pb_stats pb_stats; 2968}; 2969 2970/* 2971 * struct ionic_lif_stats - LIF statistics structure 2972 */ 2973struct ionic_lif_stats { 2974 /* RX */ 2975 __le64 rx_ucast_bytes; 2976 __le64 rx_ucast_packets; 2977 __le64 rx_mcast_bytes; 2978 __le64 rx_mcast_packets; 2979 __le64 rx_bcast_bytes; 2980 __le64 rx_bcast_packets; 2981 __le64 rsvd0; 2982 __le64 rsvd1; 2983 /* RX drops */ 2984 __le64 rx_ucast_drop_bytes; 2985 __le64 rx_ucast_drop_packets; 2986 __le64 rx_mcast_drop_bytes; 2987 __le64 rx_mcast_drop_packets; 2988 __le64 rx_bcast_drop_bytes; 2989 __le64 rx_bcast_drop_packets; 2990 __le64 rx_dma_error; 2991 __le64 rsvd2; 2992 /* TX */ 2993 __le64 tx_ucast_bytes; 2994 __le64 tx_ucast_packets; 2995 __le64 tx_mcast_bytes; 2996 __le64 tx_mcast_packets; 2997 __le64 tx_bcast_bytes; 2998 __le64 tx_bcast_packets; 2999 __le64 rsvd3; 3000 __le64 rsvd4; 3001 /* TX drops */ 3002 __le64 tx_ucast_drop_bytes; 3003 __le64 tx_ucast_drop_packets; 3004 __le64 tx_mcast_drop_bytes; 3005 __le64 tx_mcast_drop_packets; 3006 __le64 tx_bcast_drop_bytes; 3007 __le64 tx_bcast_drop_packets; 3008 __le64 tx_dma_error; 3009 __le64 rsvd5; 3010 /* Rx Queue/Ring drops */ 3011 __le64 rx_queue_disabled; 3012 __le64 rx_queue_empty; 3013 __le64 rx_queue_error; 3014 __le64 rx_desc_fetch_error; 3015 __le64 rx_desc_data_error; 3016 __le64 rsvd6; 3017 __le64 rsvd7; 3018 __le64 rsvd8; 3019 /* Tx Queue/Ring drops */ 3020 __le64 tx_queue_disabled; 3021 __le64 tx_queue_error; 3022 __le64 tx_desc_fetch_error; 3023 __le64 tx_desc_data_error; 3024 __le64 tx_queue_empty; 3025 __le64 rsvd10; 3026 __le64 rsvd11; 3027 __le64 rsvd12; 3028 3029 /* RDMA/ROCE TX */ 3030 __le64 tx_rdma_ucast_bytes; 3031 __le64 tx_rdma_ucast_packets; 3032 __le64 tx_rdma_mcast_bytes; 3033 __le64 tx_rdma_mcast_packets; 3034 __le64 tx_rdma_cnp_packets; 3035 __le64 rsvd13; 3036 __le64 rsvd14; 3037 __le64 rsvd15; 3038 3039 /* RDMA/ROCE RX */ 3040 __le64 rx_rdma_ucast_bytes; 3041 __le64 rx_rdma_ucast_packets; 3042 __le64 rx_rdma_mcast_bytes; 3043 __le64 rx_rdma_mcast_packets; 3044 __le64 rx_rdma_cnp_packets; 3045 __le64 rx_rdma_ecn_packets; 3046 __le64 rsvd16; 3047 __le64 rsvd17; 3048 3049 __le64 rsvd18; 3050 __le64 rsvd19; 3051 __le64 rsvd20; 3052 __le64 rsvd21; 3053 __le64 rsvd22; 3054 __le64 rsvd23; 3055 __le64 rsvd24; 3056 __le64 rsvd25; 3057 3058 __le64 rsvd26; 3059 __le64 rsvd27; 3060 __le64 rsvd28; 3061 __le64 rsvd29; 3062 __le64 rsvd30; 3063 __le64 rsvd31; 3064 __le64 rsvd32; 3065 __le64 rsvd33; 3066 3067 __le64 rsvd34; 3068 __le64 rsvd35; 3069 __le64 rsvd36; 3070 __le64 rsvd37; 3071 __le64 rsvd38; 3072 __le64 rsvd39; 3073 __le64 rsvd40; 3074 __le64 rsvd41; 3075 3076 __le64 rsvd42; 3077 __le64 rsvd43; 3078 __le64 rsvd44; 3079 __le64 rsvd45; 3080 __le64 rsvd46; 3081 __le64 rsvd47; 3082 __le64 rsvd48; 3083 __le64 rsvd49; 3084 3085 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 3086 __le64 rdma_req_rx_pkt_seq_err; 3087 __le64 rdma_req_rx_rnr_retry_err; 3088 __le64 rdma_req_rx_remote_access_err; 3089 __le64 rdma_req_rx_remote_inv_req_err; 3090 __le64 rdma_req_rx_remote_oper_err; 3091 __le64 rdma_req_rx_implied_nak_seq_err; 3092 __le64 rdma_req_rx_cqe_err; 3093 __le64 rdma_req_rx_cqe_flush_err; 3094 3095 __le64 rdma_req_rx_dup_responses; 3096 __le64 rdma_req_rx_invalid_packets; 3097 __le64 rdma_req_tx_local_access_err; 3098 __le64 rdma_req_tx_local_oper_err; 3099 __le64 rdma_req_tx_memory_mgmt_err; 3100 __le64 rsvd52; 3101 __le64 rsvd53; 3102 __le64 rsvd54; 3103 3104 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 3105 __le64 rdma_resp_rx_dup_requests; 3106 __le64 rdma_resp_rx_out_of_buffer; 3107 __le64 rdma_resp_rx_out_of_seq_pkts; 3108 __le64 rdma_resp_rx_cqe_err; 3109 __le64 rdma_resp_rx_cqe_flush_err; 3110 __le64 rdma_resp_rx_local_len_err; 3111 __le64 rdma_resp_rx_inv_request_err; 3112 __le64 rdma_resp_rx_local_qp_oper_err; 3113 3114 __le64 rdma_resp_rx_out_of_atomic_resource; 3115 __le64 rdma_resp_tx_pkt_seq_err; 3116 __le64 rdma_resp_tx_remote_inv_req_err; 3117 __le64 rdma_resp_tx_remote_access_err; 3118 __le64 rdma_resp_tx_remote_oper_err; 3119 __le64 rdma_resp_tx_rnr_retry_err; 3120 __le64 rsvd57; 3121 __le64 rsvd58; 3122}; 3123 3124/** 3125 * struct ionic_lif_info - LIF info structure 3126 * @config: LIF configuration structure 3127 * @status: LIF status structure 3128 * @stats: LIF statistics structure 3129 */ 3130struct ionic_lif_info { 3131 union ionic_lif_config config; 3132 struct ionic_lif_status status; 3133 struct ionic_lif_stats stats; 3134}; 3135 3136union ionic_dev_cmd { 3137 u32 words[16]; 3138 struct ionic_admin_cmd cmd; 3139 struct ionic_nop_cmd nop; 3140 3141 struct ionic_dev_identify_cmd identify; 3142 struct ionic_dev_init_cmd init; 3143 struct ionic_dev_reset_cmd reset; 3144 struct ionic_dev_getattr_cmd getattr; 3145 struct ionic_dev_setattr_cmd setattr; 3146 3147 struct ionic_port_identify_cmd port_identify; 3148 struct ionic_port_init_cmd port_init; 3149 struct ionic_port_reset_cmd port_reset; 3150 struct ionic_port_getattr_cmd port_getattr; 3151 struct ionic_port_setattr_cmd port_setattr; 3152 3153 struct ionic_vf_setattr_cmd vf_setattr; 3154 struct ionic_vf_getattr_cmd vf_getattr; 3155 struct ionic_vf_ctrl_cmd vf_ctrl; 3156 3157 struct ionic_discover_cmb_cmd discover_cmb; 3158 3159 struct ionic_lif_identify_cmd lif_identify; 3160 struct ionic_lif_init_cmd lif_init; 3161 struct ionic_lif_reset_cmd lif_reset; 3162 3163 struct ionic_qos_identify_cmd qos_identify; 3164 struct ionic_qos_init_cmd qos_init; 3165 struct ionic_qos_reset_cmd qos_reset; 3166 struct ionic_qos_clear_stats_cmd qos_clear_stats; 3167 3168 struct ionic_q_identify_cmd q_identify; 3169 struct ionic_q_init_cmd q_init; 3170 struct ionic_q_control_cmd q_control; 3171 3172 struct ionic_fw_download_cmd fw_download; 3173 struct ionic_fw_control_cmd fw_control; 3174}; 3175 3176union ionic_dev_cmd_comp { 3177 u32 words[4]; 3178 u8 status; 3179 struct ionic_admin_comp comp; 3180 struct ionic_nop_comp nop; 3181 3182 struct ionic_dev_identify_comp identify; 3183 struct ionic_dev_init_comp init; 3184 struct ionic_dev_reset_comp reset; 3185 struct ionic_dev_getattr_comp getattr; 3186 struct ionic_dev_setattr_comp setattr; 3187 3188 struct ionic_port_identify_comp port_identify; 3189 struct ionic_port_init_comp port_init; 3190 struct ionic_port_reset_comp port_reset; 3191 struct ionic_port_getattr_comp port_getattr; 3192 struct ionic_port_setattr_comp port_setattr; 3193 3194 struct ionic_vf_setattr_comp vf_setattr; 3195 struct ionic_vf_getattr_comp vf_getattr; 3196 struct ionic_vf_ctrl_comp vf_ctrl; 3197 3198 struct ionic_discover_cmb_comp discover_cmb; 3199 3200 struct ionic_lif_identify_comp lif_identify; 3201 struct ionic_lif_init_comp lif_init; 3202 ionic_lif_reset_comp lif_reset; 3203 3204 struct ionic_qos_identify_comp qos_identify; 3205 ionic_qos_init_comp qos_init; 3206 ionic_qos_reset_comp qos_reset; 3207 3208 struct ionic_q_identify_comp q_identify; 3209 struct ionic_q_init_comp q_init; 3210 3211 ionic_fw_download_comp fw_download; 3212 struct ionic_fw_control_comp fw_control; 3213}; 3214 3215/** 3216 * struct ionic_hwstamp_regs - Hardware current timestamp registers 3217 * @tick_low: Low 32 bits of hardware timestamp 3218 * @tick_high: High 32 bits of hardware timestamp 3219 */ 3220struct ionic_hwstamp_regs { 3221 u32 tick_low; 3222 u32 tick_high; 3223}; 3224 3225/** 3226 * union ionic_dev_info_regs - Device info register format (read-only) 3227 * @signature: Signature value of 0x44455649 ('DEVI') 3228 * @version: Current version of info 3229 * @asic_type: Asic type 3230 * @asic_rev: Asic revision 3231 * @fw_status: Firmware status 3232 * bit 0 - 1 = fw running 3233 * bit 4-7 - 4 bit generation number, changes on fw restart 3234 * @fw_heartbeat: Firmware heartbeat counter 3235 * @serial_num: Serial number 3236 * @rsvd_pad1024: reserved byte(s) 3237 * @fw_version: Firmware version 3238 * @hwstamp: Hardware current timestamp registers 3239 * @words: word access to struct contents 3240 */ 3241union ionic_dev_info_regs { 3242#define IONIC_DEVINFO_FWVERS_BUFLEN 32 3243#define IONIC_DEVINFO_SERIAL_BUFLEN 32 3244 struct { 3245 u32 signature; 3246 u8 version; 3247 u8 asic_type; 3248 u8 asic_rev; 3249#define IONIC_FW_STS_F_RUNNING 0x01 3250#define IONIC_FW_STS_F_GENERATION 0xF0 3251 u8 fw_status; 3252 u32 fw_heartbeat; 3253 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 3254 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 3255 u8 rsvd_pad1024[948]; 3256 struct ionic_hwstamp_regs hwstamp; 3257 }; 3258 u32 words[512]; 3259}; 3260 3261/** 3262 * union ionic_dev_cmd_regs - Device command register format (read-write) 3263 * @doorbell: Device Cmd Doorbell, write-only 3264 * Write a 1 to signal device to process cmd, 3265 * poll done for completion. 3266 * @done: Done indicator, bit 0 == 1 when command is complete 3267 * @cmd: Opcode-specific command bytes 3268 * @comp: Opcode-specific response bytes 3269 * @rsvd: reserved byte(s) 3270 * @data: Opcode-specific side-data 3271 * @words: word access to struct contents 3272 */ 3273union ionic_dev_cmd_regs { 3274 struct { 3275 u32 doorbell; 3276 u32 done; 3277 union ionic_dev_cmd cmd; 3278 union ionic_dev_cmd_comp comp; 3279 u8 rsvd[48]; 3280 u32 data[478]; 3281 } __packed; 3282 u32 words[512]; 3283}; 3284 3285/** 3286 * union ionic_dev_regs - Device register format for bar 0 page 0 3287 * @info: Device info registers 3288 * @devcmd: Device command registers 3289 * @words: word access to struct contents 3290 */ 3291union ionic_dev_regs { 3292 struct { 3293 union ionic_dev_info_regs info; 3294 union ionic_dev_cmd_regs devcmd; 3295 } __packed; 3296 __le32 words[1024]; 3297}; 3298 3299union ionic_adminq_cmd { 3300 struct ionic_admin_cmd cmd; 3301 struct ionic_nop_cmd nop; 3302 struct ionic_q_identify_cmd q_identify; 3303 struct ionic_q_init_cmd q_init; 3304 struct ionic_q_control_cmd q_control; 3305 struct ionic_lif_setattr_cmd lif_setattr; 3306 struct ionic_lif_getattr_cmd lif_getattr; 3307 struct ionic_lif_setphc_cmd lif_setphc; 3308 struct ionic_rx_mode_set_cmd rx_mode_set; 3309 struct ionic_rx_filter_add_cmd rx_filter_add; 3310 struct ionic_rx_filter_del_cmd rx_filter_del; 3311 struct ionic_rdma_reset_cmd rdma_reset; 3312 struct ionic_rdma_queue_cmd rdma_queue; 3313 struct ionic_fw_download_cmd fw_download; 3314 struct ionic_fw_control_cmd fw_control; 3315}; 3316 3317union ionic_adminq_comp { 3318 struct ionic_admin_comp comp; 3319 struct ionic_nop_comp nop; 3320 struct ionic_q_identify_comp q_identify; 3321 struct ionic_q_init_comp q_init; 3322 struct ionic_lif_setattr_comp lif_setattr; 3323 struct ionic_lif_getattr_comp lif_getattr; 3324 struct ionic_admin_comp lif_setphc; 3325 struct ionic_rx_filter_add_comp rx_filter_add; 3326 struct ionic_fw_control_comp fw_control; 3327}; 3328 3329#define IONIC_BARS_MAX 6 3330#define IONIC_PCI_BAR_DBELL 1 3331#define IONIC_PCI_BAR_CMB 2 3332 3333#define IONIC_BAR0_SIZE 0x8000 3334#define IONIC_BAR2_SIZE 0x800000 3335 3336#define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 3337#define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 3338#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 3339#define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 3340#define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 3341 3342/* BAR2 */ 3343#define IONIC_BAR2_CMB_ENTRY_SIZE 0x800000 3344#define IONIC_DEV_CMD_DONE 0x00000001 3345 3346#define IONIC_ASIC_TYPE_NONE 0 3347#define IONIC_ASIC_TYPE_CAPRI 1 3348#define IONIC_ASIC_TYPE_ELBA 2 3349#define IONIC_ASIC_TYPE_GIGLIO 3 3350#define IONIC_ASIC_TYPE_SALINA 4 3351 3352/** 3353 * struct ionic_doorbell - Doorbell register layout 3354 * @p_index: Producer index 3355 * @ring: Selects the specific ring of the queue to update 3356 * Type-specific meaning: 3357 * ring=0: Default producer/consumer queue 3358 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 3359 * send events to EQs when armed. EQs send 3360 * interrupts when armed. 3361 * @qid_lo: Queue destination for the producer index and flags (low bits) 3362 * @qid_hi: Queue destination for the producer index and flags (high bits) 3363 * @rsvd2: reserved byte(s) 3364 */ 3365struct ionic_doorbell { 3366 __le16 p_index; 3367 u8 ring; 3368 u8 qid_lo; 3369 __le16 qid_hi; 3370 u16 rsvd2; 3371}; 3372 3373struct ionic_intr_status { 3374 u32 status[2]; 3375}; 3376 3377struct ionic_notifyq_cmd { 3378 __le32 data; /* Not used but needed for qcq structure */ 3379}; 3380 3381union ionic_notifyq_comp { 3382 struct ionic_notifyq_event event; 3383 struct ionic_link_change_event link_change; 3384 struct ionic_reset_event reset; 3385 struct ionic_heartbeat_event heartbeat; 3386 struct ionic_log_event log; 3387}; 3388 3389/* Deprecate */ 3390struct ionic_identity { 3391 union ionic_drv_identity drv; 3392 union ionic_dev_identity dev; 3393 union ionic_lif_identity lif; 3394 union ionic_port_identity port; 3395 union ionic_qos_identity qos; 3396 union ionic_q_identity txq; 3397 union ionic_discover_cmb_identity cmb_layout; 3398}; 3399 3400#endif /* _IONIC_IF_H_ */
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