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pch_gbe_main.c
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linux-6.19.14/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 1999 - 2010 Intel Corporation. 4 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD. 5 * 6 * This code was derived from the Intel e1000e Linux driver. 7 */ 8 9#include "pch_gbe.h" 10#include "pch_gbe_phy.h" 11 12#include <linux/gpio/consumer.h> 13#include <linux/gpio/machine.h> 14#include <linux/iopoll.h> 15#include <linux/module.h> 16#include <linux/net_tstamp.h> 17#include <linux/ptp_classify.h> 18#include <linux/ptp_pch.h> 19#include <linux/gpio.h> 20 21#define PCH_GBE_MAR_ENTRIES 16 22#define PCH_GBE_SHORT_PKT 64 23#define DSC_INIT16 0xC000 24#define PCH_GBE_DMA_ALIGN 0 25#define PCH_GBE_DMA_PADDING 2 26#define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */ 27#define PCH_GBE_PCI_BAR 1 28#define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */ 29 30#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 31 32#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 33#define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802 34 35#define PCH_GBE_RX_BUFFER_WRITE 16 36 37/* Initialize the wake-on-LAN settings */ 38#define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP) 39 40#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \ 41 PCH_GBE_CHIP_TYPE_INTERNAL | \ 42 PCH_GBE_RGMII_MODE_RGMII \ 43 ) 44 45/* Ethertype field values */ 46#define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880 47#define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 48#define PCH_GBE_FRAME_SIZE_2048 2048 49#define PCH_GBE_FRAME_SIZE_4096 4096 50#define PCH_GBE_FRAME_SIZE_8192 8192 51 52#define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 53#define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc) 54#define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc) 55#define PCH_GBE_DESC_UNUSED(R) \ 56 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 57 (R)->next_to_clean - (R)->next_to_use - 1) 58 59/* Pause packet value */ 60#define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001 61#define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100 62#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888 63#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF 64 65 66/* This defines the bits that are set in the Interrupt Mask 67 * Set/Read Register. Each bit is documented below: 68 * o RXT0 = Receiver Timer Interrupt (ring 0) 69 * o TXDW = Transmit Descriptor Written Back 70 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 71 * o RXSEQ = Receive Sequence Error 72 * o LSC = Link Status Change 73 */ 74#define PCH_GBE_INT_ENABLE_MASK ( \ 75 PCH_GBE_INT_RX_DMA_CMPLT | \ 76 PCH_GBE_INT_RX_DSC_EMP | \ 77 PCH_GBE_INT_RX_FIFO_ERR | \ 78 PCH_GBE_INT_WOL_DET | \ 79 PCH_GBE_INT_TX_CMPLT \ 80 ) 81 82#define PCH_GBE_INT_DISABLE_ALL 0 83 84/* Macros for ieee1588 */ 85/* 0x40 Time Synchronization Channel Control Register Bits */ 86#define MASTER_MODE (1<<0) 87#define SLAVE_MODE (0) 88#define V2_MODE (1<<31) 89#define CAP_MODE0 (0) 90#define CAP_MODE2 (1<<17) 91 92/* 0x44 Time Synchronization Channel Event Register Bits */ 93#define TX_SNAPSHOT_LOCKED (1<<0) 94#define RX_SNAPSHOT_LOCKED (1<<1) 95 96#define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81" 97#define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00" 98 99static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg); 100static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg, 101 int data); 102static void pch_gbe_set_multi(struct net_device *netdev); 103 104static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 105{ 106 u8 *data = skb->data; 107 unsigned int offset; 108 u16 hi, id; 109 u32 lo; 110 111 if (ptp_classify_raw(skb) == PTP_CLASS_NONE) 112 return 0; 113 114 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 115 116 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 117 return 0; 118 119 hi = get_unaligned_be16(data + offset + OFF_PTP_SOURCE_UUID + 0); 120 lo = get_unaligned_be32(data + offset + OFF_PTP_SOURCE_UUID + 2); 121 id = get_unaligned_be16(data + offset + OFF_PTP_SEQUENCE_ID); 122 123 return (uid_hi == hi && uid_lo == lo && seqid == id); 124} 125 126static void 127pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) 128{ 129 struct skb_shared_hwtstamps *shhwtstamps; 130 struct pci_dev *pdev; 131 u64 ns; 132 u32 hi, lo, val; 133 134 if (!adapter->hwts_rx_en) 135 return; 136 137 /* Get ieee1588's dev information */ 138 pdev = adapter->ptp_pdev; 139 140 val = pch_ch_event_read(pdev); 141 142 if (!(val & RX_SNAPSHOT_LOCKED)) 143 return; 144 145 lo = pch_src_uuid_lo_read(pdev); 146 hi = pch_src_uuid_hi_read(pdev); 147 148 if (!pch_ptp_match(skb, hi, lo, hi >> 16)) 149 goto out; 150 151 ns = pch_rx_snap_read(pdev); 152 153 shhwtstamps = skb_hwtstamps(skb); 154 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 155 shhwtstamps->hwtstamp = ns_to_ktime(ns); 156out: 157 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED); 158} 159 160static void 161pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) 162{ 163 struct skb_shared_hwtstamps shhwtstamps; 164 struct pci_dev *pdev; 165 struct skb_shared_info *shtx; 166 u64 ns; 167 u32 cnt, val; 168 169 shtx = skb_shinfo(skb); 170 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en))) 171 return; 172 173 shtx->tx_flags |= SKBTX_IN_PROGRESS; 174 175 /* Get ieee1588's dev information */ 176 pdev = adapter->ptp_pdev; 177 178 /* 179 * This really stinks, but we have to poll for the Tx time stamp. 180 */ 181 for (cnt = 0; cnt < 100; cnt++) { 182 val = pch_ch_event_read(pdev); 183 if (val & TX_SNAPSHOT_LOCKED) 184 break; 185 udelay(1); 186 } 187 if (!(val & TX_SNAPSHOT_LOCKED)) { 188 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 189 return; 190 } 191 192 ns = pch_tx_snap_read(pdev); 193 194 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 195 shhwtstamps.hwtstamp = ns_to_ktime(ns); 196 skb_tstamp_tx(skb, &shhwtstamps); 197 198 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED); 199} 200 201static int pch_gbe_hwtstamp_set(struct net_device *netdev, 202 struct kernel_hwtstamp_config *cfg, 203 struct netlink_ext_ack *extack) 204{ 205 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 206 struct pci_dev *pdev; 207 u8 station[20]; 208 209 /* Get ieee1588's dev information */ 210 pdev = adapter->ptp_pdev; 211 212 if (cfg->tx_type != HWTSTAMP_TX_OFF && cfg->tx_type != HWTSTAMP_TX_ON) 213 return -ERANGE; 214 215 switch (cfg->rx_filter) { 216 case HWTSTAMP_FILTER_NONE: 217 adapter->hwts_rx_en = 0; 218 break; 219 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 220 adapter->hwts_rx_en = 0; 221 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0); 222 break; 223 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 224 adapter->hwts_rx_en = cfg->rx_filter; 225 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0); 226 break; 227 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 228 adapter->hwts_rx_en = cfg->rx_filter; 229 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); 230 strcpy(station, PTP_L4_MULTICAST_SA); 231 pch_set_station_address(station, pdev); 232 break; 233 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 234 adapter->hwts_rx_en = cfg->rx_filter; 235 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); 236 strcpy(station, PTP_L2_MULTICAST_SA); 237 pch_set_station_address(station, pdev); 238 break; 239 default: 240 return -ERANGE; 241 } 242 243 adapter->hwts_tx_en = cfg->tx_type == HWTSTAMP_TX_ON; 244 245 /* Clear out any old time stamps. */ 246 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED); 247 248 return 0; 249} 250 251static int pch_gbe_hwtstamp_get(struct net_device *netdev, 252 struct kernel_hwtstamp_config *cfg) 253{ 254 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 255 256 cfg->tx_type = adapter->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 257 cfg->rx_filter = adapter->hwts_rx_en; 258 259 return 0; 260} 261 262static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw) 263{ 264 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD); 265} 266 267/** 268 * pch_gbe_mac_read_mac_addr - Read MAC address 269 * @hw: Pointer to the HW structure 270 * Returns: 271 * 0: Successful. 272 */ 273static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw) 274{ 275 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 276 u32 adr1a, adr1b; 277 278 adr1a = ioread32(&hw->reg->mac_adr[0].high); 279 adr1b = ioread32(&hw->reg->mac_adr[0].low); 280 281 hw->mac.addr[0] = (u8)(adr1a & 0xFF); 282 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF); 283 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF); 284 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF); 285 hw->mac.addr[4] = (u8)(adr1b & 0xFF); 286 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF); 287 288 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr); 289 return 0; 290} 291 292/** 293 * pch_gbe_wait_clr_bit - Wait to clear a bit 294 * @reg: Pointer of register 295 * @bit: Busy bit 296 */ 297static void pch_gbe_wait_clr_bit(void __iomem *reg, u32 bit) 298{ 299 u32 tmp; 300 301 /* wait busy */ 302 if (readx_poll_timeout_atomic(ioread32, reg, tmp, !(tmp & bit), 0, 10)) 303 pr_err("Error: busy bit is not cleared\n"); 304} 305 306/** 307 * pch_gbe_mac_mar_set - Set MAC address register 308 * @hw: Pointer to the HW structure 309 * @addr: Pointer to the MAC address 310 * @index: MAC address array register 311 */ 312static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index) 313{ 314 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 315 u32 mar_low, mar_high, adrmask; 316 317 netdev_dbg(adapter->netdev, "index : 0x%x\n", index); 318 319 /* 320 * HW expects these in little endian so we reverse the byte order 321 * from network order (big endian) to little endian 322 */ 323 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) | 324 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 325 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8)); 326 /* Stop the MAC Address of index. */ 327 adrmask = ioread32(&hw->reg->ADDR_MASK); 328 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); 329 /* wait busy */ 330 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 331 /* Set the MAC address to the MAC address 1A/1B register */ 332 iowrite32(mar_high, &hw->reg->mac_adr[index].high); 333 iowrite32(mar_low, &hw->reg->mac_adr[index].low); 334 /* Start the MAC address of index */ 335 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); 336 /* wait busy */ 337 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 338} 339 340/** 341 * pch_gbe_mac_reset_hw - Reset hardware 342 * @hw: Pointer to the HW structure 343 */ 344static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) 345{ 346 /* Read the MAC address. and store to the private data */ 347 pch_gbe_mac_read_mac_addr(hw); 348 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET); 349 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); 350 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); 351 /* Setup the receive addresses */ 352 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); 353 return; 354} 355 356static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw) 357{ 358 u32 rctl; 359 /* Disables Receive MAC */ 360 rctl = ioread32(&hw->reg->MAC_RX_EN); 361 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); 362} 363 364static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw) 365{ 366 u32 rctl; 367 /* Enables Receive MAC */ 368 rctl = ioread32(&hw->reg->MAC_RX_EN); 369 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); 370} 371 372/** 373 * pch_gbe_mac_init_rx_addrs - Initialize receive address's 374 * @hw: Pointer to the HW structure 375 * @mar_count: Receive address registers 376 */ 377static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count) 378{ 379 u32 i; 380 381 /* Setup the receive address */ 382 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); 383 384 /* Zero out the other receive addresses */ 385 for (i = 1; i < mar_count; i++) { 386 iowrite32(0, &hw->reg->mac_adr[i].high); 387 iowrite32(0, &hw->reg->mac_adr[i].low); 388 } 389 iowrite32(0xFFFE, &hw->reg->ADDR_MASK); 390 /* wait busy */ 391 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 392} 393 394/** 395 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings 396 * @hw: Pointer to the HW structure 397 * Returns: 398 * 0: Successful. 399 * Negative value: Failed. 400 */ 401s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw) 402{ 403 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 404 struct pch_gbe_mac_info *mac = &hw->mac; 405 u32 rx_fctrl; 406 407 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc); 408 409 rx_fctrl = ioread32(&hw->reg->RX_FCTRL); 410 411 switch (mac->fc) { 412 case PCH_GBE_FC_NONE: 413 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 414 mac->tx_fc_enable = false; 415 break; 416 case PCH_GBE_FC_RX_PAUSE: 417 rx_fctrl |= PCH_GBE_FL_CTRL_EN; 418 mac->tx_fc_enable = false; 419 break; 420 case PCH_GBE_FC_TX_PAUSE: 421 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 422 mac->tx_fc_enable = true; 423 break; 424 case PCH_GBE_FC_FULL: 425 rx_fctrl |= PCH_GBE_FL_CTRL_EN; 426 mac->tx_fc_enable = true; 427 break; 428 default: 429 netdev_err(adapter->netdev, 430 "Flow control param set incorrectly\n"); 431 return -EINVAL; 432 } 433 if (mac->link_duplex == DUPLEX_HALF) 434 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 435 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL); 436 netdev_dbg(adapter->netdev, 437 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n", 438 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable); 439 return 0; 440} 441 442/** 443 * pch_gbe_mac_set_wol_event - Set wake-on-lan event 444 * @hw: Pointer to the HW structure 445 * @wu_evt: Wake up event 446 */ 447static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt) 448{ 449 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 450 u32 addr_mask; 451 452 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n", 453 wu_evt, ioread32(&hw->reg->ADDR_MASK)); 454 455 if (wu_evt) { 456 /* Set Wake-On-Lan address mask */ 457 addr_mask = ioread32(&hw->reg->ADDR_MASK); 458 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK); 459 /* wait busy */ 460 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY); 461 iowrite32(0, &hw->reg->WOL_ST); 462 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL); 463 iowrite32(0x02, &hw->reg->TCPIP_ACC); 464 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); 465 } else { 466 iowrite32(0, &hw->reg->WOL_CTRL); 467 iowrite32(0, &hw->reg->WOL_ST); 468 } 469 return; 470} 471 472/** 473 * pch_gbe_mac_ctrl_miim - Control MIIM interface 474 * @hw: Pointer to the HW structure 475 * @addr: Address of PHY 476 * @dir: Operetion. (Write or Read) 477 * @reg: Access register of PHY 478 * @data: Write data. 479 * 480 * Returns: Read date. 481 */ 482u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, 483 u16 data) 484{ 485 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 486 unsigned long flags; 487 u32 data_out; 488 489 spin_lock_irqsave(&hw->miim_lock, flags); 490 491 if (readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, 492 data_out & PCH_GBE_MIIM_OPER_READY, 20, 2000)) { 493 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n"); 494 spin_unlock_irqrestore(&hw->miim_lock, flags); 495 return 0; /* No way to indicate timeout error */ 496 } 497 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | 498 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | 499 dir | data), &hw->reg->MIIM); 500 readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, 501 data_out & PCH_GBE_MIIM_OPER_READY, 20, 2000); 502 spin_unlock_irqrestore(&hw->miim_lock, flags); 503 504 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n", 505 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg, 506 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data); 507 return (u16) data_out; 508} 509 510/** 511 * pch_gbe_mac_set_pause_packet - Set pause packet 512 * @hw: Pointer to the HW structure 513 */ 514static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw) 515{ 516 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 517 unsigned long tmp2, tmp3; 518 519 /* Set Pause packet */ 520 tmp2 = hw->mac.addr[1]; 521 tmp2 = (tmp2 << 8) | hw->mac.addr[0]; 522 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16); 523 524 tmp3 = hw->mac.addr[5]; 525 tmp3 = (tmp3 << 8) | hw->mac.addr[4]; 526 tmp3 = (tmp3 << 8) | hw->mac.addr[3]; 527 tmp3 = (tmp3 << 8) | hw->mac.addr[2]; 528 529 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1); 530 iowrite32(tmp2, &hw->reg->PAUSE_PKT2); 531 iowrite32(tmp3, &hw->reg->PAUSE_PKT3); 532 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4); 533 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5); 534 535 /* Transmit Pause Packet */ 536 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ); 537 538 netdev_dbg(adapter->netdev, 539 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 540 ioread32(&hw->reg->PAUSE_PKT1), 541 ioread32(&hw->reg->PAUSE_PKT2), 542 ioread32(&hw->reg->PAUSE_PKT3), 543 ioread32(&hw->reg->PAUSE_PKT4), 544 ioread32(&hw->reg->PAUSE_PKT5)); 545 546 return; 547} 548 549 550/** 551 * pch_gbe_alloc_queues - Allocate memory for all rings 552 * @adapter: Board private structure to initialize 553 * Returns: 554 * 0: Successfully 555 * Negative value: Failed 556 */ 557static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter) 558{ 559 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev, 560 sizeof(*adapter->tx_ring), GFP_KERNEL); 561 if (!adapter->tx_ring) 562 return -ENOMEM; 563 564 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev, 565 sizeof(*adapter->rx_ring), GFP_KERNEL); 566 if (!adapter->rx_ring) 567 return -ENOMEM; 568 return 0; 569} 570 571/** 572 * pch_gbe_init_stats - Initialize status 573 * @adapter: Board private structure to initialize 574 */ 575static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter) 576{ 577 memset(&adapter->stats, 0, sizeof(adapter->stats)); 578 return; 579} 580 581/** 582 * pch_gbe_init_phy - Initialize PHY 583 * @adapter: Board private structure to initialize 584 * Returns: 585 * 0: Successfully 586 * Negative value: Failed 587 */ 588static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter) 589{ 590 struct net_device *netdev = adapter->netdev; 591 u32 addr; 592 u16 bmcr, stat; 593 594 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */ 595 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { 596 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr; 597 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR); 598 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); 599 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); 600 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0)))) 601 break; 602 } 603 adapter->hw.phy.addr = adapter->mii.phy_id; 604 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id); 605 if (addr == PCH_GBE_PHY_REGS_LEN) 606 return -EAGAIN; 607 /* Selected the phy and isolate the rest */ 608 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { 609 if (addr != adapter->mii.phy_id) { 610 pch_gbe_mdio_write(netdev, addr, MII_BMCR, 611 BMCR_ISOLATE); 612 } else { 613 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR); 614 pch_gbe_mdio_write(netdev, addr, MII_BMCR, 615 bmcr & ~BMCR_ISOLATE); 616 } 617 } 618 619 /* MII setup */ 620 adapter->mii.phy_id_mask = 0x1F; 621 adapter->mii.reg_num_mask = 0x1F; 622 adapter->mii.dev = adapter->netdev; 623 adapter->mii.mdio_read = pch_gbe_mdio_read; 624 adapter->mii.mdio_write = pch_gbe_mdio_write; 625 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii); 626 return 0; 627} 628 629/** 630 * pch_gbe_mdio_read - The read function for mii 631 * @netdev: Network interface device structure 632 * @addr: Phy ID 633 * @reg: Access location 634 * Returns: 635 * 0: Successfully 636 * Negative value: Failed 637 */ 638static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg) 639{ 640 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 641 struct pch_gbe_hw *hw = &adapter->hw; 642 643 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg, 644 (u16) 0); 645} 646 647/** 648 * pch_gbe_mdio_write - The write function for mii 649 * @netdev: Network interface device structure 650 * @addr: Phy ID (not used) 651 * @reg: Access location 652 * @data: Write data 653 */ 654static void pch_gbe_mdio_write(struct net_device *netdev, 655 int addr, int reg, int data) 656{ 657 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 658 struct pch_gbe_hw *hw = &adapter->hw; 659 660 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data); 661} 662 663/** 664 * pch_gbe_reset_task - Reset processing at the time of transmission timeout 665 * @work: Pointer of board private structure 666 */ 667static void pch_gbe_reset_task(struct work_struct *work) 668{ 669 struct pch_gbe_adapter *adapter; 670 adapter = container_of(work, struct pch_gbe_adapter, reset_task); 671 672 rtnl_lock(); 673 pch_gbe_reinit_locked(adapter); 674 rtnl_unlock(); 675} 676 677/** 678 * pch_gbe_reinit_locked- Re-initialization 679 * @adapter: Board private structure 680 */ 681void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter) 682{ 683 pch_gbe_down(adapter); 684 pch_gbe_up(adapter); 685} 686 687/** 688 * pch_gbe_reset - Reset GbE 689 * @adapter: Board private structure 690 */ 691void pch_gbe_reset(struct pch_gbe_adapter *adapter) 692{ 693 struct net_device *netdev = adapter->netdev; 694 struct pch_gbe_hw *hw = &adapter->hw; 695 s32 ret_val; 696 697 pch_gbe_mac_reset_hw(hw); 698 /* reprogram multicast address register after reset */ 699 pch_gbe_set_multi(netdev); 700 /* Setup the receive address. */ 701 pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES); 702 703 ret_val = pch_gbe_phy_get_id(hw); 704 if (ret_val) { 705 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n"); 706 return; 707 } 708 pch_gbe_phy_init_setting(hw); 709 /* Setup Mac interface option RGMII */ 710 pch_gbe_phy_set_rgmii(hw); 711} 712 713/** 714 * pch_gbe_free_irq - Free an interrupt 715 * @adapter: Board private structure 716 */ 717static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter) 718{ 719 struct net_device *netdev = adapter->netdev; 720 721 free_irq(adapter->irq, netdev); 722 pci_free_irq_vectors(adapter->pdev); 723} 724 725/** 726 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC 727 * @adapter: Board private structure 728 */ 729static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter) 730{ 731 struct pch_gbe_hw *hw = &adapter->hw; 732 733 atomic_inc(&adapter->irq_sem); 734 iowrite32(0, &hw->reg->INT_EN); 735 ioread32(&hw->reg->INT_ST); 736 synchronize_irq(adapter->irq); 737 738 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n", 739 ioread32(&hw->reg->INT_EN)); 740} 741 742/** 743 * pch_gbe_irq_enable - Enable default interrupt generation settings 744 * @adapter: Board private structure 745 */ 746static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter) 747{ 748 struct pch_gbe_hw *hw = &adapter->hw; 749 750 if (likely(atomic_dec_and_test(&adapter->irq_sem))) 751 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); 752 ioread32(&hw->reg->INT_ST); 753 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n", 754 ioread32(&hw->reg->INT_EN)); 755} 756 757 758 759/** 760 * pch_gbe_setup_tctl - configure the Transmit control registers 761 * @adapter: Board private structure 762 */ 763static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter) 764{ 765 struct pch_gbe_hw *hw = &adapter->hw; 766 u32 tx_mode, tcpip; 767 768 tx_mode = PCH_GBE_TM_LONG_PKT | 769 PCH_GBE_TM_ST_AND_FD | 770 PCH_GBE_TM_SHORT_PKT | 771 PCH_GBE_TM_TH_TX_STRT_8 | 772 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8; 773 774 iowrite32(tx_mode, &hw->reg->TX_MODE); 775 776 tcpip = ioread32(&hw->reg->TCPIP_ACC); 777 tcpip |= PCH_GBE_TX_TCPIPACC_EN; 778 iowrite32(tcpip, &hw->reg->TCPIP_ACC); 779 return; 780} 781 782/** 783 * pch_gbe_configure_tx - Configure Transmit Unit after Reset 784 * @adapter: Board private structure 785 */ 786static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter) 787{ 788 struct pch_gbe_hw *hw = &adapter->hw; 789 u32 tdba, tdlen, dctrl; 790 791 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n", 792 (unsigned long long)adapter->tx_ring->dma, 793 adapter->tx_ring->size); 794 795 /* Setup the HW Tx Head and Tail descriptor pointers */ 796 tdba = adapter->tx_ring->dma; 797 tdlen = adapter->tx_ring->size - 0x10; 798 iowrite32(tdba, &hw->reg->TX_DSC_BASE); 799 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE); 800 iowrite32(tdba, &hw->reg->TX_DSC_SW_P); 801 802 /* Enables Transmission DMA */ 803 dctrl = ioread32(&hw->reg->DMA_CTRL); 804 dctrl |= PCH_GBE_TX_DMA_EN; 805 iowrite32(dctrl, &hw->reg->DMA_CTRL); 806} 807 808/** 809 * pch_gbe_setup_rctl - Configure the receive control registers 810 * @adapter: Board private structure 811 */ 812static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter) 813{ 814 struct pch_gbe_hw *hw = &adapter->hw; 815 u32 rx_mode, tcpip; 816 817 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN | 818 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8; 819 820 iowrite32(rx_mode, &hw->reg->RX_MODE); 821 822 tcpip = ioread32(&hw->reg->TCPIP_ACC); 823 824 tcpip |= PCH_GBE_RX_TCPIPACC_OFF; 825 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; 826 iowrite32(tcpip, &hw->reg->TCPIP_ACC); 827 return; 828} 829 830/** 831 * pch_gbe_configure_rx - Configure Receive Unit after Reset 832 * @adapter: Board private structure 833 */ 834static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter) 835{ 836 struct pch_gbe_hw *hw = &adapter->hw; 837 u32 rdba, rdlen, rxdma; 838 839 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n", 840 (unsigned long long)adapter->rx_ring->dma, 841 adapter->rx_ring->size); 842 843 pch_gbe_mac_force_mac_fc(hw); 844 845 pch_gbe_disable_mac_rx(hw); 846 847 /* Disables Receive DMA */ 848 rxdma = ioread32(&hw->reg->DMA_CTRL); 849 rxdma &= ~PCH_GBE_RX_DMA_EN; 850 iowrite32(rxdma, &hw->reg->DMA_CTRL); 851 852 netdev_dbg(adapter->netdev, 853 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n", 854 ioread32(&hw->reg->MAC_RX_EN), 855 ioread32(&hw->reg->DMA_CTRL)); 856 857 /* Setup the HW Rx Head and Tail Descriptor Pointers and 858 * the Base and Length of the Rx Descriptor Ring */ 859 rdba = adapter->rx_ring->dma; 860 rdlen = adapter->rx_ring->size - 0x10; 861 iowrite32(rdba, &hw->reg->RX_DSC_BASE); 862 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); 863 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); 864} 865 866/** 867 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer 868 * @adapter: Board private structure 869 * @buffer_info: Buffer information structure 870 */ 871static void pch_gbe_unmap_and_free_tx_resource( 872 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info) 873{ 874 if (buffer_info->mapped) { 875 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 876 buffer_info->length, DMA_TO_DEVICE); 877 buffer_info->mapped = false; 878 } 879 if (buffer_info->skb) { 880 dev_kfree_skb_any(buffer_info->skb); 881 buffer_info->skb = NULL; 882 } 883} 884 885/** 886 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer 887 * @adapter: Board private structure 888 * @buffer_info: Buffer information structure 889 */ 890static void pch_gbe_unmap_and_free_rx_resource( 891 struct pch_gbe_adapter *adapter, 892 struct pch_gbe_buffer *buffer_info) 893{ 894 if (buffer_info->mapped) { 895 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 896 buffer_info->length, DMA_FROM_DEVICE); 897 buffer_info->mapped = false; 898 } 899 if (buffer_info->skb) { 900 dev_kfree_skb_any(buffer_info->skb); 901 buffer_info->skb = NULL; 902 } 903} 904 905/** 906 * pch_gbe_clean_tx_ring - Free Tx Buffers 907 * @adapter: Board private structure 908 * @tx_ring: Ring to be cleaned 909 */ 910static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter, 911 struct pch_gbe_tx_ring *tx_ring) 912{ 913 struct pch_gbe_hw *hw = &adapter->hw; 914 struct pch_gbe_buffer *buffer_info; 915 unsigned long size; 916 unsigned int i; 917 918 /* Free all the Tx ring sk_buffs */ 919 for (i = 0; i < tx_ring->count; i++) { 920 buffer_info = &tx_ring->buffer_info[i]; 921 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info); 922 } 923 netdev_dbg(adapter->netdev, 924 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i); 925 926 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count; 927 memset(tx_ring->buffer_info, 0, size); 928 929 /* Zero out the descriptor ring */ 930 memset(tx_ring->desc, 0, tx_ring->size); 931 tx_ring->next_to_use = 0; 932 tx_ring->next_to_clean = 0; 933 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P); 934 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE); 935} 936 937/** 938 * pch_gbe_clean_rx_ring - Free Rx Buffers 939 * @adapter: Board private structure 940 * @rx_ring: Ring to free buffers from 941 */ 942static void 943pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter, 944 struct pch_gbe_rx_ring *rx_ring) 945{ 946 struct pch_gbe_hw *hw = &adapter->hw; 947 struct pch_gbe_buffer *buffer_info; 948 unsigned long size; 949 unsigned int i; 950 951 /* Free all the Rx ring sk_buffs */ 952 for (i = 0; i < rx_ring->count; i++) { 953 buffer_info = &rx_ring->buffer_info[i]; 954 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info); 955 } 956 netdev_dbg(adapter->netdev, 957 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i); 958 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count; 959 memset(rx_ring->buffer_info, 0, size); 960 961 /* Zero out the descriptor ring */ 962 memset(rx_ring->desc, 0, rx_ring->size); 963 rx_ring->next_to_clean = 0; 964 rx_ring->next_to_use = 0; 965 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P); 966 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE); 967} 968 969static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed, 970 u16 duplex) 971{ 972 struct pch_gbe_hw *hw = &adapter->hw; 973 unsigned long rgmii = 0; 974 975 /* Set the RGMII control. */ 976 switch (speed) { 977 case SPEED_10: 978 rgmii = (PCH_GBE_RGMII_RATE_2_5M | 979 PCH_GBE_MAC_RGMII_CTRL_SETTING); 980 break; 981 case SPEED_100: 982 rgmii = (PCH_GBE_RGMII_RATE_25M | 983 PCH_GBE_MAC_RGMII_CTRL_SETTING); 984 break; 985 case SPEED_1000: 986 rgmii = (PCH_GBE_RGMII_RATE_125M | 987 PCH_GBE_MAC_RGMII_CTRL_SETTING); 988 break; 989 } 990 iowrite32(rgmii, &hw->reg->RGMII_CTRL); 991} 992static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed, 993 u16 duplex) 994{ 995 struct net_device *netdev = adapter->netdev; 996 struct pch_gbe_hw *hw = &adapter->hw; 997 unsigned long mode = 0; 998 999 /* Set the communication mode */ 1000 switch (speed) { 1001 case SPEED_10: 1002 mode = PCH_GBE_MODE_MII_ETHER; 1003 netdev->tx_queue_len = 10; 1004 break; 1005 case SPEED_100: 1006 mode = PCH_GBE_MODE_MII_ETHER; 1007 netdev->tx_queue_len = 100; 1008 break; 1009 case SPEED_1000: 1010 mode = PCH_GBE_MODE_GMII_ETHER; 1011 break; 1012 } 1013 if (duplex == DUPLEX_FULL) 1014 mode |= PCH_GBE_MODE_FULL_DUPLEX; 1015 else 1016 mode |= PCH_GBE_MODE_HALF_DUPLEX; 1017 iowrite32(mode, &hw->reg->MODE); 1018} 1019 1020/** 1021 * pch_gbe_watchdog - Watchdog process 1022 * @t: timer list containing a Board private structure 1023 */ 1024static void pch_gbe_watchdog(struct timer_list *t) 1025{ 1026 struct pch_gbe_adapter *adapter = timer_container_of(adapter, t, 1027 watchdog_timer); 1028 struct net_device *netdev = adapter->netdev; 1029 struct pch_gbe_hw *hw = &adapter->hw; 1030 1031 netdev_dbg(netdev, "right now = %ld\n", jiffies); 1032 1033 pch_gbe_update_stats(adapter); 1034 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) { 1035 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; 1036 netdev->tx_queue_len = adapter->tx_queue_len; 1037 /* mii library handles link maintenance tasks */ 1038 mii_ethtool_gset(&adapter->mii, &cmd); 1039 hw->mac.link_speed = ethtool_cmd_speed(&cmd); 1040 hw->mac.link_duplex = cmd.duplex; 1041 /* Set the RGMII control. */ 1042 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, 1043 hw->mac.link_duplex); 1044 /* Set the communication mode */ 1045 pch_gbe_set_mode(adapter, hw->mac.link_speed, 1046 hw->mac.link_duplex); 1047 netdev_dbg(netdev, 1048 "Link is Up %d Mbps %s-Duplex\n", 1049 hw->mac.link_speed, 1050 cmd.duplex == DUPLEX_FULL ? "Full" : "Half"); 1051 netif_carrier_on(netdev); 1052 netif_wake_queue(netdev); 1053 } else if ((!mii_link_ok(&adapter->mii)) && 1054 (netif_carrier_ok(netdev))) { 1055 netdev_dbg(netdev, "NIC Link is Down\n"); 1056 hw->mac.link_speed = SPEED_10; 1057 hw->mac.link_duplex = DUPLEX_HALF; 1058 netif_carrier_off(netdev); 1059 netif_stop_queue(netdev); 1060 } 1061 mod_timer(&adapter->watchdog_timer, 1062 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD)); 1063} 1064 1065/** 1066 * pch_gbe_tx_queue - Carry out queuing of the transmission data 1067 * @adapter: Board private structure 1068 * @tx_ring: Tx descriptor ring structure 1069 * @skb: Sockt buffer structure 1070 */ 1071static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter, 1072 struct pch_gbe_tx_ring *tx_ring, 1073 struct sk_buff *skb) 1074{ 1075 struct pch_gbe_hw *hw = &adapter->hw; 1076 struct pch_gbe_tx_desc *tx_desc; 1077 struct pch_gbe_buffer *buffer_info; 1078 struct sk_buff *tmp_skb; 1079 unsigned int frame_ctrl; 1080 unsigned int ring_num; 1081 1082 /*-- Set frame control --*/ 1083 frame_ctrl = 0; 1084 if (unlikely(skb->len < PCH_GBE_SHORT_PKT)) 1085 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; 1086 if (skb->ip_summed == CHECKSUM_NONE) 1087 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; 1088 1089 /* Performs checksum processing */ 1090 /* 1091 * It is because the hardware accelerator does not support a checksum, 1092 * when the received data size is less than 64 bytes. 1093 */ 1094 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) { 1095 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD | 1096 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; 1097 if (skb->protocol == htons(ETH_P_IP)) { 1098 struct iphdr *iph = ip_hdr(skb); 1099 unsigned int offset; 1100 offset = skb_transport_offset(skb); 1101 if (iph->protocol == IPPROTO_TCP) { 1102 skb->csum = 0; 1103 tcp_hdr(skb)->check = 0; 1104 skb->csum = skb_checksum(skb, offset, 1105 skb->len - offset, 0); 1106 tcp_hdr(skb)->check = 1107 csum_tcpudp_magic(iph->saddr, 1108 iph->daddr, 1109 skb->len - offset, 1110 IPPROTO_TCP, 1111 skb->csum); 1112 } else if (iph->protocol == IPPROTO_UDP) { 1113 skb->csum = 0; 1114 udp_hdr(skb)->check = 0; 1115 skb->csum = 1116 skb_checksum(skb, offset, 1117 skb->len - offset, 0); 1118 udp_hdr(skb)->check = 1119 csum_tcpudp_magic(iph->saddr, 1120 iph->daddr, 1121 skb->len - offset, 1122 IPPROTO_UDP, 1123 skb->csum); 1124 } 1125 } 1126 } 1127 1128 ring_num = tx_ring->next_to_use; 1129 if (unlikely((ring_num + 1) == tx_ring->count)) 1130 tx_ring->next_to_use = 0; 1131 else 1132 tx_ring->next_to_use = ring_num + 1; 1133 1134 1135 buffer_info = &tx_ring->buffer_info[ring_num]; 1136 tmp_skb = buffer_info->skb; 1137 1138 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */ 1139 memcpy(tmp_skb->data, skb->data, ETH_HLEN); 1140 tmp_skb->data[ETH_HLEN] = 0x00; 1141 tmp_skb->data[ETH_HLEN + 1] = 0x00; 1142 tmp_skb->len = skb->len; 1143 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN], 1144 (skb->len - ETH_HLEN)); 1145 /*-- Set Buffer information --*/ 1146 buffer_info->length = tmp_skb->len; 1147 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data, 1148 buffer_info->length, 1149 DMA_TO_DEVICE); 1150 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { 1151 netdev_err(adapter->netdev, "TX DMA map failed\n"); 1152 buffer_info->dma = 0; 1153 buffer_info->time_stamp = 0; 1154 tx_ring->next_to_use = ring_num; 1155 dev_kfree_skb_any(skb); 1156 return; 1157 } 1158 buffer_info->mapped = true; 1159 buffer_info->time_stamp = jiffies; 1160 1161 /*-- Set Tx descriptor --*/ 1162 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num); 1163 tx_desc->buffer_addr = (buffer_info->dma); 1164 tx_desc->length = (tmp_skb->len); 1165 tx_desc->tx_words_eob = ((tmp_skb->len + 3)); 1166 tx_desc->tx_frame_ctrl = (frame_ctrl); 1167 tx_desc->gbec_status = (DSC_INIT16); 1168 1169 if (unlikely(++ring_num == tx_ring->count)) 1170 ring_num = 0; 1171 1172 /* Update software pointer of TX descriptor */ 1173 iowrite32(tx_ring->dma + 1174 (int)sizeof(struct pch_gbe_tx_desc) * ring_num, 1175 &hw->reg->TX_DSC_SW_P); 1176 1177 pch_tx_timestamp(adapter, skb); 1178 1179 dev_kfree_skb_any(skb); 1180} 1181 1182/** 1183 * pch_gbe_update_stats - Update the board statistics counters 1184 * @adapter: Board private structure 1185 */ 1186void pch_gbe_update_stats(struct pch_gbe_adapter *adapter) 1187{ 1188 struct net_device *netdev = adapter->netdev; 1189 struct pci_dev *pdev = adapter->pdev; 1190 struct pch_gbe_hw_stats *stats = &adapter->stats; 1191 unsigned long flags; 1192 1193 /* 1194 * Prevent stats update while adapter is being reset, or if the pci 1195 * connection is down. 1196 */ 1197 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal)) 1198 return; 1199 1200 spin_lock_irqsave(&adapter->stats_lock, flags); 1201 1202 /* Update device status "adapter->stats" */ 1203 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1204 stats->tx_errors = stats->tx_length_errors + 1205 stats->tx_aborted_errors + 1206 stats->tx_carrier_errors + stats->tx_timeout_count; 1207 1208 /* Update network device status "adapter->net_stats" */ 1209 netdev->stats.rx_packets = stats->rx_packets; 1210 netdev->stats.rx_bytes = stats->rx_bytes; 1211 netdev->stats.rx_dropped = stats->rx_dropped; 1212 netdev->stats.tx_packets = stats->tx_packets; 1213 netdev->stats.tx_bytes = stats->tx_bytes; 1214 netdev->stats.tx_dropped = stats->tx_dropped; 1215 /* Fill out the OS statistics structure */ 1216 netdev->stats.multicast = stats->multicast; 1217 netdev->stats.collisions = stats->collisions; 1218 /* Rx Errors */ 1219 netdev->stats.rx_errors = stats->rx_errors; 1220 netdev->stats.rx_crc_errors = stats->rx_crc_errors; 1221 netdev->stats.rx_frame_errors = stats->rx_frame_errors; 1222 /* Tx Errors */ 1223 netdev->stats.tx_errors = stats->tx_errors; 1224 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors; 1225 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors; 1226 1227 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1228} 1229 1230static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw) 1231{ 1232 u32 rxdma; 1233 1234 /* Disable Receive DMA */ 1235 rxdma = ioread32(&hw->reg->DMA_CTRL); 1236 rxdma &= ~PCH_GBE_RX_DMA_EN; 1237 iowrite32(rxdma, &hw->reg->DMA_CTRL); 1238} 1239 1240static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw) 1241{ 1242 u32 rxdma; 1243 1244 /* Enables Receive DMA */ 1245 rxdma = ioread32(&hw->reg->DMA_CTRL); 1246 rxdma |= PCH_GBE_RX_DMA_EN; 1247 iowrite32(rxdma, &hw->reg->DMA_CTRL); 1248} 1249 1250/** 1251 * pch_gbe_intr - Interrupt Handler 1252 * @irq: Interrupt number 1253 * @data: Pointer to a network interface device structure 1254 * Returns: 1255 * - IRQ_HANDLED: Our interrupt 1256 * - IRQ_NONE: Not our interrupt 1257 */ 1258static irqreturn_t pch_gbe_intr(int irq, void *data) 1259{ 1260 struct net_device *netdev = data; 1261 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 1262 struct pch_gbe_hw *hw = &adapter->hw; 1263 u32 int_st; 1264 u32 int_en; 1265 1266 /* Check request status */ 1267 int_st = ioread32(&hw->reg->INT_ST); 1268 int_st = int_st & ioread32(&hw->reg->INT_EN); 1269 /* When request status is no interruption factor */ 1270 if (unlikely(!int_st)) 1271 return IRQ_NONE; /* Not our interrupt. End processing. */ 1272 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st); 1273 if (int_st & PCH_GBE_INT_RX_FRAME_ERR) 1274 adapter->stats.intr_rx_frame_err_count++; 1275 if (int_st & PCH_GBE_INT_RX_FIFO_ERR) 1276 if (!adapter->rx_stop_flag) { 1277 adapter->stats.intr_rx_fifo_err_count++; 1278 netdev_dbg(netdev, "Rx fifo over run\n"); 1279 adapter->rx_stop_flag = true; 1280 int_en = ioread32(&hw->reg->INT_EN); 1281 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR), 1282 &hw->reg->INT_EN); 1283 pch_gbe_disable_dma_rx(&adapter->hw); 1284 int_st |= ioread32(&hw->reg->INT_ST); 1285 int_st = int_st & ioread32(&hw->reg->INT_EN); 1286 } 1287 if (int_st & PCH_GBE_INT_RX_DMA_ERR) 1288 adapter->stats.intr_rx_dma_err_count++; 1289 if (int_st & PCH_GBE_INT_TX_FIFO_ERR) 1290 adapter->stats.intr_tx_fifo_err_count++; 1291 if (int_st & PCH_GBE_INT_TX_DMA_ERR) 1292 adapter->stats.intr_tx_dma_err_count++; 1293 if (int_st & PCH_GBE_INT_TCPIP_ERR) 1294 adapter->stats.intr_tcpip_err_count++; 1295 /* When Rx descriptor is empty */ 1296 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { 1297 adapter->stats.intr_rx_dsc_empty_count++; 1298 netdev_dbg(netdev, "Rx descriptor is empty\n"); 1299 int_en = ioread32(&hw->reg->INT_EN); 1300 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); 1301 if (hw->mac.tx_fc_enable) { 1302 /* Set Pause packet */ 1303 pch_gbe_mac_set_pause_packet(hw); 1304 } 1305 } 1306 1307 /* When request status is Receive interruption */ 1308 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) || 1309 (adapter->rx_stop_flag)) { 1310 if (likely(napi_schedule_prep(&adapter->napi))) { 1311 /* Enable only Rx Descriptor empty */ 1312 atomic_inc(&adapter->irq_sem); 1313 int_en = ioread32(&hw->reg->INT_EN); 1314 int_en &= 1315 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT); 1316 iowrite32(int_en, &hw->reg->INT_EN); 1317 /* Start polling for NAPI */ 1318 __napi_schedule(&adapter->napi); 1319 } 1320 } 1321 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n", 1322 IRQ_HANDLED, ioread32(&hw->reg->INT_EN)); 1323 return IRQ_HANDLED; 1324} 1325 1326/** 1327 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended 1328 * @adapter: Board private structure 1329 * @rx_ring: Rx descriptor ring 1330 * @cleaned_count: Cleaned count 1331 */ 1332static void 1333pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, 1334 struct pch_gbe_rx_ring *rx_ring, int cleaned_count) 1335{ 1336 struct net_device *netdev = adapter->netdev; 1337 struct pci_dev *pdev = adapter->pdev; 1338 struct pch_gbe_hw *hw = &adapter->hw; 1339 struct pch_gbe_rx_desc *rx_desc; 1340 struct pch_gbe_buffer *buffer_info; 1341 struct sk_buff *skb; 1342 unsigned int i; 1343 unsigned int bufsz; 1344 1345 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; 1346 i = rx_ring->next_to_use; 1347 1348 while ((cleaned_count--)) { 1349 buffer_info = &rx_ring->buffer_info[i]; 1350 skb = netdev_alloc_skb(netdev, bufsz); 1351 if (unlikely(!skb)) { 1352 /* Better luck next round */ 1353 adapter->stats.rx_alloc_buff_failed++; 1354 break; 1355 } 1356 /* align */ 1357 skb_reserve(skb, NET_IP_ALIGN); 1358 buffer_info->skb = skb; 1359 1360 buffer_info->dma = dma_map_single(&pdev->dev, 1361 buffer_info->rx_buffer, 1362 buffer_info->length, 1363 DMA_FROM_DEVICE); 1364 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { 1365 dev_kfree_skb(skb); 1366 buffer_info->skb = NULL; 1367 buffer_info->dma = 0; 1368 adapter->stats.rx_alloc_buff_failed++; 1369 break; /* while !buffer_info->skb */ 1370 } 1371 buffer_info->mapped = true; 1372 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); 1373 rx_desc->buffer_addr = (buffer_info->dma); 1374 rx_desc->gbec_status = DSC_INIT16; 1375 1376 netdev_dbg(netdev, 1377 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n", 1378 i, (unsigned long long)buffer_info->dma, 1379 buffer_info->length); 1380 1381 if (unlikely(++i == rx_ring->count)) 1382 i = 0; 1383 } 1384 if (likely(rx_ring->next_to_use != i)) { 1385 rx_ring->next_to_use = i; 1386 if (unlikely(i-- == 0)) 1387 i = (rx_ring->count - 1); 1388 iowrite32(rx_ring->dma + 1389 (int)sizeof(struct pch_gbe_rx_desc) * i, 1390 &hw->reg->RX_DSC_SW_P); 1391 } 1392 return; 1393} 1394 1395static int 1396pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter, 1397 struct pch_gbe_rx_ring *rx_ring, int cleaned_count) 1398{ 1399 struct pci_dev *pdev = adapter->pdev; 1400 struct pch_gbe_buffer *buffer_info; 1401 unsigned int i; 1402 unsigned int bufsz; 1403 unsigned int size; 1404 1405 bufsz = adapter->rx_buffer_len; 1406 1407 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY; 1408 rx_ring->rx_buff_pool = 1409 dma_alloc_coherent(&pdev->dev, size, 1410 &rx_ring->rx_buff_pool_logic, GFP_KERNEL); 1411 if (!rx_ring->rx_buff_pool) 1412 return -ENOMEM; 1413 1414 rx_ring->rx_buff_pool_size = size; 1415 for (i = 0; i < rx_ring->count; i++) { 1416 buffer_info = &rx_ring->buffer_info[i]; 1417 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i; 1418 buffer_info->length = bufsz; 1419 } 1420 return 0; 1421} 1422 1423/** 1424 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers 1425 * @adapter: Board private structure 1426 * @tx_ring: Tx descriptor ring 1427 */ 1428static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter, 1429 struct pch_gbe_tx_ring *tx_ring) 1430{ 1431 struct pch_gbe_buffer *buffer_info; 1432 struct sk_buff *skb; 1433 unsigned int i; 1434 unsigned int bufsz; 1435 struct pch_gbe_tx_desc *tx_desc; 1436 1437 bufsz = 1438 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN; 1439 1440 for (i = 0; i < tx_ring->count; i++) { 1441 buffer_info = &tx_ring->buffer_info[i]; 1442 skb = netdev_alloc_skb(adapter->netdev, bufsz); 1443 skb_reserve(skb, PCH_GBE_DMA_ALIGN); 1444 buffer_info->skb = skb; 1445 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1446 tx_desc->gbec_status = (DSC_INIT16); 1447 } 1448 return; 1449} 1450 1451/** 1452 * pch_gbe_clean_tx - Reclaim resources after transmit completes 1453 * @adapter: Board private structure 1454 * @tx_ring: Tx descriptor ring 1455 * Returns: 1456 * true: Cleaned the descriptor 1457 * false: Not cleaned the descriptor 1458 */ 1459static bool 1460pch_gbe_clean_tx(struct pch_gbe_adapter *adapter, 1461 struct pch_gbe_tx_ring *tx_ring) 1462{ 1463 struct pch_gbe_tx_desc *tx_desc; 1464 struct pch_gbe_buffer *buffer_info; 1465 struct sk_buff *skb; 1466 unsigned int i; 1467 unsigned int cleaned_count = 0; 1468 bool cleaned = false; 1469 int unused, thresh; 1470 1471 netdev_dbg(adapter->netdev, "next_to_clean : %d\n", 1472 tx_ring->next_to_clean); 1473 1474 i = tx_ring->next_to_clean; 1475 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1476 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n", 1477 tx_desc->gbec_status, tx_desc->dma_status); 1478 1479 unused = PCH_GBE_DESC_UNUSED(tx_ring); 1480 thresh = tx_ring->count - NAPI_POLL_WEIGHT; 1481 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh)) 1482 { /* current marked clean, tx queue filling up, do extra clean */ 1483 int j, k; 1484 if (unused < 8) { /* tx queue nearly full */ 1485 netdev_dbg(adapter->netdev, 1486 "clean_tx: transmit queue warning (%x,%x) unused=%d\n", 1487 tx_ring->next_to_clean, tx_ring->next_to_use, 1488 unused); 1489 } 1490 1491 /* current marked clean, scan for more that need cleaning. */ 1492 k = i; 1493 for (j = 0; j < NAPI_POLL_WEIGHT; j++) 1494 { 1495 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k); 1496 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/ 1497 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/ 1498 } 1499 if (j < NAPI_POLL_WEIGHT) { 1500 netdev_dbg(adapter->netdev, 1501 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n", 1502 unused, j, i, k, tx_ring->next_to_use, 1503 tx_desc->gbec_status); 1504 i = k; /*found one to clean, usu gbec_status==2000.*/ 1505 } 1506 } 1507 1508 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) { 1509 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n", 1510 tx_desc->gbec_status); 1511 buffer_info = &tx_ring->buffer_info[i]; 1512 skb = buffer_info->skb; 1513 cleaned = true; 1514 1515 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) { 1516 adapter->stats.tx_aborted_errors++; 1517 netdev_err(adapter->netdev, "Transfer Abort Error\n"); 1518 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER) 1519 ) { 1520 adapter->stats.tx_carrier_errors++; 1521 netdev_err(adapter->netdev, 1522 "Transfer Carrier Sense Error\n"); 1523 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL) 1524 ) { 1525 adapter->stats.tx_aborted_errors++; 1526 netdev_err(adapter->netdev, 1527 "Transfer Collision Abort Error\n"); 1528 } else if ((tx_desc->gbec_status & 1529 (PCH_GBE_TXD_GMAC_STAT_SNGCOL | 1530 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) { 1531 adapter->stats.collisions++; 1532 adapter->stats.tx_packets++; 1533 adapter->stats.tx_bytes += skb->len; 1534 netdev_dbg(adapter->netdev, "Transfer Collision\n"); 1535 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT) 1536 ) { 1537 adapter->stats.tx_packets++; 1538 adapter->stats.tx_bytes += skb->len; 1539 } 1540 if (buffer_info->mapped) { 1541 netdev_dbg(adapter->netdev, 1542 "unmap buffer_info->dma : %d\n", i); 1543 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1544 buffer_info->length, DMA_TO_DEVICE); 1545 buffer_info->mapped = false; 1546 } 1547 if (buffer_info->skb) { 1548 netdev_dbg(adapter->netdev, 1549 "trim buffer_info->skb : %d\n", i); 1550 skb_trim(buffer_info->skb, 0); 1551 } 1552 tx_desc->gbec_status = DSC_INIT16; 1553 if (unlikely(++i == tx_ring->count)) 1554 i = 0; 1555 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1556 1557 /* weight of a sort for tx, to avoid endless transmit cleanup */ 1558 if (cleaned_count++ == NAPI_POLL_WEIGHT) { 1559 cleaned = false; 1560 break; 1561 } 1562 } 1563 netdev_dbg(adapter->netdev, 1564 "called pch_gbe_unmap_and_free_tx_resource() %d count\n", 1565 cleaned_count); 1566 if (cleaned_count > 0) { /*skip this if nothing cleaned*/ 1567 /* Recover from running out of Tx resources in xmit_frame */ 1568 netif_tx_lock(adapter->netdev); 1569 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) 1570 { 1571 netif_wake_queue(adapter->netdev); 1572 adapter->stats.tx_restart_count++; 1573 netdev_dbg(adapter->netdev, "Tx wake queue\n"); 1574 } 1575 1576 tx_ring->next_to_clean = i; 1577 1578 netdev_dbg(adapter->netdev, "next_to_clean : %d\n", 1579 tx_ring->next_to_clean); 1580 netif_tx_unlock(adapter->netdev); 1581 } 1582 return cleaned; 1583} 1584 1585/** 1586 * pch_gbe_clean_rx - Send received data up the network stack; legacy 1587 * @adapter: Board private structure 1588 * @rx_ring: Rx descriptor ring 1589 * @work_done: Completed count 1590 * @work_to_do: Request count 1591 * Returns: 1592 * true: Cleaned the descriptor 1593 * false: Not cleaned the descriptor 1594 */ 1595static bool 1596pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, 1597 struct pch_gbe_rx_ring *rx_ring, 1598 int *work_done, int work_to_do) 1599{ 1600 struct net_device *netdev = adapter->netdev; 1601 struct pci_dev *pdev = adapter->pdev; 1602 struct pch_gbe_buffer *buffer_info; 1603 struct pch_gbe_rx_desc *rx_desc; 1604 u32 length; 1605 unsigned int i; 1606 unsigned int cleaned_count = 0; 1607 bool cleaned = false; 1608 struct sk_buff *skb; 1609 u8 dma_status; 1610 u16 gbec_status; 1611 u32 tcp_ip_status; 1612 1613 i = rx_ring->next_to_clean; 1614 1615 while (*work_done < work_to_do) { 1616 /* Check Rx descriptor status */ 1617 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); 1618 if (rx_desc->gbec_status == DSC_INIT16) 1619 break; 1620 cleaned = true; 1621 cleaned_count++; 1622 1623 dma_status = rx_desc->dma_status; 1624 gbec_status = rx_desc->gbec_status; 1625 tcp_ip_status = rx_desc->tcp_ip_status; 1626 rx_desc->gbec_status = DSC_INIT16; 1627 buffer_info = &rx_ring->buffer_info[i]; 1628 skb = buffer_info->skb; 1629 buffer_info->skb = NULL; 1630 1631 /* unmap dma */ 1632 dma_unmap_single(&pdev->dev, buffer_info->dma, 1633 buffer_info->length, DMA_FROM_DEVICE); 1634 buffer_info->mapped = false; 1635 1636 netdev_dbg(netdev, 1637 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n", 1638 i, dma_status, gbec_status, tcp_ip_status, 1639 buffer_info); 1640 /* Error check */ 1641 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) { 1642 adapter->stats.rx_frame_errors++; 1643 netdev_err(netdev, "Receive Not Octal Error\n"); 1644 } else if (unlikely(gbec_status & 1645 PCH_GBE_RXD_GMAC_STAT_NBLERR)) { 1646 adapter->stats.rx_frame_errors++; 1647 netdev_err(netdev, "Receive Nibble Error\n"); 1648 } else if (unlikely(gbec_status & 1649 PCH_GBE_RXD_GMAC_STAT_CRCERR)) { 1650 adapter->stats.rx_crc_errors++; 1651 netdev_err(netdev, "Receive CRC Error\n"); 1652 } else { 1653 /* get receive length */ 1654 /* length convert[-3], length includes FCS length */ 1655 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN; 1656 if (rx_desc->rx_words_eob & 0x02) 1657 length = length - 4; 1658 /* 1659 * buffer_info->rx_buffer: [Header:14][payload] 1660 * skb->data: [Reserve:2][Header:14][payload] 1661 */ 1662 memcpy(skb->data, buffer_info->rx_buffer, length); 1663 1664 /* update status of driver */ 1665 adapter->stats.rx_bytes += length; 1666 adapter->stats.rx_packets++; 1667 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT)) 1668 adapter->stats.multicast++; 1669 /* Write meta date of skb */ 1670 skb_put(skb, length); 1671 1672 pch_rx_timestamp(adapter, skb); 1673 1674 skb->protocol = eth_type_trans(skb, netdev); 1675 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) 1676 skb->ip_summed = CHECKSUM_UNNECESSARY; 1677 else 1678 skb->ip_summed = CHECKSUM_NONE; 1679 1680 napi_gro_receive(&adapter->napi, skb); 1681 (*work_done)++; 1682 netdev_dbg(netdev, 1683 "Receive skb->ip_summed: %d length: %d\n", 1684 skb->ip_summed, length); 1685 } 1686 /* return some buffers to hardware, one at a time is too slow */ 1687 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { 1688 pch_gbe_alloc_rx_buffers(adapter, rx_ring, 1689 cleaned_count); 1690 cleaned_count = 0; 1691 } 1692 if (++i == rx_ring->count) 1693 i = 0; 1694 } 1695 rx_ring->next_to_clean = i; 1696 if (cleaned_count) 1697 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); 1698 return cleaned; 1699} 1700 1701/** 1702 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors) 1703 * @adapter: Board private structure 1704 * @tx_ring: Tx descriptor ring (for a specific queue) to setup 1705 * Returns: 1706 * 0: Successfully 1707 * Negative value: Failed 1708 */ 1709int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter, 1710 struct pch_gbe_tx_ring *tx_ring) 1711{ 1712 struct pci_dev *pdev = adapter->pdev; 1713 struct pch_gbe_tx_desc *tx_desc; 1714 int size; 1715 int desNo; 1716 1717 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count; 1718 tx_ring->buffer_info = vzalloc(size); 1719 if (!tx_ring->buffer_info) 1720 return -ENOMEM; 1721 1722 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc); 1723 1724 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, 1725 &tx_ring->dma, GFP_KERNEL); 1726 if (!tx_ring->desc) { 1727 vfree(tx_ring->buffer_info); 1728 return -ENOMEM; 1729 } 1730 1731 tx_ring->next_to_use = 0; 1732 tx_ring->next_to_clean = 0; 1733 1734 for (desNo = 0; desNo < tx_ring->count; desNo++) { 1735 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo); 1736 tx_desc->gbec_status = DSC_INIT16; 1737 } 1738 netdev_dbg(adapter->netdev, 1739 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n", 1740 tx_ring->desc, (unsigned long long)tx_ring->dma, 1741 tx_ring->next_to_clean, tx_ring->next_to_use); 1742 return 0; 1743} 1744 1745/** 1746 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors) 1747 * @adapter: Board private structure 1748 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1749 * Returns: 1750 * 0: Successfully 1751 * Negative value: Failed 1752 */ 1753int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter, 1754 struct pch_gbe_rx_ring *rx_ring) 1755{ 1756 struct pci_dev *pdev = adapter->pdev; 1757 struct pch_gbe_rx_desc *rx_desc; 1758 int size; 1759 int desNo; 1760 1761 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count; 1762 rx_ring->buffer_info = vzalloc(size); 1763 if (!rx_ring->buffer_info) 1764 return -ENOMEM; 1765 1766 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc); 1767 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, 1768 &rx_ring->dma, GFP_KERNEL); 1769 if (!rx_ring->desc) { 1770 vfree(rx_ring->buffer_info); 1771 return -ENOMEM; 1772 } 1773 rx_ring->next_to_clean = 0; 1774 rx_ring->next_to_use = 0; 1775 for (desNo = 0; desNo < rx_ring->count; desNo++) { 1776 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo); 1777 rx_desc->gbec_status = DSC_INIT16; 1778 } 1779 netdev_dbg(adapter->netdev, 1780 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n", 1781 rx_ring->desc, (unsigned long long)rx_ring->dma, 1782 rx_ring->next_to_clean, rx_ring->next_to_use); 1783 return 0; 1784} 1785 1786/** 1787 * pch_gbe_free_tx_resources - Free Tx Resources 1788 * @adapter: Board private structure 1789 * @tx_ring: Tx descriptor ring for a specific queue 1790 */ 1791void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter, 1792 struct pch_gbe_tx_ring *tx_ring) 1793{ 1794 struct pci_dev *pdev = adapter->pdev; 1795 1796 pch_gbe_clean_tx_ring(adapter, tx_ring); 1797 vfree(tx_ring->buffer_info); 1798 tx_ring->buffer_info = NULL; 1799 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 1800 tx_ring->dma); 1801 tx_ring->desc = NULL; 1802} 1803 1804/** 1805 * pch_gbe_free_rx_resources - Free Rx Resources 1806 * @adapter: Board private structure 1807 * @rx_ring: Ring to clean the resources from 1808 */ 1809void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter, 1810 struct pch_gbe_rx_ring *rx_ring) 1811{ 1812 struct pci_dev *pdev = adapter->pdev; 1813 1814 pch_gbe_clean_rx_ring(adapter, rx_ring); 1815 vfree(rx_ring->buffer_info); 1816 rx_ring->buffer_info = NULL; 1817 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 1818 rx_ring->dma); 1819 rx_ring->desc = NULL; 1820} 1821 1822/** 1823 * pch_gbe_request_irq - Allocate an interrupt line 1824 * @adapter: Board private structure 1825 * Returns: 1826 * 0: Successfully 1827 * Negative value: Failed 1828 */ 1829static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter) 1830{ 1831 struct net_device *netdev = adapter->netdev; 1832 int err; 1833 1834 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1835 if (err < 0) 1836 return err; 1837 1838 adapter->irq = pci_irq_vector(adapter->pdev, 0); 1839 1840 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED, 1841 netdev->name, netdev); 1842 if (err) 1843 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n", 1844 err); 1845 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n", 1846 pci_dev_msi_enabled(adapter->pdev), err); 1847 return err; 1848} 1849 1850/** 1851 * pch_gbe_up - Up GbE network device 1852 * @adapter: Board private structure 1853 * Returns: 1854 * 0: Successfully 1855 * Negative value: Failed 1856 */ 1857int pch_gbe_up(struct pch_gbe_adapter *adapter) 1858{ 1859 struct net_device *netdev = adapter->netdev; 1860 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; 1861 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; 1862 int err = -EINVAL; 1863 1864 /* Ensure we have a valid MAC */ 1865 if (!is_valid_ether_addr(adapter->hw.mac.addr)) { 1866 netdev_err(netdev, "Error: Invalid MAC address\n"); 1867 goto out; 1868 } 1869 1870 /* hardware has been reset, we need to reload some things */ 1871 pch_gbe_set_multi(netdev); 1872 1873 pch_gbe_setup_tctl(adapter); 1874 pch_gbe_configure_tx(adapter); 1875 pch_gbe_setup_rctl(adapter); 1876 pch_gbe_configure_rx(adapter); 1877 1878 err = pch_gbe_request_irq(adapter); 1879 if (err) { 1880 netdev_err(netdev, 1881 "Error: can't bring device up - irq request failed\n"); 1882 goto out; 1883 } 1884 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count); 1885 if (err) { 1886 netdev_err(netdev, 1887 "Error: can't bring device up - alloc rx buffers pool failed\n"); 1888 goto freeirq; 1889 } 1890 pch_gbe_alloc_tx_buffers(adapter, tx_ring); 1891 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); 1892 adapter->tx_queue_len = netdev->tx_queue_len; 1893 pch_gbe_enable_dma_rx(&adapter->hw); 1894 pch_gbe_enable_mac_rx(&adapter->hw); 1895 1896 mod_timer(&adapter->watchdog_timer, jiffies); 1897 1898 napi_enable(&adapter->napi); 1899 pch_gbe_irq_enable(adapter); 1900 netif_start_queue(adapter->netdev); 1901 1902 return 0; 1903 1904freeirq: 1905 pch_gbe_free_irq(adapter); 1906out: 1907 return err; 1908} 1909 1910/** 1911 * pch_gbe_down - Down GbE network device 1912 * @adapter: Board private structure 1913 */ 1914void pch_gbe_down(struct pch_gbe_adapter *adapter) 1915{ 1916 struct net_device *netdev = adapter->netdev; 1917 struct pci_dev *pdev = adapter->pdev; 1918 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; 1919 1920 /* signal that we're down so the interrupt handler does not 1921 * reschedule our watchdog timer */ 1922 napi_disable(&adapter->napi); 1923 atomic_set(&adapter->irq_sem, 0); 1924 1925 pch_gbe_irq_disable(adapter); 1926 pch_gbe_free_irq(adapter); 1927 1928 timer_delete_sync(&adapter->watchdog_timer); 1929 1930 netdev->tx_queue_len = adapter->tx_queue_len; 1931 netif_carrier_off(netdev); 1932 netif_stop_queue(netdev); 1933 1934 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal)) 1935 pch_gbe_reset(adapter); 1936 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); 1937 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); 1938 1939 dma_free_coherent(&adapter->pdev->dev, rx_ring->rx_buff_pool_size, 1940 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic); 1941 rx_ring->rx_buff_pool_logic = 0; 1942 rx_ring->rx_buff_pool_size = 0; 1943 rx_ring->rx_buff_pool = NULL; 1944} 1945 1946/** 1947 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter) 1948 * @adapter: Board private structure to initialize 1949 * Returns: 1950 * 0: Successfully 1951 * Negative value: Failed 1952 */ 1953static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter) 1954{ 1955 struct pch_gbe_hw *hw = &adapter->hw; 1956 struct net_device *netdev = adapter->netdev; 1957 1958 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; 1959 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 1960 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 1961 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US; 1962 1963 if (pch_gbe_alloc_queues(adapter)) { 1964 netdev_err(netdev, "Unable to allocate memory for queues\n"); 1965 return -ENOMEM; 1966 } 1967 spin_lock_init(&adapter->hw.miim_lock); 1968 spin_lock_init(&adapter->stats_lock); 1969 spin_lock_init(&adapter->ethtool_lock); 1970 atomic_set(&adapter->irq_sem, 0); 1971 pch_gbe_irq_disable(adapter); 1972 1973 pch_gbe_init_stats(adapter); 1974 1975 netdev_dbg(netdev, 1976 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n", 1977 (u32) adapter->rx_buffer_len, 1978 hw->mac.min_frame_size, hw->mac.max_frame_size); 1979 return 0; 1980} 1981 1982/** 1983 * pch_gbe_open - Called when a network interface is made active 1984 * @netdev: Network interface device structure 1985 * Returns: 1986 * 0: Successfully 1987 * Negative value: Failed 1988 */ 1989static int pch_gbe_open(struct net_device *netdev) 1990{ 1991 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 1992 struct pch_gbe_hw *hw = &adapter->hw; 1993 int err; 1994 1995 /* allocate transmit descriptors */ 1996 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring); 1997 if (err) 1998 goto err_setup_tx; 1999 /* allocate receive descriptors */ 2000 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring); 2001 if (err) 2002 goto err_setup_rx; 2003 pch_gbe_phy_power_up(hw); 2004 err = pch_gbe_up(adapter); 2005 if (err) 2006 goto err_up; 2007 netdev_dbg(netdev, "Success End\n"); 2008 return 0; 2009 2010err_up: 2011 if (!adapter->wake_up_evt) 2012 pch_gbe_phy_power_down(hw); 2013 pch_gbe_free_rx_resources(adapter, adapter->rx_ring); 2014err_setup_rx: 2015 pch_gbe_free_tx_resources(adapter, adapter->tx_ring); 2016err_setup_tx: 2017 pch_gbe_reset(adapter); 2018 netdev_err(netdev, "Error End\n"); 2019 return err; 2020} 2021 2022/** 2023 * pch_gbe_stop - Disables a network interface 2024 * @netdev: Network interface device structure 2025 * Returns: 2026 * 0: Successfully 2027 */ 2028static int pch_gbe_stop(struct net_device *netdev) 2029{ 2030 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2031 struct pch_gbe_hw *hw = &adapter->hw; 2032 2033 pch_gbe_down(adapter); 2034 if (!adapter->wake_up_evt) 2035 pch_gbe_phy_power_down(hw); 2036 pch_gbe_free_tx_resources(adapter, adapter->tx_ring); 2037 pch_gbe_free_rx_resources(adapter, adapter->rx_ring); 2038 return 0; 2039} 2040 2041/** 2042 * pch_gbe_xmit_frame - Packet transmitting start 2043 * @skb: Socket buffer structure 2044 * @netdev: Network interface device structure 2045 * Returns: 2046 * - NETDEV_TX_OK: Normal end 2047 * - NETDEV_TX_BUSY: Error end 2048 */ 2049static netdev_tx_t pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2050{ 2051 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2052 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; 2053 2054 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) { 2055 netif_stop_queue(netdev); 2056 netdev_dbg(netdev, 2057 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n", 2058 tx_ring->next_to_use, tx_ring->next_to_clean); 2059 return NETDEV_TX_BUSY; 2060 } 2061 2062 /* CRC,ITAG no support */ 2063 pch_gbe_tx_queue(adapter, tx_ring, skb); 2064 return NETDEV_TX_OK; 2065} 2066 2067/** 2068 * pch_gbe_set_multi - Multicast and Promiscuous mode set 2069 * @netdev: Network interface device structure 2070 */ 2071static void pch_gbe_set_multi(struct net_device *netdev) 2072{ 2073 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2074 struct pch_gbe_hw *hw = &adapter->hw; 2075 struct netdev_hw_addr *ha; 2076 u32 rctl, adrmask; 2077 int mc_count, i; 2078 2079 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags); 2080 2081 /* By default enable address & multicast filtering */ 2082 rctl = ioread32(&hw->reg->RX_MODE); 2083 rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN; 2084 2085 /* Promiscuous mode disables all hardware address filtering */ 2086 if (netdev->flags & IFF_PROMISC) 2087 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN); 2088 2089 /* If we want to monitor more multicast addresses than the hardware can 2090 * support then disable hardware multicast filtering. 2091 */ 2092 mc_count = netdev_mc_count(netdev); 2093 if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES) 2094 rctl &= ~PCH_GBE_MLT_FIL_EN; 2095 2096 iowrite32(rctl, &hw->reg->RX_MODE); 2097 2098 /* If we're not using multicast filtering then there's no point 2099 * configuring the unused MAC address registers. 2100 */ 2101 if (!(rctl & PCH_GBE_MLT_FIL_EN)) 2102 return; 2103 2104 /* Load the first set of multicast addresses into MAC address registers 2105 * for use by hardware filtering. 2106 */ 2107 i = 1; 2108 netdev_for_each_mc_addr(ha, netdev) 2109 pch_gbe_mac_mar_set(hw, ha->addr, i++); 2110 2111 /* If there are spare MAC registers, mask & clear them */ 2112 for (; i < PCH_GBE_MAR_ENTRIES; i++) { 2113 /* Clear MAC address mask */ 2114 adrmask = ioread32(&hw->reg->ADDR_MASK); 2115 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK); 2116 /* wait busy */ 2117 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 2118 /* Clear MAC address */ 2119 iowrite32(0, &hw->reg->mac_adr[i].high); 2120 iowrite32(0, &hw->reg->mac_adr[i].low); 2121 } 2122 2123 netdev_dbg(netdev, 2124 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n", 2125 ioread32(&hw->reg->RX_MODE), mc_count); 2126} 2127 2128/** 2129 * pch_gbe_set_mac - Change the Ethernet Address of the NIC 2130 * @netdev: Network interface device structure 2131 * @addr: Pointer to an address structure 2132 * Returns: 2133 * 0: Successfully 2134 * -EADDRNOTAVAIL: Failed 2135 */ 2136static int pch_gbe_set_mac(struct net_device *netdev, void *addr) 2137{ 2138 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2139 struct sockaddr *skaddr = addr; 2140 int ret_val; 2141 2142 if (!is_valid_ether_addr(skaddr->sa_data)) { 2143 ret_val = -EADDRNOTAVAIL; 2144 } else { 2145 eth_hw_addr_set(netdev, skaddr->sa_data); 2146 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len); 2147 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2148 ret_val = 0; 2149 } 2150 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val); 2151 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr); 2152 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr); 2153 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n", 2154 ioread32(&adapter->hw.reg->mac_adr[0].high), 2155 ioread32(&adapter->hw.reg->mac_adr[0].low)); 2156 return ret_val; 2157} 2158 2159/** 2160 * pch_gbe_change_mtu - Change the Maximum Transfer Unit 2161 * @netdev: Network interface device structure 2162 * @new_mtu: New value for maximum frame size 2163 * Returns: 2164 * 0: Successfully 2165 * -EINVAL: Failed 2166 */ 2167static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) 2168{ 2169 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2170 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 2171 unsigned long old_rx_buffer_len = adapter->rx_buffer_len; 2172 int err; 2173 2174 if (max_frame <= PCH_GBE_FRAME_SIZE_2048) 2175 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; 2176 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096) 2177 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096; 2178 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) 2179 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; 2180 else 2181 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE; 2182 2183 if (netif_running(netdev)) { 2184 pch_gbe_down(adapter); 2185 err = pch_gbe_up(adapter); 2186 if (err) { 2187 adapter->rx_buffer_len = old_rx_buffer_len; 2188 pch_gbe_up(adapter); 2189 return err; 2190 } else { 2191 netdev->mtu = new_mtu; 2192 adapter->hw.mac.max_frame_size = max_frame; 2193 } 2194 } else { 2195 pch_gbe_reset(adapter); 2196 WRITE_ONCE(netdev->mtu, new_mtu); 2197 adapter->hw.mac.max_frame_size = max_frame; 2198 } 2199 2200 netdev_dbg(netdev, 2201 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", 2202 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, 2203 adapter->hw.mac.max_frame_size); 2204 return 0; 2205} 2206 2207/** 2208 * pch_gbe_set_features - Reset device after features changed 2209 * @netdev: Network interface device structure 2210 * @features: New features 2211 * Returns: 2212 * 0: HW state updated successfully 2213 */ 2214static int pch_gbe_set_features(struct net_device *netdev, 2215 netdev_features_t features) 2216{ 2217 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2218 netdev_features_t changed = features ^ netdev->features; 2219 2220 if (!(changed & NETIF_F_RXCSUM)) 2221 return 0; 2222 2223 if (netif_running(netdev)) 2224 pch_gbe_reinit_locked(adapter); 2225 else 2226 pch_gbe_reset(adapter); 2227 2228 return 0; 2229} 2230 2231/** 2232 * pch_gbe_ioctl - Controls register through a MII interface 2233 * @netdev: Network interface device structure 2234 * @ifr: Pointer to ifr structure 2235 * @cmd: Control command 2236 * Returns: 2237 * 0: Successfully 2238 * Negative value: Failed 2239 */ 2240static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2241{ 2242 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2243 2244 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd); 2245 2246 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); 2247} 2248 2249/** 2250 * pch_gbe_tx_timeout - Respond to a Tx Hang 2251 * @netdev: Network interface device structure 2252 * @txqueue: index of hanging queue 2253 */ 2254static void pch_gbe_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2255{ 2256 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2257 2258 /* Do the reset outside of interrupt context */ 2259 adapter->stats.tx_timeout_count++; 2260 schedule_work(&adapter->reset_task); 2261} 2262 2263/** 2264 * pch_gbe_napi_poll - NAPI receive and transfer polling callback 2265 * @napi: Pointer of polling device struct 2266 * @budget: The maximum number of a packet 2267 * Returns: 2268 * false: Exit the polling mode 2269 * true: Continue the polling mode 2270 */ 2271static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) 2272{ 2273 struct pch_gbe_adapter *adapter = 2274 container_of(napi, struct pch_gbe_adapter, napi); 2275 int work_done = 0; 2276 bool poll_end_flag = false; 2277 bool cleaned = false; 2278 2279 netdev_dbg(adapter->netdev, "budget : %d\n", budget); 2280 2281 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); 2282 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); 2283 2284 if (cleaned) 2285 work_done = budget; 2286 /* If no Tx and not enough Rx work done, 2287 * exit the polling mode 2288 */ 2289 if (work_done < budget) 2290 poll_end_flag = true; 2291 2292 if (poll_end_flag) { 2293 napi_complete_done(napi, work_done); 2294 pch_gbe_irq_enable(adapter); 2295 } 2296 2297 if (adapter->rx_stop_flag) { 2298 adapter->rx_stop_flag = false; 2299 pch_gbe_enable_dma_rx(&adapter->hw); 2300 } 2301 2302 netdev_dbg(adapter->netdev, 2303 "poll_end_flag : %d work_done : %d budget : %d\n", 2304 poll_end_flag, work_done, budget); 2305 2306 return work_done; 2307} 2308 2309#ifdef CONFIG_NET_POLL_CONTROLLER 2310/** 2311 * pch_gbe_netpoll - Used by things like netconsole to send skbs 2312 * @netdev: Network interface device structure 2313 */ 2314static void pch_gbe_netpoll(struct net_device *netdev) 2315{ 2316 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2317 2318 disable_irq(adapter->irq); 2319 pch_gbe_intr(adapter->irq, netdev); 2320 enable_irq(adapter->irq); 2321} 2322#endif 2323 2324static const struct net_device_ops pch_gbe_netdev_ops = { 2325 .ndo_open = pch_gbe_open, 2326 .ndo_stop = pch_gbe_stop, 2327 .ndo_start_xmit = pch_gbe_xmit_frame, 2328 .ndo_set_mac_address = pch_gbe_set_mac, 2329 .ndo_tx_timeout = pch_gbe_tx_timeout, 2330 .ndo_change_mtu = pch_gbe_change_mtu, 2331 .ndo_set_features = pch_gbe_set_features, 2332 .ndo_eth_ioctl = pch_gbe_ioctl, 2333 .ndo_set_rx_mode = pch_gbe_set_multi, 2334#ifdef CONFIG_NET_POLL_CONTROLLER 2335 .ndo_poll_controller = pch_gbe_netpoll, 2336#endif 2337 .ndo_hwtstamp_get = pch_gbe_hwtstamp_get, 2338 .ndo_hwtstamp_set = pch_gbe_hwtstamp_set, 2339}; 2340 2341static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev, 2342 pci_channel_state_t state) 2343{ 2344 struct net_device *netdev = pci_get_drvdata(pdev); 2345 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2346 2347 netif_device_detach(netdev); 2348 if (netif_running(netdev)) 2349 pch_gbe_down(adapter); 2350 pci_disable_device(pdev); 2351 /* Request a slot slot reset. */ 2352 return PCI_ERS_RESULT_NEED_RESET; 2353} 2354 2355static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev) 2356{ 2357 struct net_device *netdev = pci_get_drvdata(pdev); 2358 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2359 struct pch_gbe_hw *hw = &adapter->hw; 2360 2361 if (pci_enable_device(pdev)) { 2362 netdev_err(netdev, "Cannot re-enable PCI device after reset\n"); 2363 return PCI_ERS_RESULT_DISCONNECT; 2364 } 2365 pci_set_master(pdev); 2366 pci_enable_wake(pdev, PCI_D0, 0); 2367 pch_gbe_phy_power_up(hw); 2368 pch_gbe_reset(adapter); 2369 /* Clear wake up status */ 2370 pch_gbe_mac_set_wol_event(hw, 0); 2371 2372 return PCI_ERS_RESULT_RECOVERED; 2373} 2374 2375static void pch_gbe_io_resume(struct pci_dev *pdev) 2376{ 2377 struct net_device *netdev = pci_get_drvdata(pdev); 2378 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2379 2380 if (netif_running(netdev)) { 2381 if (pch_gbe_up(adapter)) { 2382 netdev_dbg(netdev, 2383 "can't bring device back up after reset\n"); 2384 return; 2385 } 2386 } 2387 netif_device_attach(netdev); 2388} 2389 2390static int __pch_gbe_suspend(struct pci_dev *pdev) 2391{ 2392 struct net_device *netdev = pci_get_drvdata(pdev); 2393 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2394 struct pch_gbe_hw *hw = &adapter->hw; 2395 u32 wufc = adapter->wake_up_evt; 2396 2397 netif_device_detach(netdev); 2398 if (netif_running(netdev)) 2399 pch_gbe_down(adapter); 2400 if (wufc) { 2401 pch_gbe_set_multi(netdev); 2402 pch_gbe_setup_rctl(adapter); 2403 pch_gbe_configure_rx(adapter); 2404 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, 2405 hw->mac.link_duplex); 2406 pch_gbe_set_mode(adapter, hw->mac.link_speed, 2407 hw->mac.link_duplex); 2408 pch_gbe_mac_set_wol_event(hw, wufc); 2409 pci_disable_device(pdev); 2410 } else { 2411 pch_gbe_phy_power_down(hw); 2412 pch_gbe_mac_set_wol_event(hw, wufc); 2413 pci_disable_device(pdev); 2414 } 2415 return 0; 2416} 2417 2418#ifdef CONFIG_PM 2419static int pch_gbe_suspend(struct device *device) 2420{ 2421 struct pci_dev *pdev = to_pci_dev(device); 2422 2423 return __pch_gbe_suspend(pdev); 2424} 2425 2426static int pch_gbe_resume(struct device *device) 2427{ 2428 struct pci_dev *pdev = to_pci_dev(device); 2429 struct net_device *netdev = pci_get_drvdata(pdev); 2430 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2431 struct pch_gbe_hw *hw = &adapter->hw; 2432 u32 err; 2433 2434 err = pci_enable_device(pdev); 2435 if (err) { 2436 netdev_err(netdev, "Cannot enable PCI device from suspend\n"); 2437 return err; 2438 } 2439 pci_set_master(pdev); 2440 pch_gbe_phy_power_up(hw); 2441 pch_gbe_reset(adapter); 2442 /* Clear wake on lan control and status */ 2443 pch_gbe_mac_set_wol_event(hw, 0); 2444 2445 if (netif_running(netdev)) 2446 pch_gbe_up(adapter); 2447 netif_device_attach(netdev); 2448 2449 return 0; 2450} 2451#endif /* CONFIG_PM */ 2452 2453static void pch_gbe_shutdown(struct pci_dev *pdev) 2454{ 2455 __pch_gbe_suspend(pdev); 2456 if (system_state == SYSTEM_POWER_OFF) { 2457 pci_wake_from_d3(pdev, true); 2458 pci_set_power_state(pdev, PCI_D3hot); 2459 } 2460} 2461 2462static void pch_gbe_remove(struct pci_dev *pdev) 2463{ 2464 struct net_device *netdev = pci_get_drvdata(pdev); 2465 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2466 2467 cancel_work_sync(&adapter->reset_task); 2468 unregister_netdev(netdev); 2469 2470 pch_gbe_phy_hw_reset(&adapter->hw); 2471 pci_dev_put(adapter->ptp_pdev); 2472 2473 free_netdev(netdev); 2474} 2475 2476static int pch_gbe_probe(struct pci_dev *pdev, 2477 const struct pci_device_id *pci_id) 2478{ 2479 struct net_device *netdev; 2480 struct pch_gbe_adapter *adapter; 2481 int ret; 2482 2483 ret = pcim_enable_device(pdev); 2484 if (ret) 2485 return ret; 2486 2487 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 2488 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2489 if (ret) { 2490 dev_err(&pdev->dev, "ERR: No usable DMA configuration, aborting\n"); 2491 return ret; 2492 } 2493 } 2494 2495 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev)); 2496 if (ret) { 2497 dev_err(&pdev->dev, 2498 "ERR: Can't reserve PCI I/O and memory resources\n"); 2499 return ret; 2500 } 2501 pci_set_master(pdev); 2502 2503 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter)); 2504 if (!netdev) 2505 return -ENOMEM; 2506 SET_NETDEV_DEV(netdev, &pdev->dev); 2507 2508 pci_set_drvdata(pdev, netdev); 2509 adapter = netdev_priv(netdev); 2510 adapter->netdev = netdev; 2511 adapter->pdev = pdev; 2512 adapter->hw.back = adapter; 2513 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR]; 2514 2515 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data; 2516 if (adapter->pdata && adapter->pdata->platform_init) { 2517 ret = adapter->pdata->platform_init(pdev); 2518 if (ret) 2519 goto err_free_netdev; 2520 } 2521 2522 adapter->ptp_pdev = 2523 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus), 2524 adapter->pdev->bus->number, 2525 PCI_DEVFN(12, 4)); 2526 2527 netdev->netdev_ops = &pch_gbe_netdev_ops; 2528 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD; 2529 netif_napi_add(netdev, &adapter->napi, pch_gbe_napi_poll); 2530 netdev->hw_features = NETIF_F_RXCSUM | 2531 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2532 netdev->features = netdev->hw_features; 2533 pch_gbe_set_ethtool_ops(netdev); 2534 2535 /* MTU range: 46 - 10300 */ 2536 netdev->min_mtu = ETH_ZLEN - ETH_HLEN; 2537 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE - 2538 (ETH_HLEN + ETH_FCS_LEN); 2539 2540 pch_gbe_mac_load_mac_addr(&adapter->hw); 2541 pch_gbe_mac_reset_hw(&adapter->hw); 2542 2543 /* setup the private structure */ 2544 ret = pch_gbe_sw_init(adapter); 2545 if (ret) 2546 goto err_put_dev; 2547 2548 /* Initialize PHY */ 2549 ret = pch_gbe_init_phy(adapter); 2550 if (ret) { 2551 dev_err(&pdev->dev, "PHY initialize error\n"); 2552 goto err_free_adapter; 2553 } 2554 2555 /* Read the MAC address. and store to the private data */ 2556 ret = pch_gbe_mac_read_mac_addr(&adapter->hw); 2557 if (ret) { 2558 dev_err(&pdev->dev, "MAC address Read Error\n"); 2559 goto err_free_adapter; 2560 } 2561 2562 eth_hw_addr_set(netdev, adapter->hw.mac.addr); 2563 if (!is_valid_ether_addr(netdev->dev_addr)) { 2564 /* 2565 * If the MAC is invalid (or just missing), display a warning 2566 * but do not abort setting up the device. pch_gbe_up will 2567 * prevent the interface from being brought up until a valid MAC 2568 * is set. 2569 */ 2570 dev_err(&pdev->dev, "Invalid MAC address, " 2571 "interface disabled.\n"); 2572 } 2573 timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0); 2574 2575 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task); 2576 2577 pch_gbe_check_options(adapter); 2578 2579 /* initialize the wol settings based on the eeprom settings */ 2580 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING; 2581 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr); 2582 2583 /* reset the hardware with the new settings */ 2584 pch_gbe_reset(adapter); 2585 2586 ret = register_netdev(netdev); 2587 if (ret) 2588 goto err_free_adapter; 2589 /* tell the stack to leave us alone until pch_gbe_open() is called */ 2590 netif_carrier_off(netdev); 2591 netif_stop_queue(netdev); 2592 2593 dev_dbg(&pdev->dev, "PCH Network Connection\n"); 2594 2595 /* Disable hibernation on certain platforms */ 2596 if (adapter->pdata && adapter->pdata->phy_disable_hibernate) 2597 pch_gbe_phy_disable_hibernate(&adapter->hw); 2598 2599 device_set_wakeup_enable(&pdev->dev, 1); 2600 return 0; 2601 2602err_free_adapter: 2603 pch_gbe_phy_hw_reset(&adapter->hw); 2604err_put_dev: 2605 pci_dev_put(adapter->ptp_pdev); 2606err_free_netdev: 2607 free_netdev(netdev); 2608 return ret; 2609} 2610 2611static void pch_gbe_gpio_remove_table(void *table) 2612{ 2613 gpiod_remove_lookup_table(table); 2614} 2615 2616static int pch_gbe_gpio_add_table(struct device *dev, void *table) 2617{ 2618 gpiod_add_lookup_table(table); 2619 return devm_add_action_or_reset(dev, pch_gbe_gpio_remove_table, table); 2620} 2621 2622static struct gpiod_lookup_table pch_gbe_minnow_gpio_table = { 2623 .dev_id = "0000:02:00.1", 2624 .table = { 2625 GPIO_LOOKUP("sch_gpio.33158", 13, NULL, GPIO_ACTIVE_LOW), 2626 {} 2627 }, 2628}; 2629 2630/* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to 2631 * ensure it is awake for probe and init. Request the line and reset the PHY. 2632 */ 2633static int pch_gbe_minnow_platform_init(struct pci_dev *pdev) 2634{ 2635 struct gpio_desc *gpiod; 2636 int ret; 2637 2638 ret = pch_gbe_gpio_add_table(&pdev->dev, &pch_gbe_minnow_gpio_table); 2639 if (ret) 2640 return ret; 2641 2642 gpiod = devm_gpiod_get(&pdev->dev, NULL, GPIOD_OUT_HIGH); 2643 if (IS_ERR(gpiod)) 2644 return dev_err_probe(&pdev->dev, PTR_ERR(gpiod), 2645 "Can't request PHY reset GPIO line\n"); 2646 2647 gpiod_set_value(gpiod, 1); 2648 usleep_range(1250, 1500); 2649 gpiod_set_value(gpiod, 0); 2650 usleep_range(1250, 1500); 2651 2652 return ret; 2653} 2654 2655static struct pch_gbe_privdata pch_gbe_minnow_privdata = { 2656 .phy_tx_clk_delay = true, 2657 .phy_disable_hibernate = true, 2658 .platform_init = pch_gbe_minnow_platform_init, 2659}; 2660 2661static const struct pci_device_id pch_gbe_pcidev_id[] = { 2662 {.vendor = PCI_VENDOR_ID_INTEL, 2663 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE, 2664 .subvendor = PCI_VENDOR_ID_CIRCUITCO, 2665 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD, 2666 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2667 .class_mask = (0xFFFF00), 2668 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata 2669 }, 2670 {.vendor = PCI_VENDOR_ID_INTEL, 2671 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE, 2672 .subvendor = PCI_ANY_ID, 2673 .subdevice = PCI_ANY_ID, 2674 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2675 .class_mask = (0xFFFF00) 2676 }, 2677 {.vendor = PCI_VENDOR_ID_ROHM, 2678 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE, 2679 .subvendor = PCI_ANY_ID, 2680 .subdevice = PCI_ANY_ID, 2681 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2682 .class_mask = (0xFFFF00) 2683 }, 2684 {.vendor = PCI_VENDOR_ID_ROHM, 2685 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE, 2686 .subvendor = PCI_ANY_ID, 2687 .subdevice = PCI_ANY_ID, 2688 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2689 .class_mask = (0xFFFF00) 2690 }, 2691 /* required last entry */ 2692 {0} 2693}; 2694 2695#ifdef CONFIG_PM 2696static const struct dev_pm_ops pch_gbe_pm_ops = { 2697 .suspend = pch_gbe_suspend, 2698 .resume = pch_gbe_resume, 2699 .freeze = pch_gbe_suspend, 2700 .thaw = pch_gbe_resume, 2701 .poweroff = pch_gbe_suspend, 2702 .restore = pch_gbe_resume, 2703}; 2704#endif 2705 2706static const struct pci_error_handlers pch_gbe_err_handler = { 2707 .error_detected = pch_gbe_io_error_detected, 2708 .slot_reset = pch_gbe_io_slot_reset, 2709 .resume = pch_gbe_io_resume 2710}; 2711 2712static struct pci_driver pch_gbe_driver = { 2713 .name = KBUILD_MODNAME, 2714 .id_table = pch_gbe_pcidev_id, 2715 .probe = pch_gbe_probe, 2716 .remove = pch_gbe_remove, 2717#ifdef CONFIG_PM 2718 .driver.pm = &pch_gbe_pm_ops, 2719#endif 2720 .shutdown = pch_gbe_shutdown, 2721 .err_handler = &pch_gbe_err_handler 2722}; 2723module_pci_driver(pch_gbe_driver); 2724 2725MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver"); 2726MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>"); 2727MODULE_LICENSE("GPL"); 2728MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id); 2729 2730/* pch_gbe_main.c */
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