forcedeth.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   4 *
   5 * Note: This driver is a cleanroom reimplementation based on reverse
   6 *      engineered documentation written by Carl-Daniel Hailfinger
   7 *      and Andrew de Quincey.
   8 *
   9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10 * trademarks of NVIDIA Corporation in the United States and other
  11 * countries.
  12 *
  13 * Copyright (C) 2003,4,5 Manfred Spraul
  14 * Copyright (C) 2004 Andrew de Quincey (wol support)
  15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16 *		IRQ rate fixes, bigendian fixes, cleanups, verification)
  17 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  18 *
  19 * Known bugs:
  20 * We suspect that on some hardware no TX done interrupts are generated.
  21 * This means recovery from netif_stop_queue only happens if the hw timer
  22 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  23 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  24 * If your hardware reliably generates tx done interrupts, then you can remove
  25 * DEV_NEED_TIMERIRQ from the driver_data flags.
  26 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  27 * superfluous timer interrupts from the nic.
  28 */
  29
  30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32#define FORCEDETH_VERSION		"0.64"
  33#define DRV_NAME			"forcedeth"
  34
  35#include <linux/module.h>
  36#include <linux/types.h>
  37#include <linux/pci.h>
  38#include <linux/interrupt.h>
  39#include <linux/netdevice.h>
  40#include <linux/etherdevice.h>
  41#include <linux/delay.h>
  42#include <linux/sched.h>
  43#include <linux/spinlock.h>
  44#include <linux/ethtool.h>
  45#include <linux/timer.h>
  46#include <linux/skbuff.h>
  47#include <linux/mii.h>
  48#include <linux/random.h>
  49#include <linux/if_vlan.h>
  50#include <linux/dma-mapping.h>
  51#include <linux/slab.h>
  52#include <linux/uaccess.h>
  53#include <linux/prefetch.h>
  54#include <linux/u64_stats_sync.h>
  55#include <linux/io.h>
  56
  57#include <asm/irq.h>
  58
  59#define TX_WORK_PER_LOOP  NAPI_POLL_WEIGHT
  60#define RX_WORK_PER_LOOP  NAPI_POLL_WEIGHT
  61
  62/*
  63 * Hardware access:
  64 */
  65
  66#define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  67#define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  68#define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  69#define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  70#define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  71#define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  72#define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  73#define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  74#define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  75#define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  76#define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  77#define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  78#define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  79#define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  80#define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  81#define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  82#define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  83#define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  84#define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  85#define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
  86#define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
  87#define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
  88#define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
  89#define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
  90#define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
  91#define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
  92#define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
  93
  94enum {
  95	NvRegIrqStatus = 0x000,
  96#define NVREG_IRQSTAT_MIIEVENT	0x040
  97#define NVREG_IRQSTAT_MASK		0x83ff
  98	NvRegIrqMask = 0x004,
  99#define NVREG_IRQ_RX_ERROR		0x0001
 100#define NVREG_IRQ_RX			0x0002
 101#define NVREG_IRQ_RX_NOBUF		0x0004
 102#define NVREG_IRQ_TX_ERR		0x0008
 103#define NVREG_IRQ_TX_OK			0x0010
 104#define NVREG_IRQ_TIMER			0x0020
 105#define NVREG_IRQ_LINK			0x0040
 106#define NVREG_IRQ_RX_FORCED		0x0080
 107#define NVREG_IRQ_TX_FORCED		0x0100
 108#define NVREG_IRQ_RECOVER_ERROR		0x8200
 109#define NVREG_IRQMASK_THROUGHPUT	0x00df
 110#define NVREG_IRQMASK_CPU		0x0060
 111#define NVREG_IRQ_TX_ALL		(NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 112#define NVREG_IRQ_RX_ALL		(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 113#define NVREG_IRQ_OTHER			(NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 114
 115	NvRegUnknownSetupReg6 = 0x008,
 116#define NVREG_UNKSETUP6_VAL		3
 117
 118/*
 119 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 120 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 121 */
 122	NvRegPollingInterval = 0x00c,
 123#define NVREG_POLL_DEFAULT_THROUGHPUT	65535 /* backup tx cleanup if loop max reached */
 124#define NVREG_POLL_DEFAULT_CPU	13
 125	NvRegMSIMap0 = 0x020,
 126	NvRegMSIMap1 = 0x024,
 127	NvRegMSIIrqMask = 0x030,
 128#define NVREG_MSI_VECTOR_0_ENABLED 0x01
 129	NvRegMisc1 = 0x080,
 130#define NVREG_MISC1_PAUSE_TX	0x01
 131#define NVREG_MISC1_HD		0x02
 132#define NVREG_MISC1_FORCE	0x3b0f3c
 133
 134	NvRegMacReset = 0x34,
 135#define NVREG_MAC_RESET_ASSERT	0x0F3
 136	NvRegTransmitterControl = 0x084,
 137#define NVREG_XMITCTL_START	0x01
 138#define NVREG_XMITCTL_MGMT_ST	0x40000000
 139#define NVREG_XMITCTL_SYNC_MASK		0x000f0000
 140#define NVREG_XMITCTL_SYNC_NOT_READY	0x0
 141#define NVREG_XMITCTL_SYNC_PHY_INIT	0x00040000
 142#define NVREG_XMITCTL_MGMT_SEMA_MASK	0x00000f00
 143#define NVREG_XMITCTL_MGMT_SEMA_FREE	0x0
 144#define NVREG_XMITCTL_HOST_SEMA_MASK	0x0000f000
 145#define NVREG_XMITCTL_HOST_SEMA_ACQ	0x0000f000
 146#define NVREG_XMITCTL_HOST_LOADED	0x00004000
 147#define NVREG_XMITCTL_TX_PATH_EN	0x01000000
 148#define NVREG_XMITCTL_DATA_START	0x00100000
 149#define NVREG_XMITCTL_DATA_READY	0x00010000
 150#define NVREG_XMITCTL_DATA_ERROR	0x00020000
 151	NvRegTransmitterStatus = 0x088,
 152#define NVREG_XMITSTAT_BUSY	0x01
 153
 154	NvRegPacketFilterFlags = 0x8c,
 155#define NVREG_PFF_PAUSE_RX	0x08
 156#define NVREG_PFF_ALWAYS	0x7F0000
 157#define NVREG_PFF_PROMISC	0x80
 158#define NVREG_PFF_MYADDR	0x20
 159#define NVREG_PFF_LOOPBACK	0x10
 160
 161	NvRegOffloadConfig = 0x90,
 162#define NVREG_OFFLOAD_HOMEPHY	0x601
 163#define NVREG_OFFLOAD_NORMAL	RX_NIC_BUFSIZE
 164	NvRegReceiverControl = 0x094,
 165#define NVREG_RCVCTL_START	0x01
 166#define NVREG_RCVCTL_RX_PATH_EN	0x01000000
 167	NvRegReceiverStatus = 0x98,
 168#define NVREG_RCVSTAT_BUSY	0x01
 169
 170	NvRegSlotTime = 0x9c,
 171#define NVREG_SLOTTIME_LEGBF_ENABLED	0x80000000
 172#define NVREG_SLOTTIME_10_100_FULL	0x00007f00
 173#define NVREG_SLOTTIME_1000_FULL	0x0003ff00
 174#define NVREG_SLOTTIME_HALF		0x0000ff00
 175#define NVREG_SLOTTIME_DEFAULT		0x00007f00
 176#define NVREG_SLOTTIME_MASK		0x000000ff
 177
 178	NvRegTxDeferral = 0xA0,
 179#define NVREG_TX_DEFERRAL_DEFAULT		0x15050f
 180#define NVREG_TX_DEFERRAL_RGMII_10_100		0x16070f
 181#define NVREG_TX_DEFERRAL_RGMII_1000		0x14050f
 182#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10	0x16190f
 183#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100	0x16300f
 184#define NVREG_TX_DEFERRAL_MII_STRETCH		0x152000
 185	NvRegRxDeferral = 0xA4,
 186#define NVREG_RX_DEFERRAL_DEFAULT	0x16
 187	NvRegMacAddrA = 0xA8,
 188	NvRegMacAddrB = 0xAC,
 189	NvRegMulticastAddrA = 0xB0,
 190#define NVREG_MCASTADDRA_FORCE	0x01
 191	NvRegMulticastAddrB = 0xB4,
 192	NvRegMulticastMaskA = 0xB8,
 193#define NVREG_MCASTMASKA_NONE		0xffffffff
 194	NvRegMulticastMaskB = 0xBC,
 195#define NVREG_MCASTMASKB_NONE		0xffff
 196
 197	NvRegPhyInterface = 0xC0,
 198#define PHY_RGMII		0x10000000
 199	NvRegBackOffControl = 0xC4,
 200#define NVREG_BKOFFCTRL_DEFAULT			0x70000000
 201#define NVREG_BKOFFCTRL_SEED_MASK		0x000003ff
 202#define NVREG_BKOFFCTRL_SELECT			24
 203#define NVREG_BKOFFCTRL_GEAR			12
 204
 205	NvRegTxRingPhysAddr = 0x100,
 206	NvRegRxRingPhysAddr = 0x104,
 207	NvRegRingSizes = 0x108,
 208#define NVREG_RINGSZ_TXSHIFT 0
 209#define NVREG_RINGSZ_RXSHIFT 16
 210	NvRegTransmitPoll = 0x10c,
 211#define NVREG_TRANSMITPOLL_MAC_ADDR_REV	0x00008000
 212	NvRegLinkSpeed = 0x110,
 213#define NVREG_LINKSPEED_FORCE 0x10000
 214#define NVREG_LINKSPEED_10	1000
 215#define NVREG_LINKSPEED_100	100
 216#define NVREG_LINKSPEED_1000	50
 217#define NVREG_LINKSPEED_MASK	(0xFFF)
 218	NvRegUnknownSetupReg5 = 0x130,
 219#define NVREG_UNKSETUP5_BIT31	(1<<31)
 220	NvRegTxWatermark = 0x13c,
 221#define NVREG_TX_WM_DESC1_DEFAULT	0x0200010
 222#define NVREG_TX_WM_DESC2_3_DEFAULT	0x1e08000
 223#define NVREG_TX_WM_DESC2_3_1000	0xfe08000
 224	NvRegTxRxControl = 0x144,
 225#define NVREG_TXRXCTL_KICK	0x0001
 226#define NVREG_TXRXCTL_BIT1	0x0002
 227#define NVREG_TXRXCTL_BIT2	0x0004
 228#define NVREG_TXRXCTL_IDLE	0x0008
 229#define NVREG_TXRXCTL_RESET	0x0010
 230#define NVREG_TXRXCTL_RXCHECK	0x0400
 231#define NVREG_TXRXCTL_DESC_1	0
 232#define NVREG_TXRXCTL_DESC_2	0x002100
 233#define NVREG_TXRXCTL_DESC_3	0xc02200
 234#define NVREG_TXRXCTL_VLANSTRIP 0x00040
 235#define NVREG_TXRXCTL_VLANINS	0x00080
 236	NvRegTxRingPhysAddrHigh = 0x148,
 237	NvRegRxRingPhysAddrHigh = 0x14C,
 238	NvRegTxPauseFrame = 0x170,
 239#define NVREG_TX_PAUSEFRAME_DISABLE	0x0fff0080
 240#define NVREG_TX_PAUSEFRAME_ENABLE_V1	0x01800010
 241#define NVREG_TX_PAUSEFRAME_ENABLE_V2	0x056003f0
 242#define NVREG_TX_PAUSEFRAME_ENABLE_V3	0x09f00880
 243	NvRegTxPauseFrameLimit = 0x174,
 244#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE	0x00010000
 245	NvRegMIIStatus = 0x180,
 246#define NVREG_MIISTAT_ERROR		0x0001
 247#define NVREG_MIISTAT_LINKCHANGE	0x0008
 248#define NVREG_MIISTAT_MASK_RW		0x0007
 249#define NVREG_MIISTAT_MASK_ALL		0x000f
 250	NvRegMIIMask = 0x184,
 251#define NVREG_MII_LINKCHANGE		0x0008
 252
 253	NvRegAdapterControl = 0x188,
 254#define NVREG_ADAPTCTL_START	0x02
 255#define NVREG_ADAPTCTL_LINKUP	0x04
 256#define NVREG_ADAPTCTL_PHYVALID	0x40000
 257#define NVREG_ADAPTCTL_RUNNING	0x100000
 258#define NVREG_ADAPTCTL_PHYSHIFT	24
 259	NvRegMIISpeed = 0x18c,
 260#define NVREG_MIISPEED_BIT8	(1<<8)
 261#define NVREG_MIIDELAY	5
 262	NvRegMIIControl = 0x190,
 263#define NVREG_MIICTL_INUSE	0x08000
 264#define NVREG_MIICTL_WRITE	0x00400
 265#define NVREG_MIICTL_ADDRSHIFT	5
 266	NvRegMIIData = 0x194,
 267	NvRegTxUnicast = 0x1a0,
 268	NvRegTxMulticast = 0x1a4,
 269	NvRegTxBroadcast = 0x1a8,
 270	NvRegWakeUpFlags = 0x200,
 271#define NVREG_WAKEUPFLAGS_VAL		0x7770
 272#define NVREG_WAKEUPFLAGS_BUSYSHIFT	24
 273#define NVREG_WAKEUPFLAGS_ENABLESHIFT	16
 274#define NVREG_WAKEUPFLAGS_D3SHIFT	12
 275#define NVREG_WAKEUPFLAGS_D2SHIFT	8
 276#define NVREG_WAKEUPFLAGS_D1SHIFT	4
 277#define NVREG_WAKEUPFLAGS_D0SHIFT	0
 278#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT		0x01
 279#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT	0x02
 280#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE	0x04
 281#define NVREG_WAKEUPFLAGS_ENABLE	0x1111
 282
 283	NvRegMgmtUnitGetVersion = 0x204,
 284#define NVREG_MGMTUNITGETVERSION	0x01
 285	NvRegMgmtUnitVersion = 0x208,
 286#define NVREG_MGMTUNITVERSION		0x08
 287	NvRegPowerCap = 0x268,
 288#define NVREG_POWERCAP_D3SUPP	(1<<30)
 289#define NVREG_POWERCAP_D2SUPP	(1<<26)
 290#define NVREG_POWERCAP_D1SUPP	(1<<25)
 291	NvRegPowerState = 0x26c,
 292#define NVREG_POWERSTATE_POWEREDUP	0x8000
 293#define NVREG_POWERSTATE_VALID		0x0100
 294#define NVREG_POWERSTATE_MASK		0x0003
 295#define NVREG_POWERSTATE_D0		0x0000
 296#define NVREG_POWERSTATE_D1		0x0001
 297#define NVREG_POWERSTATE_D2		0x0002
 298#define NVREG_POWERSTATE_D3		0x0003
 299	NvRegMgmtUnitControl = 0x278,
 300#define NVREG_MGMTUNITCONTROL_INUSE	0x20000
 301	NvRegTxCnt = 0x280,
 302	NvRegTxZeroReXmt = 0x284,
 303	NvRegTxOneReXmt = 0x288,
 304	NvRegTxManyReXmt = 0x28c,
 305	NvRegTxLateCol = 0x290,
 306	NvRegTxUnderflow = 0x294,
 307	NvRegTxLossCarrier = 0x298,
 308	NvRegTxExcessDef = 0x29c,
 309	NvRegTxRetryErr = 0x2a0,
 310	NvRegRxFrameErr = 0x2a4,
 311	NvRegRxExtraByte = 0x2a8,
 312	NvRegRxLateCol = 0x2ac,
 313	NvRegRxRunt = 0x2b0,
 314	NvRegRxFrameTooLong = 0x2b4,
 315	NvRegRxOverflow = 0x2b8,
 316	NvRegRxFCSErr = 0x2bc,
 317	NvRegRxFrameAlignErr = 0x2c0,
 318	NvRegRxLenErr = 0x2c4,
 319	NvRegRxUnicast = 0x2c8,
 320	NvRegRxMulticast = 0x2cc,
 321	NvRegRxBroadcast = 0x2d0,
 322	NvRegTxDef = 0x2d4,
 323	NvRegTxFrame = 0x2d8,
 324	NvRegRxCnt = 0x2dc,
 325	NvRegTxPause = 0x2e0,
 326	NvRegRxPause = 0x2e4,
 327	NvRegRxDropFrame = 0x2e8,
 328	NvRegVlanControl = 0x300,
 329#define NVREG_VLANCONTROL_ENABLE	0x2000
 330	NvRegMSIXMap0 = 0x3e0,
 331	NvRegMSIXMap1 = 0x3e4,
 332	NvRegMSIXIrqStatus = 0x3f0,
 333
 334	NvRegPowerState2 = 0x600,
 335#define NVREG_POWERSTATE2_POWERUP_MASK		0x0F15
 336#define NVREG_POWERSTATE2_POWERUP_REV_A3	0x0001
 337#define NVREG_POWERSTATE2_PHY_RESET		0x0004
 338#define NVREG_POWERSTATE2_GATE_CLOCKS		0x0F00
 339};
 340
 341/* Big endian: should work, but is untested */
 342struct ring_desc {
 343	__le32 buf;
 344	__le32 flaglen;
 345};
 346
 347struct ring_desc_ex {
 348	__le32 bufhigh;
 349	__le32 buflow;
 350	__le32 txvlan;
 351	__le32 flaglen;
 352};
 353
 354union ring_type {
 355	struct ring_desc *orig;
 356	struct ring_desc_ex *ex;
 357};
 358
 359#define FLAG_MASK_V1 0xffff0000
 360#define FLAG_MASK_V2 0xffffc000
 361#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 362#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 363
 364#define NV_TX_LASTPACKET	(1<<16)
 365#define NV_TX_RETRYERROR	(1<<19)
 366#define NV_TX_RETRYCOUNT_MASK	(0xF<<20)
 367#define NV_TX_FORCED_INTERRUPT	(1<<24)
 368#define NV_TX_DEFERRED		(1<<26)
 369#define NV_TX_CARRIERLOST	(1<<27)
 370#define NV_TX_LATECOLLISION	(1<<28)
 371#define NV_TX_UNDERFLOW		(1<<29)
 372#define NV_TX_ERROR		(1<<30)
 373#define NV_TX_VALID		(1<<31)
 374
 375#define NV_TX2_LASTPACKET	(1<<29)
 376#define NV_TX2_RETRYERROR	(1<<18)
 377#define NV_TX2_RETRYCOUNT_MASK	(0xF<<19)
 378#define NV_TX2_FORCED_INTERRUPT	(1<<30)
 379#define NV_TX2_DEFERRED		(1<<25)
 380#define NV_TX2_CARRIERLOST	(1<<26)
 381#define NV_TX2_LATECOLLISION	(1<<27)
 382#define NV_TX2_UNDERFLOW	(1<<28)
 383/* error and valid are the same for both */
 384#define NV_TX2_ERROR		(1<<30)
 385#define NV_TX2_VALID		(1<<31)
 386#define NV_TX2_TSO		(1<<28)
 387#define NV_TX2_TSO_SHIFT	14
 388#define NV_TX2_TSO_MAX_SHIFT	14
 389#define NV_TX2_TSO_MAX_SIZE	(1<<NV_TX2_TSO_MAX_SHIFT)
 390#define NV_TX2_CHECKSUM_L3	(1<<27)
 391#define NV_TX2_CHECKSUM_L4	(1<<26)
 392
 393#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 394
 395#define NV_RX_DESCRIPTORVALID	(1<<16)
 396#define NV_RX_MISSEDFRAME	(1<<17)
 397#define NV_RX_SUBTRACT1		(1<<18)
 398#define NV_RX_ERROR1		(1<<23)
 399#define NV_RX_ERROR2		(1<<24)
 400#define NV_RX_ERROR3		(1<<25)
 401#define NV_RX_ERROR4		(1<<26)
 402#define NV_RX_CRCERR		(1<<27)
 403#define NV_RX_OVERFLOW		(1<<28)
 404#define NV_RX_FRAMINGERR	(1<<29)
 405#define NV_RX_ERROR		(1<<30)
 406#define NV_RX_AVAIL		(1<<31)
 407#define NV_RX_ERROR_MASK	(NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 408
 409#define NV_RX2_CHECKSUMMASK	(0x1C000000)
 410#define NV_RX2_CHECKSUM_IP	(0x10000000)
 411#define NV_RX2_CHECKSUM_IP_TCP	(0x14000000)
 412#define NV_RX2_CHECKSUM_IP_UDP	(0x18000000)
 413#define NV_RX2_DESCRIPTORVALID	(1<<29)
 414#define NV_RX2_SUBTRACT1	(1<<25)
 415#define NV_RX2_ERROR1		(1<<18)
 416#define NV_RX2_ERROR2		(1<<19)
 417#define NV_RX2_ERROR3		(1<<20)
 418#define NV_RX2_ERROR4		(1<<21)
 419#define NV_RX2_CRCERR		(1<<22)
 420#define NV_RX2_OVERFLOW		(1<<23)
 421#define NV_RX2_FRAMINGERR	(1<<24)
 422/* error and avail are the same for both */
 423#define NV_RX2_ERROR		(1<<30)
 424#define NV_RX2_AVAIL		(1<<31)
 425#define NV_RX2_ERROR_MASK	(NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 426
 427#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 428#define NV_RX3_VLAN_TAG_MASK	(0x0000FFFF)
 429
 430/* Miscellaneous hardware related defines: */
 431#define NV_PCI_REGSZ_VER1	0x270
 432#define NV_PCI_REGSZ_VER2	0x2d4
 433#define NV_PCI_REGSZ_VER3	0x604
 434#define NV_PCI_REGSZ_MAX	0x604
 435
 436/* various timeout delays: all in usec */
 437#define NV_TXRX_RESET_DELAY	4
 438#define NV_TXSTOP_DELAY1	10
 439#define NV_TXSTOP_DELAY1MAX	500000
 440#define NV_TXSTOP_DELAY2	100
 441#define NV_RXSTOP_DELAY1	10
 442#define NV_RXSTOP_DELAY1MAX	500000
 443#define NV_RXSTOP_DELAY2	100
 444#define NV_SETUP5_DELAY		5
 445#define NV_SETUP5_DELAYMAX	50000
 446#define NV_POWERUP_DELAY	5
 447#define NV_POWERUP_DELAYMAX	5000
 448#define NV_MIIBUSY_DELAY	50
 449#define NV_MIIPHY_DELAY	10
 450#define NV_MIIPHY_DELAYMAX	10000
 451#define NV_MAC_RESET_DELAY	64
 452
 453#define NV_WAKEUPPATTERNS	5
 454#define NV_WAKEUPMASKENTRIES	4
 455
 456/* General driver defaults */
 457#define NV_WATCHDOG_TIMEO	(5*HZ)
 458
 459#define RX_RING_DEFAULT		512
 460#define TX_RING_DEFAULT		256
 461#define RX_RING_MIN		128
 462#define TX_RING_MIN		64
 463#define RING_MAX_DESC_VER_1	1024
 464#define RING_MAX_DESC_VER_2_3	16384
 465
 466/* rx/tx mac addr + type + vlan + align + slack*/
 467#define NV_RX_HEADERS		(64)
 468/* even more slack. */
 469#define NV_RX_ALLOC_PAD		(64)
 470
 471/* maximum mtu size */
 472#define NV_PKTLIMIT_1	ETH_DATA_LEN	/* hard limit not known */
 473#define NV_PKTLIMIT_2	9100	/* Actual limit according to NVidia: 9202 */
 474
 475#define OOM_REFILL	(1+HZ/20)
 476#define POLL_WAIT	(1+HZ/100)
 477#define LINK_TIMEOUT	(3*HZ)
 478#define STATS_INTERVAL	(10*HZ)
 479
 480/*
 481 * desc_ver values:
 482 * The nic supports three different descriptor types:
 483 * - DESC_VER_1: Original
 484 * - DESC_VER_2: support for jumbo frames.
 485 * - DESC_VER_3: 64-bit format.
 486 */
 487#define DESC_VER_1	1
 488#define DESC_VER_2	2
 489#define DESC_VER_3	3
 490
 491/* PHY defines */
 492#define PHY_OUI_MARVELL		0x5043
 493#define PHY_OUI_CICADA		0x03f1
 494#define PHY_OUI_VITESSE		0x01c1
 495#define PHY_OUI_REALTEK		0x0732
 496#define PHY_OUI_REALTEK2	0x0020
 497#define PHYID1_OUI_MASK	0x03ff
 498#define PHYID1_OUI_SHFT	6
 499#define PHYID2_OUI_MASK	0xfc00
 500#define PHYID2_OUI_SHFT	10
 501#define PHYID2_MODEL_MASK		0x03f0
 502#define PHY_MODEL_REALTEK_8211		0x0110
 503#define PHY_REV_MASK			0x0001
 504#define PHY_REV_REALTEK_8211B		0x0000
 505#define PHY_REV_REALTEK_8211C		0x0001
 506#define PHY_MODEL_REALTEK_8201		0x0200
 507#define PHY_MODEL_MARVELL_E3016		0x0220
 508#define PHY_MARVELL_E3016_INITMASK	0x0300
 509#define PHY_CICADA_INIT1	0x0f000
 510#define PHY_CICADA_INIT2	0x0e00
 511#define PHY_CICADA_INIT3	0x01000
 512#define PHY_CICADA_INIT4	0x0200
 513#define PHY_CICADA_INIT5	0x0004
 514#define PHY_CICADA_INIT6	0x02000
 515#define PHY_VITESSE_INIT_REG1	0x1f
 516#define PHY_VITESSE_INIT_REG2	0x10
 517#define PHY_VITESSE_INIT_REG3	0x11
 518#define PHY_VITESSE_INIT_REG4	0x12
 519#define PHY_VITESSE_INIT_MSK1	0xc
 520#define PHY_VITESSE_INIT_MSK2	0x0180
 521#define PHY_VITESSE_INIT1	0x52b5
 522#define PHY_VITESSE_INIT2	0xaf8a
 523#define PHY_VITESSE_INIT3	0x8
 524#define PHY_VITESSE_INIT4	0x8f8a
 525#define PHY_VITESSE_INIT5	0xaf86
 526#define PHY_VITESSE_INIT6	0x8f86
 527#define PHY_VITESSE_INIT7	0xaf82
 528#define PHY_VITESSE_INIT8	0x0100
 529#define PHY_VITESSE_INIT9	0x8f82
 530#define PHY_VITESSE_INIT10	0x0
 531#define PHY_REALTEK_INIT_REG1	0x1f
 532#define PHY_REALTEK_INIT_REG2	0x19
 533#define PHY_REALTEK_INIT_REG3	0x13
 534#define PHY_REALTEK_INIT_REG4	0x14
 535#define PHY_REALTEK_INIT_REG5	0x18
 536#define PHY_REALTEK_INIT_REG6	0x11
 537#define PHY_REALTEK_INIT_REG7	0x01
 538#define PHY_REALTEK_INIT1	0x0000
 539#define PHY_REALTEK_INIT2	0x8e00
 540#define PHY_REALTEK_INIT3	0x0001
 541#define PHY_REALTEK_INIT4	0xad17
 542#define PHY_REALTEK_INIT5	0xfb54
 543#define PHY_REALTEK_INIT6	0xf5c7
 544#define PHY_REALTEK_INIT7	0x1000
 545#define PHY_REALTEK_INIT8	0x0003
 546#define PHY_REALTEK_INIT9	0x0008
 547#define PHY_REALTEK_INIT10	0x0005
 548#define PHY_REALTEK_INIT11	0x0200
 549#define PHY_REALTEK_INIT_MSK1	0x0003
 550
 551#define PHY_GIGABIT	0x0100
 552
 553#define PHY_TIMEOUT	0x1
 554#define PHY_ERROR	0x2
 555
 556#define PHY_100	0x1
 557#define PHY_1000	0x2
 558#define PHY_HALF	0x100
 559
 560#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 561#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 562#define NV_PAUSEFRAME_RX_ENABLE  0x0004
 563#define NV_PAUSEFRAME_TX_ENABLE  0x0008
 564#define NV_PAUSEFRAME_RX_REQ     0x0010
 565#define NV_PAUSEFRAME_TX_REQ     0x0020
 566#define NV_PAUSEFRAME_AUTONEG    0x0040
 567
 568/* MSI/MSI-X defines */
 569#define NV_MSI_X_MAX_VECTORS  8
 570#define NV_MSI_X_VECTORS_MASK 0x000f
 571#define NV_MSI_CAPABLE        0x0010
 572#define NV_MSI_X_CAPABLE      0x0020
 573#define NV_MSI_ENABLED        0x0040
 574#define NV_MSI_X_ENABLED      0x0080
 575
 576#define NV_MSI_X_VECTOR_ALL   0x0
 577#define NV_MSI_X_VECTOR_RX    0x0
 578#define NV_MSI_X_VECTOR_TX    0x1
 579#define NV_MSI_X_VECTOR_OTHER 0x2
 580
 581#define NV_MSI_PRIV_OFFSET 0x68
 582#define NV_MSI_PRIV_VALUE  0xffffffff
 583
 584#define NV_RESTART_TX         0x1
 585#define NV_RESTART_RX         0x2
 586
 587#define NV_TX_LIMIT_COUNT     16
 588
 589#define NV_DYNAMIC_THRESHOLD        4
 590#define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 591
 592/* statistics */
 593struct nv_ethtool_str {
 594	char name[ETH_GSTRING_LEN];
 595};
 596
 597static const struct nv_ethtool_str nv_estats_str[] = {
 598	{ "tx_bytes" }, /* includes Ethernet FCS CRC */
 599	{ "tx_zero_rexmt" },
 600	{ "tx_one_rexmt" },
 601	{ "tx_many_rexmt" },
 602	{ "tx_late_collision" },
 603	{ "tx_fifo_errors" },
 604	{ "tx_carrier_errors" },
 605	{ "tx_excess_deferral" },
 606	{ "tx_retry_error" },
 607	{ "rx_frame_error" },
 608	{ "rx_extra_byte" },
 609	{ "rx_late_collision" },
 610	{ "rx_runt" },
 611	{ "rx_frame_too_long" },
 612	{ "rx_over_errors" },
 613	{ "rx_crc_errors" },
 614	{ "rx_frame_align_error" },
 615	{ "rx_length_error" },
 616	{ "rx_unicast" },
 617	{ "rx_multicast" },
 618	{ "rx_broadcast" },
 619	{ "rx_packets" },
 620	{ "rx_errors_total" },
 621	{ "tx_errors_total" },
 622
 623	/* version 2 stats */
 624	{ "tx_deferral" },
 625	{ "tx_packets" },
 626	{ "rx_bytes" }, /* includes Ethernet FCS CRC */
 627	{ "tx_pause" },
 628	{ "rx_pause" },
 629	{ "rx_drop_frame" },
 630
 631	/* version 3 stats */
 632	{ "tx_unicast" },
 633	{ "tx_multicast" },
 634	{ "tx_broadcast" }
 635};
 636
 637struct nv_ethtool_stats {
 638	u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
 639	u64 tx_zero_rexmt;
 640	u64 tx_one_rexmt;
 641	u64 tx_many_rexmt;
 642	u64 tx_late_collision;
 643	u64 tx_fifo_errors;
 644	u64 tx_carrier_errors;
 645	u64 tx_excess_deferral;
 646	u64 tx_retry_error;
 647	u64 rx_frame_error;
 648	u64 rx_extra_byte;
 649	u64 rx_late_collision;
 650	u64 rx_runt;
 651	u64 rx_frame_too_long;
 652	u64 rx_over_errors;
 653	u64 rx_crc_errors;
 654	u64 rx_frame_align_error;
 655	u64 rx_length_error;
 656	u64 rx_unicast;
 657	u64 rx_multicast;
 658	u64 rx_broadcast;
 659	u64 rx_packets; /* should be ifconfig->rx_packets */
 660	u64 rx_errors_total;
 661	u64 tx_errors_total;
 662
 663	/* version 2 stats */
 664	u64 tx_deferral;
 665	u64 tx_packets; /* should be ifconfig->tx_packets */
 666	u64 rx_bytes;   /* should be ifconfig->rx_bytes + 4*rx_packets */
 667	u64 tx_pause;
 668	u64 rx_pause;
 669	u64 rx_drop_frame;
 670
 671	/* version 3 stats */
 672	u64 tx_unicast;
 673	u64 tx_multicast;
 674	u64 tx_broadcast;
 675};
 676
 677#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 678#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 679#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 680
 681/* diagnostics */
 682#define NV_TEST_COUNT_BASE 3
 683#define NV_TEST_COUNT_EXTENDED 4
 684
 685static const struct nv_ethtool_str nv_etests_str[] = {
 686	{ "link      (online/offline)" },
 687	{ "register  (offline)       " },
 688	{ "interrupt (offline)       " },
 689	{ "loopback  (offline)       " }
 690};
 691
 692struct register_test {
 693	__u32 reg;
 694	__u32 mask;
 695};
 696
 697static const struct register_test nv_registers_test[] = {
 698	{ NvRegUnknownSetupReg6, 0x01 },
 699	{ NvRegMisc1, 0x03c },
 700	{ NvRegOffloadConfig, 0x03ff },
 701	{ NvRegMulticastAddrA, 0xffffffff },
 702	{ NvRegTxWatermark, 0x0ff },
 703	{ NvRegWakeUpFlags, 0x07777 },
 704	{ 0, 0 }
 705};
 706
 707struct nv_skb_map {
 708	struct sk_buff *skb;
 709	dma_addr_t dma;
 710	unsigned int dma_len:31;
 711	unsigned int dma_single:1;
 712	struct ring_desc_ex *first_tx_desc;
 713	struct nv_skb_map *next_tx_ctx;
 714};
 715
 716struct nv_txrx_stats {
 717	u64 stat_rx_packets;
 718	u64 stat_rx_bytes; /* not always available in HW */
 719	u64 stat_rx_missed_errors;
 720	u64 stat_rx_dropped;
 721	u64 stat_tx_packets; /* not always available in HW */
 722	u64 stat_tx_bytes;
 723	u64 stat_tx_dropped;
 724};
 725
 726#define nv_txrx_stats_inc(member) \
 727		__this_cpu_inc(np->txrx_stats->member)
 728#define nv_txrx_stats_add(member, count) \
 729		__this_cpu_add(np->txrx_stats->member, (count))
 730
 731/*
 732 * SMP locking:
 733 * All hardware access under netdev_priv(dev)->lock, except the performance
 734 * critical parts:
 735 * - rx is (pseudo-) lockless: it relies on the single-threading provided
 736 *	by the arch code for interrupts.
 737 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 738 *	needs netdev_priv(dev)->lock :-(
 739 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 740 *
 741 * Hardware stats updates are protected by hwstats_lock:
 742 * - updated by nv_do_stats_poll (timer). This is meant to avoid
 743 *   integer wraparound in the NIC stats registers, at low frequency
 744 *   (0.1 Hz)
 745 * - updated by nv_get_ethtool_stats + nv_get_stats64
 746 *
 747 * Software stats are accessed only through 64b synchronization points
 748 * and are not subject to other synchronization techniques (single
 749 * update thread on the TX or RX paths).
 750 */
 751
 752/* in dev: base, irq */
 753struct fe_priv {
 754	spinlock_t lock;
 755
 756	struct net_device *dev;
 757	struct napi_struct napi;
 758
 759	/* hardware stats are updated in syscall and timer */
 760	spinlock_t hwstats_lock;
 761	struct nv_ethtool_stats estats;
 762
 763	int in_shutdown;
 764	u32 linkspeed;
 765	int duplex;
 766	int autoneg;
 767	int fixed_mode;
 768	int phyaddr;
 769	int wolenabled;
 770	unsigned int phy_oui;
 771	unsigned int phy_model;
 772	unsigned int phy_rev;
 773	u16 gigabit;
 774	int intr_test;
 775	int recover_error;
 776	int quiet_count;
 777
 778	/* General data: RO fields */
 779	dma_addr_t ring_addr;
 780	struct pci_dev *pci_dev;
 781	u32 orig_mac[2];
 782	u32 events;
 783	u32 irqmask;
 784	u32 desc_ver;
 785	u32 txrxctl_bits;
 786	u32 vlanctl_bits;
 787	u32 driver_data;
 788	u32 device_id;
 789	u32 register_size;
 790	u32 mac_in_use;
 791	int mgmt_version;
 792	int mgmt_sema;
 793
 794	void __iomem *base;
 795
 796	/* rx specific fields.
 797	 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 798	 */
 799	union ring_type get_rx, put_rx, last_rx;
 800	struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 801	struct nv_skb_map *last_rx_ctx;
 802	struct nv_skb_map *rx_skb;
 803
 804	union ring_type rx_ring;
 805	unsigned int rx_buf_sz;
 806	unsigned int pkt_limit;
 807	struct timer_list oom_kick;
 808	struct timer_list nic_poll;
 809	struct timer_list stats_poll;
 810	u32 nic_poll_irq;
 811	int rx_ring_size;
 812
 813	/* RX software stats */
 814	struct u64_stats_sync swstats_rx_syncp;
 815	struct nv_txrx_stats __percpu *txrx_stats;
 816
 817	/* media detection workaround.
 818	 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 819	 */
 820	int need_linktimer;
 821	unsigned long link_timeout;
 822	/*
 823	 * tx specific fields.
 824	 */
 825	union ring_type get_tx, put_tx, last_tx;
 826	struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 827	struct nv_skb_map *last_tx_ctx;
 828	struct nv_skb_map *tx_skb;
 829
 830	union ring_type tx_ring;
 831	u32 tx_flags;
 832	int tx_ring_size;
 833	int tx_limit;
 834	u32 tx_pkts_in_progress;
 835	struct nv_skb_map *tx_change_owner;
 836	struct nv_skb_map *tx_end_flip;
 837	int tx_stop;
 838
 839	/* TX software stats */
 840	struct u64_stats_sync swstats_tx_syncp;
 841
 842	/* msi/msi-x fields */
 843	u32 msi_flags;
 844	struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 845
 846	/* flow control */
 847	u32 pause_flags;
 848
 849	/* power saved state */
 850	u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 851
 852	/* for different msi-x irq type */
 853	char name_rx[IFNAMSIZ + 3];       /* -rx    */
 854	char name_tx[IFNAMSIZ + 3];       /* -tx    */
 855	char name_other[IFNAMSIZ + 6];    /* -other */
 856};
 857
 858/*
 859 * Maximum number of loops until we assume that a bit in the irq mask
 860 * is stuck. Overridable with module param.
 861 */
 862static int max_interrupt_work = 4;
 863
 864/*
 865 * Optimization can be either throuput mode or cpu mode
 866 *
 867 * Throughput Mode: Every tx and rx packet will generate an interrupt.
 868 * CPU Mode: Interrupts are controlled by a timer.
 869 */
 870enum {
 871	NV_OPTIMIZATION_MODE_THROUGHPUT,
 872	NV_OPTIMIZATION_MODE_CPU,
 873	NV_OPTIMIZATION_MODE_DYNAMIC
 874};
 875static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 876
 877/*
 878 * Poll interval for timer irq
 879 *
 880 * This interval determines how frequent an interrupt is generated.
 881 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 882 * Min = 0, and Max = 65535
 883 */
 884static int poll_interval = -1;
 885
 886/*
 887 * MSI interrupts
 888 */
 889enum {
 890	NV_MSI_INT_DISABLED,
 891	NV_MSI_INT_ENABLED
 892};
 893static int msi = NV_MSI_INT_ENABLED;
 894
 895/*
 896 * MSIX interrupts
 897 */
 898enum {
 899	NV_MSIX_INT_DISABLED,
 900	NV_MSIX_INT_ENABLED
 901};
 902static int msix = NV_MSIX_INT_ENABLED;
 903
 904/*
 905 * DMA 64bit
 906 */
 907enum {
 908	NV_DMA_64BIT_DISABLED,
 909	NV_DMA_64BIT_ENABLED
 910};
 911static int dma_64bit = NV_DMA_64BIT_ENABLED;
 912
 913/*
 914 * Debug output control for tx_timeout
 915 */
 916static bool debug_tx_timeout = false;
 917
 918/*
 919 * Crossover Detection
 920 * Realtek 8201 phy + some OEM boards do not work properly.
 921 */
 922enum {
 923	NV_CROSSOVER_DETECTION_DISABLED,
 924	NV_CROSSOVER_DETECTION_ENABLED
 925};
 926static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 927
 928/*
 929 * Power down phy when interface is down (persists through reboot;
 930 * older Linux and other OSes may not power it up again)
 931 */
 932static int phy_power_down;
 933
 934static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 935{
 936	return netdev_priv(dev);
 937}
 938
 939static inline u8 __iomem *get_hwbase(struct net_device *dev)
 940{
 941	return ((struct fe_priv *)netdev_priv(dev))->base;
 942}
 943
 944static inline void pci_push(u8 __iomem *base)
 945{
 946	/* force out pending posted writes */
 947	readl(base);
 948}
 949
 950static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 951{
 952	return le32_to_cpu(prd->flaglen)
 953		& ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 954}
 955
 956static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 957{
 958	return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 959}
 960
 961static bool nv_optimized(struct fe_priv *np)
 962{
 963	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 964		return false;
 965	return true;
 966}
 967
 968static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 969		     int delay, int delaymax)
 970{
 971	u8 __iomem *base = get_hwbase(dev);
 972
 973	pci_push(base);
 974	do {
 975		udelay(delay);
 976		delaymax -= delay;
 977		if (delaymax < 0)
 978			return 1;
 979	} while ((readl(base + offset) & mask) != target);
 980	return 0;
 981}
 982
 983#define NV_SETUP_RX_RING 0x01
 984#define NV_SETUP_TX_RING 0x02
 985
 986static inline u32 dma_low(dma_addr_t addr)
 987{
 988	return addr;
 989}
 990
 991static inline u32 dma_high(dma_addr_t addr)
 992{
 993	return addr>>31>>1;	/* 0 if 32bit, shift down by 32 if 64bit */
 994}
 995
 996static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 997{
 998	struct fe_priv *np = get_nvpriv(dev);
 999	u8 __iomem *base = get_hwbase(dev);
1000
1001	if (!nv_optimized(np)) {
1002		if (rxtx_flags & NV_SETUP_RX_RING)
1003			writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1004		if (rxtx_flags & NV_SETUP_TX_RING)
1005			writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1006	} else {
1007		if (rxtx_flags & NV_SETUP_RX_RING) {
1008			writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1009			writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1010		}
1011		if (rxtx_flags & NV_SETUP_TX_RING) {
1012			writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1013			writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1014		}
1015	}
1016}
1017
1018static void free_rings(struct net_device *dev)
1019{
1020	struct fe_priv *np = get_nvpriv(dev);
1021
1022	if (!nv_optimized(np)) {
1023		if (np->rx_ring.orig)
1024			dma_free_coherent(&np->pci_dev->dev,
1025					  sizeof(struct ring_desc) *
1026					  (np->rx_ring_size +
1027					  np->tx_ring_size),
1028					  np->rx_ring.orig, np->ring_addr);
1029	} else {
1030		if (np->rx_ring.ex)
1031			dma_free_coherent(&np->pci_dev->dev,
1032					  sizeof(struct ring_desc_ex) *
1033					  (np->rx_ring_size +
1034					  np->tx_ring_size),
1035					  np->rx_ring.ex, np->ring_addr);
1036	}
1037	kfree(np->rx_skb);
1038	kfree(np->tx_skb);
1039}
1040
1041static int using_multi_irqs(struct net_device *dev)
1042{
1043	struct fe_priv *np = get_nvpriv(dev);
1044
1045	if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1046	    ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))
1047		return 0;
1048	else
1049		return 1;
1050}
1051
1052static void nv_txrx_gate(struct net_device *dev, bool gate)
1053{
1054	struct fe_priv *np = get_nvpriv(dev);
1055	u8 __iomem *base = get_hwbase(dev);
1056	u32 powerstate;
1057
1058	if (!np->mac_in_use &&
1059	    (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1060		powerstate = readl(base + NvRegPowerState2);
1061		if (gate)
1062			powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1063		else
1064			powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1065		writel(powerstate, base + NvRegPowerState2);
1066	}
1067}
1068
1069static void nv_enable_irq(struct net_device *dev)
1070{
1071	struct fe_priv *np = get_nvpriv(dev);
1072
1073	if (!using_multi_irqs(dev)) {
1074		if (np->msi_flags & NV_MSI_X_ENABLED)
1075			enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1076		else
1077			enable_irq(np->pci_dev->irq);
1078	} else {
1079		enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1080		enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1081		enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1082	}
1083}
1084
1085static void nv_disable_irq(struct net_device *dev)
1086{
1087	struct fe_priv *np = get_nvpriv(dev);
1088
1089	if (!using_multi_irqs(dev)) {
1090		if (np->msi_flags & NV_MSI_X_ENABLED)
1091			disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1092		else
1093			disable_irq(np->pci_dev->irq);
1094	} else {
1095		disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1096		disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1097		disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1098	}
1099}
1100
1101/* In MSIX mode, a write to irqmask behaves as XOR */
1102static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1103{
1104	u8 __iomem *base = get_hwbase(dev);
1105
1106	writel(mask, base + NvRegIrqMask);
1107}
1108
1109static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1110{
1111	struct fe_priv *np = get_nvpriv(dev);
1112	u8 __iomem *base = get_hwbase(dev);
1113
1114	if (np->msi_flags & NV_MSI_X_ENABLED) {
1115		writel(mask, base + NvRegIrqMask);
1116	} else {
1117		if (np->msi_flags & NV_MSI_ENABLED)
1118			writel(0, base + NvRegMSIIrqMask);
1119		writel(0, base + NvRegIrqMask);
1120	}
1121}
1122
1123#define MII_READ	(-1)
1124/* mii_rw: read/write a register on the PHY.
1125 *
1126 * Caller must guarantee serialization
1127 */
1128static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1129{
1130	u8 __iomem *base = get_hwbase(dev);
1131	u32 reg;
1132	int retval;
1133
1134	writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1135
1136	reg = readl(base + NvRegMIIControl);
1137	if (reg & NVREG_MIICTL_INUSE) {
1138		writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1139		udelay(NV_MIIBUSY_DELAY);
1140	}
1141
1142	reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1143	if (value != MII_READ) {
1144		writel(value, base + NvRegMIIData);
1145		reg |= NVREG_MIICTL_WRITE;
1146	}
1147	writel(reg, base + NvRegMIIControl);
1148
1149	if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1150			NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1151		retval = -1;
1152	} else if (value != MII_READ) {
1153		/* it was a write operation - fewer failures are detectable */
1154		retval = 0;
1155	} else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1156		retval = -1;
1157	} else {
1158		retval = readl(base + NvRegMIIData);
1159	}
1160
1161	return retval;
1162}
1163
1164static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1165{
1166	struct fe_priv *np = netdev_priv(dev);
1167	u32 miicontrol;
1168	unsigned int tries = 0;
1169
1170	miicontrol = BMCR_RESET | bmcr_setup;
1171	if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1172		return -1;
1173
1174	/* wait for 500ms */
1175	msleep(500);
1176
1177	/* must wait till reset is deasserted */
1178	while (miicontrol & BMCR_RESET) {
1179		usleep_range(10000, 20000);
1180		miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1181		/* FIXME: 100 tries seem excessive */
1182		if (tries++ > 100)
1183			return -1;
1184	}
1185	return 0;
1186}
1187
1188static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1189{
1190	static const struct {
1191		int reg;
1192		int init;
1193	} ri[] = {
1194		{ PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1195		{ PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1196		{ PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1197		{ PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1198		{ PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1199		{ PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1200		{ PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1201	};
1202	int i;
1203
1204	for (i = 0; i < ARRAY_SIZE(ri); i++) {
1205		if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1206			return PHY_ERROR;
1207	}
1208
1209	return 0;
1210}
1211
1212static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1213{
1214	u32 reg;
1215	u8 __iomem *base = get_hwbase(dev);
1216	u32 powerstate = readl(base + NvRegPowerState2);
1217
1218	/* need to perform hw phy reset */
1219	powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1220	writel(powerstate, base + NvRegPowerState2);
1221	msleep(25);
1222
1223	powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1224	writel(powerstate, base + NvRegPowerState2);
1225	msleep(25);
1226
1227	reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1228	reg |= PHY_REALTEK_INIT9;
1229	if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1230		return PHY_ERROR;
1231	if (mii_rw(dev, np->phyaddr,
1232		   PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1233		return PHY_ERROR;
1234	reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1235	if (!(reg & PHY_REALTEK_INIT11)) {
1236		reg |= PHY_REALTEK_INIT11;
1237		if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1238			return PHY_ERROR;
1239	}
1240	if (mii_rw(dev, np->phyaddr,
1241		   PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1242		return PHY_ERROR;
1243
1244	return 0;
1245}
1246
1247static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1248{
1249	u32 phy_reserved;
1250
1251	if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1252		phy_reserved = mii_rw(dev, np->phyaddr,
1253				      PHY_REALTEK_INIT_REG6, MII_READ);
1254		phy_reserved |= PHY_REALTEK_INIT7;
1255		if (mii_rw(dev, np->phyaddr,
1256			   PHY_REALTEK_INIT_REG6, phy_reserved))
1257			return PHY_ERROR;
1258	}
1259
1260	return 0;
1261}
1262
1263static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1264{
1265	u32 phy_reserved;
1266
1267	if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1268		if (mii_rw(dev, np->phyaddr,
1269			   PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1270			return PHY_ERROR;
1271		phy_reserved = mii_rw(dev, np->phyaddr,
1272				      PHY_REALTEK_INIT_REG2, MII_READ);
1273		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1274		phy_reserved |= PHY_REALTEK_INIT3;
1275		if (mii_rw(dev, np->phyaddr,
1276			   PHY_REALTEK_INIT_REG2, phy_reserved))
1277			return PHY_ERROR;
1278		if (mii_rw(dev, np->phyaddr,
1279			   PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1280			return PHY_ERROR;
1281	}
1282
1283	return 0;
1284}
1285
1286static int init_cicada(struct net_device *dev, struct fe_priv *np,
1287		       u32 phyinterface)
1288{
1289	u32 phy_reserved;
1290
1291	if (phyinterface & PHY_RGMII) {
1292		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1293		phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1294		phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1295		if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1296			return PHY_ERROR;
1297		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1298		phy_reserved |= PHY_CICADA_INIT5;
1299		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1300			return PHY_ERROR;
1301	}
1302	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1303	phy_reserved |= PHY_CICADA_INIT6;
1304	if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1305		return PHY_ERROR;
1306
1307	return 0;
1308}
1309
1310static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1311{
1312	u32 phy_reserved;
1313
1314	if (mii_rw(dev, np->phyaddr,
1315		   PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1316		return PHY_ERROR;
1317	if (mii_rw(dev, np->phyaddr,
1318		   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1319		return PHY_ERROR;
1320	phy_reserved = mii_rw(dev, np->phyaddr,
1321			      PHY_VITESSE_INIT_REG4, MII_READ);
1322	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1323		return PHY_ERROR;
1324	phy_reserved = mii_rw(dev, np->phyaddr,
1325			      PHY_VITESSE_INIT_REG3, MII_READ);
1326	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1327	phy_reserved |= PHY_VITESSE_INIT3;
1328	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1329		return PHY_ERROR;
1330	if (mii_rw(dev, np->phyaddr,
1331		   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1332		return PHY_ERROR;
1333	if (mii_rw(dev, np->phyaddr,
1334		   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1335		return PHY_ERROR;
1336	phy_reserved = mii_rw(dev, np->phyaddr,
1337			      PHY_VITESSE_INIT_REG4, MII_READ);
1338	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1339	phy_reserved |= PHY_VITESSE_INIT3;
1340	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1341		return PHY_ERROR;
1342	phy_reserved = mii_rw(dev, np->phyaddr,
1343			      PHY_VITESSE_INIT_REG3, MII_READ);
1344	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1345		return PHY_ERROR;
1346	if (mii_rw(dev, np->phyaddr,
1347		   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1348		return PHY_ERROR;
1349	if (mii_rw(dev, np->phyaddr,
1350		   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1351		return PHY_ERROR;
1352	phy_reserved = mii_rw(dev, np->phyaddr,
1353			      PHY_VITESSE_INIT_REG4, MII_READ);
1354	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1355		return PHY_ERROR;
1356	phy_reserved = mii_rw(dev, np->phyaddr,
1357			      PHY_VITESSE_INIT_REG3, MII_READ);
1358	phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1359	phy_reserved |= PHY_VITESSE_INIT8;
1360	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1361		return PHY_ERROR;
1362	if (mii_rw(dev, np->phyaddr,
1363		   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1364		return PHY_ERROR;
1365	if (mii_rw(dev, np->phyaddr,
1366		   PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1367		return PHY_ERROR;
1368
1369	return 0;
1370}
1371
1372static int phy_init(struct net_device *dev)
1373{
1374	struct fe_priv *np = get_nvpriv(dev);
1375	u8 __iomem *base = get_hwbase(dev);
1376	u32 phyinterface;
1377	u32 mii_status, mii_control, mii_control_1000, reg;
1378
1379	/* phy errata for E3016 phy */
1380	if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1381		reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1382		reg &= ~PHY_MARVELL_E3016_INITMASK;
1383		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1384			netdev_info(dev, "%s: phy write to errata reg failed\n",
1385				    pci_name(np->pci_dev));
1386			return PHY_ERROR;
1387		}
1388	}
1389	if (np->phy_oui == PHY_OUI_REALTEK) {
1390		if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1391		    np->phy_rev == PHY_REV_REALTEK_8211B) {
1392			if (init_realtek_8211b(dev, np)) {
1393				netdev_info(dev, "%s: phy init failed\n",
1394					    pci_name(np->pci_dev));
1395				return PHY_ERROR;
1396			}
1397		} else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1398			   np->phy_rev == PHY_REV_REALTEK_8211C) {
1399			if (init_realtek_8211c(dev, np)) {
1400				netdev_info(dev, "%s: phy init failed\n",
1401					    pci_name(np->pci_dev));
1402				return PHY_ERROR;
1403			}
1404		} else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1405			if (init_realtek_8201(dev, np)) {
1406				netdev_info(dev, "%s: phy init failed\n",
1407					    pci_name(np->pci_dev));
1408				return PHY_ERROR;
1409			}
1410		}
1411	}
1412
1413	/* set advertise register */
1414	reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1415	reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1416		ADVERTISE_100HALF | ADVERTISE_100FULL |
1417		ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1418	if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1419		netdev_info(dev, "%s: phy write to advertise failed\n",
1420			    pci_name(np->pci_dev));
1421		return PHY_ERROR;
1422	}
1423
1424	/* get phy interface type */
1425	phyinterface = readl(base + NvRegPhyInterface);
1426
1427	/* see if gigabit phy */
1428	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1429	if (mii_status & PHY_GIGABIT) {
1430		np->gigabit = PHY_GIGABIT;
1431		mii_control_1000 = mii_rw(dev, np->phyaddr,
1432					  MII_CTRL1000, MII_READ);
1433		mii_control_1000 &= ~ADVERTISE_1000HALF;
1434		if (phyinterface & PHY_RGMII)
1435			mii_control_1000 |= ADVERTISE_1000FULL;
1436		else
1437			mii_control_1000 &= ~ADVERTISE_1000FULL;
1438
1439		if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1440			netdev_info(dev, "%s: phy init failed\n",
1441				    pci_name(np->pci_dev));
1442			return PHY_ERROR;
1443		}
1444	} else
1445		np->gigabit = 0;
1446
1447	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1448	mii_control |= BMCR_ANENABLE;
1449
1450	if (np->phy_oui == PHY_OUI_REALTEK &&
1451	    np->phy_model == PHY_MODEL_REALTEK_8211 &&
1452	    np->phy_rev == PHY_REV_REALTEK_8211C) {
1453		/* start autoneg since we already performed hw reset above */
1454		mii_control |= BMCR_ANRESTART;
1455		if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1456			netdev_info(dev, "%s: phy init failed\n",
1457				    pci_name(np->pci_dev));
1458			return PHY_ERROR;
1459		}
1460	} else {
1461		/* reset the phy
1462		 * (certain phys need bmcr to be setup with reset)
1463		 */
1464		if (phy_reset(dev, mii_control)) {
1465			netdev_info(dev, "%s: phy reset failed\n",
1466				    pci_name(np->pci_dev));
1467			return PHY_ERROR;
1468		}
1469	}
1470
1471	/* phy vendor specific configuration */
1472	if (np->phy_oui == PHY_OUI_CICADA) {
1473		if (init_cicada(dev, np, phyinterface)) {
1474			netdev_info(dev, "%s: phy init failed\n",
1475				    pci_name(np->pci_dev));
1476			return PHY_ERROR;
1477		}
1478	} else if (np->phy_oui == PHY_OUI_VITESSE) {
1479		if (init_vitesse(dev, np)) {
1480			netdev_info(dev, "%s: phy init failed\n",
1481				    pci_name(np->pci_dev));
1482			return PHY_ERROR;
1483		}
1484	} else if (np->phy_oui == PHY_OUI_REALTEK) {
1485		if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1486		    np->phy_rev == PHY_REV_REALTEK_8211B) {
1487			/* reset could have cleared these out, set them back */
1488			if (init_realtek_8211b(dev, np)) {
1489				netdev_info(dev, "%s: phy init failed\n",
1490					    pci_name(np->pci_dev));
1491				return PHY_ERROR;
1492			}
1493		} else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1494			if (init_realtek_8201(dev, np) ||
1495			    init_realtek_8201_cross(dev, np)) {
1496				netdev_info(dev, "%s: phy init failed\n",
1497					    pci_name(np->pci_dev));
1498				return PHY_ERROR;
1499			}
1500		}
1501	}
1502
1503	/* some phys clear out pause advertisement on reset, set it back */
1504	mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1505
1506	/* restart auto negotiation, power down phy */
1507	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1508	mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1509	if (phy_power_down)
1510		mii_control |= BMCR_PDOWN;
1511	if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1512		return PHY_ERROR;
1513
1514	return 0;
1515}
1516
1517static void nv_start_rx(struct net_device *dev)
1518{
1519	struct fe_priv *np = netdev_priv(dev);
1520	u8 __iomem *base = get_hwbase(dev);
1521	u32 rx_ctrl = readl(base + NvRegReceiverControl);
1522
1523	/* Already running? Stop it. */
1524	if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1525		rx_ctrl &= ~NVREG_RCVCTL_START;
1526		writel(rx_ctrl, base + NvRegReceiverControl);
1527		pci_push(base);
1528	}
1529	writel(np->linkspeed, base + NvRegLinkSpeed);
1530	pci_push(base);
1531	rx_ctrl |= NVREG_RCVCTL_START;
1532	if (np->mac_in_use)
1533		rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1534	writel(rx_ctrl, base + NvRegReceiverControl);
1535	pci_push(base);
1536}
1537
1538static void nv_stop_rx(struct net_device *dev)
1539{
1540	struct fe_priv *np = netdev_priv(dev);
1541	u8 __iomem *base = get_hwbase(dev);
1542	u32 rx_ctrl = readl(base + NvRegReceiverControl);
1543
1544	if (!np->mac_in_use)
1545		rx_ctrl &= ~NVREG_RCVCTL_START;
1546	else
1547		rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1548	writel(rx_ctrl, base + NvRegReceiverControl);
1549	if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1550		      NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1551		netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1552			    __func__);
1553
1554	udelay(NV_RXSTOP_DELAY2);
1555	if (!np->mac_in_use)
1556		writel(0, base + NvRegLinkSpeed);
1557}
1558
1559static void nv_start_tx(struct net_device *dev)
1560{
1561	struct fe_priv *np = netdev_priv(dev);
1562	u8 __iomem *base = get_hwbase(dev);
1563	u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1564
1565	tx_ctrl |= NVREG_XMITCTL_START;
1566	if (np->mac_in_use)
1567		tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1568	writel(tx_ctrl, base + NvRegTransmitterControl);
1569	pci_push(base);
1570}
1571
1572static void nv_stop_tx(struct net_device *dev)
1573{
1574	struct fe_priv *np = netdev_priv(dev);
1575	u8 __iomem *base = get_hwbase(dev);
1576	u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1577
1578	if (!np->mac_in_use)
1579		tx_ctrl &= ~NVREG_XMITCTL_START;
1580	else
1581		tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1582	writel(tx_ctrl, base + NvRegTransmitterControl);
1583	if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1584		      NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1585		netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1586			    __func__);
1587
1588	udelay(NV_TXSTOP_DELAY2);
1589	if (!np->mac_in_use)
1590		writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1591		       base + NvRegTransmitPoll);
1592}
1593
1594static void nv_start_rxtx(struct net_device *dev)
1595{
1596	nv_start_rx(dev);
1597	nv_start_tx(dev);
1598}
1599
1600static void nv_stop_rxtx(struct net_device *dev)
1601{
1602	nv_stop_rx(dev);
1603	nv_stop_tx(dev);
1604}
1605
1606static void nv_txrx_reset(struct net_device *dev)
1607{
1608	struct fe_priv *np = netdev_priv(dev);
1609	u8 __iomem *base = get_hwbase(dev);
1610
1611	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1612	pci_push(base);
1613	udelay(NV_TXRX_RESET_DELAY);
1614	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1615	pci_push(base);
1616}
1617
1618static void nv_mac_reset(struct net_device *dev)
1619{
1620	struct fe_priv *np = netdev_priv(dev);
1621	u8 __iomem *base = get_hwbase(dev);
1622	u32 temp1, temp2, temp3;
1623
1624	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1625	pci_push(base);
1626
1627	/* save registers since they will be cleared on reset */
1628	temp1 = readl(base + NvRegMacAddrA);
1629	temp2 = readl(base + NvRegMacAddrB);
1630	temp3 = readl(base + NvRegTransmitPoll);
1631
1632	writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1633	pci_push(base);
1634	udelay(NV_MAC_RESET_DELAY);
1635	writel(0, base + NvRegMacReset);
1636	pci_push(base);
1637	udelay(NV_MAC_RESET_DELAY);
1638
1639	/* restore saved registers */
1640	writel(temp1, base + NvRegMacAddrA);
1641	writel(temp2, base + NvRegMacAddrB);
1642	writel(temp3, base + NvRegTransmitPoll);
1643
1644	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1645	pci_push(base);
1646}
1647
1648/* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1649static void nv_update_stats(struct net_device *dev)
1650{
1651	struct fe_priv *np = netdev_priv(dev);
1652	u8 __iomem *base = get_hwbase(dev);
1653
1654	lockdep_assert_held(&np->hwstats_lock);
1655
1656	/* query hardware */
1657	np->estats.tx_bytes += readl(base + NvRegTxCnt);
1658	np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1659	np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1660	np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1661	np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1662	np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1663	np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1664	np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1665	np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1666	np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1667	np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1668	np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1669	np->estats.rx_runt += readl(base + NvRegRxRunt);
1670	np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1671	np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1672	np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1673	np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1674	np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1675	np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1676	np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1677	np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1678	np->estats.rx_packets =
1679		np->estats.rx_unicast +
1680		np->estats.rx_multicast +
1681		np->estats.rx_broadcast;
1682	np->estats.rx_errors_total =
1683		np->estats.rx_crc_errors +
1684		np->estats.rx_over_errors +
1685		np->estats.rx_frame_error +
1686		(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1687		np->estats.rx_late_collision +
1688		np->estats.rx_runt +
1689		np->estats.rx_frame_too_long;
1690	np->estats.tx_errors_total =
1691		np->estats.tx_late_collision +
1692		np->estats.tx_fifo_errors +
1693		np->estats.tx_carrier_errors +
1694		np->estats.tx_excess_deferral +
1695		np->estats.tx_retry_error;
1696
1697	if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1698		np->estats.tx_deferral += readl(base + NvRegTxDef);
1699		np->estats.tx_packets += readl(base + NvRegTxFrame);
1700		np->estats.rx_bytes += readl(base + NvRegRxCnt);
1701		np->estats.tx_pause += readl(base + NvRegTxPause);
1702		np->estats.rx_pause += readl(base + NvRegRxPause);
1703		np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1704		np->estats.rx_errors_total += np->estats.rx_drop_frame;
1705	}
1706
1707	if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1708		np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1709		np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1710		np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1711	}
1712}
1713
1714static void nv_get_stats(int cpu, struct fe_priv *np,
1715			 struct rtnl_link_stats64 *storage)
1716{
1717	struct nv_txrx_stats *src = per_cpu_ptr(np->txrx_stats, cpu);
1718	unsigned int syncp_start;
1719	u64 rx_packets, rx_bytes, rx_dropped, rx_missed_errors;
1720	u64 tx_packets, tx_bytes, tx_dropped;
1721
1722	do {
1723		syncp_start = u64_stats_fetch_begin(&np->swstats_rx_syncp);
1724		rx_packets       = src->stat_rx_packets;
1725		rx_bytes         = src->stat_rx_bytes;
1726		rx_dropped       = src->stat_rx_dropped;
1727		rx_missed_errors = src->stat_rx_missed_errors;
1728	} while (u64_stats_fetch_retry(&np->swstats_rx_syncp, syncp_start));
1729
1730	storage->rx_packets       += rx_packets;
1731	storage->rx_bytes         += rx_bytes;
1732	storage->rx_dropped       += rx_dropped;
1733	storage->rx_missed_errors += rx_missed_errors;
1734
1735	do {
1736		syncp_start = u64_stats_fetch_begin(&np->swstats_tx_syncp);
1737		tx_packets  = src->stat_tx_packets;
1738		tx_bytes    = src->stat_tx_bytes;
1739		tx_dropped  = src->stat_tx_dropped;
1740	} while (u64_stats_fetch_retry(&np->swstats_tx_syncp, syncp_start));
1741
1742	storage->tx_packets += tx_packets;
1743	storage->tx_bytes   += tx_bytes;
1744	storage->tx_dropped += tx_dropped;
1745}
1746
1747/*
1748 * nv_get_stats64: dev->ndo_get_stats64 function
1749 * Get latest stats value from the nic.
1750 * Called with rcu_read_lock() held -
1751 * only synchronized against unregister_netdevice.
1752 */
1753static void
1754nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1755	__acquires(&netdev_priv(dev)->hwstats_lock)
1756	__releases(&netdev_priv(dev)->hwstats_lock)
1757{
1758	struct fe_priv *np = netdev_priv(dev);
1759	int cpu;
1760
1761	/*
1762	 * Note: because HW stats are not always available and for
1763	 * consistency reasons, the following ifconfig stats are
1764	 * managed by software: rx_bytes, tx_bytes, rx_packets and
1765	 * tx_packets. The related hardware stats reported by ethtool
1766	 * should be equivalent to these ifconfig stats, with 4
1767	 * additional bytes per packet (Ethernet FCS CRC), except for
1768	 * tx_packets when TSO kicks in.
1769	 */
1770
1771	/* software stats */
1772	for_each_online_cpu(cpu)
1773		nv_get_stats(cpu, np, storage);
1774
1775	/* If the nic supports hw counters then retrieve latest values */
1776	if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1777		spin_lock_bh(&np->hwstats_lock);
1778
1779		nv_update_stats(dev);
1780
1781		/* generic stats */
1782		storage->rx_errors = np->estats.rx_errors_total;
1783		storage->tx_errors = np->estats.tx_errors_total;
1784
1785		/* meaningful only when NIC supports stats v3 */
1786		storage->multicast = np->estats.rx_multicast;
1787
1788		/* detailed rx_errors */
1789		storage->rx_length_errors = np->estats.rx_length_error;
1790		storage->rx_over_errors   = np->estats.rx_over_errors;
1791		storage->rx_crc_errors    = np->estats.rx_crc_errors;
1792		storage->rx_frame_errors  = np->estats.rx_frame_align_error;
1793		storage->rx_fifo_errors   = np->estats.rx_drop_frame;
1794
1795		/* detailed tx_errors */
1796		storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1797		storage->tx_fifo_errors    = np->estats.tx_fifo_errors;
1798
1799		spin_unlock_bh(&np->hwstats_lock);
1800	}
1801}
1802
1803/*
1804 * nv_alloc_rx: fill rx ring entries.
1805 * Return 1 if the allocations for the skbs failed and the
1806 * rx engine is without Available descriptors
1807 */
1808static int nv_alloc_rx(struct net_device *dev)
1809{
1810	struct fe_priv *np = netdev_priv(dev);
1811	struct ring_desc *less_rx;
1812
1813	less_rx = np->get_rx.orig;
1814	if (less_rx-- == np->rx_ring.orig)
1815		less_rx = np->last_rx.orig;
1816
1817	while (np->put_rx.orig != less_rx) {
1818		struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1819		if (likely(skb)) {
1820			np->put_rx_ctx->skb = skb;
1821			np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev,
1822							     skb->data,
1823							     skb_tailroom(skb),
1824							     DMA_FROM_DEVICE);
1825			if (unlikely(dma_mapping_error(&np->pci_dev->dev,
1826						       np->put_rx_ctx->dma))) {
1827				kfree_skb(skb);
1828				goto packet_dropped;
1829			}
1830			np->put_rx_ctx->dma_len = skb_tailroom(skb);
1831			np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1832			wmb();
1833			np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1834			if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1835				np->put_rx.orig = np->rx_ring.orig;
1836			if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1837				np->put_rx_ctx = np->rx_skb;
1838		} else {
1839packet_dropped:
1840			u64_stats_update_begin(&np->swstats_rx_syncp);
1841			nv_txrx_stats_inc(stat_rx_dropped);
1842			u64_stats_update_end(&np->swstats_rx_syncp);
1843			return 1;
1844		}
1845	}
1846	return 0;
1847}
1848
1849static int nv_alloc_rx_optimized(struct net_device *dev)
1850{
1851	struct fe_priv *np = netdev_priv(dev);
1852	struct ring_desc_ex *less_rx;
1853
1854	less_rx = np->get_rx.ex;
1855	if (less_rx-- == np->rx_ring.ex)
1856		less_rx = np->last_rx.ex;
1857
1858	while (np->put_rx.ex != less_rx) {
1859		struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1860		if (likely(skb)) {
1861			np->put_rx_ctx->skb = skb;
1862			np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev,
1863							     skb->data,
1864							     skb_tailroom(skb),
1865							     DMA_FROM_DEVICE);
1866			if (unlikely(dma_mapping_error(&np->pci_dev->dev,
1867						       np->put_rx_ctx->dma))) {
1868				kfree_skb(skb);
1869				goto packet_dropped;
1870			}
1871			np->put_rx_ctx->dma_len = skb_tailroom(skb);
1872			np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1873			np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1874			wmb();
1875			np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1876			if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1877				np->put_rx.ex = np->rx_ring.ex;
1878			if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1879				np->put_rx_ctx = np->rx_skb;
1880		} else {
1881packet_dropped:
1882			u64_stats_update_begin(&np->swstats_rx_syncp);
1883			nv_txrx_stats_inc(stat_rx_dropped);
1884			u64_stats_update_end(&np->swstats_rx_syncp);
1885			return 1;
1886		}
1887	}
1888	return 0;
1889}
1890
1891/* If rx bufs are exhausted called after 50ms to attempt to refresh */
1892static void nv_do_rx_refill(struct timer_list *t)
1893{
1894	struct fe_priv *np = timer_container_of(np, t, oom_kick);
1895
1896	/* Just reschedule NAPI rx processing */
1897	napi_schedule(&np->napi);
1898}
1899
1900static void nv_init_rx(struct net_device *dev)
1901{
1902	struct fe_priv *np = netdev_priv(dev);
1903	int i;
1904
1905	np->get_rx = np->rx_ring;
1906	np->put_rx = np->rx_ring;
1907
1908	if (!nv_optimized(np))
1909		np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1910	else
1911		np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1912	np->get_rx_ctx = np->rx_skb;
1913	np->put_rx_ctx = np->rx_skb;
1914	np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1915
1916	for (i = 0; i < np->rx_ring_size; i++) {
1917		if (!nv_optimized(np)) {
1918			np->rx_ring.orig[i].flaglen = 0;
1919			np->rx_ring.orig[i].buf = 0;
1920		} else {
1921			np->rx_ring.ex[i].flaglen = 0;
1922			np->rx_ring.ex[i].txvlan = 0;
1923			np->rx_ring.ex[i].bufhigh = 0;
1924			np->rx_ring.ex[i].buflow = 0;
1925		}
1926		np->rx_skb[i].skb = NULL;
1927		np->rx_skb[i].dma = 0;
1928	}
1929}
1930
1931static void nv_init_tx(struct net_device *dev)
1932{
1933	struct fe_priv *np = netdev_priv(dev);
1934	int i;
1935
1936	np->get_tx = np->tx_ring;
1937	np->put_tx = np->tx_ring;
1938
1939	if (!nv_optimized(np))
1940		np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1941	else
1942		np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1943	np->get_tx_ctx = np->tx_skb;
1944	np->put_tx_ctx = np->tx_skb;
1945	np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1946	netdev_reset_queue(np->dev);
1947	np->tx_pkts_in_progress = 0;
1948	np->tx_change_owner = NULL;
1949	np->tx_end_flip = NULL;
1950	np->tx_stop = 0;
1951
1952	for (i = 0; i < np->tx_ring_size; i++) {
1953		if (!nv_optimized(np)) {
1954			np->tx_ring.orig[i].flaglen = 0;
1955			np->tx_ring.orig[i].buf = 0;
1956		} else {
1957			np->tx_ring.ex[i].flaglen = 0;
1958			np->tx_ring.ex[i].txvlan = 0;
1959			np->tx_ring.ex[i].bufhigh = 0;
1960			np->tx_ring.ex[i].buflow = 0;
1961		}
1962		np->tx_skb[i].skb = NULL;
1963		np->tx_skb[i].dma = 0;
1964		np->tx_skb[i].dma_len = 0;
1965		np->tx_skb[i].dma_single = 0;
1966		np->tx_skb[i].first_tx_desc = NULL;
1967		np->tx_skb[i].next_tx_ctx = NULL;
1968	}
1969}
1970
1971static int nv_init_ring(struct net_device *dev)
1972{
1973	struct fe_priv *np = netdev_priv(dev);
1974
1975	nv_init_tx(dev);
1976	nv_init_rx(dev);
1977
1978	if (!nv_optimized(np))
1979		return nv_alloc_rx(dev);
1980	else
1981		return nv_alloc_rx_optimized(dev);
1982}
1983
1984static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1985{
1986	if (tx_skb->dma) {
1987		if (tx_skb->dma_single)
1988			dma_unmap_single(&np->pci_dev->dev, tx_skb->dma,
1989					 tx_skb->dma_len,
1990					 DMA_TO_DEVICE);
1991		else
1992			dma_unmap_page(&np->pci_dev->dev, tx_skb->dma,
1993				       tx_skb->dma_len,
1994				       DMA_TO_DEVICE);
1995		tx_skb->dma = 0;
1996	}
1997}
1998
1999static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
2000{
2001	nv_unmap_txskb(np, tx_skb);
2002	if (tx_skb->skb) {
2003		dev_kfree_skb_any(tx_skb->skb);
2004		tx_skb->skb = NULL;
2005		return 1;
2006	}
2007	return 0;
2008}
2009
2010static void nv_drain_tx(struct net_device *dev)
2011{
2012	struct fe_priv *np = netdev_priv(dev);
2013	unsigned int i;
2014
2015	for (i = 0; i < np->tx_ring_size; i++) {
2016		if (!nv_optimized(np)) {
2017			np->tx_ring.orig[i].flaglen = 0;
2018			np->tx_ring.orig[i].buf = 0;
2019		} else {
2020			np->tx_ring.ex[i].flaglen = 0;
2021			np->tx_ring.ex[i].txvlan = 0;
2022			np->tx_ring.ex[i].bufhigh = 0;
2023			np->tx_ring.ex[i].buflow = 0;
2024		}
2025		if (nv_release_txskb(np, &np->tx_skb[i])) {
2026			u64_stats_update_begin(&np->swstats_tx_syncp);
2027			nv_txrx_stats_inc(stat_tx_dropped);
2028			u64_stats_update_end(&np->swstats_tx_syncp);
2029		}
2030		np->tx_skb[i].dma = 0;
2031		np->tx_skb[i].dma_len = 0;
2032		np->tx_skb[i].dma_single = 0;
2033		np->tx_skb[i].first_tx_desc = NULL;
2034		np->tx_skb[i].next_tx_ctx = NULL;
2035	}
2036	np->tx_pkts_in_progress = 0;
2037	np->tx_change_owner = NULL;
2038	np->tx_end_flip = NULL;
2039}
2040
2041static void nv_drain_rx(struct net_device *dev)
2042{
2043	struct fe_priv *np = netdev_priv(dev);
2044	int i;
2045
2046	for (i = 0; i < np->rx_ring_size; i++) {
2047		if (!nv_optimized(np)) {
2048			np->rx_ring.orig[i].flaglen = 0;
2049			np->rx_ring.orig[i].buf = 0;
2050		} else {
2051			np->rx_ring.ex[i].flaglen = 0;
2052			np->rx_ring.ex[i].txvlan = 0;
2053			np->rx_ring.ex[i].bufhigh = 0;
2054			np->rx_ring.ex[i].buflow = 0;
2055		}
2056		wmb();
2057		if (np->rx_skb[i].skb) {
2058			dma_unmap_single(&np->pci_dev->dev, np->rx_skb[i].dma,
2059					 (skb_end_pointer(np->rx_skb[i].skb) -
2060					 np->rx_skb[i].skb->data),
2061					 DMA_FROM_DEVICE);
2062			dev_kfree_skb(np->rx_skb[i].skb);
2063			np->rx_skb[i].skb = NULL;
2064		}
2065	}
2066}
2067
2068static void nv_drain_rxtx(struct net_device *dev)
2069{
2070	nv_drain_tx(dev);
2071	nv_drain_rx(dev);
2072}
2073
2074static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2075{
2076	return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2077}
2078
2079static void nv_legacybackoff_reseed(struct net_device *dev)
2080{
2081	u8 __iomem *base = get_hwbase(dev);
2082	u32 reg;
2083	u32 low;
2084	int tx_status = 0;
2085
2086	reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2087	get_random_bytes(&low, sizeof(low));
2088	reg |= low & NVREG_SLOTTIME_MASK;
2089
2090	/* Need to stop tx before change takes effect.
2091	 * Caller has already gained np->lock.
2092	 */
2093	tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2094	if (tx_status)
2095		nv_stop_tx(dev);
2096	nv_stop_rx(dev);
2097	writel(reg, base + NvRegSlotTime);
2098	if (tx_status)
2099		nv_start_tx(dev);
2100	nv_start_rx(dev);
2101}
2102
2103/* Gear Backoff Seeds */
2104#define BACKOFF_SEEDSET_ROWS	8
2105#define BACKOFF_SEEDSET_LFSRS	15
2106
2107/* Known Good seed sets */
2108static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2109	{145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2110	{245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2111	{145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2112	{245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2113	{266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2114	{266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2115	{366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2116	{466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2117
2118static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2119	{251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2120	{351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2121	{351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2122	{251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2123	{251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2124	{351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2125	{351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2126	{351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2127
2128static void nv_gear_backoff_reseed(struct net_device *dev)
2129{
2130	u8 __iomem *base = get_hwbase(dev);
2131	u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2132	u32 temp, seedset, combinedSeed;
2133	int i;
2134
2135	/* Setup seed for free running LFSR */
2136	/* We are going to read the time stamp counter 3 times
2137	   and swizzle bits around to increase randomness */
2138	get_random_bytes(&miniseed1, sizeof(miniseed1));
2139	miniseed1 &= 0x0fff;
2140	if (miniseed1 == 0)
2141		miniseed1 = 0xabc;
2142
2143	get_random_bytes(&miniseed2, sizeof(miniseed2));
2144	miniseed2 &= 0x0fff;
2145	if (miniseed2 == 0)
2146		miniseed2 = 0xabc;
2147	miniseed2_reversed =
2148		((miniseed2 & 0xF00) >> 8) |
2149		 (miniseed2 & 0x0F0) |
2150		 ((miniseed2 & 0x00F) << 8);
2151
2152	get_random_bytes(&miniseed3, sizeof(miniseed3));
2153	miniseed3 &= 0x0fff;
2154	if (miniseed3 == 0)
2155		miniseed3 = 0xabc;
2156	miniseed3_reversed =
2157		((miniseed3 & 0xF00) >> 8) |
2158		 (miniseed3 & 0x0F0) |
2159		 ((miniseed3 & 0x00F) << 8);
2160
2161	combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2162		       (miniseed2 ^ miniseed3_reversed);
2163
2164	/* Seeds can not be zero */
2165	if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2166		combinedSeed |= 0x08;
2167	if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2168		combinedSeed |= 0x8000;
2169
2170	/* No need to disable tx here */
2171	temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2172	temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2173	temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2174	writel(temp, base + NvRegBackOffControl);
2175
2176	/* Setup seeds for all gear LFSRs. */
2177	get_random_bytes(&seedset, sizeof(seedset));
2178	seedset = seedset % BACKOFF_SEEDSET_ROWS;
2179	for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2180		temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2181		temp |= main_seedset[seedset][i-1] & 0x3ff;
2182		temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2183		writel(temp, base + NvRegBackOffControl);
2184	}
2185}
2186
2187/*
2188 * nv_start_xmit: dev->hard_start_xmit function
2189 * Called with netif_tx_lock held.
2190 */
2191static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2192{
2193	struct fe_priv *np = netdev_priv(dev);
2194	u32 tx_flags = 0;
2195	u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2196	unsigned int fragments = skb_shinfo(skb)->nr_frags;
2197	unsigned int i;
2198	u32 offset = 0;
2199	u32 bcnt;
2200	u32 size = skb_headlen(skb);
2201	u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2202	u32 empty_slots;
2203	struct ring_desc *put_tx;
2204	struct ring_desc *start_tx;
2205	struct ring_desc *prev_tx;
2206	struct nv_skb_map *prev_tx_ctx;
2207	struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL;
2208	unsigned long flags;
2209	netdev_tx_t ret = NETDEV_TX_OK;
2210
2211	/* add fragments to entries count */
2212	for (i = 0; i < fragments; i++) {
2213		u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2214
2215		entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2216			   ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2217	}
2218
2219	spin_lock_irqsave(&np->lock, flags);
2220	empty_slots = nv_get_empty_tx_slots(np);
2221	if (unlikely(empty_slots <= entries)) {
2222		netif_stop_queue(dev);
2223		np->tx_stop = 1;
2224		spin_unlock_irqrestore(&np->lock, flags);
2225
2226		/* When normal packets and/or xmit_more packets fill up
2227		 * tx_desc, it is necessary to trigger NIC tx reg.
2228		 */
2229		ret = NETDEV_TX_BUSY;
2230		goto txkick;
2231	}
2232	spin_unlock_irqrestore(&np->lock, flags);
2233
2234	start_tx = put_tx = np->put_tx.orig;
2235
2236	/* setup the header buffer */
2237	do {
2238		bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2239		np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev,
2240						     skb->data + offset, bcnt,
2241						     DMA_TO_DEVICE);
2242		if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2243					       np->put_tx_ctx->dma))) {
2244			/* on DMA mapping error - drop the packet */
2245			dev_kfree_skb_any(skb);
2246			u64_stats_update_begin(&np->swstats_tx_syncp);
2247			nv_txrx_stats_inc(stat_tx_dropped);
2248			u64_stats_update_end(&np->swstats_tx_syncp);
2249
2250			ret = NETDEV_TX_OK;
2251
2252			goto dma_error;
2253		}
2254		np->put_tx_ctx->dma_len = bcnt;
2255		np->put_tx_ctx->dma_single = 1;
2256		put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2257		put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2258
2259		tx_flags = np->tx_flags;
2260		offset += bcnt;
2261		size -= bcnt;
2262		if (unlikely(put_tx++ == np->last_tx.orig))
2263			put_tx = np->tx_ring.orig;
2264		if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2265			np->put_tx_ctx = np->tx_skb;
2266	} while (size);
2267
2268	/* setup the fragments */
2269	for (i = 0; i < fragments; i++) {
2270		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2271		u32 frag_size = skb_frag_size(frag);
2272		offset = 0;
2273
2274		do {
2275			if (!start_tx_ctx)
2276				start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2277
2278			bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2279			np->put_tx_ctx->dma = skb_frag_dma_map(
2280							&np->pci_dev->dev,
2281							frag, offset,
2282							bcnt,
2283							DMA_TO_DEVICE);
2284			if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2285						       np->put_tx_ctx->dma))) {
2286
2287				/* Unwind the mapped fragments */
2288				do {
2289					nv_unmap_txskb(np, start_tx_ctx);
2290					if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2291						tmp_tx_ctx = np->tx_skb;
2292				} while (tmp_tx_ctx != np->put_tx_ctx);
2293				dev_kfree_skb_any(skb);
2294				np->put_tx_ctx = start_tx_ctx;
2295				u64_stats_update_begin(&np->swstats_tx_syncp);
2296				nv_txrx_stats_inc(stat_tx_dropped);
2297				u64_stats_update_end(&np->swstats_tx_syncp);
2298
2299				ret = NETDEV_TX_OK;
2300
2301				goto dma_error;
2302			}
2303
2304			np->put_tx_ctx->dma_len = bcnt;
2305			np->put_tx_ctx->dma_single = 0;
2306			put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2307			put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2308
2309			offset += bcnt;
2310			frag_size -= bcnt;
2311			if (unlikely(put_tx++ == np->last_tx.orig))
2312				put_tx = np->tx_ring.orig;
2313			if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2314				np->put_tx_ctx = np->tx_skb;
2315		} while (frag_size);
2316	}
2317
2318	if (unlikely(put_tx == np->tx_ring.orig))
2319		prev_tx = np->last_tx.orig;
2320	else
2321		prev_tx = put_tx - 1;
2322
2323	if (unlikely(np->put_tx_ctx == np->tx_skb))
2324		prev_tx_ctx = np->last_tx_ctx;
2325	else
2326		prev_tx_ctx = np->put_tx_ctx - 1;
2327
2328	/* set last fragment flag  */
2329	prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2330
2331	/* save skb in this slot's context area */
2332	prev_tx_ctx->skb = skb;
2333
2334	if (skb_is_gso(skb))
2335		tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2336	else
2337		tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2338			 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2339
2340	spin_lock_irqsave(&np->lock, flags);
2341
2342	/* set tx flags */
2343	start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2344
2345	netdev_sent_queue(np->dev, skb->len);
2346
2347	skb_tx_timestamp(skb);
2348
2349	np->put_tx.orig = put_tx;
2350
2351	spin_unlock_irqrestore(&np->lock, flags);
2352
2353txkick:
2354	if (netif_queue_stopped(dev) || !netdev_xmit_more()) {
2355		u32 txrxctl_kick;
2356dma_error:
2357		txrxctl_kick = NVREG_TXRXCTL_KICK | np->txrxctl_bits;
2358		writel(txrxctl_kick, get_hwbase(dev) + NvRegTxRxControl);
2359	}
2360
2361	return ret;
2362}
2363
2364static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2365					   struct net_device *dev)
2366{
2367	struct fe_priv *np = netdev_priv(dev);
2368	u32 tx_flags = 0;
2369	u32 tx_flags_extra;
2370	unsigned int fragments = skb_shinfo(skb)->nr_frags;
2371	unsigned int i;
2372	u32 offset = 0;
2373	u32 bcnt;
2374	u32 size = skb_headlen(skb);
2375	u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2376	u32 empty_slots;
2377	struct ring_desc_ex *put_tx;
2378	struct ring_desc_ex *start_tx;
2379	struct ring_desc_ex *prev_tx;
2380	struct nv_skb_map *prev_tx_ctx;
2381	struct nv_skb_map *start_tx_ctx = NULL;
2382	struct nv_skb_map *tmp_tx_ctx = NULL;
2383	unsigned long flags;
2384	netdev_tx_t ret = NETDEV_TX_OK;
2385
2386	/* add fragments to entries count */
2387	for (i = 0; i < fragments; i++) {
2388		u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2389
2390		entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2391			   ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2392	}
2393
2394	spin_lock_irqsave(&np->lock, flags);
2395	empty_slots = nv_get_empty_tx_slots(np);
2396	if (unlikely(empty_slots <= entries)) {
2397		netif_stop_queue(dev);
2398		np->tx_stop = 1;
2399		spin_unlock_irqrestore(&np->lock, flags);
2400
2401		/* When normal packets and/or xmit_more packets fill up
2402		 * tx_desc, it is necessary to trigger NIC tx reg.
2403		 */
2404		ret = NETDEV_TX_BUSY;
2405
2406		goto txkick;
2407	}
2408	spin_unlock_irqrestore(&np->lock, flags);
2409
2410	start_tx = put_tx = np->put_tx.ex;
2411	start_tx_ctx = np->put_tx_ctx;
2412
2413	/* setup the header buffer */
2414	do {
2415		bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2416		np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev,
2417						     skb->data + offset, bcnt,
2418						     DMA_TO_DEVICE);
2419		if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2420					       np->put_tx_ctx->dma))) {
2421			/* on DMA mapping error - drop the packet */
2422			dev_kfree_skb_any(skb);
2423			u64_stats_update_begin(&np->swstats_tx_syncp);
2424			nv_txrx_stats_inc(stat_tx_dropped);
2425			u64_stats_update_end(&np->swstats_tx_syncp);
2426
2427			ret = NETDEV_TX_OK;
2428
2429			goto dma_error;
2430		}
2431		np->put_tx_ctx->dma_len = bcnt;
2432		np->put_tx_ctx->dma_single = 1;
2433		put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2434		put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2435		put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2436
2437		tx_flags = NV_TX2_VALID;
2438		offset += bcnt;
2439		size -= bcnt;
2440		if (unlikely(put_tx++ == np->last_tx.ex))
2441			put_tx = np->tx_ring.ex;
2442		if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2443			np->put_tx_ctx = np->tx_skb;
2444	} while (size);
2445
2446	/* setup the fragments */
2447	for (i = 0; i < fragments; i++) {
2448		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2449		u32 frag_size = skb_frag_size(frag);
2450		offset = 0;
2451
2452		do {
2453			bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2454			if (!start_tx_ctx)
2455				start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2456			np->put_tx_ctx->dma = skb_frag_dma_map(
2457							&np->pci_dev->dev,
2458							frag, offset,
2459							bcnt,
2460							DMA_TO_DEVICE);
2461
2462			if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2463						       np->put_tx_ctx->dma))) {
2464
2465				/* Unwind the mapped fragments */
2466				do {
2467					nv_unmap_txskb(np, start_tx_ctx);
2468					if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2469						tmp_tx_ctx = np->tx_skb;
2470				} while (tmp_tx_ctx != np->put_tx_ctx);
2471				dev_kfree_skb_any(skb);
2472				np->put_tx_ctx = start_tx_ctx;
2473				u64_stats_update_begin(&np->swstats_tx_syncp);
2474				nv_txrx_stats_inc(stat_tx_dropped);
2475				u64_stats_update_end(&np->swstats_tx_syncp);
2476
2477				ret = NETDEV_TX_OK;
2478
2479				goto dma_error;
2480			}
2481			np->put_tx_ctx->dma_len = bcnt;
2482			np->put_tx_ctx->dma_single = 0;
2483			put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2484			put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2485			put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2486
2487			offset += bcnt;
2488			frag_size -= bcnt;
2489			if (unlikely(put_tx++ == np->last_tx.ex))
2490				put_tx = np->tx_ring.ex;
2491			if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2492				np->put_tx_ctx = np->tx_skb;
2493		} while (frag_size);
2494	}
2495
2496	if (unlikely(put_tx == np->tx_ring.ex))
2497		prev_tx = np->last_tx.ex;
2498	else
2499		prev_tx = put_tx - 1;
2500
2501	if (unlikely(np->put_tx_ctx == np->tx_skb))
2502		prev_tx_ctx = np->last_tx_ctx;
2503	else
2504		prev_tx_ctx = np->put_tx_ctx - 1;
2505
2506	/* set last fragment flag  */
2507	prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2508
2509	/* save skb in this slot's context area */
2510	prev_tx_ctx->skb = skb;
2511
2512	if (skb_is_gso(skb))
2513		tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2514	else
2515		tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2516			 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2517
2518	/* vlan tag */
2519	if (skb_vlan_tag_present(skb))
2520		start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2521					skb_vlan_tag_get(skb));
2522	else
2523		start_tx->txvlan = 0;
2524
2525	spin_lock_irqsave(&np->lock, flags);
2526
2527	if (np->tx_limit) {
2528		/* Limit the number of outstanding tx. Setup all fragments, but
2529		 * do not set the VALID bit on the first descriptor. Save a pointer
2530		 * to that descriptor and also for next skb_map element.
2531		 */
2532
2533		if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2534			if (!np->tx_change_owner)
2535				np->tx_change_owner = start_tx_ctx;
2536
2537			/* remove VALID bit */
2538			tx_flags &= ~NV_TX2_VALID;
2539			start_tx_ctx->first_tx_desc = start_tx;
2540			start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2541			np->tx_end_flip = np->put_tx_ctx;
2542		} else {
2543			np->tx_pkts_in_progress++;
2544		}
2545	}
2546
2547	/* set tx flags */
2548	start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2549
2550	netdev_sent_queue(np->dev, skb->len);
2551
2552	skb_tx_timestamp(skb);
2553
2554	np->put_tx.ex = put_tx;
2555
2556	spin_unlock_irqrestore(&np->lock, flags);
2557
2558txkick:
2559	if (netif_queue_stopped(dev) || !netdev_xmit_more()) {
2560		u32 txrxctl_kick;
2561dma_error:
2562		txrxctl_kick = NVREG_TXRXCTL_KICK | np->txrxctl_bits;
2563		writel(txrxctl_kick, get_hwbase(dev) + NvRegTxRxControl);
2564	}
2565
2566	return ret;
2567}
2568
2569static inline void nv_tx_flip_ownership(struct net_device *dev)
2570{
2571	struct fe_priv *np = netdev_priv(dev);
2572
2573	np->tx_pkts_in_progress--;
2574	if (np->tx_change_owner) {
2575		np->tx_change_owner->first_tx_desc->flaglen |=
2576			cpu_to_le32(NV_TX2_VALID);
2577		np->tx_pkts_in_progress++;
2578
2579		np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2580		if (np->tx_change_owner == np->tx_end_flip)
2581			np->tx_change_owner = NULL;
2582
2583		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2584	}
2585}
2586
2587/*
2588 * nv_tx_done: check for completed packets, release the skbs.
2589 *
2590 * Caller must own np->lock.
2591 */
2592static int nv_tx_done(struct net_device *dev, int limit)
2593{
2594	struct fe_priv *np = netdev_priv(dev);
2595	u32 flags;
2596	int tx_work = 0;
2597	struct ring_desc *orig_get_tx = np->get_tx.orig;
2598	unsigned int bytes_compl = 0;
2599
2600	while ((np->get_tx.orig != np->put_tx.orig) &&
2601	       !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2602	       (tx_work < limit)) {
2603
2604		nv_unmap_txskb(np, np->get_tx_ctx);
2605
2606		if (np->desc_ver == DESC_VER_1) {
2607			if (flags & NV_TX_LASTPACKET) {
2608				if (unlikely(flags & NV_TX_ERROR)) {
2609					if ((flags & NV_TX_RETRYERROR)
2610					    && !(flags & NV_TX_RETRYCOUNT_MASK))
2611						nv_legacybackoff_reseed(dev);
2612				} else {
2613					unsigned int len;
2614
2615					u64_stats_update_begin(&np->swstats_tx_syncp);
2616					nv_txrx_stats_inc(stat_tx_packets);
2617					len = np->get_tx_ctx->skb->len;
2618					nv_txrx_stats_add(stat_tx_bytes, len);
2619					u64_stats_update_end(&np->swstats_tx_syncp);
2620				}
2621				bytes_compl += np->get_tx_ctx->skb->len;
2622				dev_kfree_skb_any(np->get_tx_ctx->skb);
2623				np->get_tx_ctx->skb = NULL;
2624				tx_work++;
2625			}
2626		} else {
2627			if (flags & NV_TX2_LASTPACKET) {
2628				if (unlikely(flags & NV_TX2_ERROR)) {
2629					if ((flags & NV_TX2_RETRYERROR)
2630					    && !(flags & NV_TX2_RETRYCOUNT_MASK))
2631						nv_legacybackoff_reseed(dev);
2632				} else {
2633					unsigned int len;
2634
2635					u64_stats_update_begin(&np->swstats_tx_syncp);
2636					nv_txrx_stats_inc(stat_tx_packets);
2637					len = np->get_tx_ctx->skb->len;
2638					nv_txrx_stats_add(stat_tx_bytes, len);
2639					u64_stats_update_end(&np->swstats_tx_syncp);
2640				}
2641				bytes_compl += np->get_tx_ctx->skb->len;
2642				dev_kfree_skb_any(np->get_tx_ctx->skb);
2643				np->get_tx_ctx->skb = NULL;
2644				tx_work++;
2645			}
2646		}
2647		if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2648			np->get_tx.orig = np->tx_ring.orig;
2649		if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2650			np->get_tx_ctx = np->tx_skb;
2651	}
2652
2653	netdev_completed_queue(np->dev, tx_work, bytes_compl);
2654
2655	if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2656		np->tx_stop = 0;
2657		netif_wake_queue(dev);
2658	}
2659	return tx_work;
2660}
2661
2662static int nv_tx_done_optimized(struct net_device *dev, int limit)
2663{
2664	struct fe_priv *np = netdev_priv(dev);
2665	u32 flags;
2666	int tx_work = 0;
2667	struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2668	unsigned long bytes_cleaned = 0;
2669
2670	while ((np->get_tx.ex != np->put_tx.ex) &&
2671	       !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2672	       (tx_work < limit)) {
2673
2674		nv_unmap_txskb(np, np->get_tx_ctx);
2675
2676		if (flags & NV_TX2_LASTPACKET) {
2677			if (unlikely(flags & NV_TX2_ERROR)) {
2678				if ((flags & NV_TX2_RETRYERROR)
2679				    && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2680					if (np->driver_data & DEV_HAS_GEAR_MODE)
2681						nv_gear_backoff_reseed(dev);
2682					else
2683						nv_legacybackoff_reseed(dev);
2684				}
2685			} else {
2686				unsigned int len;
2687
2688				u64_stats_update_begin(&np->swstats_tx_syncp);
2689				nv_txrx_stats_inc(stat_tx_packets);
2690				len = np->get_tx_ctx->skb->len;
2691				nv_txrx_stats_add(stat_tx_bytes, len);
2692				u64_stats_update_end(&np->swstats_tx_syncp);
2693			}
2694
2695			bytes_cleaned += np->get_tx_ctx->skb->len;
2696			dev_kfree_skb_any(np->get_tx_ctx->skb);
2697			np->get_tx_ctx->skb = NULL;
2698			tx_work++;
2699
2700			if (np->tx_limit)
2701				nv_tx_flip_ownership(dev);
2702		}
2703
2704		if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2705			np->get_tx.ex = np->tx_ring.ex;
2706		if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2707			np->get_tx_ctx = np->tx_skb;
2708	}
2709
2710	netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2711
2712	if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2713		np->tx_stop = 0;
2714		netif_wake_queue(dev);
2715	}
2716	return tx_work;
2717}
2718
2719/*
2720 * nv_tx_timeout: dev->tx_timeout function
2721 * Called with netif_tx_lock held.
2722 */
2723static void nv_tx_timeout(struct net_device *dev, unsigned int txqueue)
2724{
2725	struct fe_priv *np = netdev_priv(dev);
2726	u8 __iomem *base = get_hwbase(dev);
2727	u32 status;
2728	union ring_type put_tx;
2729	int saved_tx_limit;
2730
2731	if (np->msi_flags & NV_MSI_X_ENABLED)
2732		status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2733	else
2734		status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2735
2736	netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2737
2738	if (unlikely(debug_tx_timeout)) {
2739		int i;
2740
2741		netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2742		netdev_info(dev, "Dumping tx registers\n");
2743		for (i = 0; i <= np->register_size; i += 32) {
2744			netdev_info(dev,
2745				    "%3x: %08x %08x %08x %08x "
2746				    "%08x %08x %08x %08x\n",
2747				    i,
2748				    readl(base + i + 0), readl(base + i + 4),
2749				    readl(base + i + 8), readl(base + i + 12),
2750				    readl(base + i + 16), readl(base + i + 20),
2751				    readl(base + i + 24), readl(base + i + 28));
2752		}
2753		netdev_info(dev, "Dumping tx ring\n");
2754		for (i = 0; i < np->tx_ring_size; i += 4) {
2755			if (!nv_optimized(np)) {
2756				netdev_info(dev,
2757					    "%03x: %08x %08x // %08x %08x "
2758					    "// %08x %08x // %08x %08x\n",
2759					    i,
2760					    le32_to_cpu(np->tx_ring.orig[i].buf),
2761					    le32_to_cpu(np->tx_ring.orig[i].flaglen),
2762					    le32_to_cpu(np->tx_ring.orig[i+1].buf),
2763					    le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2764					    le32_to_cpu(np->tx_ring.orig[i+2].buf),
2765					    le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2766					    le32_to_cpu(np->tx_ring.orig[i+3].buf),
2767					    le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2768			} else {
2769				netdev_info(dev,
2770					    "%03x: %08x %08x %08x "
2771					    "// %08x %08x %08x "
2772					    "// %08x %08x %08x "
2773					    "// %08x %08x %08x\n",
2774					    i,
2775					    le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2776					    le32_to_cpu(np->tx_ring.ex[i].buflow),
2777					    le32_to_cpu(np->tx_ring.ex[i].flaglen),
2778					    le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2779					    le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2780					    le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2781					    le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2782					    le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2783					    le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2784					    le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2785					    le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2786					    le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2787			}
2788		}
2789	}
2790
2791	spin_lock_irq(&np->lock);
2792
2793	/* 1) stop tx engine */
2794	nv_stop_tx(dev);
2795
2796	/* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2797	saved_tx_limit = np->tx_limit;
2798	np->tx_limit = 0; /* prevent giving HW any limited pkts */
2799	np->tx_stop = 0;  /* prevent waking tx queue */
2800	if (!nv_optimized(np))
2801		nv_tx_done(dev, np->tx_ring_size);
2802	else
2803		nv_tx_done_optimized(dev, np->tx_ring_size);
2804
2805	/* save current HW position */
2806	if (np->tx_change_owner)
2807		put_tx.ex = np->tx_change_owner->first_tx_desc;
2808	else
2809		put_tx = np->put_tx;
2810
2811	/* 3) clear all tx state */
2812	nv_drain_tx(dev);
2813	nv_init_tx(dev);
2814
2815	/* 4) restore state to current HW position */
2816	np->get_tx = np->put_tx = put_tx;
2817	np->tx_limit = saved_tx_limit;
2818
2819	/* 5) restart tx engine */
2820	nv_start_tx(dev);
2821	netif_wake_queue(dev);
2822	spin_unlock_irq(&np->lock);
2823}
2824
2825/*
2826 * Called when the nic notices a mismatch between the actual data len on the
2827 * wire and the len indicated in the 802 header
2828 */
2829static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2830{
2831	int hdrlen;	/* length of the 802 header */
2832	int protolen;	/* length as stored in the proto field */
2833
2834	/* 1) calculate len according to header */
2835	if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2836		protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2837		hdrlen = VLAN_HLEN;
2838	} else {
2839		protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2840		hdrlen = ETH_HLEN;
2841	}
2842	if (protolen > ETH_DATA_LEN)
2843		return datalen; /* Value in proto field not a len, no checks possible */
2844
2845	protolen += hdrlen;
2846	/* consistency checks: */
2847	if (datalen > ETH_ZLEN) {
2848		if (datalen >= protolen) {
2849			/* more data on wire than in 802 header, trim of
2850			 * additional data.
2851			 */
2852			return protolen;
2853		} else {
2854			/* less data on wire than mentioned in header.
2855			 * Discard the packet.
2856			 */
2857			return -1;
2858		}
2859	} else {
2860		/* short packet. Accept only if 802 values are also short */
2861		if (protolen > ETH_ZLEN) {
2862			return -1;
2863		}
2864		return datalen;
2865	}
2866}
2867
2868static void rx_missing_handler(u32 flags, struct fe_priv *np)
2869{
2870	if (flags & NV_RX_MISSEDFRAME) {
2871		u64_stats_update_begin(&np->swstats_rx_syncp);
2872		nv_txrx_stats_inc(stat_rx_missed_errors);
2873		u64_stats_update_end(&np->swstats_rx_syncp);
2874	}
2875}
2876
2877static int nv_rx_process(struct net_device *dev, int limit)
2878{
2879	struct fe_priv *np = netdev_priv(dev);
2880	u32 flags;
2881	int rx_work = 0;
2882	struct sk_buff *skb;
2883	int len;
2884
2885	while ((np->get_rx.orig != np->put_rx.orig) &&
2886	      !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2887		(rx_work < limit)) {
2888
2889		/*
2890		 * the packet is for us - immediately tear down the pci mapping.
2891		 * TODO: check if a prefetch of the first cacheline improves
2892		 * the performance.
2893		 */
2894		dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma,
2895				 np->get_rx_ctx->dma_len,
2896				 DMA_FROM_DEVICE);
2897		skb = np->get_rx_ctx->skb;
2898		np->get_rx_ctx->skb = NULL;
2899
2900		/* look at what we actually got: */
2901		if (np->desc_ver == DESC_VER_1) {
2902			if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2903				len = flags & LEN_MASK_V1;
2904				if (unlikely(flags & NV_RX_ERROR)) {
2905					if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2906						len = nv_getlen(dev, skb->data, len);
2907						if (len < 0) {
2908							dev_kfree_skb(skb);
2909							goto next_pkt;
2910						}
2911					}
2912					/* framing errors are soft errors */
2913					else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2914						if (flags & NV_RX_SUBTRACT1)
2915							len--;
2916					}
2917					/* the rest are hard errors */
2918					else {
2919						rx_missing_handler(flags, np);
2920						dev_kfree_skb(skb);
2921						goto next_pkt;
2922					}
2923				}
2924			} else {
2925				dev_kfree_skb(skb);
2926				goto next_pkt;
2927			}
2928		} else {
2929			if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2930				len = flags & LEN_MASK_V2;
2931				if (unlikely(flags & NV_RX2_ERROR)) {
2932					if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2933						len = nv_getlen(dev, skb->data, len);
2934						if (len < 0) {
2935							dev_kfree_skb(skb);
2936							goto next_pkt;
2937						}
2938					}
2939					/* framing errors are soft errors */
2940					else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2941						if (flags & NV_RX2_SUBTRACT1)
2942							len--;
2943					}
2944					/* the rest are hard errors */
2945					else {
2946						dev_kfree_skb(skb);
2947						goto next_pkt;
2948					}
2949				}
2950				if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2951				    ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2952					skb->ip_summed = CHECKSUM_UNNECESSARY;
2953			} else {
2954				dev_kfree_skb(skb);
2955				goto next_pkt;
2956			}
2957		}
2958		/* got a valid packet - forward it to the network core */
2959		skb_put(skb, len);
2960		skb->protocol = eth_type_trans(skb, dev);
2961		napi_gro_receive(&np->napi, skb);
2962		u64_stats_update_begin(&np->swstats_rx_syncp);
2963		nv_txrx_stats_inc(stat_rx_packets);
2964		nv_txrx_stats_add(stat_rx_bytes, len);
2965		u64_stats_update_end(&np->swstats_rx_syncp);
2966next_pkt:
2967		if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2968			np->get_rx.orig = np->rx_ring.orig;
2969		if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2970			np->get_rx_ctx = np->rx_skb;
2971
2972		rx_work++;
2973	}
2974
2975	return rx_work;
2976}
2977
2978static int nv_rx_process_optimized(struct net_device *dev, int limit)
2979{
2980	struct fe_priv *np = netdev_priv(dev);
2981	u32 flags;
2982	u32 vlanflags = 0;
2983	int rx_work = 0;
2984	struct sk_buff *skb;
2985	int len;
2986
2987	while ((np->get_rx.ex != np->put_rx.ex) &&
2988	      !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2989	      (rx_work < limit)) {
2990
2991		/*
2992		 * the packet is for us - immediately tear down the pci mapping.
2993		 * TODO: check if a prefetch of the first cacheline improves
2994		 * the performance.
2995		 */
2996		dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma,
2997				 np->get_rx_ctx->dma_len,
2998				 DMA_FROM_DEVICE);
2999		skb = np->get_rx_ctx->skb;
3000		np->get_rx_ctx->skb = NULL;
3001
3002		/* look at what we actually got: */
3003		if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
3004			len = flags & LEN_MASK_V2;
3005			if (unlikely(flags & NV_RX2_ERROR)) {
3006				if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
3007					len = nv_getlen(dev, skb->data, len);
3008					if (len < 0) {
3009						dev_kfree_skb(skb);
3010						goto next_pkt;
3011					}
3012				}
3013				/* framing errors are soft errors */
3014				else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
3015					if (flags & NV_RX2_SUBTRACT1)
3016						len--;
3017				}
3018				/* the rest are hard errors */
3019				else {
3020					dev_kfree_skb(skb);
3021					goto next_pkt;
3022				}
3023			}
3024
3025			if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
3026			    ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
3027				skb->ip_summed = CHECKSUM_UNNECESSARY;
3028
3029			/* got a valid packet - forward it to the network core */
3030			skb_put(skb, len);
3031			skb->protocol = eth_type_trans(skb, dev);
3032			prefetch(skb->data);
3033
3034			vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
3035
3036			/*
3037			 * There's need to check for NETIF_F_HW_VLAN_CTAG_RX
3038			 * here. Even if vlan rx accel is disabled,
3039			 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
3040			 */
3041			if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3042			    vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
3043				u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
3044
3045				__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
3046			}
3047			napi_gro_receive(&np->napi, skb);
3048			u64_stats_update_begin(&np->swstats_rx_syncp);
3049			nv_txrx_stats_inc(stat_rx_packets);
3050			nv_txrx_stats_add(stat_rx_bytes, len);
3051			u64_stats_update_end(&np->swstats_rx_syncp);
3052		} else {
3053			dev_kfree_skb(skb);
3054		}
3055next_pkt:
3056		if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
3057			np->get_rx.ex = np->rx_ring.ex;
3058		if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
3059			np->get_rx_ctx = np->rx_skb;
3060
3061		rx_work++;
3062	}
3063
3064	return rx_work;
3065}
3066
3067static void set_bufsize(struct net_device *dev)
3068{
3069	struct fe_priv *np = netdev_priv(dev);
3070
3071	if (dev->mtu <= ETH_DATA_LEN)
3072		np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
3073	else
3074		np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
3075}
3076
3077/*
3078 * nv_change_mtu: dev->change_mtu function
3079 * Called with RTNL held for read.
3080 */
3081static int nv_change_mtu(struct net_device *dev, int new_mtu)
3082{
3083	struct fe_priv *np = netdev_priv(dev);
3084	int old_mtu;
3085
3086	old_mtu = dev->mtu;
3087	WRITE_ONCE(dev->mtu, new_mtu);
3088
3089	/* return early if the buffer sizes will not change */
3090	if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
3091		return 0;
3092
3093	/* synchronized against open : rtnl_lock() held by caller */
3094	if (netif_running(dev)) {
3095		u8 __iomem *base = get_hwbase(dev);
3096		/*
3097		 * It seems that the nic preloads valid ring entries into an
3098		 * internal buffer. The procedure for flushing everything is
3099		 * guessed, there is probably a simpler approach.
3100		 * Changing the MTU is a rare event, it shouldn't matter.
3101		 */
3102		nv_disable_irq(dev);
3103		napi_disable(&np->napi);
3104		netif_tx_lock_bh(dev);
3105		netif_addr_lock(dev);
3106		spin_lock(&np->lock);
3107		/* stop engines */
3108		nv_stop_rxtx(dev);
3109		nv_txrx_reset(dev);
3110		/* drain rx queue */
3111		nv_drain_rxtx(dev);
3112		/* reinit driver view of the rx queue */
3113		set_bufsize(dev);
3114		if (nv_init_ring(dev)) {
3115			if (!np->in_shutdown)
3116				mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3117		}
3118		/* reinit nic view of the rx queue */
3119		writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3120		setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3121		writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3122			base + NvRegRingSizes);
3123		pci_push(base);
3124		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3125		pci_push(base);
3126
3127		/* restart rx engine */
3128		nv_start_rxtx(dev);
3129		spin_unlock(&np->lock);
3130		netif_addr_unlock(dev);
3131		netif_tx_unlock_bh(dev);
3132		napi_enable(&np->napi);
3133		nv_enable_irq(dev);
3134	}
3135	return 0;
3136}
3137
3138static void nv_copy_mac_to_hw(struct net_device *dev)
3139{
3140	u8 __iomem *base = get_hwbase(dev);
3141	u32 mac[2];
3142
3143	mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3144			(dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3145	mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3146
3147	writel(mac[0], base + NvRegMacAddrA);
3148	writel(mac[1], base + NvRegMacAddrB);
3149}
3150
3151/*
3152 * nv_set_mac_address: dev->set_mac_address function
3153 * Called with rtnl_lock() held.
3154 */
3155static int nv_set_mac_address(struct net_device *dev, void *addr)
3156{
3157	struct fe_priv *np = netdev_priv(dev);
3158	struct sockaddr *macaddr = (struct sockaddr *)addr;
3159
3160	if (!is_valid_ether_addr(macaddr->sa_data))
3161		return -EADDRNOTAVAIL;
3162
3163	/* synchronized against open : rtnl_lock() held by caller */
3164	eth_hw_addr_set(dev, macaddr->sa_data);
3165
3166	if (netif_running(dev)) {
3167		netif_tx_lock_bh(dev);
3168		netif_addr_lock(dev);
3169		spin_lock_irq(&np->lock);
3170
3171		/* stop rx engine */
3172		nv_stop_rx(dev);
3173
3174		/* set mac address */
3175		nv_copy_mac_to_hw(dev);
3176
3177		/* restart rx engine */
3178		nv_start_rx(dev);
3179		spin_unlock_irq(&np->lock);
3180		netif_addr_unlock(dev);
3181		netif_tx_unlock_bh(dev);
3182	} else {
3183		nv_copy_mac_to_hw(dev);
3184	}
3185	return 0;
3186}
3187
3188/*
3189 * nv_set_multicast: dev->set_multicast function
3190 * Called with netif_tx_lock held.
3191 */
3192static void nv_set_multicast(struct net_device *dev)
3193{
3194	struct fe_priv *np = netdev_priv(dev);
3195	u8 __iomem *base = get_hwbase(dev);
3196	u32 addr[2];
3197	u32 mask[2];
3198	u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3199
3200	memset(addr, 0, sizeof(addr));
3201	memset(mask, 0, sizeof(mask));
3202
3203	if (dev->flags & IFF_PROMISC) {
3204		pff |= NVREG_PFF_PROMISC;
3205	} else {
3206		pff |= NVREG_PFF_MYADDR;
3207
3208		if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3209			u32 alwaysOff[2];
3210			u32 alwaysOn[2];
3211
3212			alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3213			if (dev->flags & IFF_ALLMULTI) {
3214				alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3215			} else {
3216				struct netdev_hw_addr *ha;
3217
3218				netdev_for_each_mc_addr(ha, dev) {
3219					unsigned char *hw_addr = ha->addr;
3220					u32 a, b;
3221
3222					a = le32_to_cpu(*(__le32 *) hw_addr);
3223					b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3224					alwaysOn[0] &= a;
3225					alwaysOff[0] &= ~a;
3226					alwaysOn[1] &= b;
3227					alwaysOff[1] &= ~b;
3228				}
3229			}
3230			addr[0] = alwaysOn[0];
3231			addr[1] = alwaysOn[1];
3232			mask[0] = alwaysOn[0] | alwaysOff[0];
3233			mask[1] = alwaysOn[1] | alwaysOff[1];
3234		} else {
3235			mask[0] = NVREG_MCASTMASKA_NONE;
3236			mask[1] = NVREG_MCASTMASKB_NONE;
3237		}
3238	}
3239	addr[0] |= NVREG_MCASTADDRA_FORCE;
3240	pff |= NVREG_PFF_ALWAYS;
3241	spin_lock_irq(&np->lock);
3242	nv_stop_rx(dev);
3243	writel(addr[0], base + NvRegMulticastAddrA);
3244	writel(addr[1], base + NvRegMulticastAddrB);
3245	writel(mask[0], base + NvRegMulticastMaskA);
3246	writel(mask[1], base + NvRegMulticastMaskB);
3247	writel(pff, base + NvRegPacketFilterFlags);
3248	nv_start_rx(dev);
3249	spin_unlock_irq(&np->lock);
3250}
3251
3252static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3253{
3254	struct fe_priv *np = netdev_priv(dev);
3255	u8 __iomem *base = get_hwbase(dev);
3256
3257	np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3258
3259	if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3260		u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3261		if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3262			writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3263			np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3264		} else {
3265			writel(pff, base + NvRegPacketFilterFlags);
3266		}
3267	}
3268	if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3269		u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3270		if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3271			u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3272			if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3273				pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3274			if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3275				pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3276				/* limit the number of tx pause frames to a default of 8 */
3277				writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3278			}
3279			writel(pause_enable,  base + NvRegTxPauseFrame);
3280			writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3281			np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3282		} else {
3283			writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3284			writel(regmisc, base + NvRegMisc1);
3285		}
3286	}
3287}
3288
3289static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3290{
3291	struct fe_priv *np = netdev_priv(dev);
3292	u8 __iomem *base = get_hwbase(dev);
3293	u32 phyreg, txreg;
3294	int mii_status;
3295
3296	np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3297	np->duplex = duplex;
3298
3299	/* see if gigabit phy */
3300	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3301	if (mii_status & PHY_GIGABIT) {
3302		np->gigabit = PHY_GIGABIT;
3303		phyreg = readl(base + NvRegSlotTime);
3304		phyreg &= ~(0x3FF00);
3305		if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3306			phyreg |= NVREG_SLOTTIME_10_100_FULL;
3307		else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3308			phyreg |= NVREG_SLOTTIME_10_100_FULL;
3309		else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3310			phyreg |= NVREG_SLOTTIME_1000_FULL;
3311		writel(phyreg, base + NvRegSlotTime);
3312	}
3313
3314	phyreg = readl(base + NvRegPhyInterface);
3315	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3316	if (np->duplex == 0)
3317		phyreg |= PHY_HALF;
3318	if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3319		phyreg |= PHY_100;
3320	else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3321							NVREG_LINKSPEED_1000)
3322		phyreg |= PHY_1000;
3323	writel(phyreg, base + NvRegPhyInterface);
3324
3325	if (phyreg & PHY_RGMII) {
3326		if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3327							NVREG_LINKSPEED_1000)
3328			txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3329		else
3330			txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3331	} else {
3332		txreg = NVREG_TX_DEFERRAL_DEFAULT;
3333	}
3334	writel(txreg, base + NvRegTxDeferral);
3335
3336	if (np->desc_ver == DESC_VER_1) {
3337		txreg = NVREG_TX_WM_DESC1_DEFAULT;
3338	} else {
3339		if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3340					 NVREG_LINKSPEED_1000)
3341			txreg = NVREG_TX_WM_DESC2_3_1000;
3342		else
3343			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3344	}
3345	writel(txreg, base + NvRegTxWatermark);
3346
3347	writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3348			base + NvRegMisc1);
3349	pci_push(base);
3350	writel(np->linkspeed, base + NvRegLinkSpeed);
3351	pci_push(base);
3352}
3353
3354/**
3355 * nv_update_linkspeed - Setup the MAC according to the link partner
3356 * @dev: Network device to be configured
3357 *
3358 * The function queries the PHY and checks if there is a link partner.
3359 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3360 * set to 10 MBit HD.
3361 *
3362 * The function returns 0 if there is no link partner and 1 if there is
3363 * a good link partner.
3364 */
3365static int nv_update_linkspeed(struct net_device *dev)
3366{
3367	struct fe_priv *np = netdev_priv(dev);
3368	u8 __iomem *base = get_hwbase(dev);
3369	int adv = 0;
3370	int lpa = 0;
3371	int adv_lpa, adv_pause, lpa_pause;
3372	int newls = np->linkspeed;
3373	int newdup = np->duplex;
3374	int mii_status;
3375	u32 bmcr;
3376	int retval = 0;
3377	u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3378	u32 txrxFlags = 0;
3379	u32 phy_exp;
3380
3381	/* If device loopback is enabled, set carrier on and enable max link
3382	 * speed.
3383	 */
3384	bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3385	if (bmcr & BMCR_LOOPBACK) {
3386		if (netif_running(dev)) {
3387			nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3388			if (!netif_carrier_ok(dev))
3389				netif_carrier_on(dev);
3390		}
3391		return 1;
3392	}
3393
3394	/* BMSR_LSTATUS is latched, read it twice:
3395	 * we want the current value.
3396	 */
3397	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3398	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3399
3400	if (!(mii_status & BMSR_LSTATUS)) {
3401		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3402		newdup = 0;
3403		retval = 0;
3404		goto set_speed;
3405	}
3406
3407	if (np->autoneg == 0) {
3408		if (np->fixed_mode & LPA_100FULL) {
3409			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3410			newdup = 1;
3411		} else if (np->fixed_mode & LPA_100HALF) {
3412			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3413			newdup = 0;
3414		} else if (np->fixed_mode & LPA_10FULL) {
3415			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3416			newdup = 1;
3417		} else {
3418			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3419			newdup = 0;
3420		}
3421		retval = 1;
3422		goto set_speed;
3423	}
3424	/* check auto negotiation is complete */
3425	if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3426		/* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3427		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3428		newdup = 0;
3429		retval = 0;
3430		goto set_speed;
3431	}
3432
3433	adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3434	lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3435
3436	retval = 1;
3437	if (np->gigabit == PHY_GIGABIT) {
3438		control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3439		status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3440
3441		if ((control_1000 & ADVERTISE_1000FULL) &&
3442			(status_1000 & LPA_1000FULL)) {
3443			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3444			newdup = 1;
3445			goto set_speed;
3446		}
3447	}
3448
3449	/* FIXME: handle parallel detection properly */
3450	adv_lpa = lpa & adv;
3451	if (adv_lpa & LPA_100FULL) {
3452		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3453		newdup = 1;
3454	} else if (adv_lpa & LPA_100HALF) {
3455		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3456		newdup = 0;
3457	} else if (adv_lpa & LPA_10FULL) {
3458		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3459		newdup = 1;
3460	} else if (adv_lpa & LPA_10HALF) {
3461		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3462		newdup = 0;
3463	} else {
3464		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3465		newdup = 0;
3466	}
3467
3468set_speed:
3469	if (np->duplex == newdup && np->linkspeed == newls)
3470		return retval;
3471
3472	np->duplex = newdup;
3473	np->linkspeed = newls;
3474
3475	/* The transmitter and receiver must be restarted for safe update */
3476	if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3477		txrxFlags |= NV_RESTART_TX;
3478		nv_stop_tx(dev);
3479	}
3480	if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3481		txrxFlags |= NV_RESTART_RX;
3482		nv_stop_rx(dev);
3483	}
3484
3485	if (np->gigabit == PHY_GIGABIT) {
3486		phyreg = readl(base + NvRegSlotTime);
3487		phyreg &= ~(0x3FF00);
3488		if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3489		    ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3490			phyreg |= NVREG_SLOTTIME_10_100_FULL;
3491		else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3492			phyreg |= NVREG_SLOTTIME_1000_FULL;
3493		writel(phyreg, base + NvRegSlotTime);
3494	}
3495
3496	phyreg = readl(base + NvRegPhyInterface);
3497	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3498	if (np->duplex == 0)
3499		phyreg |= PHY_HALF;
3500	if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3501		phyreg |= PHY_100;
3502	else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3503		phyreg |= PHY_1000;
3504	writel(phyreg, base + NvRegPhyInterface);
3505
3506	phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3507	if (phyreg & PHY_RGMII) {
3508		if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3509			txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3510		} else {
3511			if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3512				if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3513					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3514				else
3515					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3516			} else {
3517				txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3518			}
3519		}
3520	} else {
3521		if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3522			txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3523		else
3524			txreg = NVREG_TX_DEFERRAL_DEFAULT;
3525	}
3526	writel(txreg, base + NvRegTxDeferral);
3527
3528	if (np->desc_ver == DESC_VER_1) {
3529		txreg = NVREG_TX_WM_DESC1_DEFAULT;
3530	} else {
3531		if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3532			txreg = NVREG_TX_WM_DESC2_3_1000;
3533		else
3534			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3535	}
3536	writel(txreg, base + NvRegTxWatermark);
3537
3538	writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3539		base + NvRegMisc1);
3540	pci_push(base);
3541	writel(np->linkspeed, base + NvRegLinkSpeed);
3542	pci_push(base);
3543
3544	pause_flags = 0;
3545	/* setup pause frame */
3546	if (netif_running(dev) && (np->duplex != 0)) {
3547		if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3548			adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3549			lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3550
3551			switch (adv_pause) {
3552			case ADVERTISE_PAUSE_CAP:
3553				if (lpa_pause & LPA_PAUSE_CAP) {
3554					pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3555					if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3556						pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3557				}
3558				break;
3559			case ADVERTISE_PAUSE_ASYM:
3560				if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3561					pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3562				break;
3563			case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3564				if (lpa_pause & LPA_PAUSE_CAP) {
3565					pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3566					if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3567						pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3568				}
3569				if (lpa_pause == LPA_PAUSE_ASYM)
3570					pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3571				break;
3572			}
3573		} else {
3574			pause_flags = np->pause_flags;
3575		}
3576	}
3577	nv_update_pause(dev, pause_flags);
3578
3579	if (txrxFlags & NV_RESTART_TX)
3580		nv_start_tx(dev);
3581	if (txrxFlags & NV_RESTART_RX)
3582		nv_start_rx(dev);
3583
3584	return retval;
3585}
3586
3587static void nv_linkchange(struct net_device *dev)
3588{
3589	if (nv_update_linkspeed(dev)) {
3590		if (!netif_carrier_ok(dev)) {
3591			netif_carrier_on(dev);
3592			netdev_info(dev, "link up\n");
3593			nv_txrx_gate(dev, false);
3594			nv_start_rx(dev);
3595		}
3596	} else {
3597		if (netif_carrier_ok(dev)) {
3598			netif_carrier_off(dev);
3599			netdev_info(dev, "link down\n");
3600			nv_txrx_gate(dev, true);
3601			nv_stop_rx(dev);
3602		}
3603	}
3604}
3605
3606static void nv_link_irq(struct net_device *dev)
3607{
3608	u8 __iomem *base = get_hwbase(dev);
3609	u32 miistat;
3610
3611	miistat = readl(base + NvRegMIIStatus);
3612	writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3613
3614	if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3615		nv_linkchange(dev);
3616}
3617
3618static void nv_msi_workaround(struct fe_priv *np)
3619{
3620
3621	/* Need to toggle the msi irq mask within the ethernet device,
3622	 * otherwise, future interrupts will not be detected.
3623	 */
3624	if (np->msi_flags & NV_MSI_ENABLED) {
3625		u8 __iomem *base = np->base;
3626
3627		writel(0, base + NvRegMSIIrqMask);
3628		writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3629	}
3630}
3631
3632static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3633{
3634	struct fe_priv *np = netdev_priv(dev);
3635
3636	if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3637		if (total_work > NV_DYNAMIC_THRESHOLD) {
3638			/* transition to poll based interrupts */
3639			np->quiet_count = 0;
3640			if (np->irqmask != NVREG_IRQMASK_CPU) {
3641				np->irqmask = NVREG_IRQMASK_CPU;
3642				return 1;
3643			}
3644		} else {
3645			if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3646				np->quiet_count++;
3647			} else {
3648				/* reached a period of low activity, switch
3649				   to per tx/rx packet interrupts */
3650				if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3651					np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3652					return 1;
3653				}
3654			}
3655		}
3656	}
3657	return 0;
3658}
3659
3660static irqreturn_t nv_nic_irq(int foo, void *data)
3661{
3662	struct net_device *dev = (struct net_device *) data;
3663	struct fe_priv *np = netdev_priv(dev);
3664	u8 __iomem *base = get_hwbase(dev);
3665
3666	if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3667		np->events = readl(base + NvRegIrqStatus);
3668		writel(np->events, base + NvRegIrqStatus);
3669	} else {
3670		np->events = readl(base + NvRegMSIXIrqStatus);
3671		writel(np->events, base + NvRegMSIXIrqStatus);
3672	}
3673	if (!(np->events & np->irqmask))
3674		return IRQ_NONE;
3675
3676	nv_msi_workaround(np);
3677
3678	if (napi_schedule_prep(&np->napi)) {
3679		/*
3680		 * Disable further irq's (msix not enabled with napi)
3681		 */
3682		writel(0, base + NvRegIrqMask);
3683		__napi_schedule(&np->napi);
3684	}
3685
3686	return IRQ_HANDLED;
3687}
3688
3689/* All _optimized functions are used to help increase performance
3690 * (reduce CPU and increase throughput). They use descripter version 3,
3691 * compiler directives, and reduce memory accesses.
3692 */
3693static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3694{
3695	struct net_device *dev = (struct net_device *) data;
3696	struct fe_priv *np = netdev_priv(dev);
3697	u8 __iomem *base = get_hwbase(dev);
3698
3699	if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3700		np->events = readl(base + NvRegIrqStatus);
3701		writel(np->events, base + NvRegIrqStatus);
3702	} else {
3703		np->events = readl(base + NvRegMSIXIrqStatus);
3704		writel(np->events, base + NvRegMSIXIrqStatus);
3705	}
3706	if (!(np->events & np->irqmask))
3707		return IRQ_NONE;
3708
3709	nv_msi_workaround(np);
3710
3711	if (napi_schedule_prep(&np->napi)) {
3712		/*
3713		 * Disable further irq's (msix not enabled with napi)
3714		 */
3715		writel(0, base + NvRegIrqMask);
3716		__napi_schedule(&np->napi);
3717	}
3718
3719	return IRQ_HANDLED;
3720}
3721
3722static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3723{
3724	struct net_device *dev = (struct net_device *) data;
3725	struct fe_priv *np = netdev_priv(dev);
3726	u8 __iomem *base = get_hwbase(dev);
3727	u32 events;
3728	int i;
3729	unsigned long flags;
3730
3731	for (i = 0;; i++) {
3732		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3733		writel(events, base + NvRegMSIXIrqStatus);
3734		netdev_dbg(dev, "tx irq events: %08x\n", events);
3735		if (!(events & np->irqmask))
3736			break;
3737
3738		spin_lock_irqsave(&np->lock, flags);
3739		nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3740		spin_unlock_irqrestore(&np->lock, flags);
3741
3742		if (unlikely(i > max_interrupt_work)) {
3743			spin_lock_irqsave(&np->lock, flags);
3744			/* disable interrupts on the nic */
3745			writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3746			pci_push(base);
3747
3748			if (!np->in_shutdown) {
3749				np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3750				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3751			}
3752			spin_unlock_irqrestore(&np->lock, flags);
3753			netdev_dbg(dev, "%s: too many iterations (%d)\n",
3754				   __func__, i);
3755			break;
3756		}
3757
3758	}
3759
3760	return IRQ_RETVAL(i);
3761}
3762
3763static int nv_napi_poll(struct napi_struct *napi, int budget)
3764{
3765	struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3766	struct net_device *dev = np->dev;
3767	u8 __iomem *base = get_hwbase(dev);
3768	unsigned long flags;
3769	int retcode;
3770	int rx_count, tx_work = 0, rx_work = 0;
3771
3772	do {
3773		if (!nv_optimized(np)) {
3774			spin_lock_irqsave(&np->lock, flags);
3775			tx_work += nv_tx_done(dev, np->tx_ring_size);
3776			spin_unlock_irqrestore(&np->lock, flags);
3777
3778			rx_count = nv_rx_process(dev, budget - rx_work);
3779			retcode = nv_alloc_rx(dev);
3780		} else {
3781			spin_lock_irqsave(&np->lock, flags);
3782			tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3783			spin_unlock_irqrestore(&np->lock, flags);
3784
3785			rx_count = nv_rx_process_optimized(dev,
3786			    budget - rx_work);
3787			retcode = nv_alloc_rx_optimized(dev);
3788		}
3789	} while (retcode == 0 &&
3790		 rx_count > 0 && (rx_work += rx_count) < budget);
3791
3792	if (retcode) {
3793		spin_lock_irqsave(&np->lock, flags);
3794		if (!np->in_shutdown)
3795			mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3796		spin_unlock_irqrestore(&np->lock, flags);
3797	}
3798
3799	nv_change_interrupt_mode(dev, tx_work + rx_work);
3800
3801	if (unlikely(np->events & NVREG_IRQ_LINK)) {
3802		spin_lock_irqsave(&np->lock, flags);
3803		nv_link_irq(dev);
3804		spin_unlock_irqrestore(&np->lock, flags);
3805	}
3806	if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3807		spin_lock_irqsave(&np->lock, flags);
3808		nv_linkchange(dev);
3809		spin_unlock_irqrestore(&np->lock, flags);
3810		np->link_timeout = jiffies + LINK_TIMEOUT;
3811	}
3812	if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3813		spin_lock_irqsave(&np->lock, flags);
3814		if (!np->in_shutdown) {
3815			np->nic_poll_irq = np->irqmask;
3816			np->recover_error = 1;
3817			mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3818		}
3819		spin_unlock_irqrestore(&np->lock, flags);
3820		napi_complete(napi);
3821		return rx_work;
3822	}
3823
3824	if (rx_work < budget) {
3825		/* re-enable interrupts
3826		   (msix not enabled in napi) */
3827		napi_complete_done(napi, rx_work);
3828
3829		writel(np->irqmask, base + NvRegIrqMask);
3830	}
3831	return rx_work;
3832}
3833
3834static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3835{
3836	struct net_device *dev = (struct net_device *) data;
3837	struct fe_priv *np = netdev_priv(dev);
3838	u8 __iomem *base = get_hwbase(dev);
3839	u32 events;
3840	int i;
3841	unsigned long flags;
3842
3843	for (i = 0;; i++) {
3844		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3845		writel(events, base + NvRegMSIXIrqStatus);
3846		netdev_dbg(dev, "rx irq events: %08x\n", events);
3847		if (!(events & np->irqmask))
3848			break;
3849
3850		if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3851			if (unlikely(nv_alloc_rx_optimized(dev))) {
3852				spin_lock_irqsave(&np->lock, flags);
3853				if (!np->in_shutdown)
3854					mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3855				spin_unlock_irqrestore(&np->lock, flags);
3856			}
3857		}
3858
3859		if (unlikely(i > max_interrupt_work)) {
3860			spin_lock_irqsave(&np->lock, flags);
3861			/* disable interrupts on the nic */
3862			writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3863			pci_push(base);
3864
3865			if (!np->in_shutdown) {
3866				np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3867				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3868			}
3869			spin_unlock_irqrestore(&np->lock, flags);
3870			netdev_dbg(dev, "%s: too many iterations (%d)\n",
3871				   __func__, i);
3872			break;
3873		}
3874	}
3875
3876	return IRQ_RETVAL(i);
3877}
3878
3879static irqreturn_t nv_nic_irq_other(int foo, void *data)
3880{
3881	struct net_device *dev = (struct net_device *) data;
3882	struct fe_priv *np = netdev_priv(dev);
3883	u8 __iomem *base = get_hwbase(dev);
3884	u32 events;
3885	int i;
3886	unsigned long flags;
3887
3888	for (i = 0;; i++) {
3889		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3890		writel(events, base + NvRegMSIXIrqStatus);
3891		netdev_dbg(dev, "irq events: %08x\n", events);
3892		if (!(events & np->irqmask))
3893			break;
3894
3895		/* check tx in case we reached max loop limit in tx isr */
3896		spin_lock_irqsave(&np->lock, flags);
3897		nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3898		spin_unlock_irqrestore(&np->lock, flags);
3899
3900		if (events & NVREG_IRQ_LINK) {
3901			spin_lock_irqsave(&np->lock, flags);
3902			nv_link_irq(dev);
3903			spin_unlock_irqrestore(&np->lock, flags);
3904		}
3905		if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3906			spin_lock_irqsave(&np->lock, flags);
3907			nv_linkchange(dev);
3908			spin_unlock_irqrestore(&np->lock, flags);
3909			np->link_timeout = jiffies + LINK_TIMEOUT;
3910		}
3911		if (events & NVREG_IRQ_RECOVER_ERROR) {
3912			spin_lock_irqsave(&np->lock, flags);
3913			/* disable interrupts on the nic */
3914			writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3915			pci_push(base);
3916
3917			if (!np->in_shutdown) {
3918				np->nic_poll_irq |= NVREG_IRQ_OTHER;
3919				np->recover_error = 1;
3920				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3921			}
3922			spin_unlock_irqrestore(&np->lock, flags);
3923			break;
3924		}
3925		if (unlikely(i > max_interrupt_work)) {
3926			spin_lock_irqsave(&np->lock, flags);
3927			/* disable interrupts on the nic */
3928			writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3929			pci_push(base);
3930
3931			if (!np->in_shutdown) {
3932				np->nic_poll_irq |= NVREG_IRQ_OTHER;
3933				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3934			}
3935			spin_unlock_irqrestore(&np->lock, flags);
3936			netdev_dbg(dev, "%s: too many iterations (%d)\n",
3937				   __func__, i);
3938			break;
3939		}
3940
3941	}
3942
3943	return IRQ_RETVAL(i);
3944}
3945
3946static irqreturn_t nv_nic_irq_test(int foo, void *data)
3947{
3948	struct net_device *dev = (struct net_device *) data;
3949	struct fe_priv *np = netdev_priv(dev);
3950	u8 __iomem *base = get_hwbase(dev);
3951	u32 events;
3952
3953	if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3954		events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3955		writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3956	} else {
3957		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3958		writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3959	}
3960	pci_push(base);
3961	if (!(events & NVREG_IRQ_TIMER))
3962		return IRQ_RETVAL(0);
3963
3964	nv_msi_workaround(np);
3965
3966	spin_lock(&np->lock);
3967	np->intr_test = 1;
3968	spin_unlock(&np->lock);
3969
3970	return IRQ_RETVAL(1);
3971}
3972
3973static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3974{
3975	u8 __iomem *base = get_hwbase(dev);
3976	int i;
3977	u32 msixmap = 0;
3978
3979	/* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3980	 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3981	 * the remaining 8 interrupts.
3982	 */
3983	for (i = 0; i < 8; i++) {
3984		if ((irqmask >> i) & 0x1)
3985			msixmap |= vector << (i << 2);
3986	}
3987	writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3988
3989	msixmap = 0;
3990	for (i = 0; i < 8; i++) {
3991		if ((irqmask >> (i + 8)) & 0x1)
3992			msixmap |= vector << (i << 2);
3993	}
3994	writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3995}
3996
3997static int nv_request_irq(struct net_device *dev, int intr_test)
3998{
3999	struct fe_priv *np = get_nvpriv(dev);
4000	u8 __iomem *base = get_hwbase(dev);
4001	int ret;
4002	int i;
4003	irqreturn_t (*handler)(int foo, void *data);
4004
4005	if (intr_test) {
4006		handler = nv_nic_irq_test;
4007	} else {
4008		if (nv_optimized(np))
4009			handler = nv_nic_irq_optimized;
4010		else
4011			handler = nv_nic_irq;
4012	}
4013
4014	if (np->msi_flags & NV_MSI_X_CAPABLE) {
4015		for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4016			np->msi_x_entry[i].entry = i;
4017		ret = pci_enable_msix_range(np->pci_dev,
4018					    np->msi_x_entry,
4019					    np->msi_flags & NV_MSI_X_VECTORS_MASK,
4020					    np->msi_flags & NV_MSI_X_VECTORS_MASK);
4021		if (ret > 0) {
4022			np->msi_flags |= NV_MSI_X_ENABLED;
4023			if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
4024				/* Request irq for rx handling */
4025				sprintf(np->name_rx, "%s-rx", dev->name);
4026				ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
4027						  nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev);
4028				if (ret) {
4029					netdev_info(dev,
4030						    "request_irq failed for rx %d\n",
4031						    ret);
4032					pci_disable_msix(np->pci_dev);
4033					np->msi_flags &= ~NV_MSI_X_ENABLED;
4034					goto out_err;
4035				}
4036				/* Request irq for tx handling */
4037				sprintf(np->name_tx, "%s-tx", dev->name);
4038				ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4039						  nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev);
4040				if (ret) {
4041					netdev_info(dev,
4042						    "request_irq failed for tx %d\n",
4043						    ret);
4044					pci_disable_msix(np->pci_dev);
4045					np->msi_flags &= ~NV_MSI_X_ENABLED;
4046					goto out_free_rx;
4047				}
4048				/* Request irq for link and timer handling */
4049				sprintf(np->name_other, "%s-other", dev->name);
4050				ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4051						  nv_nic_irq_other, IRQF_SHARED, np->name_other, dev);
4052				if (ret) {
4053					netdev_info(dev,
4054						    "request_irq failed for link %d\n",
4055						    ret);
4056					pci_disable_msix(np->pci_dev);
4057					np->msi_flags &= ~NV_MSI_X_ENABLED;
4058					goto out_free_tx;
4059				}
4060				/* map interrupts to their respective vector */
4061				writel(0, base + NvRegMSIXMap0);
4062				writel(0, base + NvRegMSIXMap1);
4063				set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4064				set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4065				set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4066			} else {
4067				/* Request irq for all interrupts */
4068				ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector,
4069						  handler, IRQF_SHARED, dev->name, dev);
4070				if (ret) {
4071					netdev_info(dev,
4072						    "request_irq failed %d\n",
4073						    ret);
4074					pci_disable_msix(np->pci_dev);
4075					np->msi_flags &= ~NV_MSI_X_ENABLED;
4076					goto out_err;
4077				}
4078
4079				/* map interrupts to vector 0 */
4080				writel(0, base + NvRegMSIXMap0);
4081				writel(0, base + NvRegMSIXMap1);
4082			}
4083			netdev_info(dev, "MSI-X enabled\n");
4084			return 0;
4085		}
4086	}
4087	if (np->msi_flags & NV_MSI_CAPABLE) {
4088		ret = pci_enable_msi(np->pci_dev);
4089		if (ret == 0) {
4090			np->msi_flags |= NV_MSI_ENABLED;
4091			ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev);
4092			if (ret) {
4093				netdev_info(dev, "request_irq failed %d\n",
4094					    ret);
4095				pci_disable_msi(np->pci_dev);
4096				np->msi_flags &= ~NV_MSI_ENABLED;
4097				goto out_err;
4098			}
4099
4100			/* map interrupts to vector 0 */
4101			writel(0, base + NvRegMSIMap0);
4102			writel(0, base + NvRegMSIMap1);
4103			/* enable msi vector 0 */
4104			writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4105			netdev_info(dev, "MSI enabled\n");
4106			return 0;
4107		}
4108	}
4109
4110	if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4111		goto out_err;
4112
4113	return 0;
4114out_free_tx:
4115	free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4116out_free_rx:
4117	free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4118out_err:
4119	return 1;
4120}
4121
4122static void nv_free_irq(struct net_device *dev)
4123{
4124	struct fe_priv *np = get_nvpriv(dev);
4125	int i;
4126
4127	if (np->msi_flags & NV_MSI_X_ENABLED) {
4128		for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4129			free_irq(np->msi_x_entry[i].vector, dev);
4130		pci_disable_msix(np->pci_dev);
4131		np->msi_flags &= ~NV_MSI_X_ENABLED;
4132	} else {
4133		free_irq(np->pci_dev->irq, dev);
4134		if (np->msi_flags & NV_MSI_ENABLED) {
4135			pci_disable_msi(np->pci_dev);
4136			np->msi_flags &= ~NV_MSI_ENABLED;
4137		}
4138	}
4139}
4140
4141static void nv_do_nic_poll(struct timer_list *t)
4142{
4143	struct fe_priv *np = timer_container_of(np, t, nic_poll);
4144	struct net_device *dev = np->dev;
4145	u8 __iomem *base = get_hwbase(dev);
4146	u32 mask = 0;
4147	unsigned long flags;
4148	unsigned int irq = 0;
4149
4150	/*
4151	 * First disable irq(s) and then
4152	 * reenable interrupts on the nic, we have to do this before calling
4153	 * nv_nic_irq because that may decide to do otherwise
4154	 */
4155
4156	if (!using_multi_irqs(dev)) {
4157		if (np->msi_flags & NV_MSI_X_ENABLED)
4158			irq = np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector;
4159		else
4160			irq = np->pci_dev->irq;
4161		mask = np->irqmask;
4162	} else {
4163		if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4164			irq = np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector;
4165			mask |= NVREG_IRQ_RX_ALL;
4166		}
4167		if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4168			irq = np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector;
4169			mask |= NVREG_IRQ_TX_ALL;
4170		}
4171		if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4172			irq = np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector;
4173			mask |= NVREG_IRQ_OTHER;
4174		}
4175	}
4176
4177	disable_irq_nosync_lockdep_irqsave(irq, &flags);
4178	synchronize_irq(irq);
4179
4180	if (np->recover_error) {
4181		np->recover_error = 0;
4182		netdev_info(dev, "MAC in recoverable error state\n");
4183		if (netif_running(dev)) {
4184			netif_tx_lock_bh(dev);
4185			netif_addr_lock(dev);
4186			spin_lock(&np->lock);
4187			/* stop engines */
4188			nv_stop_rxtx(dev);
4189			if (np->driver_data & DEV_HAS_POWER_CNTRL)
4190				nv_mac_reset(dev);
4191			nv_txrx_reset(dev);
4192			/* drain rx queue */
4193			nv_drain_rxtx(dev);
4194			/* reinit driver view of the rx queue */
4195			set_bufsize(dev);
4196			if (nv_init_ring(dev)) {
4197				if (!np->in_shutdown)
4198					mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4199			}
4200			/* reinit nic view of the rx queue */
4201			writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4202			setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4203			writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4204				base + NvRegRingSizes);
4205			pci_push(base);
4206			writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4207			pci_push(base);
4208			/* clear interrupts */
4209			if (!(np->msi_flags & NV_MSI_X_ENABLED))
4210				writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4211			else
4212				writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4213
4214			/* restart rx engine */
4215			nv_start_rxtx(dev);
4216			spin_unlock(&np->lock);
4217			netif_addr_unlock(dev);
4218			netif_tx_unlock_bh(dev);
4219		}
4220	}
4221
4222	writel(mask, base + NvRegIrqMask);
4223	pci_push(base);
4224
4225	if (!using_multi_irqs(dev)) {
4226		np->nic_poll_irq = 0;
4227		if (nv_optimized(np))
4228			nv_nic_irq_optimized(0, dev);
4229		else
4230			nv_nic_irq(0, dev);
4231	} else {
4232		if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4233			np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4234			nv_nic_irq_rx(0, dev);
4235		}
4236		if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4237			np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4238			nv_nic_irq_tx(0, dev);
4239		}
4240		if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4241			np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4242			nv_nic_irq_other(0, dev);
4243		}
4244	}
4245
4246	enable_irq_lockdep_irqrestore(irq, &flags);
4247}
4248
4249#ifdef CONFIG_NET_POLL_CONTROLLER
4250static void nv_poll_controller(struct net_device *dev)
4251{
4252	struct fe_priv *np = netdev_priv(dev);
4253
4254	nv_do_nic_poll(&np->nic_poll);
4255}
4256#endif
4257
4258static void nv_do_stats_poll(struct timer_list *t)
4259	__acquires(&netdev_priv(dev)->hwstats_lock)
4260	__releases(&netdev_priv(dev)->hwstats_lock)
4261{
4262	struct fe_priv *np = timer_container_of(np, t, stats_poll);
4263	struct net_device *dev = np->dev;
4264
4265	/* If lock is currently taken, the stats are being refreshed
4266	 * and hence fresh enough */
4267	if (spin_trylock(&np->hwstats_lock)) {
4268		nv_update_stats(dev);
4269		spin_unlock(&np->hwstats_lock);
4270	}
4271
4272	if (!np->in_shutdown)
4273		mod_timer(&np->stats_poll,
4274			round_jiffies(jiffies + STATS_INTERVAL));
4275}
4276
4277static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4278{
4279	struct fe_priv *np = netdev_priv(dev);
4280	strscpy(info->driver, DRV_NAME, sizeof(info->driver));
4281	strscpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4282	strscpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4283}
4284
4285static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4286{
4287	struct fe_priv *np = netdev_priv(dev);
4288	wolinfo->supported = WAKE_MAGIC;
4289
4290	spin_lock_irq(&np->lock);
4291	if (np->wolenabled)
4292		wolinfo->wolopts = WAKE_MAGIC;
4293	spin_unlock_irq(&np->lock);
4294}
4295
4296static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4297{
4298	struct fe_priv *np = netdev_priv(dev);
4299	u8 __iomem *base = get_hwbase(dev);
4300	u32 flags = 0;
4301
4302	if (wolinfo->wolopts == 0) {
4303		np->wolenabled = 0;
4304	} else if (wolinfo->wolopts & WAKE_MAGIC) {
4305		np->wolenabled = 1;
4306		flags = NVREG_WAKEUPFLAGS_ENABLE;
4307	}
4308	if (netif_running(dev)) {
4309		spin_lock_irq(&np->lock);
4310		writel(flags, base + NvRegWakeUpFlags);
4311		spin_unlock_irq(&np->lock);
4312	}
4313	device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4314	return 0;
4315}
4316
4317static int nv_get_link_ksettings(struct net_device *dev,
4318				 struct ethtool_link_ksettings *cmd)
4319{
4320	struct fe_priv *np = netdev_priv(dev);
4321	u32 speed, supported, advertising;
4322	int adv;
4323
4324	spin_lock_irq(&np->lock);
4325	cmd->base.port = PORT_MII;
4326	if (!netif_running(dev)) {
4327		/* We do not track link speed / duplex setting if the
4328		 * interface is disabled. Force a link check */
4329		if (nv_update_linkspeed(dev)) {
4330			netif_carrier_on(dev);
4331		} else {
4332			netif_carrier_off(dev);
4333		}
4334	}
4335
4336	if (netif_carrier_ok(dev)) {
4337		switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4338		case NVREG_LINKSPEED_10:
4339			speed = SPEED_10;
4340			break;
4341		case NVREG_LINKSPEED_100:
4342			speed = SPEED_100;
4343			break;
4344		case NVREG_LINKSPEED_1000:
4345			speed = SPEED_1000;
4346			break;
4347		default:
4348			speed = -1;
4349			break;
4350		}
4351		cmd->base.duplex = DUPLEX_HALF;
4352		if (np->duplex)
4353			cmd->base.duplex = DUPLEX_FULL;
4354	} else {
4355		speed = SPEED_UNKNOWN;
4356		cmd->base.duplex = DUPLEX_UNKNOWN;
4357	}
4358	cmd->base.speed = speed;
4359	cmd->base.autoneg = np->autoneg;
4360
4361	advertising = ADVERTISED_MII;
4362	if (np->autoneg) {
4363		advertising |= ADVERTISED_Autoneg;
4364		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4365		if (adv & ADVERTISE_10HALF)
4366			advertising |= ADVERTISED_10baseT_Half;
4367		if (adv & ADVERTISE_10FULL)
4368			advertising |= ADVERTISED_10baseT_Full;
4369		if (adv & ADVERTISE_100HALF)
4370			advertising |= ADVERTISED_100baseT_Half;
4371		if (adv & ADVERTISE_100FULL)
4372			advertising |= ADVERTISED_100baseT_Full;
4373		if (np->gigabit == PHY_GIGABIT) {
4374			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4375			if (adv & ADVERTISE_1000FULL)
4376				advertising |= ADVERTISED_1000baseT_Full;
4377		}
4378	}
4379	supported = (SUPPORTED_Autoneg |
4380		SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4381		SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4382		SUPPORTED_MII);
4383	if (np->gigabit == PHY_GIGABIT)
4384		supported |= SUPPORTED_1000baseT_Full;
4385
4386	cmd->base.phy_address = np->phyaddr;
4387
4388	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
4389						supported);
4390	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
4391						advertising);
4392
4393	/* ignore maxtxpkt, maxrxpkt for now */
4394	spin_unlock_irq(&np->lock);
4395	return 0;
4396}
4397
4398static int nv_set_link_ksettings(struct net_device *dev,
4399				 const struct ethtool_link_ksettings *cmd)
4400{
4401	struct fe_priv *np = netdev_priv(dev);
4402	u32 speed = cmd->base.speed;
4403	u32 advertising;
4404
4405	ethtool_convert_link_mode_to_legacy_u32(&advertising,
4406						cmd->link_modes.advertising);
4407
4408	if (cmd->base.port != PORT_MII)
4409		return -EINVAL;
4410	if (cmd->base.phy_address != np->phyaddr) {
4411		/* TODO: support switching between multiple phys. Should be
4412		 * trivial, but not enabled due to lack of test hardware. */
4413		return -EINVAL;
4414	}
4415	if (cmd->base.autoneg == AUTONEG_ENABLE) {
4416		u32 mask;
4417
4418		mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4419			  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4420		if (np->gigabit == PHY_GIGABIT)
4421			mask |= ADVERTISED_1000baseT_Full;
4422
4423		if ((advertising & mask) == 0)
4424			return -EINVAL;
4425
4426	} else if (cmd->base.autoneg == AUTONEG_DISABLE) {
4427		/* Note: autonegotiation disable, speed 1000 intentionally
4428		 * forbidden - no one should need that. */
4429
4430		if (speed != SPEED_10 && speed != SPEED_100)
4431			return -EINVAL;
4432		if (cmd->base.duplex != DUPLEX_HALF &&
4433		    cmd->base.duplex != DUPLEX_FULL)
4434			return -EINVAL;
4435	} else {
4436		return -EINVAL;
4437	}
4438
4439	netif_carrier_off(dev);
4440	if (netif_running(dev)) {
4441		unsigned long flags;
4442
4443		nv_disable_irq(dev);
4444		netif_tx_lock_bh(dev);
4445		netif_addr_lock(dev);
4446		/* with plain spinlock lockdep complains */
4447		spin_lock_irqsave(&np->lock, flags);
4448		/* stop engines */
4449		/* FIXME:
4450		 * this can take some time, and interrupts are disabled
4451		 * due to spin_lock_irqsave, but let's hope no daemon
4452		 * is going to change the settings very often...
4453		 * Worst case:
4454		 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4455		 * + some minor delays, which is up to a second approximately
4456		 */
4457		nv_stop_rxtx(dev);
4458		spin_unlock_irqrestore(&np->lock, flags);
4459		netif_addr_unlock(dev);
4460		netif_tx_unlock_bh(dev);
4461	}
4462
4463	if (cmd->base.autoneg == AUTONEG_ENABLE) {
4464		int adv, bmcr;
4465
4466		np->autoneg = 1;
4467
4468		/* advertise only what has been requested */
4469		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4470		adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4471		if (advertising & ADVERTISED_10baseT_Half)
4472			adv |= ADVERTISE_10HALF;
4473		if (advertising & ADVERTISED_10baseT_Full)
4474			adv |= ADVERTISE_10FULL;
4475		if (advertising & ADVERTISED_100baseT_Half)
4476			adv |= ADVERTISE_100HALF;
4477		if (advertising & ADVERTISED_100baseT_Full)
4478			adv |= ADVERTISE_100FULL;
4479		if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisements but disable tx pause */
4480			adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4481		if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4482			adv |=  ADVERTISE_PAUSE_ASYM;
4483		mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4484
4485		if (np->gigabit == PHY_GIGABIT) {
4486			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4487			adv &= ~ADVERTISE_1000FULL;
4488			if (advertising & ADVERTISED_1000baseT_Full)
4489				adv |= ADVERTISE_1000FULL;
4490			mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4491		}
4492
4493		if (netif_running(dev))
4494			netdev_info(dev, "link down\n");
4495		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4496		if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4497			bmcr |= BMCR_ANENABLE;
4498			/* reset the phy in order for settings to stick,
4499			 * and cause autoneg to start */
4500			if (phy_reset(dev, bmcr)) {
4501				netdev_info(dev, "phy reset failed\n");
4502				return -EINVAL;
4503			}
4504		} else {
4505			bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4506			mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4507		}
4508	} else {
4509		int adv, bmcr;
4510
4511		np->autoneg = 0;
4512
4513		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4514		adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4515		if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF)
4516			adv |= ADVERTISE_10HALF;
4517		if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL)
4518			adv |= ADVERTISE_10FULL;
4519		if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF)
4520			adv |= ADVERTISE_100HALF;
4521		if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL)
4522			adv |= ADVERTISE_100FULL;
4523		np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4524		if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4525			adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4526			np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4527		}
4528		if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4529			adv |=  ADVERTISE_PAUSE_ASYM;
4530			np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4531		}
4532		mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4533		np->fixed_mode = adv;
4534
4535		if (np->gigabit == PHY_GIGABIT) {
4536			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4537			adv &= ~ADVERTISE_1000FULL;
4538			mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4539		}
4540
4541		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4542		bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4543		if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4544			bmcr |= BMCR_FULLDPLX;
4545		if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4546			bmcr |= BMCR_SPEED100;
4547		if (np->phy_oui == PHY_OUI_MARVELL) {
4548			/* reset the phy in order for forced mode settings to stick */
4549			if (phy_reset(dev, bmcr)) {
4550				netdev_info(dev, "phy reset failed\n");
4551				return -EINVAL;
4552			}
4553		} else {
4554			mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4555			if (netif_running(dev)) {
4556				/* Wait a bit and then reconfigure the nic. */
4557				udelay(10);
4558				nv_linkchange(dev);
4559			}
4560		}
4561	}
4562
4563	if (netif_running(dev)) {
4564		nv_start_rxtx(dev);
4565		nv_enable_irq(dev);
4566	}
4567
4568	return 0;
4569}
4570
4571#define FORCEDETH_REGS_VER	1
4572
4573static int nv_get_regs_len(struct net_device *dev)
4574{
4575	struct fe_priv *np = netdev_priv(dev);
4576	return np->register_size;
4577}
4578
4579static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4580{
4581	struct fe_priv *np = netdev_priv(dev);
4582	u8 __iomem *base = get_hwbase(dev);
4583	u32 *rbuf = buf;
4584	int i;
4585
4586	regs->version = FORCEDETH_REGS_VER;
4587	spin_lock_irq(&np->lock);
4588	for (i = 0; i < np->register_size/sizeof(u32); i++)
4589		rbuf[i] = readl(base + i*sizeof(u32));
4590	spin_unlock_irq(&np->lock);
4591}
4592
4593static int nv_nway_reset(struct net_device *dev)
4594{
4595	struct fe_priv *np = netdev_priv(dev);
4596	int ret;
4597
4598	if (np->autoneg) {
4599		int bmcr;
4600
4601		netif_carrier_off(dev);
4602		if (netif_running(dev)) {
4603			nv_disable_irq(dev);
4604			netif_tx_lock_bh(dev);
4605			netif_addr_lock(dev);
4606			spin_lock(&np->lock);
4607			/* stop engines */
4608			nv_stop_rxtx(dev);
4609			spin_unlock(&np->lock);
4610			netif_addr_unlock(dev);
4611			netif_tx_unlock_bh(dev);
4612			netdev_info(dev, "link down\n");
4613		}
4614
4615		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4616		if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4617			bmcr |= BMCR_ANENABLE;
4618			/* reset the phy in order for settings to stick*/
4619			if (phy_reset(dev, bmcr)) {
4620				netdev_info(dev, "phy reset failed\n");
4621				return -EINVAL;
4622			}
4623		} else {
4624			bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4625			mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4626		}
4627
4628		if (netif_running(dev)) {
4629			nv_start_rxtx(dev);
4630			nv_enable_irq(dev);
4631		}
4632		ret = 0;
4633	} else {
4634		ret = -EINVAL;
4635	}
4636
4637	return ret;
4638}
4639
4640static void nv_get_ringparam(struct net_device *dev,
4641			     struct ethtool_ringparam *ring,
4642			     struct kernel_ethtool_ringparam *kernel_ring,
4643			     struct netlink_ext_ack *extack)
4644{
4645	struct fe_priv *np = netdev_priv(dev);
4646
4647	ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4648	ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4649
4650	ring->rx_pending = np->rx_ring_size;
4651	ring->tx_pending = np->tx_ring_size;
4652}
4653
4654static int nv_set_ringparam(struct net_device *dev,
4655			    struct ethtool_ringparam *ring,
4656			    struct kernel_ethtool_ringparam *kernel_ring,
4657			    struct netlink_ext_ack *extack)
4658{
4659	struct fe_priv *np = netdev_priv(dev);
4660	u8 __iomem *base = get_hwbase(dev);
4661	u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4662	dma_addr_t ring_addr;
4663
4664	if (ring->rx_pending < RX_RING_MIN ||
4665	    ring->tx_pending < TX_RING_MIN ||
4666	    ring->rx_mini_pending != 0 ||
4667	    ring->rx_jumbo_pending != 0 ||
4668	    (np->desc_ver == DESC_VER_1 &&
4669	     (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4670	      ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4671	    (np->desc_ver != DESC_VER_1 &&
4672	     (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4673	      ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4674		return -EINVAL;
4675	}
4676
4677	/* allocate new rings */
4678	if (!nv_optimized(np)) {
4679		rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev,
4680					       sizeof(struct ring_desc) *
4681					       (ring->rx_pending +
4682					       ring->tx_pending),
4683					       &ring_addr, GFP_ATOMIC);
4684	} else {
4685		rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev,
4686					       sizeof(struct ring_desc_ex) *
4687					       (ring->rx_pending +
4688					       ring->tx_pending),
4689					       &ring_addr, GFP_ATOMIC);
4690	}
4691	rx_skbuff = kmalloc_array(ring->rx_pending, sizeof(struct nv_skb_map),
4692				  GFP_KERNEL);
4693	tx_skbuff = kmalloc_array(ring->tx_pending, sizeof(struct nv_skb_map),
4694				  GFP_KERNEL);
4695	if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4696		/* fall back to old rings */
4697		if (!nv_optimized(np)) {
4698			if (rxtx_ring)
4699				dma_free_coherent(&np->pci_dev->dev,
4700						  sizeof(struct ring_desc) *
4701						  (ring->rx_pending +
4702						  ring->tx_pending),
4703						  rxtx_ring, ring_addr);
4704		} else {
4705			if (rxtx_ring)
4706				dma_free_coherent(&np->pci_dev->dev,
4707						  sizeof(struct ring_desc_ex) *
4708						  (ring->rx_pending +
4709						  ring->tx_pending),
4710						  rxtx_ring, ring_addr);
4711		}
4712
4713		kfree(rx_skbuff);
4714		kfree(tx_skbuff);
4715		goto exit;
4716	}
4717
4718	if (netif_running(dev)) {
4719		nv_disable_irq(dev);
4720		napi_disable(&np->napi);
4721		netif_tx_lock_bh(dev);
4722		netif_addr_lock(dev);
4723		spin_lock(&np->lock);
4724		/* stop engines */
4725		nv_stop_rxtx(dev);
4726		nv_txrx_reset(dev);
4727		/* drain queues */
4728		nv_drain_rxtx(dev);
4729		/* delete queues */
4730		free_rings(dev);
4731	}
4732
4733	/* set new values */
4734	np->rx_ring_size = ring->rx_pending;
4735	np->tx_ring_size = ring->tx_pending;
4736
4737	if (!nv_optimized(np)) {
4738		np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4739		np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4740	} else {
4741		np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4742		np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4743	}
4744	np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4745	np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4746	np->ring_addr = ring_addr;
4747
4748	memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4749	memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4750
4751	if (netif_running(dev)) {
4752		/* reinit driver view of the queues */
4753		set_bufsize(dev);
4754		if (nv_init_ring(dev)) {
4755			if (!np->in_shutdown)
4756				mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4757		}
4758
4759		/* reinit nic view of the queues */
4760		writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4761		setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4762		writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4763			base + NvRegRingSizes);
4764		pci_push(base);
4765		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4766		pci_push(base);
4767
4768		/* restart engines */
4769		nv_start_rxtx(dev);
4770		spin_unlock(&np->lock);
4771		netif_addr_unlock(dev);
4772		netif_tx_unlock_bh(dev);
4773		napi_enable(&np->napi);
4774		nv_enable_irq(dev);
4775	}
4776	return 0;
4777exit:
4778	return -ENOMEM;
4779}
4780
4781static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4782{
4783	struct fe_priv *np = netdev_priv(dev);
4784
4785	pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4786	pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4787	pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4788}
4789
4790static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4791{
4792	struct fe_priv *np = netdev_priv(dev);
4793	int adv, bmcr;
4794
4795	if ((!np->autoneg && np->duplex == 0) ||
4796	    (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4797		netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4798		return -EINVAL;
4799	}
4800	if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4801		netdev_info(dev, "hardware does not support tx pause frames\n");
4802		return -EINVAL;
4803	}
4804
4805	netif_carrier_off(dev);
4806	if (netif_running(dev)) {
4807		nv_disable_irq(dev);
4808		netif_tx_lock_bh(dev);
4809		netif_addr_lock(dev);
4810		spin_lock(&np->lock);
4811		/* stop engines */
4812		nv_stop_rxtx(dev);
4813		spin_unlock(&np->lock);
4814		netif_addr_unlock(dev);
4815		netif_tx_unlock_bh(dev);
4816	}
4817
4818	np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4819	if (pause->rx_pause)
4820		np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4821	if (pause->tx_pause)
4822		np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4823
4824	if (np->autoneg && pause->autoneg) {
4825		np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4826
4827		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4828		adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4829		if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4830			adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4831		if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4832			adv |=  ADVERTISE_PAUSE_ASYM;
4833		mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4834
4835		if (netif_running(dev))
4836			netdev_info(dev, "link down\n");
4837		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4838		bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4839		mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4840	} else {
4841		np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4842		if (pause->rx_pause)
4843			np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4844		if (pause->tx_pause)
4845			np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4846
4847		if (!netif_running(dev))
4848			nv_update_linkspeed(dev);
4849		else
4850			nv_update_pause(dev, np->pause_flags);
4851	}
4852
4853	if (netif_running(dev)) {
4854		nv_start_rxtx(dev);
4855		nv_enable_irq(dev);
4856	}
4857	return 0;
4858}
4859
4860static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4861{
4862	struct fe_priv *np = netdev_priv(dev);
4863	unsigned long flags;
4864	u32 miicontrol;
4865	int err, retval = 0;
4866
4867	spin_lock_irqsave(&np->lock, flags);
4868	miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4869	if (features & NETIF_F_LOOPBACK) {
4870		if (miicontrol & BMCR_LOOPBACK) {
4871			spin_unlock_irqrestore(&np->lock, flags);
4872			netdev_info(dev, "Loopback already enabled\n");
4873			return 0;
4874		}
4875		nv_disable_irq(dev);
4876		/* Turn on loopback mode */
4877		miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4878		err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4879		if (err) {
4880			retval = PHY_ERROR;
4881			spin_unlock_irqrestore(&np->lock, flags);
4882			phy_init(dev);
4883		} else {
4884			if (netif_running(dev)) {
4885				/* Force 1000 Mbps full-duplex */
4886				nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4887									 1);
4888				/* Force link up */
4889				netif_carrier_on(dev);
4890			}
4891			spin_unlock_irqrestore(&np->lock, flags);
4892			netdev_info(dev,
4893				"Internal PHY loopback mode enabled.\n");
4894		}
4895	} else {
4896		if (!(miicontrol & BMCR_LOOPBACK)) {
4897			spin_unlock_irqrestore(&np->lock, flags);
4898			netdev_info(dev, "Loopback already disabled\n");
4899			return 0;
4900		}
4901		nv_disable_irq(dev);
4902		/* Turn off loopback */
4903		spin_unlock_irqrestore(&np->lock, flags);
4904		netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4905		phy_init(dev);
4906	}
4907	msleep(500);
4908	spin_lock_irqsave(&np->lock, flags);
4909	nv_enable_irq(dev);
4910	spin_unlock_irqrestore(&np->lock, flags);
4911
4912	return retval;
4913}
4914
4915static netdev_features_t nv_fix_features(struct net_device *dev,
4916	netdev_features_t features)
4917{
4918	/* vlan is dependent on rx checksum offload */
4919	if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4920		features |= NETIF_F_RXCSUM;
4921
4922	return features;
4923}
4924
4925static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4926{
4927	struct fe_priv *np = get_nvpriv(dev);
4928
4929	spin_lock_irq(&np->lock);
4930
4931	if (features & NETIF_F_HW_VLAN_CTAG_RX)
4932		np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4933	else
4934		np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4935
4936	if (features & NETIF_F_HW_VLAN_CTAG_TX)
4937		np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4938	else
4939		np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4940
4941	writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4942
4943	spin_unlock_irq(&np->lock);
4944}
4945
4946static int nv_set_features(struct net_device *dev, netdev_features_t features)
4947{
4948	struct fe_priv *np = netdev_priv(dev);
4949	u8 __iomem *base = get_hwbase(dev);
4950	netdev_features_t changed = dev->features ^ features;
4951	int retval;
4952
4953	if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4954		retval = nv_set_loopback(dev, features);
4955		if (retval != 0)
4956			return retval;
4957	}
4958
4959	if (changed & NETIF_F_RXCSUM) {
4960		spin_lock_irq(&np->lock);
4961
4962		if (features & NETIF_F_RXCSUM)
4963			np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4964		else
4965			np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4966
4967		if (netif_running(dev))
4968			writel(np->txrxctl_bits, base + NvRegTxRxControl);
4969
4970		spin_unlock_irq(&np->lock);
4971	}
4972
4973	if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))
4974		nv_vlan_mode(dev, features);
4975
4976	return 0;
4977}
4978
4979static int nv_get_sset_count(struct net_device *dev, int sset)
4980{
4981	struct fe_priv *np = netdev_priv(dev);
4982
4983	switch (sset) {
4984	case ETH_SS_TEST:
4985		if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4986			return NV_TEST_COUNT_EXTENDED;
4987		else
4988			return NV_TEST_COUNT_BASE;
4989	case ETH_SS_STATS:
4990		if (np->driver_data & DEV_HAS_STATISTICS_V3)
4991			return NV_DEV_STATISTICS_V3_COUNT;
4992		else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4993			return NV_DEV_STATISTICS_V2_COUNT;
4994		else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4995			return NV_DEV_STATISTICS_V1_COUNT;
4996		else
4997			return 0;
4998	default:
4999		return -EOPNOTSUPP;
5000	}
5001}
5002
5003static void nv_get_ethtool_stats(struct net_device *dev,
5004				 struct ethtool_stats *estats, u64 *buffer)
5005	__acquires(&netdev_priv(dev)->hwstats_lock)
5006	__releases(&netdev_priv(dev)->hwstats_lock)
5007{
5008	struct fe_priv *np = netdev_priv(dev);
5009
5010	spin_lock_bh(&np->hwstats_lock);
5011	nv_update_stats(dev);
5012	memcpy(buffer, &np->estats,
5013	       nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
5014	spin_unlock_bh(&np->hwstats_lock);
5015}
5016
5017static int nv_link_test(struct net_device *dev)
5018{
5019	struct fe_priv *np = netdev_priv(dev);
5020	int mii_status;
5021
5022	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5023	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5024
5025	/* check phy link status */
5026	if (!(mii_status & BMSR_LSTATUS))
5027		return 0;
5028	else
5029		return 1;
5030}
5031
5032static int nv_register_test(struct net_device *dev)
5033{
5034	u8 __iomem *base = get_hwbase(dev);
5035	int i = 0;
5036	u32 orig_read, new_read;
5037
5038	do {
5039		orig_read = readl(base + nv_registers_test[i].reg);
5040
5041		/* xor with mask to toggle bits */
5042		orig_read ^= nv_registers_test[i].mask;
5043
5044		writel(orig_read, base + nv_registers_test[i].reg);
5045
5046		new_read = readl(base + nv_registers_test[i].reg);
5047
5048		if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
5049			return 0;
5050
5051		/* restore original value */
5052		orig_read ^= nv_registers_test[i].mask;
5053		writel(orig_read, base + nv_registers_test[i].reg);
5054
5055	} while (nv_registers_test[++i].reg != 0);
5056
5057	return 1;
5058}
5059
5060static int nv_interrupt_test(struct net_device *dev)
5061{
5062	struct fe_priv *np = netdev_priv(dev);
5063	u8 __iomem *base = get_hwbase(dev);
5064	int ret = 1;
5065	int testcnt;
5066	u32 save_msi_flags, save_poll_interval = 0;
5067
5068	if (netif_running(dev)) {
5069		/* free current irq */
5070		nv_free_irq(dev);
5071		save_poll_interval = readl(base+NvRegPollingInterval);
5072	}
5073
5074	/* flag to test interrupt handler */
5075	np->intr_test = 0;
5076
5077	/* setup test irq */
5078	save_msi_flags = np->msi_flags;
5079	np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
5080	np->msi_flags |= 0x001; /* setup 1 vector */
5081	if (nv_request_irq(dev, 1))
5082		return 0;
5083
5084	/* setup timer interrupt */
5085	writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5086	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5087
5088	nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5089
5090	/* wait for at least one interrupt */
5091	msleep(100);
5092
5093	spin_lock_irq(&np->lock);
5094
5095	/* flag should be set within ISR */
5096	testcnt = np->intr_test;
5097	if (!testcnt)
5098		ret = 2;
5099
5100	nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5101	if (!(np->msi_flags & NV_MSI_X_ENABLED))
5102		writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5103	else
5104		writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5105
5106	spin_unlock_irq(&np->lock);
5107
5108	nv_free_irq(dev);
5109
5110	np->msi_flags = save_msi_flags;
5111
5112	if (netif_running(dev)) {
5113		writel(save_poll_interval, base + NvRegPollingInterval);
5114		writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5115		/* restore original irq */
5116		if (nv_request_irq(dev, 0))
5117			return 0;
5118	}
5119
5120	return ret;
5121}
5122
5123static int nv_loopback_test(struct net_device *dev)
5124{
5125	struct fe_priv *np = netdev_priv(dev);
5126	u8 __iomem *base = get_hwbase(dev);
5127	struct sk_buff *tx_skb, *rx_skb;
5128	dma_addr_t test_dma_addr;
5129	u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5130	u32 flags;
5131	int len, i, pkt_len;
5132	u8 *pkt_data;
5133	u32 filter_flags = 0;
5134	u32 misc1_flags = 0;
5135	int ret = 1;
5136
5137	if (netif_running(dev)) {
5138		nv_disable_irq(dev);
5139		filter_flags = readl(base + NvRegPacketFilterFlags);
5140		misc1_flags = readl(base + NvRegMisc1);
5141	} else {
5142		nv_txrx_reset(dev);
5143	}
5144
5145	/* reinit driver view of the rx queue */
5146	set_bufsize(dev);
5147	nv_init_ring(dev);
5148
5149	/* setup hardware for loopback */
5150	writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5151	writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5152
5153	/* reinit nic view of the rx queue */
5154	writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5155	setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5156	writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5157		base + NvRegRingSizes);
5158	pci_push(base);
5159
5160	/* restart rx engine */
5161	nv_start_rxtx(dev);
5162
5163	/* setup packet for tx */
5164	pkt_len = ETH_DATA_LEN;
5165	tx_skb = netdev_alloc_skb(dev, pkt_len);
5166	if (!tx_skb) {
5167		ret = 0;
5168		goto out;
5169	}
5170	test_dma_addr = dma_map_single(&np->pci_dev->dev, tx_skb->data,
5171				       skb_tailroom(tx_skb),
5172				       DMA_FROM_DEVICE);
5173	if (unlikely(dma_mapping_error(&np->pci_dev->dev,
5174				       test_dma_addr))) {
5175		dev_kfree_skb_any(tx_skb);
5176		goto out;
5177	}
5178	pkt_data = skb_put(tx_skb, pkt_len);
5179	for (i = 0; i < pkt_len; i++)
5180		pkt_data[i] = (u8)(i & 0xff);
5181
5182	if (!nv_optimized(np)) {
5183		np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5184		np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5185	} else {
5186		np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5187		np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5188		np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5189	}
5190	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5191	pci_push(get_hwbase(dev));
5192
5193	msleep(500);
5194
5195	/* check for rx of the packet */
5196	if (!nv_optimized(np)) {
5197		flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5198		len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5199
5200	} else {
5201		flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5202		len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5203	}
5204
5205	if (flags & NV_RX_AVAIL) {
5206		ret = 0;
5207	} else if (np->desc_ver == DESC_VER_1) {
5208		if (flags & NV_RX_ERROR)
5209			ret = 0;
5210	} else {
5211		if (flags & NV_RX2_ERROR)
5212			ret = 0;
5213	}
5214
5215	if (ret) {
5216		if (len != pkt_len) {
5217			ret = 0;
5218		} else {
5219			rx_skb = np->rx_skb[0].skb;
5220			for (i = 0; i < pkt_len; i++) {
5221				if (rx_skb->data[i] != (u8)(i & 0xff)) {
5222					ret = 0;
5223					break;
5224				}
5225			}
5226		}
5227	}
5228
5229	dma_unmap_single(&np->pci_dev->dev, test_dma_addr,
5230			 (skb_end_pointer(tx_skb) - tx_skb->data),
5231			 DMA_TO_DEVICE);
5232	dev_kfree_skb_any(tx_skb);
5233 out:
5234	/* stop engines */
5235	nv_stop_rxtx(dev);
5236	nv_txrx_reset(dev);
5237	/* drain rx queue */
5238	nv_drain_rxtx(dev);
5239
5240	if (netif_running(dev)) {
5241		writel(misc1_flags, base + NvRegMisc1);
5242		writel(filter_flags, base + NvRegPacketFilterFlags);
5243		nv_enable_irq(dev);
5244	}
5245
5246	return ret;
5247}
5248
5249static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5250{
5251	struct fe_priv *np = netdev_priv(dev);
5252	u8 __iomem *base = get_hwbase(dev);
5253	int result, count;
5254
5255	count = nv_get_sset_count(dev, ETH_SS_TEST);
5256	memset(buffer, 0, count * sizeof(u64));
5257
5258	if (!nv_link_test(dev)) {
5259		test->flags |= ETH_TEST_FL_FAILED;
5260		buffer[0] = 1;
5261	}
5262
5263	if (test->flags & ETH_TEST_FL_OFFLINE) {
5264		if (netif_running(dev)) {
5265			netif_stop_queue(dev);
5266			napi_disable(&np->napi);
5267			netif_tx_lock_bh(dev);
5268			netif_addr_lock(dev);
5269			spin_lock_irq(&np->lock);
5270			nv_disable_hw_interrupts(dev, np->irqmask);
5271			if (!(np->msi_flags & NV_MSI_X_ENABLED))
5272				writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5273			else
5274				writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5275			/* stop engines */
5276			nv_stop_rxtx(dev);
5277			nv_txrx_reset(dev);
5278			/* drain rx queue */
5279			nv_drain_rxtx(dev);
5280			spin_unlock_irq(&np->lock);
5281			netif_addr_unlock(dev);
5282			netif_tx_unlock_bh(dev);
5283		}
5284
5285		if (!nv_register_test(dev)) {
5286			test->flags |= ETH_TEST_FL_FAILED;
5287			buffer[1] = 1;
5288		}
5289
5290		result = nv_interrupt_test(dev);
5291		if (result != 1) {
5292			test->flags |= ETH_TEST_FL_FAILED;
5293			buffer[2] = 1;
5294		}
5295		if (result == 0) {
5296			/* bail out */
5297			return;
5298		}
5299
5300		if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) {
5301			test->flags |= ETH_TEST_FL_FAILED;
5302			buffer[3] = 1;
5303		}
5304
5305		if (netif_running(dev)) {
5306			/* reinit driver view of the rx queue */
5307			set_bufsize(dev);
5308			if (nv_init_ring(dev)) {
5309				if (!np->in_shutdown)
5310					mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5311			}
5312			/* reinit nic view of the rx queue */
5313			writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5314			setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5315			writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5316				base + NvRegRingSizes);
5317			pci_push(base);
5318			writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5319			pci_push(base);
5320			/* restart rx engine */
5321			nv_start_rxtx(dev);
5322			netif_start_queue(dev);
5323			napi_enable(&np->napi);
5324			nv_enable_hw_interrupts(dev, np->irqmask);
5325		}
5326	}
5327}
5328
5329static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5330{
5331	switch (stringset) {
5332	case ETH_SS_STATS:
5333		memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5334		break;
5335	case ETH_SS_TEST:
5336		memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5337		break;
5338	}
5339}
5340
5341static const struct ethtool_ops ops = {
5342	.get_drvinfo = nv_get_drvinfo,
5343	.get_link = ethtool_op_get_link,
5344	.get_wol = nv_get_wol,
5345	.set_wol = nv_set_wol,
5346	.get_regs_len = nv_get_regs_len,
5347	.get_regs = nv_get_regs,
5348	.nway_reset = nv_nway_reset,
5349	.get_ringparam = nv_get_ringparam,
5350	.set_ringparam = nv_set_ringparam,
5351	.get_pauseparam = nv_get_pauseparam,
5352	.set_pauseparam = nv_set_pauseparam,
5353	.get_strings = nv_get_strings,
5354	.get_ethtool_stats = nv_get_ethtool_stats,
5355	.get_sset_count = nv_get_sset_count,
5356	.self_test = nv_self_test,
5357	.get_ts_info = ethtool_op_get_ts_info,
5358	.get_link_ksettings = nv_get_link_ksettings,
5359	.set_link_ksettings = nv_set_link_ksettings,
5360};
5361
5362/* The mgmt unit and driver use a semaphore to access the phy during init */
5363static int nv_mgmt_acquire_sema(struct net_device *dev)
5364{
5365	struct fe_priv *np = netdev_priv(dev);
5366	u8 __iomem *base = get_hwbase(dev);
5367	int i;
5368	u32 tx_ctrl, mgmt_sema;
5369
5370	for (i = 0; i < 10; i++) {
5371		mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5372		if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5373			break;
5374		msleep(500);
5375	}
5376
5377	if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5378		return 0;
5379
5380	for (i = 0; i < 2; i++) {
5381		tx_ctrl = readl(base + NvRegTransmitterControl);
5382		tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5383		writel(tx_ctrl, base + NvRegTransmitterControl);
5384
5385		/* verify that semaphore was acquired */
5386		tx_ctrl = readl(base + NvRegTransmitterControl);
5387		if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5388		    ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5389			np->mgmt_sema = 1;
5390			return 1;
5391		} else
5392			udelay(50);
5393	}
5394
5395	return 0;
5396}
5397
5398static void nv_mgmt_release_sema(struct net_device *dev)
5399{
5400	struct fe_priv *np = netdev_priv(dev);
5401	u8 __iomem *base = get_hwbase(dev);
5402	u32 tx_ctrl;
5403
5404	if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5405		if (np->mgmt_sema) {
5406			tx_ctrl = readl(base + NvRegTransmitterControl);
5407			tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5408			writel(tx_ctrl, base + NvRegTransmitterControl);
5409		}
5410	}
5411}
5412
5413
5414static int nv_mgmt_get_version(struct net_device *dev)
5415{
5416	struct fe_priv *np = netdev_priv(dev);
5417	u8 __iomem *base = get_hwbase(dev);
5418	u32 data_ready = readl(base + NvRegTransmitterControl);
5419	u32 data_ready2 = 0;
5420	unsigned long start;
5421	int ready = 0;
5422
5423	writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5424	writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5425	start = jiffies;
5426	while (time_before(jiffies, start + 5*HZ)) {
5427		data_ready2 = readl(base + NvRegTransmitterControl);
5428		if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5429			ready = 1;
5430			break;
5431		}
5432		schedule_timeout_uninterruptible(1);
5433	}
5434
5435	if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5436		return 0;
5437
5438	np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5439
5440	return 1;
5441}
5442
5443static int nv_open(struct net_device *dev)
5444{
5445	struct fe_priv *np = netdev_priv(dev);
5446	u8 __iomem *base = get_hwbase(dev);
5447	int ret = 1;
5448	int oom, i;
5449	u32 low;
5450
5451	/* power up phy */
5452	mii_rw(dev, np->phyaddr, MII_BMCR,
5453	       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5454
5455	nv_txrx_gate(dev, false);
5456	/* erase previous misconfiguration */
5457	if (np->driver_data & DEV_HAS_POWER_CNTRL)
5458		nv_mac_reset(dev);
5459	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5460	writel(0, base + NvRegMulticastAddrB);
5461	writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5462	writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5463	writel(0, base + NvRegPacketFilterFlags);
5464
5465	writel(0, base + NvRegTransmitterControl);
5466	writel(0, base + NvRegReceiverControl);
5467
5468	writel(0, base + NvRegAdapterControl);
5469
5470	if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5471		writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5472
5473	/* initialize descriptor rings */
5474	set_bufsize(dev);
5475	oom = nv_init_ring(dev);
5476
5477	writel(0, base + NvRegLinkSpeed);
5478	writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5479	nv_txrx_reset(dev);
5480	writel(0, base + NvRegUnknownSetupReg6);
5481
5482	np->in_shutdown = 0;
5483
5484	/* give hw rings */
5485	setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5486	writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5487		base + NvRegRingSizes);
5488
5489	writel(np->linkspeed, base + NvRegLinkSpeed);
5490	if (np->desc_ver == DESC_VER_1)
5491		writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5492	else
5493		writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5494	writel(np->txrxctl_bits, base + NvRegTxRxControl);
5495	writel(np->vlanctl_bits, base + NvRegVlanControl);
5496	pci_push(base);
5497	writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5498	if (reg_delay(dev, NvRegUnknownSetupReg5,
5499		      NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5500		      NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5501		netdev_info(dev,
5502			    "%s: SetupReg5, Bit 31 remained off\n", __func__);
5503
5504	writel(0, base + NvRegMIIMask);
5505	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5506	writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5507
5508	writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5509	writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5510	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5511	writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5512
5513	writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5514
5515	get_random_bytes(&low, sizeof(low));
5516	low &= NVREG_SLOTTIME_MASK;
5517	if (np->desc_ver == DESC_VER_1) {
5518		writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5519	} else {
5520		if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5521			/* setup legacy backoff */
5522			writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5523		} else {
5524			writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5525			nv_gear_backoff_reseed(dev);
5526		}
5527	}
5528	writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5529	writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5530	if (poll_interval == -1) {
5531		if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5532			writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5533		else
5534			writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5535	} else
5536		writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5537	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5538	writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5539			base + NvRegAdapterControl);
5540	writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5541	writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5542	if (np->wolenabled)
5543		writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5544
5545	i = readl(base + NvRegPowerState);
5546	if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5547		writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5548
5549	pci_push(base);
5550	udelay(10);
5551	writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5552
5553	nv_disable_hw_interrupts(dev, np->irqmask);
5554	pci_push(base);
5555	writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5556	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5557	pci_push(base);
5558
5559	if (nv_request_irq(dev, 0))
5560		goto out_drain;
5561
5562	/* ask for interrupts */
5563	nv_enable_hw_interrupts(dev, np->irqmask);
5564
5565	netdev_lock(dev);
5566	spin_lock_irq(&np->lock);
5567	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5568	writel(0, base + NvRegMulticastAddrB);
5569	writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5570	writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5571	writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5572	/* One manual link speed update: Interrupts are enabled, future link
5573	 * speed changes cause interrupts and are handled by nv_link_irq().
5574	 */
5575	readl(base + NvRegMIIStatus);
5576	writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5577
5578	/* set linkspeed to invalid value, thus force nv_update_linkspeed
5579	 * to init hw */
5580	np->linkspeed = 0;
5581	ret = nv_update_linkspeed(dev);
5582	nv_start_rxtx(dev);
5583	netif_start_queue(dev);
5584	napi_enable_locked(&np->napi);
5585
5586	if (ret) {
5587		netif_carrier_on(dev);
5588	} else {
5589		netdev_info(dev, "no link during initialization\n");
5590		netif_carrier_off(dev);
5591	}
5592	if (oom)
5593		mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5594
5595	/* start statistics timer */
5596	if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5597		mod_timer(&np->stats_poll,
5598			round_jiffies(jiffies + STATS_INTERVAL));
5599
5600	spin_unlock_irq(&np->lock);
5601	netdev_unlock(dev);
5602
5603	/* If the loopback feature was set while the device was down, make sure
5604	 * that it's set correctly now.
5605	 */
5606	if (dev->features & NETIF_F_LOOPBACK)
5607		nv_set_loopback(dev, dev->features);
5608
5609	return 0;
5610out_drain:
5611	nv_drain_rxtx(dev);
5612	return ret;
5613}
5614
5615static int nv_close(struct net_device *dev)
5616{
5617	struct fe_priv *np = netdev_priv(dev);
5618	u8 __iomem *base;
5619
5620	spin_lock_irq(&np->lock);
5621	np->in_shutdown = 1;
5622	spin_unlock_irq(&np->lock);
5623	napi_disable(&np->napi);
5624	synchronize_irq(np->pci_dev->irq);
5625
5626	timer_delete_sync(&np->oom_kick);
5627	timer_delete_sync(&np->nic_poll);
5628	timer_delete_sync(&np->stats_poll);
5629
5630	netif_stop_queue(dev);
5631	spin_lock_irq(&np->lock);
5632	nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
5633	nv_stop_rxtx(dev);
5634	nv_txrx_reset(dev);
5635
5636	/* disable interrupts on the nic or we will lock up */
5637	base = get_hwbase(dev);
5638	nv_disable_hw_interrupts(dev, np->irqmask);
5639	pci_push(base);
5640
5641	spin_unlock_irq(&np->lock);
5642
5643	nv_free_irq(dev);
5644
5645	nv_drain_rxtx(dev);
5646
5647	if (np->wolenabled || !phy_power_down) {
5648		nv_txrx_gate(dev, false);
5649		writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5650		nv_start_rx(dev);
5651	} else {
5652		/* power down phy */
5653		mii_rw(dev, np->phyaddr, MII_BMCR,
5654		       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5655		nv_txrx_gate(dev, true);
5656	}
5657
5658	/* FIXME: power down nic */
5659
5660	return 0;
5661}
5662
5663static const struct net_device_ops nv_netdev_ops = {
5664	.ndo_open		= nv_open,
5665	.ndo_stop		= nv_close,
5666	.ndo_get_stats64	= nv_get_stats64,
5667	.ndo_start_xmit		= nv_start_xmit,
5668	.ndo_tx_timeout		= nv_tx_timeout,
5669	.ndo_change_mtu		= nv_change_mtu,
5670	.ndo_fix_features	= nv_fix_features,
5671	.ndo_set_features	= nv_set_features,
5672	.ndo_validate_addr	= eth_validate_addr,
5673	.ndo_set_mac_address	= nv_set_mac_address,
5674	.ndo_set_rx_mode	= nv_set_multicast,
5675#ifdef CONFIG_NET_POLL_CONTROLLER
5676	.ndo_poll_controller	= nv_poll_controller,
5677#endif
5678};
5679
5680static const struct net_device_ops nv_netdev_ops_optimized = {
5681	.ndo_open		= nv_open,
5682	.ndo_stop		= nv_close,
5683	.ndo_get_stats64	= nv_get_stats64,
5684	.ndo_start_xmit		= nv_start_xmit_optimized,
5685	.ndo_tx_timeout		= nv_tx_timeout,
5686	.ndo_change_mtu		= nv_change_mtu,
5687	.ndo_fix_features	= nv_fix_features,
5688	.ndo_set_features	= nv_set_features,
5689	.ndo_validate_addr	= eth_validate_addr,
5690	.ndo_set_mac_address	= nv_set_mac_address,
5691	.ndo_set_rx_mode	= nv_set_multicast,
5692#ifdef CONFIG_NET_POLL_CONTROLLER
5693	.ndo_poll_controller	= nv_poll_controller,
5694#endif
5695};
5696
5697static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5698{
5699	struct net_device *dev;
5700	struct fe_priv *np;
5701	unsigned long addr;
5702	u8 __iomem *base;
5703	int err, i;
5704	u32 powerstate, txreg;
5705	u32 phystate_orig = 0, phystate;
5706	int phyinitialized = 0;
5707	static int printed_version;
5708	u8 mac[ETH_ALEN];
5709
5710	if (!printed_version++)
5711		pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5712			FORCEDETH_VERSION);
5713
5714	dev = alloc_etherdev(sizeof(struct fe_priv));
5715	err = -ENOMEM;
5716	if (!dev)
5717		goto out;
5718
5719	np = netdev_priv(dev);
5720	np->dev = dev;
5721	np->pci_dev = pci_dev;
5722	spin_lock_init(&np->lock);
5723	spin_lock_init(&np->hwstats_lock);
5724	SET_NETDEV_DEV(dev, &pci_dev->dev);
5725	u64_stats_init(&np->swstats_rx_syncp);
5726	u64_stats_init(&np->swstats_tx_syncp);
5727	np->txrx_stats = alloc_percpu(struct nv_txrx_stats);
5728	if (!np->txrx_stats) {
5729		pr_err("np->txrx_stats, alloc memory error.\n");
5730		err = -ENOMEM;
5731		goto out_alloc_percpu;
5732	}
5733
5734	timer_setup(&np->oom_kick, nv_do_rx_refill, 0);
5735	timer_setup(&np->nic_poll, nv_do_nic_poll, 0);
5736	timer_setup(&np->stats_poll, nv_do_stats_poll, TIMER_DEFERRABLE);
5737
5738	err = pci_enable_device(pci_dev);
5739	if (err)
5740		goto out_free;
5741
5742	pci_set_master(pci_dev);
5743
5744	err = pci_request_regions(pci_dev, DRV_NAME);
5745	if (err < 0)
5746		goto out_disable;
5747
5748	if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5749		np->register_size = NV_PCI_REGSZ_VER3;
5750	else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5751		np->register_size = NV_PCI_REGSZ_VER2;
5752	else
5753		np->register_size = NV_PCI_REGSZ_VER1;
5754
5755	err = -EINVAL;
5756	addr = 0;
5757	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5758		if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5759				pci_resource_len(pci_dev, i) >= np->register_size) {
5760			addr = pci_resource_start(pci_dev, i);
5761			break;
5762		}
5763	}
5764	if (i == DEVICE_COUNT_RESOURCE) {
5765		dev_info(&pci_dev->dev, "Couldn't find register window\n");
5766		goto out_relreg;
5767	}
5768
5769	/* copy of driver data */
5770	np->driver_data = id->driver_data;
5771	/* copy of device id */
5772	np->device_id = id->device;
5773
5774	/* handle different descriptor versions */
5775	if (id->driver_data & DEV_HAS_HIGH_DMA) {
5776		/* packet format 3: supports 40-bit addressing */
5777		np->desc_ver = DESC_VER_3;
5778		np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5779		if (dma_64bit) {
5780			if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(39)))
5781				dev_info(&pci_dev->dev,
5782					 "64-bit DMA failed, using 32-bit addressing\n");
5783			else
5784				dev->features |= NETIF_F_HIGHDMA;
5785		}
5786	} else if (id->driver_data & DEV_HAS_LARGEDESC) {
5787		/* packet format 2: supports jumbo frames */
5788		np->desc_ver = DESC_VER_2;
5789		np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5790	} else {
5791		/* original packet format */
5792		np->desc_ver = DESC_VER_1;
5793		np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5794	}
5795
5796	np->pkt_limit = NV_PKTLIMIT_1;
5797	if (id->driver_data & DEV_HAS_LARGEDESC)
5798		np->pkt_limit = NV_PKTLIMIT_2;
5799
5800	if (id->driver_data & DEV_HAS_CHECKSUM) {
5801		np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5802		dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5803			NETIF_F_TSO | NETIF_F_RXCSUM;
5804	}
5805
5806	np->vlanctl_bits = 0;
5807	if (id->driver_data & DEV_HAS_VLAN) {
5808		np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5809		dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
5810				    NETIF_F_HW_VLAN_CTAG_TX;
5811	}
5812
5813	dev->features |= dev->hw_features;
5814
5815	/* Add loopback capability to the device. */
5816	dev->hw_features |= NETIF_F_LOOPBACK;
5817
5818	/* MTU range: 64 - 1500 or 9100 */
5819	dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
5820	dev->max_mtu = np->pkt_limit;
5821
5822	np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5823	if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5824	    (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5825	    (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5826		np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5827	}
5828
5829	err = -ENOMEM;
5830	np->base = ioremap(addr, np->register_size);
5831	if (!np->base)
5832		goto out_relreg;
5833
5834	np->rx_ring_size = RX_RING_DEFAULT;
5835	np->tx_ring_size = TX_RING_DEFAULT;
5836
5837	if (!nv_optimized(np)) {
5838		np->rx_ring.orig = dma_alloc_coherent(&pci_dev->dev,
5839						      sizeof(struct ring_desc) *
5840						      (np->rx_ring_size +
5841						      np->tx_ring_size),
5842						      &np->ring_addr,
5843						      GFP_KERNEL);
5844		if (!np->rx_ring.orig)
5845			goto out_unmap;
5846		np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5847	} else {
5848		np->rx_ring.ex = dma_alloc_coherent(&pci_dev->dev,
5849						    sizeof(struct ring_desc_ex) *
5850						    (np->rx_ring_size +
5851						    np->tx_ring_size),
5852						    &np->ring_addr, GFP_KERNEL);
5853		if (!np->rx_ring.ex)
5854			goto out_unmap;
5855		np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5856	}
5857	np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5858	np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5859	if (!np->rx_skb || !np->tx_skb)
5860		goto out_freering;
5861
5862	if (!nv_optimized(np))
5863		dev->netdev_ops = &nv_netdev_ops;
5864	else
5865		dev->netdev_ops = &nv_netdev_ops_optimized;
5866
5867	netif_napi_add(dev, &np->napi, nv_napi_poll);
5868	dev->ethtool_ops = &ops;
5869	dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5870
5871	pci_set_drvdata(pci_dev, dev);
5872
5873	/* read the mac address */
5874	base = get_hwbase(dev);
5875	np->orig_mac[0] = readl(base + NvRegMacAddrA);
5876	np->orig_mac[1] = readl(base + NvRegMacAddrB);
5877
5878	/* check the workaround bit for correct mac address order */
5879	txreg = readl(base + NvRegTransmitPoll);
5880	if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5881		/* mac address is already in correct order */
5882		mac[0] = (np->orig_mac[0] >>  0) & 0xff;
5883		mac[1] = (np->orig_mac[0] >>  8) & 0xff;
5884		mac[2] = (np->orig_mac[0] >> 16) & 0xff;
5885		mac[3] = (np->orig_mac[0] >> 24) & 0xff;
5886		mac[4] = (np->orig_mac[1] >>  0) & 0xff;
5887		mac[5] = (np->orig_mac[1] >>  8) & 0xff;
5888	} else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5889		/* mac address is already in correct order */
5890		mac[0] = (np->orig_mac[0] >>  0) & 0xff;
5891		mac[1] = (np->orig_mac[0] >>  8) & 0xff;
5892		mac[2] = (np->orig_mac[0] >> 16) & 0xff;
5893		mac[3] = (np->orig_mac[0] >> 24) & 0xff;
5894		mac[4] = (np->orig_mac[1] >>  0) & 0xff;
5895		mac[5] = (np->orig_mac[1] >>  8) & 0xff;
5896		/*
5897		 * Set orig mac address back to the reversed version.
5898		 * This flag will be cleared during low power transition.
5899		 * Therefore, we should always put back the reversed address.
5900		 */
5901		np->orig_mac[0] = (mac[5] << 0) + (mac[4] << 8) +
5902			(mac[3] << 16) + (mac[2] << 24);
5903		np->orig_mac[1] = (mac[1] << 0) + (mac[0] << 8);
5904	} else {
5905		/* need to reverse mac address to correct order */
5906		mac[0] = (np->orig_mac[1] >>  8) & 0xff;
5907		mac[1] = (np->orig_mac[1] >>  0) & 0xff;
5908		mac[2] = (np->orig_mac[0] >> 24) & 0xff;
5909		mac[3] = (np->orig_mac[0] >> 16) & 0xff;
5910		mac[4] = (np->orig_mac[0] >>  8) & 0xff;
5911		mac[5] = (np->orig_mac[0] >>  0) & 0xff;
5912		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5913		dev_dbg(&pci_dev->dev,
5914			"%s: set workaround bit for reversed mac addr\n",
5915			__func__);
5916	}
5917
5918	if (is_valid_ether_addr(mac)) {
5919		eth_hw_addr_set(dev, mac);
5920	} else {
5921		/*
5922		 * Bad mac address. At least one bios sets the mac address
5923		 * to 01:23:45:67:89:ab
5924		 */
5925		dev_err(&pci_dev->dev,
5926			"Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5927			mac);
5928		eth_hw_addr_random(dev);
5929		dev_err(&pci_dev->dev,
5930			"Using random MAC address: %pM\n", dev->dev_addr);
5931	}
5932
5933	/* set mac address */
5934	nv_copy_mac_to_hw(dev);
5935
5936	/* disable WOL */
5937	writel(0, base + NvRegWakeUpFlags);
5938	np->wolenabled = 0;
5939	device_set_wakeup_enable(&pci_dev->dev, false);
5940
5941	if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5942
5943		/* take phy and nic out of low power mode */
5944		powerstate = readl(base + NvRegPowerState2);
5945		powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5946		if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5947		    pci_dev->revision >= 0xA3)
5948			powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5949		writel(powerstate, base + NvRegPowerState2);
5950	}
5951
5952	if (np->desc_ver == DESC_VER_1)
5953		np->tx_flags = NV_TX_VALID;
5954	else
5955		np->tx_flags = NV_TX2_VALID;
5956
5957	np->msi_flags = 0;
5958	if ((id->driver_data & DEV_HAS_MSI) && msi)
5959		np->msi_flags |= NV_MSI_CAPABLE;
5960
5961	if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5962		/* msix has had reported issues when modifying irqmask
5963		   as in the case of napi, therefore, disable for now
5964		*/
5965#if 0
5966		np->msi_flags |= NV_MSI_X_CAPABLE;
5967#endif
5968	}
5969
5970	if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5971		np->irqmask = NVREG_IRQMASK_CPU;
5972		if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5973			np->msi_flags |= 0x0001;
5974	} else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5975		   !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5976		/* start off in throughput mode */
5977		np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5978		/* remove support for msix mode */
5979		np->msi_flags &= ~NV_MSI_X_CAPABLE;
5980	} else {
5981		optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5982		np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5983		if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5984			np->msi_flags |= 0x0003;
5985	}
5986
5987	if (id->driver_data & DEV_NEED_TIMERIRQ)
5988		np->irqmask |= NVREG_IRQ_TIMER;
5989	if (id->driver_data & DEV_NEED_LINKTIMER) {
5990		np->need_linktimer = 1;
5991		np->link_timeout = jiffies + LINK_TIMEOUT;
5992	} else {
5993		np->need_linktimer = 0;
5994	}
5995
5996	/* Limit the number of tx's outstanding for hw bug */
5997	if (id->driver_data & DEV_NEED_TX_LIMIT) {
5998		np->tx_limit = 1;
5999		if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
6000		    pci_dev->revision >= 0xA2)
6001			np->tx_limit = 0;
6002	}
6003
6004	/* clear phy state and temporarily halt phy interrupts */
6005	writel(0, base + NvRegMIIMask);
6006	phystate = readl(base + NvRegAdapterControl);
6007	if (phystate & NVREG_ADAPTCTL_RUNNING) {
6008		phystate_orig = 1;
6009		phystate &= ~NVREG_ADAPTCTL_RUNNING;
6010		writel(phystate, base + NvRegAdapterControl);
6011	}
6012	writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
6013
6014	if (id->driver_data & DEV_HAS_MGMT_UNIT) {
6015		/* management unit running on the mac? */
6016		if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
6017		    (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
6018		    nv_mgmt_acquire_sema(dev) &&
6019		    nv_mgmt_get_version(dev)) {
6020			np->mac_in_use = 1;
6021			if (np->mgmt_version > 0)
6022				np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
6023			/* management unit setup the phy already? */
6024			if (np->mac_in_use &&
6025			    ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
6026			     NVREG_XMITCTL_SYNC_PHY_INIT)) {
6027				/* phy is inited by mgmt unit */
6028				phyinitialized = 1;
6029			} else {
6030				/* we need to init the phy */
6031			}
6032		}
6033	}
6034
6035	/* find a suitable phy */
6036	for (i = 1; i <= 32; i++) {
6037		int id1, id2;
6038		int phyaddr = i & 0x1F;
6039
6040		spin_lock_irq(&np->lock);
6041		id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
6042		spin_unlock_irq(&np->lock);
6043		if (id1 < 0 || id1 == 0xffff)
6044			continue;
6045		spin_lock_irq(&np->lock);
6046		id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
6047		spin_unlock_irq(&np->lock);
6048		if (id2 < 0 || id2 == 0xffff)
6049			continue;
6050
6051		np->phy_model = id2 & PHYID2_MODEL_MASK;
6052		id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
6053		id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
6054		np->phyaddr = phyaddr;
6055		np->phy_oui = id1 | id2;
6056
6057		/* Realtek hardcoded phy id1 to all zero's on certain phys */
6058		if (np->phy_oui == PHY_OUI_REALTEK2)
6059			np->phy_oui = PHY_OUI_REALTEK;
6060		/* Setup phy revision for Realtek */
6061		if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
6062			np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
6063
6064		break;
6065	}
6066	if (i == 33) {
6067		dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
6068		goto out_error;
6069	}
6070
6071	if (!phyinitialized) {
6072		/* reset it */
6073		phy_init(dev);
6074	} else {
6075		/* see if it is a gigabit phy */
6076		u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
6077		if (mii_status & PHY_GIGABIT)
6078			np->gigabit = PHY_GIGABIT;
6079	}
6080
6081	/* set default link speed settings */
6082	np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
6083	np->duplex = 0;
6084	np->autoneg = 1;
6085
6086	err = register_netdev(dev);
6087	if (err) {
6088		dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
6089		goto out_error;
6090	}
6091
6092	netif_carrier_off(dev);
6093
6094	/* Some NICs freeze when TX pause is enabled while NIC is
6095	 * down, and this stays across warm reboots. The sequence
6096	 * below should be enough to recover from that state.
6097	 */
6098	nv_update_pause(dev, 0);
6099	nv_start_tx(dev);
6100	nv_stop_tx(dev);
6101
6102	if (id->driver_data & DEV_HAS_VLAN)
6103		nv_vlan_mode(dev, dev->features);
6104
6105	dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
6106		 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
6107
6108	dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6109		 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6110		 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6111			"csum " : "",
6112		 dev->features & (NETIF_F_HW_VLAN_CTAG_RX |
6113				  NETIF_F_HW_VLAN_CTAG_TX) ?
6114			"vlan " : "",
6115		 dev->features & (NETIF_F_LOOPBACK) ?
6116			"loopback " : "",
6117		 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6118		 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6119		 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6120		 np->gigabit == PHY_GIGABIT ? "gbit " : "",
6121		 np->need_linktimer ? "lnktim " : "",
6122		 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6123		 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6124		 np->desc_ver);
6125
6126	return 0;
6127
6128out_error:
6129	nv_mgmt_release_sema(dev);
6130	if (phystate_orig)
6131		writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6132out_freering:
6133	free_rings(dev);
6134out_unmap:
6135	iounmap(get_hwbase(dev));
6136out_relreg:
6137	pci_release_regions(pci_dev);
6138out_disable:
6139	pci_disable_device(pci_dev);
6140out_free:
6141	free_percpu(np->txrx_stats);
6142out_alloc_percpu:
6143	free_netdev(dev);
6144out:
6145	return err;
6146}
6147
6148static void nv_restore_phy(struct net_device *dev)
6149{
6150	struct fe_priv *np = netdev_priv(dev);
6151	u16 phy_reserved, mii_control;
6152
6153	if (np->phy_oui == PHY_OUI_REALTEK &&
6154	    np->phy_model == PHY_MODEL_REALTEK_8201 &&
6155	    phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6156		mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6157		phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6158		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6159		phy_reserved |= PHY_REALTEK_INIT8;
6160		mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6161		mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6162
6163		/* restart auto negotiation */
6164		mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6165		mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6166		mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6167	}
6168}
6169
6170static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6171{
6172	struct net_device *dev = pci_get_drvdata(pci_dev);
6173	struct fe_priv *np = netdev_priv(dev);
6174	u8 __iomem *base = get_hwbase(dev);
6175
6176	/* special op: write back the misordered MAC address - otherwise
6177	 * the next nv_probe would see a wrong address.
6178	 */
6179	writel(np->orig_mac[0], base + NvRegMacAddrA);
6180	writel(np->orig_mac[1], base + NvRegMacAddrB);
6181	writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6182	       base + NvRegTransmitPoll);
6183}
6184
6185static void nv_remove(struct pci_dev *pci_dev)
6186{
6187	struct net_device *dev = pci_get_drvdata(pci_dev);
6188	struct fe_priv *np = netdev_priv(dev);
6189
6190	free_percpu(np->txrx_stats);
6191
6192	unregister_netdev(dev);
6193
6194	nv_restore_mac_addr(pci_dev);
6195
6196	/* restore any phy related changes */
6197	nv_restore_phy(dev);
6198
6199	nv_mgmt_release_sema(dev);
6200
6201	/* free all structures */
6202	free_rings(dev);
6203	iounmap(get_hwbase(dev));
6204	pci_release_regions(pci_dev);
6205	pci_disable_device(pci_dev);
6206	free_netdev(dev);
6207}
6208
6209#ifdef CONFIG_PM_SLEEP
6210static int nv_suspend(struct device *device)
6211{
6212	struct net_device *dev = dev_get_drvdata(device);
6213	struct fe_priv *np = netdev_priv(dev);
6214	u8 __iomem *base = get_hwbase(dev);
6215	int i;
6216
6217	if (netif_running(dev)) {
6218		/* Gross. */
6219		nv_close(dev);
6220	}
6221	netif_device_detach(dev);
6222
6223	/* save non-pci configuration space */
6224	for (i = 0; i <= np->register_size/sizeof(u32); i++)
6225		np->saved_config_space[i] = readl(base + i*sizeof(u32));
6226
6227	return 0;
6228}
6229
6230static int nv_resume(struct device *device)
6231{
6232	struct pci_dev *pdev = to_pci_dev(device);
6233	struct net_device *dev = pci_get_drvdata(pdev);
6234	struct fe_priv *np = netdev_priv(dev);
6235	u8 __iomem *base = get_hwbase(dev);
6236	int i, rc = 0;
6237
6238	/* restore non-pci configuration space */
6239	for (i = 0; i <= np->register_size/sizeof(u32); i++)
6240		writel(np->saved_config_space[i], base+i*sizeof(u32));
6241
6242	if (np->driver_data & DEV_NEED_MSI_FIX)
6243		pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6244
6245	/* restore phy state, including autoneg */
6246	phy_init(dev);
6247
6248	netif_device_attach(dev);
6249	if (netif_running(dev)) {
6250		rc = nv_open(dev);
6251		nv_set_multicast(dev);
6252	}
6253	return rc;
6254}
6255
6256static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6257#define NV_PM_OPS (&nv_pm_ops)
6258
6259#else
6260#define NV_PM_OPS NULL
6261#endif /* CONFIG_PM_SLEEP */
6262
6263#ifdef CONFIG_PM
6264static void nv_shutdown(struct pci_dev *pdev)
6265{
6266	struct net_device *dev = pci_get_drvdata(pdev);
6267	struct fe_priv *np = netdev_priv(dev);
6268
6269	if (netif_running(dev))
6270		nv_close(dev);
6271
6272	/*
6273	 * Restore the MAC so a kernel started by kexec won't get confused.
6274	 * If we really go for poweroff, we must not restore the MAC,
6275	 * otherwise the MAC for WOL will be reversed at least on some boards.
6276	 */
6277	if (system_state != SYSTEM_POWER_OFF)
6278		nv_restore_mac_addr(pdev);
6279
6280	pci_disable_device(pdev);
6281	/*
6282	 * Apparently it is not possible to reinitialise from D3 hot,
6283	 * only put the device into D3 if we really go for poweroff.
6284	 */
6285	if (system_state == SYSTEM_POWER_OFF) {
6286		pci_wake_from_d3(pdev, np->wolenabled);
6287		pci_set_power_state(pdev, PCI_D3hot);
6288	}
6289}
6290#else
6291#define nv_shutdown NULL
6292#endif /* CONFIG_PM */
6293
6294static const struct pci_device_id pci_tbl[] = {
6295	{	/* nForce Ethernet Controller */
6296		PCI_DEVICE(0x10DE, 0x01C3),
6297		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6298	},
6299	{	/* nForce2 Ethernet Controller */
6300		PCI_DEVICE(0x10DE, 0x0066),
6301		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6302	},
6303	{	/* nForce3 Ethernet Controller */
6304		PCI_DEVICE(0x10DE, 0x00D6),
6305		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6306	},
6307	{	/* nForce3 Ethernet Controller */
6308		PCI_DEVICE(0x10DE, 0x0086),
6309		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6310	},
6311	{	/* nForce3 Ethernet Controller */
6312		PCI_DEVICE(0x10DE, 0x008C),
6313		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6314	},
6315	{	/* nForce3 Ethernet Controller */
6316		PCI_DEVICE(0x10DE, 0x00E6),
6317		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6318	},
6319	{	/* nForce3 Ethernet Controller */
6320		PCI_DEVICE(0x10DE, 0x00DF),
6321		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6322	},
6323	{	/* CK804 Ethernet Controller */
6324		PCI_DEVICE(0x10DE, 0x0056),
6325		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6326	},
6327	{	/* CK804 Ethernet Controller */
6328		PCI_DEVICE(0x10DE, 0x0057),
6329		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6330	},
6331	{	/* MCP04 Ethernet Controller */
6332		PCI_DEVICE(0x10DE, 0x0037),
6333		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6334	},
6335	{	/* MCP04 Ethernet Controller */
6336		PCI_DEVICE(0x10DE, 0x0038),
6337		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6338	},
6339	{	/* MCP51 Ethernet Controller */
6340		PCI_DEVICE(0x10DE, 0x0268),
6341		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6342	},
6343	{	/* MCP51 Ethernet Controller */
6344		PCI_DEVICE(0x10DE, 0x0269),
6345		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6346	},
6347	{	/* MCP55 Ethernet Controller */
6348		PCI_DEVICE(0x10DE, 0x0372),
6349		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6350	},
6351	{	/* MCP55 Ethernet Controller */
6352		PCI_DEVICE(0x10DE, 0x0373),
6353		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6354	},
6355	{	/* MCP61 Ethernet Controller */
6356		PCI_DEVICE(0x10DE, 0x03E5),
6357		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6358	},
6359	{	/* MCP61 Ethernet Controller */
6360		PCI_DEVICE(0x10DE, 0x03E6),
6361		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6362	},
6363	{	/* MCP61 Ethernet Controller */
6364		PCI_DEVICE(0x10DE, 0x03EE),
6365		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6366	},
6367	{	/* MCP61 Ethernet Controller */
6368		PCI_DEVICE(0x10DE, 0x03EF),
6369		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6370	},
6371	{	/* MCP65 Ethernet Controller */
6372		PCI_DEVICE(0x10DE, 0x0450),
6373		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6374	},
6375	{	/* MCP65 Ethernet Controller */
6376		PCI_DEVICE(0x10DE, 0x0451),
6377		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6378	},
6379	{	/* MCP65 Ethernet Controller */
6380		PCI_DEVICE(0x10DE, 0x0452),
6381		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6382	},
6383	{	/* MCP65 Ethernet Controller */
6384		PCI_DEVICE(0x10DE, 0x0453),
6385		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6386	},
6387	{	/* MCP67 Ethernet Controller */
6388		PCI_DEVICE(0x10DE, 0x054C),
6389		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6390	},
6391	{	/* MCP67 Ethernet Controller */
6392		PCI_DEVICE(0x10DE, 0x054D),
6393		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6394	},
6395	{	/* MCP67 Ethernet Controller */
6396		PCI_DEVICE(0x10DE, 0x054E),
6397		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6398	},
6399	{	/* MCP67 Ethernet Controller */
6400		PCI_DEVICE(0x10DE, 0x054F),
6401		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6402	},
6403	{	/* MCP73 Ethernet Controller */
6404		PCI_DEVICE(0x10DE, 0x07DC),
6405		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6406	},
6407	{	/* MCP73 Ethernet Controller */
6408		PCI_DEVICE(0x10DE, 0x07DD),
6409		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6410	},
6411	{	/* MCP73 Ethernet Controller */
6412		PCI_DEVICE(0x10DE, 0x07DE),
6413		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6414	},
6415	{	/* MCP73 Ethernet Controller */
6416		PCI_DEVICE(0x10DE, 0x07DF),
6417		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6418	},
6419	{	/* MCP77 Ethernet Controller */
6420		PCI_DEVICE(0x10DE, 0x0760),
6421		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6422	},
6423	{	/* MCP77 Ethernet Controller */
6424		PCI_DEVICE(0x10DE, 0x0761),
6425		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6426	},
6427	{	/* MCP77 Ethernet Controller */
6428		PCI_DEVICE(0x10DE, 0x0762),
6429		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6430	},
6431	{	/* MCP77 Ethernet Controller */
6432		PCI_DEVICE(0x10DE, 0x0763),
6433		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6434	},
6435	{	/* MCP79 Ethernet Controller */
6436		PCI_DEVICE(0x10DE, 0x0AB0),
6437		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6438	},
6439	{	/* MCP79 Ethernet Controller */
6440		PCI_DEVICE(0x10DE, 0x0AB1),
6441		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6442	},
6443	{	/* MCP79 Ethernet Controller */
6444		PCI_DEVICE(0x10DE, 0x0AB2),
6445		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6446	},
6447	{	/* MCP79 Ethernet Controller */
6448		PCI_DEVICE(0x10DE, 0x0AB3),
6449		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6450	},
6451	{	/* MCP89 Ethernet Controller */
6452		PCI_DEVICE(0x10DE, 0x0D7D),
6453		.driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6454	},
6455	{0,},
6456};
6457
6458static struct pci_driver forcedeth_pci_driver = {
6459	.name		= DRV_NAME,
6460	.id_table	= pci_tbl,
6461	.probe		= nv_probe,
6462	.remove		= nv_remove,
6463	.shutdown	= nv_shutdown,
6464	.driver.pm	= NV_PM_OPS,
6465};
6466
6467module_param(max_interrupt_work, int, 0);
6468MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6469module_param(optimization_mode, int, 0);
6470MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6471module_param(poll_interval, int, 0);
6472MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6473module_param(msi, int, 0);
6474MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6475module_param(msix, int, 0);
6476MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6477module_param(dma_64bit, int, 0);
6478MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6479module_param(phy_cross, int, 0);
6480MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6481module_param(phy_power_down, int, 0);
6482MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6483module_param(debug_tx_timeout, bool, 0);
6484MODULE_PARM_DESC(debug_tx_timeout,
6485		 "Dump tx related registers and ring when tx_timeout happens");
6486
6487module_pci_driver(forcedeth_pci_driver);
6488MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6489MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6490MODULE_LICENSE("GPL");
6491MODULE_DEVICE_TABLE(pci, pci_tbl);