gdma_main.c

   1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/* Copyright (c) 2021, Microsoft Corporation. */
   3
   4#include <linux/debugfs.h>
   5#include <linux/module.h>
   6#include <linux/pci.h>
   7#include <linux/utsname.h>
   8#include <linux/version.h>
   9#include <linux/msi.h>
  10#include <linux/irqdomain.h>
  11#include <linux/export.h>
  12
  13#include <net/mana/mana.h>
  14#include <net/mana/hw_channel.h>
  15
  16struct dentry *mana_debugfs_root;
  17
  18struct mana_dev_recovery {
  19	struct list_head list;
  20	struct pci_dev *pdev;
  21	enum gdma_eqe_type type;
  22};
  23
  24static struct mana_dev_recovery_work {
  25	struct list_head dev_list;
  26	struct delayed_work work;
  27
  28	/* Lock for dev_list above */
  29	spinlock_t lock;
  30} mana_dev_recovery_work;
  31
  32static u32 mana_gd_r32(struct gdma_context *g, u64 offset)
  33{
  34	return readl(g->bar0_va + offset);
  35}
  36
  37static u64 mana_gd_r64(struct gdma_context *g, u64 offset)
  38{
  39	return readq(g->bar0_va + offset);
  40}
  41
  42static void mana_gd_init_pf_regs(struct pci_dev *pdev)
  43{
  44	struct gdma_context *gc = pci_get_drvdata(pdev);
  45	void __iomem *sriov_base_va;
  46	u64 sriov_base_off;
  47
  48	gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF;
  49	gc->db_page_base = gc->bar0_va +
  50				mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF);
  51
  52	gc->phys_db_page_base = gc->bar0_pa +
  53				mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF);
  54
  55	sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF);
  56
  57	sriov_base_va = gc->bar0_va + sriov_base_off;
  58	gc->shm_base = sriov_base_va +
  59			mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF);
  60}
  61
  62static void mana_gd_init_vf_regs(struct pci_dev *pdev)
  63{
  64	struct gdma_context *gc = pci_get_drvdata(pdev);
  65
  66	gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF;
  67
  68	gc->db_page_base = gc->bar0_va +
  69				mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET);
  70
  71	gc->phys_db_page_base = gc->bar0_pa +
  72				mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET);
  73
  74	gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET);
  75}
  76
  77static void mana_gd_init_registers(struct pci_dev *pdev)
  78{
  79	struct gdma_context *gc = pci_get_drvdata(pdev);
  80
  81	if (gc->is_pf)
  82		mana_gd_init_pf_regs(pdev);
  83	else
  84		mana_gd_init_vf_regs(pdev);
  85}
  86
  87/* Suppress logging when we set timeout to zero */
  88bool mana_need_log(struct gdma_context *gc, int err)
  89{
  90	struct hw_channel_context *hwc;
  91
  92	if (err != -ETIMEDOUT)
  93		return true;
  94
  95	if (!gc)
  96		return true;
  97
  98	hwc = gc->hwc.driver_data;
  99	if (hwc && hwc->hwc_timeout == 0)
 100		return false;
 101
 102	return true;
 103}
 104
 105static int mana_gd_query_max_resources(struct pci_dev *pdev)
 106{
 107	struct gdma_context *gc = pci_get_drvdata(pdev);
 108	struct gdma_query_max_resources_resp resp = {};
 109	struct gdma_general_req req = {};
 110	int err;
 111
 112	mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES,
 113			     sizeof(req), sizeof(resp));
 114
 115	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
 116	if (err || resp.hdr.status) {
 117		dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n",
 118			err, resp.hdr.status);
 119		return err ? err : -EPROTO;
 120	}
 121
 122	if (!pci_msix_can_alloc_dyn(pdev)) {
 123		if (gc->num_msix_usable > resp.max_msix)
 124			gc->num_msix_usable = resp.max_msix;
 125	} else {
 126		/* If dynamic allocation is enabled we have already allocated
 127		 * hwc msi
 128		 */
 129		gc->num_msix_usable = min(resp.max_msix, num_online_cpus() + 1);
 130	}
 131
 132	if (gc->num_msix_usable <= 1)
 133		return -ENOSPC;
 134
 135	gc->max_num_queues = num_online_cpus();
 136	if (gc->max_num_queues > MANA_MAX_NUM_QUEUES)
 137		gc->max_num_queues = MANA_MAX_NUM_QUEUES;
 138
 139	if (gc->max_num_queues > resp.max_eq)
 140		gc->max_num_queues = resp.max_eq;
 141
 142	if (gc->max_num_queues > resp.max_cq)
 143		gc->max_num_queues = resp.max_cq;
 144
 145	if (gc->max_num_queues > resp.max_sq)
 146		gc->max_num_queues = resp.max_sq;
 147
 148	if (gc->max_num_queues > resp.max_rq)
 149		gc->max_num_queues = resp.max_rq;
 150
 151	/* The Hardware Channel (HWC) used 1 MSI-X */
 152	if (gc->max_num_queues > gc->num_msix_usable - 1)
 153		gc->max_num_queues = gc->num_msix_usable - 1;
 154
 155	return 0;
 156}
 157
 158static int mana_gd_query_hwc_timeout(struct pci_dev *pdev, u32 *timeout_val)
 159{
 160	struct gdma_context *gc = pci_get_drvdata(pdev);
 161	struct gdma_query_hwc_timeout_resp resp = {};
 162	struct gdma_query_hwc_timeout_req req = {};
 163	int err;
 164
 165	mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_HWC_TIMEOUT,
 166			     sizeof(req), sizeof(resp));
 167	req.timeout_ms = *timeout_val;
 168	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
 169	if (err || resp.hdr.status)
 170		return err ? err : -EPROTO;
 171
 172	*timeout_val = resp.timeout_ms;
 173
 174	return 0;
 175}
 176
 177static int mana_gd_detect_devices(struct pci_dev *pdev)
 178{
 179	struct gdma_context *gc = pci_get_drvdata(pdev);
 180	struct gdma_list_devices_resp resp = {};
 181	struct gdma_general_req req = {};
 182	struct gdma_dev_id dev;
 183	int found_dev = 0;
 184	u16 dev_type;
 185	int err;
 186	u32 i;
 187
 188	mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req),
 189			     sizeof(resp));
 190
 191	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
 192	if (err || resp.hdr.status) {
 193		dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err,
 194			resp.hdr.status);
 195		return err ? err : -EPROTO;
 196	}
 197
 198	for (i = 0; i < GDMA_DEV_LIST_SIZE &&
 199	     found_dev < resp.num_of_devs; i++) {
 200		dev = resp.devs[i];
 201		dev_type = dev.type;
 202
 203		/* Skip empty devices */
 204		if (dev.as_uint32 == 0)
 205			continue;
 206
 207		found_dev++;
 208
 209		/* HWC is already detected in mana_hwc_create_channel(). */
 210		if (dev_type == GDMA_DEVICE_HWC)
 211			continue;
 212
 213		if (dev_type == GDMA_DEVICE_MANA) {
 214			gc->mana.gdma_context = gc;
 215			gc->mana.dev_id = dev;
 216		} else if (dev_type == GDMA_DEVICE_MANA_IB) {
 217			gc->mana_ib.dev_id = dev;
 218			gc->mana_ib.gdma_context = gc;
 219		}
 220	}
 221
 222	return gc->mana.dev_id.type == 0 ? -ENODEV : 0;
 223}
 224
 225int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req,
 226			 u32 resp_len, void *resp)
 227{
 228	struct hw_channel_context *hwc = gc->hwc.driver_data;
 229
 230	return mana_hwc_send_request(hwc, req_len, req, resp_len, resp);
 231}
 232EXPORT_SYMBOL_NS(mana_gd_send_request, "NET_MANA");
 233
 234int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length,
 235			 struct gdma_mem_info *gmi)
 236{
 237	dma_addr_t dma_handle;
 238	void *buf;
 239
 240	if (length < MANA_PAGE_SIZE || !is_power_of_2(length))
 241		return -EINVAL;
 242
 243	gmi->dev = gc->dev;
 244	buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL);
 245	if (!buf)
 246		return -ENOMEM;
 247
 248	gmi->dma_handle = dma_handle;
 249	gmi->virt_addr = buf;
 250	gmi->length = length;
 251
 252	return 0;
 253}
 254
 255void mana_gd_free_memory(struct gdma_mem_info *gmi)
 256{
 257	dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr,
 258			  gmi->dma_handle);
 259}
 260
 261static int mana_gd_create_hw_eq(struct gdma_context *gc,
 262				struct gdma_queue *queue)
 263{
 264	struct gdma_create_queue_resp resp = {};
 265	struct gdma_create_queue_req req = {};
 266	int err;
 267
 268	if (queue->type != GDMA_EQ)
 269		return -EINVAL;
 270
 271	mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE,
 272			     sizeof(req), sizeof(resp));
 273
 274	req.hdr.dev_id = queue->gdma_dev->dev_id;
 275	req.type = queue->type;
 276	req.pdid = queue->gdma_dev->pdid;
 277	req.doolbell_id = queue->gdma_dev->doorbell;
 278	req.gdma_region = queue->mem_info.dma_region_handle;
 279	req.queue_size = queue->queue_size;
 280	req.log2_throttle_limit = queue->eq.log2_throttle_limit;
 281	req.eq_pci_msix_index = queue->eq.msix_index;
 282
 283	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
 284	if (err || resp.hdr.status) {
 285		dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err,
 286			resp.hdr.status);
 287		return err ? err : -EPROTO;
 288	}
 289
 290	queue->id = resp.queue_index;
 291	queue->eq.disable_needed = true;
 292	queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION;
 293	return 0;
 294}
 295
 296static int mana_gd_disable_queue(struct gdma_queue *queue)
 297{
 298	struct gdma_context *gc = queue->gdma_dev->gdma_context;
 299	struct gdma_disable_queue_req req = {};
 300	struct gdma_general_resp resp = {};
 301	int err;
 302
 303	WARN_ON(queue->type != GDMA_EQ);
 304
 305	mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE,
 306			     sizeof(req), sizeof(resp));
 307
 308	req.hdr.dev_id = queue->gdma_dev->dev_id;
 309	req.type = queue->type;
 310	req.queue_index =  queue->id;
 311	req.alloc_res_id_on_creation = 1;
 312
 313	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
 314	if (err || resp.hdr.status) {
 315		if (mana_need_log(gc, err))
 316			dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err,
 317				resp.hdr.status);
 318		return err ? err : -EPROTO;
 319	}
 320
 321	return 0;
 322}
 323
 324#define DOORBELL_OFFSET_SQ	0x0
 325#define DOORBELL_OFFSET_RQ	0x400
 326#define DOORBELL_OFFSET_CQ	0x800
 327#define DOORBELL_OFFSET_EQ	0xFF8
 328
 329static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index,
 330				  enum gdma_queue_type q_type, u32 qid,
 331				  u32 tail_ptr, u8 num_req)
 332{
 333	void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index;
 334	union gdma_doorbell_entry e = {};
 335
 336	switch (q_type) {
 337	case GDMA_EQ:
 338		e.eq.id = qid;
 339		e.eq.tail_ptr = tail_ptr;
 340		e.eq.arm = num_req;
 341
 342		addr += DOORBELL_OFFSET_EQ;
 343		break;
 344
 345	case GDMA_CQ:
 346		e.cq.id = qid;
 347		e.cq.tail_ptr = tail_ptr;
 348		e.cq.arm = num_req;
 349
 350		addr += DOORBELL_OFFSET_CQ;
 351		break;
 352
 353	case GDMA_RQ:
 354		e.rq.id = qid;
 355		e.rq.tail_ptr = tail_ptr;
 356		e.rq.wqe_cnt = num_req;
 357
 358		addr += DOORBELL_OFFSET_RQ;
 359		break;
 360
 361	case GDMA_SQ:
 362		e.sq.id = qid;
 363		e.sq.tail_ptr = tail_ptr;
 364
 365		addr += DOORBELL_OFFSET_SQ;
 366		break;
 367
 368	default:
 369		WARN_ON(1);
 370		return;
 371	}
 372
 373	/* Ensure all writes are done before ring doorbell */
 374	wmb();
 375
 376	writeq(e.as_uint64, addr);
 377}
 378
 379void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue)
 380{
 381	/* Hardware Spec specifies that software client should set 0 for
 382	 * wqe_cnt for Receive Queues. This value is not used in Send Queues.
 383	 */
 384	mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type,
 385			      queue->id, queue->head * GDMA_WQE_BU_SIZE, 0);
 386}
 387EXPORT_SYMBOL_NS(mana_gd_wq_ring_doorbell, "NET_MANA");
 388
 389void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit)
 390{
 391	struct gdma_context *gc = cq->gdma_dev->gdma_context;
 392
 393	u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE;
 394
 395	u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS);
 396
 397	mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id,
 398			      head, arm_bit);
 399}
 400EXPORT_SYMBOL_NS(mana_gd_ring_cq, "NET_MANA");
 401
 402#define MANA_SERVICE_PERIOD 10
 403
 404static void mana_serv_rescan(struct pci_dev *pdev)
 405{
 406	struct pci_bus *parent;
 407
 408	pci_lock_rescan_remove();
 409
 410	parent = pdev->bus;
 411	if (!parent) {
 412		dev_err(&pdev->dev, "MANA service: no parent bus\n");
 413		goto out;
 414	}
 415
 416	pci_stop_and_remove_bus_device(pdev);
 417	pci_rescan_bus(parent);
 418
 419out:
 420	pci_unlock_rescan_remove();
 421}
 422
 423static void mana_serv_fpga(struct pci_dev *pdev)
 424{
 425	struct pci_bus *bus, *parent;
 426
 427	pci_lock_rescan_remove();
 428
 429	bus = pdev->bus;
 430	if (!bus) {
 431		dev_err(&pdev->dev, "MANA service: no bus\n");
 432		goto out;
 433	}
 434
 435	parent = bus->parent;
 436	if (!parent) {
 437		dev_err(&pdev->dev, "MANA service: no parent bus\n");
 438		goto out;
 439	}
 440
 441	pci_stop_and_remove_bus_device(bus->self);
 442
 443	msleep(MANA_SERVICE_PERIOD * 1000);
 444
 445	pci_rescan_bus(parent);
 446
 447out:
 448	pci_unlock_rescan_remove();
 449}
 450
 451static void mana_serv_reset(struct pci_dev *pdev)
 452{
 453	struct gdma_context *gc = pci_get_drvdata(pdev);
 454	struct hw_channel_context *hwc;
 455	int ret;
 456
 457	if (!gc) {
 458		/* Perform PCI rescan on device if GC is not set up */
 459		dev_err(&pdev->dev, "MANA service: GC not setup, rescanning\n");
 460		mana_serv_rescan(pdev);
 461		return;
 462	}
 463
 464	hwc = gc->hwc.driver_data;
 465	if (!hwc) {
 466		dev_err(&pdev->dev, "MANA service: no HWC\n");
 467		goto out;
 468	}
 469
 470	/* HWC is not responding in this case, so don't wait */
 471	hwc->hwc_timeout = 0;
 472
 473	dev_info(&pdev->dev, "MANA reset cycle start\n");
 474
 475	mana_gd_suspend(pdev, PMSG_SUSPEND);
 476
 477	msleep(MANA_SERVICE_PERIOD * 1000);
 478
 479	ret = mana_gd_resume(pdev);
 480	if (ret == -ETIMEDOUT || ret == -EPROTO) {
 481		/* Perform PCI rescan on device if we failed on HWC */
 482		dev_err(&pdev->dev, "MANA service: resume failed, rescanning\n");
 483		mana_serv_rescan(pdev);
 484		return;
 485	}
 486
 487	if (ret)
 488		dev_info(&pdev->dev, "MANA reset cycle failed err %d\n", ret);
 489	else
 490		dev_info(&pdev->dev, "MANA reset cycle completed\n");
 491
 492out:
 493	gc->in_service = false;
 494}
 495
 496struct mana_serv_work {
 497	struct work_struct serv_work;
 498	struct pci_dev *pdev;
 499	enum gdma_eqe_type type;
 500};
 501
 502static void mana_do_service(enum gdma_eqe_type type, struct pci_dev *pdev)
 503{
 504	switch (type) {
 505	case GDMA_EQE_HWC_FPGA_RECONFIG:
 506		mana_serv_fpga(pdev);
 507		break;
 508
 509	case GDMA_EQE_HWC_RESET_REQUEST:
 510		mana_serv_reset(pdev);
 511		break;
 512
 513	default:
 514		dev_err(&pdev->dev, "MANA service: unknown type %d\n", type);
 515		break;
 516	}
 517}
 518
 519static void mana_recovery_delayed_func(struct work_struct *w)
 520{
 521	struct mana_dev_recovery_work *work;
 522	struct mana_dev_recovery *dev;
 523	unsigned long flags;
 524
 525	work = container_of(w, struct mana_dev_recovery_work, work.work);
 526
 527	spin_lock_irqsave(&work->lock, flags);
 528
 529	while (!list_empty(&work->dev_list)) {
 530		dev = list_first_entry(&work->dev_list,
 531				       struct mana_dev_recovery, list);
 532		list_del(&dev->list);
 533		spin_unlock_irqrestore(&work->lock, flags);
 534
 535		mana_do_service(dev->type, dev->pdev);
 536		pci_dev_put(dev->pdev);
 537		kfree(dev);
 538
 539		spin_lock_irqsave(&work->lock, flags);
 540	}
 541
 542	spin_unlock_irqrestore(&work->lock, flags);
 543}
 544
 545static void mana_serv_func(struct work_struct *w)
 546{
 547	struct mana_serv_work *mns_wk;
 548	struct pci_dev *pdev;
 549
 550	mns_wk = container_of(w, struct mana_serv_work, serv_work);
 551	pdev = mns_wk->pdev;
 552
 553	if (pdev)
 554		mana_do_service(mns_wk->type, pdev);
 555
 556	pci_dev_put(pdev);
 557	kfree(mns_wk);
 558	module_put(THIS_MODULE);
 559}
 560
 561static void mana_gd_process_eqe(struct gdma_queue *eq)
 562{
 563	u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE);
 564	struct gdma_context *gc = eq->gdma_dev->gdma_context;
 565	struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr;
 566	struct mana_serv_work *mns_wk;
 567	union gdma_eqe_info eqe_info;
 568	enum gdma_eqe_type type;
 569	struct gdma_event event;
 570	struct gdma_queue *cq;
 571	struct gdma_eqe *eqe;
 572	u32 cq_id;
 573
 574	eqe = &eq_eqe_ptr[head];
 575	eqe_info.as_uint32 = eqe->eqe_info;
 576	type = eqe_info.type;
 577
 578	switch (type) {
 579	case GDMA_EQE_COMPLETION:
 580		cq_id = eqe->details[0] & 0xFFFFFF;
 581		if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs))
 582			break;
 583
 584		cq = gc->cq_table[cq_id];
 585		if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id))
 586			break;
 587
 588		if (cq->cq.callback)
 589			cq->cq.callback(cq->cq.context, cq);
 590
 591		break;
 592
 593	case GDMA_EQE_TEST_EVENT:
 594		gc->test_event_eq_id = eq->id;
 595		complete(&gc->eq_test_event);
 596		break;
 597
 598	case GDMA_EQE_HWC_INIT_EQ_ID_DB:
 599	case GDMA_EQE_HWC_INIT_DATA:
 600	case GDMA_EQE_HWC_INIT_DONE:
 601	case GDMA_EQE_HWC_SOC_SERVICE:
 602	case GDMA_EQE_RNIC_QP_FATAL:
 603	case GDMA_EQE_HWC_SOC_RECONFIG_DATA:
 604		if (!eq->eq.callback)
 605			break;
 606
 607		event.type = type;
 608		memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE);
 609		eq->eq.callback(eq->eq.context, eq, &event);
 610		break;
 611
 612	case GDMA_EQE_HWC_FPGA_RECONFIG:
 613	case GDMA_EQE_HWC_RESET_REQUEST:
 614		dev_info(gc->dev, "Recv MANA service type:%d\n", type);
 615
 616		if (!test_and_set_bit(GC_PROBE_SUCCEEDED, &gc->flags)) {
 617			/*
 618			 * Device is in probe and we received a hardware reset
 619			 * event, the probe function will detect that the flag
 620			 * has changed and perform service procedure.
 621			 */
 622			dev_info(gc->dev,
 623				 "Service is to be processed in probe\n");
 624			break;
 625		}
 626
 627		if (gc->in_service) {
 628			dev_info(gc->dev, "Already in service\n");
 629			break;
 630		}
 631
 632		if (!try_module_get(THIS_MODULE)) {
 633			dev_info(gc->dev, "Module is unloading\n");
 634			break;
 635		}
 636
 637		mns_wk = kzalloc(sizeof(*mns_wk), GFP_ATOMIC);
 638		if (!mns_wk) {
 639			module_put(THIS_MODULE);
 640			break;
 641		}
 642
 643		dev_info(gc->dev, "Start MANA service type:%d\n", type);
 644		gc->in_service = true;
 645		mns_wk->pdev = to_pci_dev(gc->dev);
 646		mns_wk->type = type;
 647		pci_dev_get(mns_wk->pdev);
 648		INIT_WORK(&mns_wk->serv_work, mana_serv_func);
 649		schedule_work(&mns_wk->serv_work);
 650		break;
 651
 652	default:
 653		break;
 654	}
 655}
 656
 657static void mana_gd_process_eq_events(void *arg)
 658{
 659	u32 owner_bits, new_bits, old_bits;
 660	union gdma_eqe_info eqe_info;
 661	struct gdma_eqe *eq_eqe_ptr;
 662	struct gdma_queue *eq = arg;
 663	struct gdma_context *gc;
 664	struct gdma_eqe *eqe;
 665	u32 head, num_eqe;
 666	int i;
 667
 668	gc = eq->gdma_dev->gdma_context;
 669
 670	num_eqe = eq->queue_size / GDMA_EQE_SIZE;
 671	eq_eqe_ptr = eq->queue_mem_ptr;
 672
 673	/* Process up to 5 EQEs at a time, and update the HW head. */
 674	for (i = 0; i < 5; i++) {
 675		eqe = &eq_eqe_ptr[eq->head % num_eqe];
 676		eqe_info.as_uint32 = eqe->eqe_info;
 677		owner_bits = eqe_info.owner_bits;
 678
 679		old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK;
 680		/* No more entries */
 681		if (owner_bits == old_bits) {
 682			/* return here without ringing the doorbell */
 683			if (i == 0)
 684				return;
 685			break;
 686		}
 687
 688		new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK;
 689		if (owner_bits != new_bits) {
 690			dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id);
 691			break;
 692		}
 693
 694		/* Per GDMA spec, rmb is necessary after checking owner_bits, before
 695		 * reading eqe.
 696		 */
 697		rmb();
 698
 699		mana_gd_process_eqe(eq);
 700
 701		eq->head++;
 702	}
 703
 704	head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS);
 705
 706	mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id,
 707			      head, SET_ARM_BIT);
 708}
 709
 710static int mana_gd_register_irq(struct gdma_queue *queue,
 711				const struct gdma_queue_spec *spec)
 712{
 713	struct gdma_dev *gd = queue->gdma_dev;
 714	struct gdma_irq_context *gic;
 715	struct gdma_context *gc;
 716	unsigned int msi_index;
 717	unsigned long flags;
 718	struct device *dev;
 719	int err = 0;
 720
 721	gc = gd->gdma_context;
 722	dev = gc->dev;
 723	msi_index = spec->eq.msix_index;
 724
 725	if (msi_index >= gc->num_msix_usable) {
 726		err = -ENOSPC;
 727		dev_err(dev, "Register IRQ err:%d, msi:%u nMSI:%u",
 728			err, msi_index, gc->num_msix_usable);
 729
 730		return err;
 731	}
 732
 733	queue->eq.msix_index = msi_index;
 734	gic = xa_load(&gc->irq_contexts, msi_index);
 735	if (WARN_ON(!gic))
 736		return -EINVAL;
 737
 738	spin_lock_irqsave(&gic->lock, flags);
 739	list_add_rcu(&queue->entry, &gic->eq_list);
 740	spin_unlock_irqrestore(&gic->lock, flags);
 741
 742	return 0;
 743}
 744
 745static void mana_gd_deregister_irq(struct gdma_queue *queue)
 746{
 747	struct gdma_dev *gd = queue->gdma_dev;
 748	struct gdma_irq_context *gic;
 749	struct gdma_context *gc;
 750	unsigned int msix_index;
 751	unsigned long flags;
 752	struct gdma_queue *eq;
 753
 754	gc = gd->gdma_context;
 755
 756	/* At most num_online_cpus() + 1 interrupts are used. */
 757	msix_index = queue->eq.msix_index;
 758	if (WARN_ON(msix_index >= gc->num_msix_usable))
 759		return;
 760
 761	gic = xa_load(&gc->irq_contexts, msix_index);
 762	if (WARN_ON(!gic))
 763		return;
 764
 765	spin_lock_irqsave(&gic->lock, flags);
 766	list_for_each_entry_rcu(eq, &gic->eq_list, entry) {
 767		if (queue == eq) {
 768			list_del_rcu(&eq->entry);
 769			break;
 770		}
 771	}
 772	spin_unlock_irqrestore(&gic->lock, flags);
 773
 774	queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
 775	synchronize_rcu();
 776}
 777
 778int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq)
 779{
 780	struct gdma_generate_test_event_req req = {};
 781	struct gdma_general_resp resp = {};
 782	struct device *dev = gc->dev;
 783	int err;
 784
 785	mutex_lock(&gc->eq_test_event_mutex);
 786
 787	init_completion(&gc->eq_test_event);
 788	gc->test_event_eq_id = INVALID_QUEUE_ID;
 789
 790	mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE,
 791			     sizeof(req), sizeof(resp));
 792
 793	req.hdr.dev_id = eq->gdma_dev->dev_id;
 794	req.queue_index = eq->id;
 795
 796	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
 797	if (err) {
 798		if (mana_need_log(gc, err))
 799			dev_err(dev, "test_eq failed: %d\n", err);
 800		goto out;
 801	}
 802
 803	err = -EPROTO;
 804
 805	if (resp.hdr.status) {
 806		dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status);
 807		goto out;
 808	}
 809
 810	if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) {
 811		dev_err(dev, "test_eq timed out on queue %d\n", eq->id);
 812		goto out;
 813	}
 814
 815	if (eq->id != gc->test_event_eq_id) {
 816		dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n",
 817			gc->test_event_eq_id, eq->id);
 818		goto out;
 819	}
 820
 821	err = 0;
 822out:
 823	mutex_unlock(&gc->eq_test_event_mutex);
 824	return err;
 825}
 826
 827static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets,
 828			       struct gdma_queue *queue)
 829{
 830	int err;
 831
 832	if (flush_evenets) {
 833		err = mana_gd_test_eq(gc, queue);
 834		if (err && mana_need_log(gc, err))
 835			dev_warn(gc->dev, "Failed to flush EQ: %d\n", err);
 836	}
 837
 838	mana_gd_deregister_irq(queue);
 839
 840	if (queue->eq.disable_needed)
 841		mana_gd_disable_queue(queue);
 842}
 843
 844static int mana_gd_create_eq(struct gdma_dev *gd,
 845			     const struct gdma_queue_spec *spec,
 846			     bool create_hwq, struct gdma_queue *queue)
 847{
 848	struct gdma_context *gc = gd->gdma_context;
 849	struct device *dev = gc->dev;
 850	u32 log2_num_entries;
 851	int err;
 852
 853	queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
 854	queue->id = INVALID_QUEUE_ID;
 855
 856	log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE);
 857
 858	if (spec->eq.log2_throttle_limit > log2_num_entries) {
 859		dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n",
 860			spec->eq.log2_throttle_limit, log2_num_entries);
 861		return -EINVAL;
 862	}
 863
 864	err = mana_gd_register_irq(queue, spec);
 865	if (err) {
 866		dev_err(dev, "Failed to register irq: %d\n", err);
 867		return err;
 868	}
 869
 870	queue->eq.callback = spec->eq.callback;
 871	queue->eq.context = spec->eq.context;
 872	queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);
 873	queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1;
 874
 875	if (create_hwq) {
 876		err = mana_gd_create_hw_eq(gc, queue);
 877		if (err)
 878			goto out;
 879
 880		err = mana_gd_test_eq(gc, queue);
 881		if (err)
 882			goto out;
 883	}
 884
 885	return 0;
 886out:
 887	dev_err(dev, "Failed to create EQ: %d\n", err);
 888	mana_gd_destroy_eq(gc, false, queue);
 889	return err;
 890}
 891
 892static void mana_gd_create_cq(const struct gdma_queue_spec *spec,
 893			      struct gdma_queue *queue)
 894{
 895	u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE);
 896
 897	queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);
 898	queue->cq.parent = spec->cq.parent_eq;
 899	queue->cq.context = spec->cq.context;
 900	queue->cq.callback = spec->cq.callback;
 901}
 902
 903static void mana_gd_destroy_cq(struct gdma_context *gc,
 904			       struct gdma_queue *queue)
 905{
 906	u32 id = queue->id;
 907
 908	if (id >= gc->max_num_cqs)
 909		return;
 910
 911	if (!gc->cq_table[id])
 912		return;
 913
 914	gc->cq_table[id] = NULL;
 915}
 916
 917int mana_gd_create_hwc_queue(struct gdma_dev *gd,
 918			     const struct gdma_queue_spec *spec,
 919			     struct gdma_queue **queue_ptr)
 920{
 921	struct gdma_context *gc = gd->gdma_context;
 922	struct gdma_mem_info *gmi;
 923	struct gdma_queue *queue;
 924	int err;
 925
 926	queue = kzalloc(sizeof(*queue), GFP_KERNEL);
 927	if (!queue)
 928		return -ENOMEM;
 929
 930	gmi = &queue->mem_info;
 931	err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
 932	if (err) {
 933		dev_err(gc->dev, "GDMA queue type: %d, size: %u, gdma memory allocation err: %d\n",
 934			spec->type, spec->queue_size, err);
 935		goto free_q;
 936	}
 937
 938	queue->head = 0;
 939	queue->tail = 0;
 940	queue->queue_mem_ptr = gmi->virt_addr;
 941	queue->queue_size = spec->queue_size;
 942	queue->monitor_avl_buf = spec->monitor_avl_buf;
 943	queue->type = spec->type;
 944	queue->gdma_dev = gd;
 945
 946	if (spec->type == GDMA_EQ)
 947		err = mana_gd_create_eq(gd, spec, false, queue);
 948	else if (spec->type == GDMA_CQ)
 949		mana_gd_create_cq(spec, queue);
 950
 951	if (err)
 952		goto out;
 953
 954	*queue_ptr = queue;
 955	return 0;
 956out:
 957	dev_err(gc->dev, "Failed to create queue type %d of size %u, err: %d\n",
 958		spec->type, spec->queue_size, err);
 959	mana_gd_free_memory(gmi);
 960free_q:
 961	kfree(queue);
 962	return err;
 963}
 964
 965int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle)
 966{
 967	struct gdma_destroy_dma_region_req req = {};
 968	struct gdma_general_resp resp = {};
 969	int err;
 970
 971	if (dma_region_handle == GDMA_INVALID_DMA_REGION)
 972		return 0;
 973
 974	mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req),
 975			     sizeof(resp));
 976	req.dma_region_handle = dma_region_handle;
 977
 978	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
 979	if (err || resp.hdr.status) {
 980		if (mana_need_log(gc, err))
 981			dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n",
 982				err, resp.hdr.status);
 983		return -EPROTO;
 984	}
 985
 986	return 0;
 987}
 988EXPORT_SYMBOL_NS(mana_gd_destroy_dma_region, "NET_MANA");
 989
 990static int mana_gd_create_dma_region(struct gdma_dev *gd,
 991				     struct gdma_mem_info *gmi)
 992{
 993	unsigned int num_page = gmi->length / MANA_PAGE_SIZE;
 994	struct gdma_create_dma_region_req *req = NULL;
 995	struct gdma_create_dma_region_resp resp = {};
 996	struct gdma_context *gc = gd->gdma_context;
 997	struct hw_channel_context *hwc;
 998	u32 length = gmi->length;
 999	size_t req_msg_size;
1000	int err;
1001	int i;
1002
1003	if (length < MANA_PAGE_SIZE || !is_power_of_2(length))
1004		return -EINVAL;
1005
1006	if (!MANA_PAGE_ALIGNED(gmi->virt_addr))
1007		return -EINVAL;
1008
1009	hwc = gc->hwc.driver_data;
1010	req_msg_size = struct_size(req, page_addr_list, num_page);
1011	if (req_msg_size > hwc->max_req_msg_size)
1012		return -EINVAL;
1013
1014	req = kzalloc(req_msg_size, GFP_KERNEL);
1015	if (!req)
1016		return -ENOMEM;
1017
1018	mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION,
1019			     req_msg_size, sizeof(resp));
1020	req->length = length;
1021	req->offset_in_page = 0;
1022	req->gdma_page_type = GDMA_PAGE_TYPE_4K;
1023	req->page_count = num_page;
1024	req->page_addr_list_len = num_page;
1025
1026	for (i = 0; i < num_page; i++)
1027		req->page_addr_list[i] = gmi->dma_handle +  i * MANA_PAGE_SIZE;
1028
1029	err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp);
1030	if (err)
1031		goto out;
1032
1033	if (resp.hdr.status ||
1034	    resp.dma_region_handle == GDMA_INVALID_DMA_REGION) {
1035		dev_err(gc->dev, "Failed to create DMA region: 0x%x\n",
1036			resp.hdr.status);
1037		err = -EPROTO;
1038		goto out;
1039	}
1040
1041	gmi->dma_region_handle = resp.dma_region_handle;
1042	dev_dbg(gc->dev, "Created DMA region handle 0x%llx\n",
1043		gmi->dma_region_handle);
1044out:
1045	if (err)
1046		dev_dbg(gc->dev,
1047			"Failed to create DMA region of length: %u, page_type: %d, status: 0x%x, err: %d\n",
1048			length, req->gdma_page_type, resp.hdr.status, err);
1049	kfree(req);
1050	return err;
1051}
1052
1053int mana_gd_create_mana_eq(struct gdma_dev *gd,
1054			   const struct gdma_queue_spec *spec,
1055			   struct gdma_queue **queue_ptr)
1056{
1057	struct gdma_context *gc = gd->gdma_context;
1058	struct gdma_mem_info *gmi;
1059	struct gdma_queue *queue;
1060	int err;
1061
1062	if (spec->type != GDMA_EQ)
1063		return -EINVAL;
1064
1065	queue = kzalloc(sizeof(*queue), GFP_KERNEL);
1066	if (!queue)
1067		return -ENOMEM;
1068
1069	gmi = &queue->mem_info;
1070	err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
1071	if (err) {
1072		dev_err(gc->dev, "GDMA queue type: %d, size: %u, gdma memory allocation err: %d\n",
1073			spec->type, spec->queue_size, err);
1074		goto free_q;
1075	}
1076
1077	err = mana_gd_create_dma_region(gd, gmi);
1078	if (err)
1079		goto out;
1080
1081	queue->head = 0;
1082	queue->tail = 0;
1083	queue->queue_mem_ptr = gmi->virt_addr;
1084	queue->queue_size = spec->queue_size;
1085	queue->monitor_avl_buf = spec->monitor_avl_buf;
1086	queue->type = spec->type;
1087	queue->gdma_dev = gd;
1088
1089	err = mana_gd_create_eq(gd, spec, true, queue);
1090	if (err)
1091		goto out;
1092
1093	*queue_ptr = queue;
1094	return 0;
1095out:
1096	dev_err(gc->dev, "Failed to create queue type %d of size: %u, err: %d\n",
1097		spec->type, spec->queue_size, err);
1098	mana_gd_free_memory(gmi);
1099free_q:
1100	kfree(queue);
1101	return err;
1102}
1103EXPORT_SYMBOL_NS(mana_gd_create_mana_eq, "NET_MANA");
1104
1105int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,
1106			      const struct gdma_queue_spec *spec,
1107			      struct gdma_queue **queue_ptr)
1108{
1109	struct gdma_context *gc = gd->gdma_context;
1110	struct gdma_mem_info *gmi;
1111	struct gdma_queue *queue;
1112	int err;
1113
1114	if (spec->type != GDMA_CQ && spec->type != GDMA_SQ &&
1115	    spec->type != GDMA_RQ)
1116		return -EINVAL;
1117
1118	queue = kzalloc(sizeof(*queue), GFP_KERNEL);
1119	if (!queue)
1120		return -ENOMEM;
1121
1122	gmi = &queue->mem_info;
1123	err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
1124	if (err) {
1125		dev_err(gc->dev, "GDMA queue type: %d, size: %u, memory allocation err: %d\n",
1126			spec->type, spec->queue_size, err);
1127		goto free_q;
1128	}
1129
1130	err = mana_gd_create_dma_region(gd, gmi);
1131	if (err)
1132		goto out;
1133
1134	queue->head = 0;
1135	queue->tail = 0;
1136	queue->queue_mem_ptr = gmi->virt_addr;
1137	queue->queue_size = spec->queue_size;
1138	queue->monitor_avl_buf = spec->monitor_avl_buf;
1139	queue->type = spec->type;
1140	queue->gdma_dev = gd;
1141
1142	if (spec->type == GDMA_CQ)
1143		mana_gd_create_cq(spec, queue);
1144
1145	*queue_ptr = queue;
1146	return 0;
1147out:
1148	dev_err(gc->dev, "Failed to create queue type %d of size: %u, err: %d\n",
1149		spec->type, spec->queue_size, err);
1150	mana_gd_free_memory(gmi);
1151free_q:
1152	kfree(queue);
1153	return err;
1154}
1155EXPORT_SYMBOL_NS(mana_gd_create_mana_wq_cq, "NET_MANA");
1156
1157void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue)
1158{
1159	struct gdma_mem_info *gmi = &queue->mem_info;
1160
1161	switch (queue->type) {
1162	case GDMA_EQ:
1163		mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue);
1164		break;
1165
1166	case GDMA_CQ:
1167		mana_gd_destroy_cq(gc, queue);
1168		break;
1169
1170	case GDMA_RQ:
1171		break;
1172
1173	case GDMA_SQ:
1174		break;
1175
1176	default:
1177		dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n",
1178			queue->type);
1179		return;
1180	}
1181
1182	mana_gd_destroy_dma_region(gc, gmi->dma_region_handle);
1183	mana_gd_free_memory(gmi);
1184	kfree(queue);
1185}
1186EXPORT_SYMBOL_NS(mana_gd_destroy_queue, "NET_MANA");
1187
1188int mana_gd_verify_vf_version(struct pci_dev *pdev)
1189{
1190	struct gdma_context *gc = pci_get_drvdata(pdev);
1191	struct gdma_verify_ver_resp resp = {};
1192	struct gdma_verify_ver_req req = {};
1193	struct hw_channel_context *hwc;
1194	int err;
1195
1196	hwc = gc->hwc.driver_data;
1197	mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION,
1198			     sizeof(req), sizeof(resp));
1199
1200	req.protocol_ver_min = GDMA_PROTOCOL_FIRST;
1201	req.protocol_ver_max = GDMA_PROTOCOL_LAST;
1202
1203	req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1;
1204	req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2;
1205	req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3;
1206	req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4;
1207
1208	req.drv_ver = 0;	/* Unused*/
1209	req.os_type = 0x10;	/* Linux */
1210	req.os_ver_major = LINUX_VERSION_MAJOR;
1211	req.os_ver_minor = LINUX_VERSION_PATCHLEVEL;
1212	req.os_ver_build = LINUX_VERSION_SUBLEVEL;
1213	strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1));
1214	strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2));
1215	strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3));
1216
1217	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
1218	if (err || resp.hdr.status) {
1219		dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n",
1220			err, resp.hdr.status);
1221		return err ? err : -EPROTO;
1222	}
1223	gc->pf_cap_flags1 = resp.pf_cap_flags1;
1224	if (resp.pf_cap_flags1 & GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG) {
1225		err = mana_gd_query_hwc_timeout(pdev, &hwc->hwc_timeout);
1226		if (err) {
1227			dev_err(gc->dev, "Failed to set the hwc timeout %d\n", err);
1228			return err;
1229		}
1230		dev_dbg(gc->dev, "set the hwc timeout to %u\n", hwc->hwc_timeout);
1231	}
1232	return 0;
1233}
1234
1235int mana_gd_register_device(struct gdma_dev *gd)
1236{
1237	struct gdma_context *gc = gd->gdma_context;
1238	struct gdma_register_device_resp resp = {};
1239	struct gdma_general_req req = {};
1240	int err;
1241
1242	gd->pdid = INVALID_PDID;
1243	gd->doorbell = INVALID_DOORBELL;
1244	gd->gpa_mkey = INVALID_MEM_KEY;
1245
1246	mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req),
1247			     sizeof(resp));
1248
1249	req.hdr.dev_id = gd->dev_id;
1250
1251	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
1252	if (err || resp.hdr.status) {
1253		dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n",
1254			err, resp.hdr.status);
1255		return err ? err : -EPROTO;
1256	}
1257
1258	gd->pdid = resp.pdid;
1259	gd->gpa_mkey = resp.gpa_mkey;
1260	gd->doorbell = resp.db_id;
1261
1262	return 0;
1263}
1264
1265int mana_gd_deregister_device(struct gdma_dev *gd)
1266{
1267	struct gdma_context *gc = gd->gdma_context;
1268	struct gdma_general_resp resp = {};
1269	struct gdma_general_req req = {};
1270	int err;
1271
1272	if (gd->pdid == INVALID_PDID)
1273		return -EINVAL;
1274
1275	mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req),
1276			     sizeof(resp));
1277
1278	req.hdr.dev_id = gd->dev_id;
1279
1280	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
1281	if (err || resp.hdr.status) {
1282		if (mana_need_log(gc, err))
1283			dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n",
1284				err, resp.hdr.status);
1285		if (!err)
1286			err = -EPROTO;
1287	}
1288
1289	gd->pdid = INVALID_PDID;
1290	gd->doorbell = INVALID_DOORBELL;
1291	gd->gpa_mkey = INVALID_MEM_KEY;
1292
1293	return err;
1294}
1295
1296u32 mana_gd_wq_avail_space(struct gdma_queue *wq)
1297{
1298	u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE;
1299	u32 wq_size = wq->queue_size;
1300
1301	WARN_ON_ONCE(used_space > wq_size);
1302
1303	return wq_size - used_space;
1304}
1305
1306u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset)
1307{
1308	u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1);
1309
1310	WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size);
1311
1312	return wq->queue_mem_ptr + offset;
1313}
1314
1315static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req,
1316				    enum gdma_queue_type q_type,
1317				    u32 client_oob_size, u32 sgl_data_size,
1318				    u8 *wqe_ptr)
1319{
1320	bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL);
1321	bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0);
1322	struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr;
1323	u8 *ptr;
1324
1325	memset(header, 0, sizeof(struct gdma_wqe));
1326	header->num_sge = wqe_req->num_sge;
1327	header->inline_oob_size_div4 = client_oob_size / sizeof(u32);
1328
1329	if (oob_in_sgl) {
1330		WARN_ON_ONCE(wqe_req->num_sge < 2);
1331
1332		header->client_oob_in_sgl = 1;
1333
1334		if (pad_data)
1335			header->last_vbytes = wqe_req->sgl[0].size;
1336	}
1337
1338	if (q_type == GDMA_SQ)
1339		header->client_data_unit = wqe_req->client_data_unit;
1340
1341	/* The size of gdma_wqe + client_oob_size must be less than or equal
1342	 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond
1343	 * the queue memory buffer boundary.
1344	 */
1345	ptr = wqe_ptr + sizeof(header);
1346
1347	if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) {
1348		memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size);
1349
1350		if (client_oob_size > wqe_req->inline_oob_size)
1351			memset(ptr + wqe_req->inline_oob_size, 0,
1352			       client_oob_size - wqe_req->inline_oob_size);
1353	}
1354
1355	return sizeof(header) + client_oob_size;
1356}
1357
1358static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr,
1359			      const struct gdma_wqe_request *wqe_req)
1360{
1361	u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge;
1362	const u8 *address = (u8 *)wqe_req->sgl;
1363	u8 *base_ptr, *end_ptr;
1364	u32 size_to_end;
1365
1366	base_ptr = wq->queue_mem_ptr;
1367	end_ptr = base_ptr + wq->queue_size;
1368	size_to_end = (u32)(end_ptr - wqe_ptr);
1369
1370	if (size_to_end < sgl_size) {
1371		memcpy(wqe_ptr, address, size_to_end);
1372
1373		wqe_ptr = base_ptr;
1374		address += size_to_end;
1375		sgl_size -= size_to_end;
1376	}
1377
1378	memcpy(wqe_ptr, address, sgl_size);
1379}
1380
1381int mana_gd_post_work_request(struct gdma_queue *wq,
1382			      const struct gdma_wqe_request *wqe_req,
1383			      struct gdma_posted_wqe_info *wqe_info)
1384{
1385	u32 client_oob_size = wqe_req->inline_oob_size;
1386	u32 sgl_data_size;
1387	u32 max_wqe_size;
1388	u32 wqe_size;
1389	u8 *wqe_ptr;
1390
1391	if (wqe_req->num_sge == 0)
1392		return -EINVAL;
1393
1394	if (wq->type == GDMA_RQ) {
1395		if (client_oob_size != 0)
1396			return -EINVAL;
1397
1398		client_oob_size = INLINE_OOB_SMALL_SIZE;
1399
1400		max_wqe_size = GDMA_MAX_RQE_SIZE;
1401	} else {
1402		if (client_oob_size != INLINE_OOB_SMALL_SIZE &&
1403		    client_oob_size != INLINE_OOB_LARGE_SIZE)
1404			return -EINVAL;
1405
1406		max_wqe_size = GDMA_MAX_SQE_SIZE;
1407	}
1408
1409	sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge;
1410	wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size +
1411			 sgl_data_size, GDMA_WQE_BU_SIZE);
1412	if (wqe_size > max_wqe_size)
1413		return -EINVAL;
1414
1415	if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq))
1416		return -ENOSPC;
1417
1418	if (wqe_info)
1419		wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE;
1420
1421	wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head);
1422	wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size,
1423					    sgl_data_size, wqe_ptr);
1424	if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size)
1425		wqe_ptr -= wq->queue_size;
1426
1427	mana_gd_write_sgl(wq, wqe_ptr, wqe_req);
1428
1429	wq->head += wqe_size / GDMA_WQE_BU_SIZE;
1430
1431	return 0;
1432}
1433EXPORT_SYMBOL_NS(mana_gd_post_work_request, "NET_MANA");
1434
1435int mana_gd_post_and_ring(struct gdma_queue *queue,
1436			  const struct gdma_wqe_request *wqe_req,
1437			  struct gdma_posted_wqe_info *wqe_info)
1438{
1439	struct gdma_context *gc = queue->gdma_dev->gdma_context;
1440	int err;
1441
1442	err = mana_gd_post_work_request(queue, wqe_req, wqe_info);
1443	if (err) {
1444		dev_err(gc->dev, "Failed to post work req from queue type %d of size %u (err=%d)\n",
1445			queue->type, queue->queue_size, err);
1446		return err;
1447	}
1448
1449	mana_gd_wq_ring_doorbell(gc, queue);
1450
1451	return 0;
1452}
1453
1454static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp)
1455{
1456	unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe);
1457	struct gdma_cqe *cq_cqe = cq->queue_mem_ptr;
1458	u32 owner_bits, new_bits, old_bits;
1459	struct gdma_cqe *cqe;
1460
1461	cqe = &cq_cqe[cq->head % num_cqe];
1462	owner_bits = cqe->cqe_info.owner_bits;
1463
1464	old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK;
1465	/* Return 0 if no more entries. */
1466	if (owner_bits == old_bits)
1467		return 0;
1468
1469	new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK;
1470	/* Return -1 if overflow detected. */
1471	if (WARN_ON_ONCE(owner_bits != new_bits))
1472		return -1;
1473
1474	/* Per GDMA spec, rmb is necessary after checking owner_bits, before
1475	 * reading completion info
1476	 */
1477	rmb();
1478
1479	comp->wq_num = cqe->cqe_info.wq_num;
1480	comp->is_sq = cqe->cqe_info.is_sq;
1481	memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE);
1482
1483	return 1;
1484}
1485
1486int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe)
1487{
1488	int cqe_idx;
1489	int ret;
1490
1491	for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) {
1492		ret = mana_gd_read_cqe(cq, &comp[cqe_idx]);
1493
1494		if (ret < 0) {
1495			cq->head -= cqe_idx;
1496			return ret;
1497		}
1498
1499		if (ret == 0)
1500			break;
1501
1502		cq->head++;
1503	}
1504
1505	return cqe_idx;
1506}
1507EXPORT_SYMBOL_NS(mana_gd_poll_cq, "NET_MANA");
1508
1509static irqreturn_t mana_gd_intr(int irq, void *arg)
1510{
1511	struct gdma_irq_context *gic = arg;
1512	struct list_head *eq_list = &gic->eq_list;
1513	struct gdma_queue *eq;
1514
1515	rcu_read_lock();
1516	list_for_each_entry_rcu(eq, eq_list, entry) {
1517		gic->handler(eq);
1518	}
1519	rcu_read_unlock();
1520
1521	return IRQ_HANDLED;
1522}
1523
1524int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r)
1525{
1526	r->map = bitmap_zalloc(res_avail, GFP_KERNEL);
1527	if (!r->map)
1528		return -ENOMEM;
1529
1530	r->size = res_avail;
1531	spin_lock_init(&r->lock);
1532
1533	return 0;
1534}
1535
1536void mana_gd_free_res_map(struct gdma_resource *r)
1537{
1538	bitmap_free(r->map);
1539	r->map = NULL;
1540	r->size = 0;
1541}
1542
1543/*
1544 * Spread on CPUs with the following heuristics:
1545 *
1546 * 1. No more than one IRQ per CPU, if possible;
1547 * 2. NUMA locality is the second priority;
1548 * 3. Sibling dislocality is the last priority.
1549 *
1550 * Let's consider this topology:
1551 *
1552 * Node            0               1
1553 * Core        0       1       2       3
1554 * CPU       0   1   2   3   4   5   6   7
1555 *
1556 * The most performant IRQ distribution based on the above topology
1557 * and heuristics may look like this:
1558 *
1559 * IRQ     Nodes   Cores   CPUs
1560 * 0       1       0       0-1
1561 * 1       1       1       2-3
1562 * 2       1       0       0-1
1563 * 3       1       1       2-3
1564 * 4       2       2       4-5
1565 * 5       2       3       6-7
1566 * 6       2       2       4-5
1567 * 7       2       3       6-7
1568 *
1569 * The heuristics is implemented as follows.
1570 *
1571 * The outer for_each() loop resets the 'weight' to the actual number
1572 * of CPUs in the hop. Then inner for_each() loop decrements it by the
1573 * number of sibling groups (cores) while assigning first set of IRQs
1574 * to each group. IRQs 0 and 1 above are distributed this way.
1575 *
1576 * Now, because NUMA locality is more important, we should walk the
1577 * same set of siblings and assign 2nd set of IRQs (2 and 3), and it's
1578 * implemented by the medium while() loop. We do like this unless the
1579 * number of IRQs assigned on this hop will not become equal to number
1580 * of CPUs in the hop (weight == 0). Then we switch to the next hop and
1581 * do the same thing.
1582 */
1583
1584static int irq_setup(unsigned int *irqs, unsigned int len, int node,
1585		     bool skip_first_cpu)
1586{
1587	const struct cpumask *next, *prev = cpu_none_mask;
1588	cpumask_var_t cpus __free(free_cpumask_var);
1589	int cpu, weight;
1590
1591	if (!alloc_cpumask_var(&cpus, GFP_KERNEL))
1592		return -ENOMEM;
1593
1594	rcu_read_lock();
1595	for_each_numa_hop_mask(next, node) {
1596		weight = cpumask_weight_andnot(next, prev);
1597		while (weight > 0) {
1598			cpumask_andnot(cpus, next, prev);
1599			for_each_cpu(cpu, cpus) {
1600				cpumask_andnot(cpus, cpus, topology_sibling_cpumask(cpu));
1601				--weight;
1602
1603				if (unlikely(skip_first_cpu)) {
1604					skip_first_cpu = false;
1605					continue;
1606				}
1607
1608				if (len-- == 0)
1609					goto done;
1610
1611				irq_set_affinity_and_hint(*irqs++, topology_sibling_cpumask(cpu));
1612			}
1613		}
1614		prev = next;
1615	}
1616done:
1617	rcu_read_unlock();
1618	return 0;
1619}
1620
1621static int mana_gd_setup_dyn_irqs(struct pci_dev *pdev, int nvec)
1622{
1623	struct gdma_context *gc = pci_get_drvdata(pdev);
1624	struct gdma_irq_context *gic;
1625	bool skip_first_cpu = false;
1626	int *irqs, irq, err, i;
1627
1628	irqs = kmalloc_array(nvec, sizeof(int), GFP_KERNEL);
1629	if (!irqs)
1630		return -ENOMEM;
1631
1632	/*
1633	 * While processing the next pci irq vector, we start with index 1,
1634	 * as IRQ vector at index 0 is already processed for HWC.
1635	 * However, the population of irqs array starts with index 0, to be
1636	 * further used in irq_setup()
1637	 */
1638	for (i = 1; i <= nvec; i++) {
1639		gic = kzalloc(sizeof(*gic), GFP_KERNEL);
1640		if (!gic) {
1641			err = -ENOMEM;
1642			goto free_irq;
1643		}
1644		gic->handler = mana_gd_process_eq_events;
1645		INIT_LIST_HEAD(&gic->eq_list);
1646		spin_lock_init(&gic->lock);
1647
1648		snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s",
1649			 i - 1, pci_name(pdev));
1650
1651		/* one pci vector is already allocated for HWC */
1652		irqs[i - 1] = pci_irq_vector(pdev, i);
1653		if (irqs[i - 1] < 0) {
1654			err = irqs[i - 1];
1655			goto free_current_gic;
1656		}
1657
1658		err = request_irq(irqs[i - 1], mana_gd_intr, 0, gic->name, gic);
1659		if (err)
1660			goto free_current_gic;
1661
1662		xa_store(&gc->irq_contexts, i, gic, GFP_KERNEL);
1663	}
1664
1665	/*
1666	 * When calling irq_setup() for dynamically added IRQs, if number of
1667	 * CPUs is more than or equal to allocated MSI-X, we need to skip the
1668	 * first CPU sibling group since they are already affinitized to HWC IRQ
1669	 */
1670	cpus_read_lock();
1671	if (gc->num_msix_usable <= num_online_cpus())
1672		skip_first_cpu = true;
1673
1674	err = irq_setup(irqs, nvec, gc->numa_node, skip_first_cpu);
1675	if (err) {
1676		cpus_read_unlock();
1677		goto free_irq;
1678	}
1679
1680	cpus_read_unlock();
1681	kfree(irqs);
1682	return 0;
1683
1684free_current_gic:
1685	kfree(gic);
1686free_irq:
1687	for (i -= 1; i > 0; i--) {
1688		irq = pci_irq_vector(pdev, i);
1689		gic = xa_load(&gc->irq_contexts, i);
1690		if (WARN_ON(!gic))
1691			continue;
1692
1693		irq_update_affinity_hint(irq, NULL);
1694		free_irq(irq, gic);
1695		xa_erase(&gc->irq_contexts, i);
1696		kfree(gic);
1697	}
1698	kfree(irqs);
1699	return err;
1700}
1701
1702static int mana_gd_setup_irqs(struct pci_dev *pdev, int nvec)
1703{
1704	struct gdma_context *gc = pci_get_drvdata(pdev);
1705	struct gdma_irq_context *gic;
1706	int *irqs, *start_irqs, irq;
1707	unsigned int cpu;
1708	int err, i;
1709
1710	irqs = kmalloc_array(nvec, sizeof(int), GFP_KERNEL);
1711	if (!irqs)
1712		return -ENOMEM;
1713
1714	start_irqs = irqs;
1715
1716	for (i = 0; i < nvec; i++) {
1717		gic = kzalloc(sizeof(*gic), GFP_KERNEL);
1718		if (!gic) {
1719			err = -ENOMEM;
1720			goto free_irq;
1721		}
1722
1723		gic->handler = mana_gd_process_eq_events;
1724		INIT_LIST_HEAD(&gic->eq_list);
1725		spin_lock_init(&gic->lock);
1726
1727		if (!i)
1728			snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s",
1729				 pci_name(pdev));
1730		else
1731			snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s",
1732				 i - 1, pci_name(pdev));
1733
1734		irqs[i] = pci_irq_vector(pdev, i);
1735		if (irqs[i] < 0) {
1736			err = irqs[i];
1737			goto free_current_gic;
1738		}
1739
1740		err = request_irq(irqs[i], mana_gd_intr, 0, gic->name, gic);
1741		if (err)
1742			goto free_current_gic;
1743
1744		xa_store(&gc->irq_contexts, i, gic, GFP_KERNEL);
1745	}
1746
1747	/* If number of IRQ is one extra than number of online CPUs,
1748	 * then we need to assign IRQ0 (hwc irq) and IRQ1 to
1749	 * same CPU.
1750	 * Else we will use different CPUs for IRQ0 and IRQ1.
1751	 * Also we are using cpumask_local_spread instead of
1752	 * cpumask_first for the node, because the node can be
1753	 * mem only.
1754	 */
1755	cpus_read_lock();
1756	if (nvec > num_online_cpus()) {
1757		cpu = cpumask_local_spread(0, gc->numa_node);
1758		irq_set_affinity_and_hint(irqs[0], cpumask_of(cpu));
1759		irqs++;
1760		nvec -= 1;
1761	}
1762
1763	err = irq_setup(irqs, nvec, gc->numa_node, false);
1764	if (err) {
1765		cpus_read_unlock();
1766		goto free_irq;
1767	}
1768
1769	cpus_read_unlock();
1770	kfree(start_irqs);
1771	return 0;
1772
1773free_current_gic:
1774	kfree(gic);
1775free_irq:
1776	for (i -= 1; i >= 0; i--) {
1777		irq = pci_irq_vector(pdev, i);
1778		gic = xa_load(&gc->irq_contexts, i);
1779		if (WARN_ON(!gic))
1780			continue;
1781
1782		irq_update_affinity_hint(irq, NULL);
1783		free_irq(irq, gic);
1784		xa_erase(&gc->irq_contexts, i);
1785		kfree(gic);
1786	}
1787
1788	kfree(start_irqs);
1789	return err;
1790}
1791
1792static int mana_gd_setup_hwc_irqs(struct pci_dev *pdev)
1793{
1794	struct gdma_context *gc = pci_get_drvdata(pdev);
1795	unsigned int max_irqs, min_irqs;
1796	int nvec, err;
1797
1798	if (pci_msix_can_alloc_dyn(pdev)) {
1799		max_irqs = 1;
1800		min_irqs = 1;
1801	} else {
1802		/* Need 1 interrupt for HWC */
1803		max_irqs = min(num_online_cpus(), MANA_MAX_NUM_QUEUES) + 1;
1804		min_irqs = 2;
1805	}
1806
1807	nvec = pci_alloc_irq_vectors(pdev, min_irqs, max_irqs, PCI_IRQ_MSIX);
1808	if (nvec < 0)
1809		return nvec;
1810
1811	err = mana_gd_setup_irqs(pdev, nvec);
1812	if (err) {
1813		pci_free_irq_vectors(pdev);
1814		return err;
1815	}
1816
1817	gc->num_msix_usable = nvec;
1818	gc->max_num_msix = nvec;
1819
1820	return 0;
1821}
1822
1823static int mana_gd_setup_remaining_irqs(struct pci_dev *pdev)
1824{
1825	struct gdma_context *gc = pci_get_drvdata(pdev);
1826	struct msi_map irq_map;
1827	int max_irqs, i, err;
1828
1829	if (!pci_msix_can_alloc_dyn(pdev))
1830		/* remain irqs are already allocated with HWC IRQ */
1831		return 0;
1832
1833	/* allocate only remaining IRQs*/
1834	max_irqs = gc->num_msix_usable - 1;
1835
1836	for (i = 1; i <= max_irqs; i++) {
1837		irq_map = pci_msix_alloc_irq_at(pdev, i, NULL);
1838		if (!irq_map.virq) {
1839			err = irq_map.index;
1840			/* caller will handle cleaning up all allocated
1841			 * irqs, after HWC is destroyed
1842			 */
1843			return err;
1844		}
1845	}
1846
1847	err = mana_gd_setup_dyn_irqs(pdev, max_irqs);
1848	if (err)
1849		return err;
1850
1851	gc->max_num_msix = gc->max_num_msix + max_irqs;
1852
1853	return 0;
1854}
1855
1856static void mana_gd_remove_irqs(struct pci_dev *pdev)
1857{
1858	struct gdma_context *gc = pci_get_drvdata(pdev);
1859	struct gdma_irq_context *gic;
1860	int irq, i;
1861
1862	if (gc->max_num_msix < 1)
1863		return;
1864
1865	for (i = 0; i < gc->max_num_msix; i++) {
1866		irq = pci_irq_vector(pdev, i);
1867		if (irq < 0)
1868			continue;
1869
1870		gic = xa_load(&gc->irq_contexts, i);
1871		if (WARN_ON(!gic))
1872			continue;
1873
1874		/* Need to clear the hint before free_irq */
1875		irq_update_affinity_hint(irq, NULL);
1876		free_irq(irq, gic);
1877		xa_erase(&gc->irq_contexts, i);
1878		kfree(gic);
1879	}
1880
1881	pci_free_irq_vectors(pdev);
1882
1883	gc->max_num_msix = 0;
1884	gc->num_msix_usable = 0;
1885}
1886
1887static int mana_gd_setup(struct pci_dev *pdev)
1888{
1889	struct gdma_context *gc = pci_get_drvdata(pdev);
1890	int err;
1891
1892	mana_gd_init_registers(pdev);
1893	mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base);
1894
1895	gc->service_wq = alloc_ordered_workqueue("gdma_service_wq", 0);
1896	if (!gc->service_wq)
1897		return -ENOMEM;
1898
1899	err = mana_gd_setup_hwc_irqs(pdev);
1900	if (err) {
1901		dev_err(gc->dev, "Failed to setup IRQs for HWC creation: %d\n",
1902			err);
1903		goto free_workqueue;
1904	}
1905
1906	err = mana_hwc_create_channel(gc);
1907	if (err)
1908		goto remove_irq;
1909
1910	err = mana_gd_verify_vf_version(pdev);
1911	if (err)
1912		goto destroy_hwc;
1913
1914	err = mana_gd_query_max_resources(pdev);
1915	if (err)
1916		goto destroy_hwc;
1917
1918	err = mana_gd_setup_remaining_irqs(pdev);
1919	if (err) {
1920		dev_err(gc->dev, "Failed to setup remaining IRQs: %d", err);
1921		goto destroy_hwc;
1922	}
1923
1924	err = mana_gd_detect_devices(pdev);
1925	if (err)
1926		goto destroy_hwc;
1927
1928	dev_dbg(&pdev->dev, "mana gdma setup successful\n");
1929	return 0;
1930
1931destroy_hwc:
1932	mana_hwc_destroy_channel(gc);
1933remove_irq:
1934	mana_gd_remove_irqs(pdev);
1935free_workqueue:
1936	destroy_workqueue(gc->service_wq);
1937	gc->service_wq = NULL;
1938	dev_err(&pdev->dev, "%s failed (error %d)\n", __func__, err);
1939	return err;
1940}
1941
1942static void mana_gd_cleanup(struct pci_dev *pdev)
1943{
1944	struct gdma_context *gc = pci_get_drvdata(pdev);
1945
1946	mana_hwc_destroy_channel(gc);
1947
1948	mana_gd_remove_irqs(pdev);
1949
1950	if (gc->service_wq) {
1951		destroy_workqueue(gc->service_wq);
1952		gc->service_wq = NULL;
1953	}
1954	dev_dbg(&pdev->dev, "mana gdma cleanup successful\n");
1955}
1956
1957static bool mana_is_pf(unsigned short dev_id)
1958{
1959	return dev_id == MANA_PF_DEVICE_ID;
1960}
1961
1962static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1963{
1964	struct gdma_context *gc;
1965	void __iomem *bar0_va;
1966	int bar = 0;
1967	int err;
1968
1969	/* Each port has 2 CQs, each CQ has at most 1 EQE at a time */
1970	BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE);
1971
1972	err = pci_enable_device(pdev);
1973	if (err) {
1974		dev_err(&pdev->dev, "Failed to enable pci device (err=%d)\n", err);
1975		return -ENXIO;
1976	}
1977
1978	pci_set_master(pdev);
1979
1980	err = pci_request_regions(pdev, "mana");
1981	if (err)
1982		goto disable_dev;
1983
1984	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1985	if (err) {
1986		dev_err(&pdev->dev, "DMA set mask failed: %d\n", err);
1987		goto release_region;
1988	}
1989	dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1990
1991	err = -ENOMEM;
1992	gc = vzalloc(sizeof(*gc));
1993	if (!gc)
1994		goto release_region;
1995
1996	mutex_init(&gc->eq_test_event_mutex);
1997	pci_set_drvdata(pdev, gc);
1998	gc->bar0_pa = pci_resource_start(pdev, 0);
1999
2000	bar0_va = pci_iomap(pdev, bar, 0);
2001	if (!bar0_va)
2002		goto free_gc;
2003
2004	gc->numa_node = dev_to_node(&pdev->dev);
2005	gc->is_pf = mana_is_pf(pdev->device);
2006	gc->bar0_va = bar0_va;
2007	gc->dev = &pdev->dev;
2008	xa_init(&gc->irq_contexts);
2009
2010	if (gc->is_pf)
2011		gc->mana_pci_debugfs = debugfs_create_dir("0", mana_debugfs_root);
2012	else
2013		gc->mana_pci_debugfs = debugfs_create_dir(pci_slot_name(pdev->slot),
2014							  mana_debugfs_root);
2015
2016	err = mana_gd_setup(pdev);
2017	if (err)
2018		goto unmap_bar;
2019
2020	err = mana_probe(&gc->mana, false);
2021	if (err)
2022		goto cleanup_gd;
2023
2024	err = mana_rdma_probe(&gc->mana_ib);
2025	if (err)
2026		goto cleanup_mana;
2027
2028	/*
2029	 * If a hardware reset event has occurred over HWC during probe,
2030	 * rollback and perform hardware reset procedure.
2031	 */
2032	if (test_and_set_bit(GC_PROBE_SUCCEEDED, &gc->flags)) {
2033		err = -EPROTO;
2034		goto cleanup_mana_rdma;
2035	}
2036
2037	return 0;
2038
2039cleanup_mana_rdma:
2040	mana_rdma_remove(&gc->mana_ib);
2041cleanup_mana:
2042	mana_remove(&gc->mana, false);
2043cleanup_gd:
2044	mana_gd_cleanup(pdev);
2045unmap_bar:
2046	/*
2047	 * at this point we know that the other debugfs child dir/files
2048	 * are either not yet created or are already cleaned up.
2049	 * The pci debugfs folder clean-up now, will only be cleaning up
2050	 * adapter-MTU file and apc->mana_pci_debugfs folder.
2051	 */
2052	debugfs_remove_recursive(gc->mana_pci_debugfs);
2053	gc->mana_pci_debugfs = NULL;
2054	xa_destroy(&gc->irq_contexts);
2055	pci_iounmap(pdev, bar0_va);
2056free_gc:
2057	pci_set_drvdata(pdev, NULL);
2058	vfree(gc);
2059release_region:
2060	pci_release_regions(pdev);
2061disable_dev:
2062	pci_disable_device(pdev);
2063	dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err);
2064
2065	/*
2066	 * Hardware could be in recovery mode and the HWC returns TIMEDOUT or
2067	 * EPROTO from mana_gd_setup(), mana_probe() or mana_rdma_probe(), or
2068	 * we received a hardware reset event over HWC interrupt. In this case,
2069	 * perform the device recovery procedure after MANA_SERVICE_PERIOD
2070	 * seconds.
2071	 */
2072	if (err == -ETIMEDOUT || err == -EPROTO) {
2073		struct mana_dev_recovery *dev;
2074		unsigned long flags;
2075
2076		dev_info(&pdev->dev, "Start MANA recovery mode\n");
2077
2078		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2079		if (!dev)
2080			return err;
2081
2082		dev->pdev = pci_dev_get(pdev);
2083		dev->type = GDMA_EQE_HWC_RESET_REQUEST;
2084
2085		spin_lock_irqsave(&mana_dev_recovery_work.lock, flags);
2086		list_add_tail(&dev->list, &mana_dev_recovery_work.dev_list);
2087		spin_unlock_irqrestore(&mana_dev_recovery_work.lock, flags);
2088
2089		schedule_delayed_work(&mana_dev_recovery_work.work,
2090				      secs_to_jiffies(MANA_SERVICE_PERIOD));
2091	}
2092
2093	return err;
2094}
2095
2096static void mana_gd_remove(struct pci_dev *pdev)
2097{
2098	struct gdma_context *gc = pci_get_drvdata(pdev);
2099
2100	mana_rdma_remove(&gc->mana_ib);
2101	mana_remove(&gc->mana, false);
2102
2103	mana_gd_cleanup(pdev);
2104
2105	debugfs_remove_recursive(gc->mana_pci_debugfs);
2106
2107	gc->mana_pci_debugfs = NULL;
2108
2109	xa_destroy(&gc->irq_contexts);
2110
2111	pci_iounmap(pdev, gc->bar0_va);
2112
2113	vfree(gc);
2114
2115	pci_release_regions(pdev);
2116	pci_disable_device(pdev);
2117
2118	dev_dbg(&pdev->dev, "mana gdma remove successful\n");
2119}
2120
2121/* The 'state' parameter is not used. */
2122int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state)
2123{
2124	struct gdma_context *gc = pci_get_drvdata(pdev);
2125
2126	mana_rdma_remove(&gc->mana_ib);
2127	mana_remove(&gc->mana, true);
2128
2129	mana_gd_cleanup(pdev);
2130
2131	return 0;
2132}
2133
2134/* In case the NIC hardware stops working, the suspend and resume callbacks will
2135 * fail -- if this happens, it's safer to just report an error than try to undo
2136 * what has been done.
2137 */
2138int mana_gd_resume(struct pci_dev *pdev)
2139{
2140	struct gdma_context *gc = pci_get_drvdata(pdev);
2141	int err;
2142
2143	err = mana_gd_setup(pdev);
2144	if (err)
2145		return err;
2146
2147	err = mana_probe(&gc->mana, true);
2148	if (err)
2149		return err;
2150
2151	err = mana_rdma_probe(&gc->mana_ib);
2152	if (err)
2153		return err;
2154
2155	return 0;
2156}
2157
2158/* Quiesce the device for kexec. This is also called upon reboot/shutdown. */
2159static void mana_gd_shutdown(struct pci_dev *pdev)
2160{
2161	struct gdma_context *gc = pci_get_drvdata(pdev);
2162
2163	dev_info(&pdev->dev, "Shutdown was called\n");
2164
2165	mana_rdma_remove(&gc->mana_ib);
2166	mana_remove(&gc->mana, true);
2167
2168	mana_gd_cleanup(pdev);
2169
2170	debugfs_remove_recursive(gc->mana_pci_debugfs);
2171
2172	gc->mana_pci_debugfs = NULL;
2173
2174	pci_disable_device(pdev);
2175}
2176
2177static const struct pci_device_id mana_id_table[] = {
2178	{ PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) },
2179	{ PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) },
2180	{ }
2181};
2182
2183static struct pci_driver mana_driver = {
2184	.name		= "mana",
2185	.id_table	= mana_id_table,
2186	.probe		= mana_gd_probe,
2187	.remove		= mana_gd_remove,
2188	.suspend	= mana_gd_suspend,
2189	.resume		= mana_gd_resume,
2190	.shutdown	= mana_gd_shutdown,
2191};
2192
2193static int __init mana_driver_init(void)
2194{
2195	int err;
2196
2197	INIT_LIST_HEAD(&mana_dev_recovery_work.dev_list);
2198	spin_lock_init(&mana_dev_recovery_work.lock);
2199	INIT_DELAYED_WORK(&mana_dev_recovery_work.work, mana_recovery_delayed_func);
2200
2201	mana_debugfs_root = debugfs_create_dir("mana", NULL);
2202
2203	err = pci_register_driver(&mana_driver);
2204	if (err) {
2205		debugfs_remove(mana_debugfs_root);
2206		mana_debugfs_root = NULL;
2207	}
2208
2209	return err;
2210}
2211
2212static void __exit mana_driver_exit(void)
2213{
2214	struct mana_dev_recovery *dev;
2215	unsigned long flags;
2216
2217	disable_delayed_work_sync(&mana_dev_recovery_work.work);
2218
2219	spin_lock_irqsave(&mana_dev_recovery_work.lock, flags);
2220	while (!list_empty(&mana_dev_recovery_work.dev_list)) {
2221		dev = list_first_entry(&mana_dev_recovery_work.dev_list,
2222				       struct mana_dev_recovery, list);
2223		list_del(&dev->list);
2224		pci_dev_put(dev->pdev);
2225		kfree(dev);
2226	}
2227	spin_unlock_irqrestore(&mana_dev_recovery_work.lock, flags);
2228
2229	pci_unregister_driver(&mana_driver);
2230
2231	debugfs_remove(mana_debugfs_root);
2232
2233	mana_debugfs_root = NULL;
2234}
2235
2236module_init(mana_driver_init);
2237module_exit(mana_driver_exit);
2238
2239MODULE_DEVICE_TABLE(pci, mana_id_table);
2240
2241MODULE_LICENSE("Dual BSD/GPL");
2242MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver");