sparx5_main.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/* Microchip Sparx5 Switch driver
  3 *
  4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
  5 */
  6
  7#ifndef __SPARX5_MAIN_H__
  8#define __SPARX5_MAIN_H__
  9
 10#include <linux/types.h>
 11#include <linux/phy/phy.h>
 12#include <linux/netdevice.h>
 13#include <linux/phy.h>
 14#include <linux/if_vlan.h>
 15#include <linux/bitmap.h>
 16#include <linux/phylink.h>
 17#include <linux/net_tstamp.h>
 18#include <linux/ptp_clock_kernel.h>
 19#include <linux/hrtimer.h>
 20#include <linux/debugfs.h>
 21#include <net/flow_offload.h>
 22
 23#include <fdma_api.h>
 24
 25#include "sparx5_main_regs.h"
 26
 27/* Target chip type */
 28enum spx5_target_chiptype {
 29	SPX5_TARGET_CT_7546       = 0x7546,  /* SparX-5-64  Enterprise */
 30	SPX5_TARGET_CT_7549       = 0x7549,  /* SparX-5-90  Enterprise */
 31	SPX5_TARGET_CT_7552       = 0x7552,  /* SparX-5-128 Enterprise */
 32	SPX5_TARGET_CT_7556       = 0x7556,  /* SparX-5-160 Enterprise */
 33	SPX5_TARGET_CT_7558       = 0x7558,  /* SparX-5-200 Enterprise */
 34	SPX5_TARGET_CT_7546TSN    = 0x47546, /* SparX-5-64i Industrial */
 35	SPX5_TARGET_CT_7549TSN    = 0x47549, /* SparX-5-90i Industrial */
 36	SPX5_TARGET_CT_7552TSN    = 0x47552, /* SparX-5-128i Industrial */
 37	SPX5_TARGET_CT_7556TSN    = 0x47556, /* SparX-5-160i Industrial */
 38	SPX5_TARGET_CT_7558TSN    = 0x47558, /* SparX-5-200i Industrial */
 39	SPX5_TARGET_CT_LAN9694    = 0x9694,  /* lan969x-40 */
 40	SPX5_TARGET_CT_LAN9691VAO = 0x9691,  /* lan969x-40-VAO */
 41	SPX5_TARGET_CT_LAN9694TSN = 0x9695,  /* lan969x-40-TSN */
 42	SPX5_TARGET_CT_LAN9694RED = 0x969A,  /* lan969x-40-RED */
 43	SPX5_TARGET_CT_LAN9696    = 0x9696,  /* lan969x-60 */
 44	SPX5_TARGET_CT_LAN9692VAO = 0x9692,  /* lan969x-65-VAO */
 45	SPX5_TARGET_CT_LAN9696TSN = 0x9697,  /* lan969x-60-TSN */
 46	SPX5_TARGET_CT_LAN9696RED = 0x969B,  /* lan969x-60-RED */
 47	SPX5_TARGET_CT_LAN9698    = 0x9698,  /* lan969x-100 */
 48	SPX5_TARGET_CT_LAN9693VAO = 0x9693,  /* lan969x-100-VAO */
 49	SPX5_TARGET_CT_LAN9698TSN = 0x9699,  /* lan969x-100-TSN */
 50	SPX5_TARGET_CT_LAN9698RED = 0x969C,  /* lan969x-100-RED */
 51};
 52
 53enum sparx5_port_max_tags {
 54	SPX5_PORT_MAX_TAGS_NONE,  /* No extra tags allowed */
 55	SPX5_PORT_MAX_TAGS_ONE,   /* Single tag allowed */
 56	SPX5_PORT_MAX_TAGS_TWO    /* Single and double tag allowed */
 57};
 58
 59enum sparx5_vlan_port_type {
 60	SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */
 61	SPX5_VLAN_PORT_TYPE_C,       /* C-port */
 62	SPX5_VLAN_PORT_TYPE_S,       /* S-port */
 63	SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */
 64};
 65
 66/* This is used in calendar configuration */
 67enum sparx5_cal_bw {
 68	SPX5_CAL_SPEED_NONE = 0,
 69	SPX5_CAL_SPEED_1G   = 1,
 70	SPX5_CAL_SPEED_2G5  = 2,
 71	SPX5_CAL_SPEED_5G   = 3,
 72	SPX5_CAL_SPEED_10G  = 4,
 73	SPX5_CAL_SPEED_25G  = 5,
 74	SPX5_CAL_SPEED_0G5  = 6,
 75	SPX5_CAL_SPEED_12G5 = 7
 76};
 77
 78enum sparx5_feature {
 79	SPX5_FEATURE_PSFP = BIT(0),
 80	SPX5_FEATURE_PTP  = BIT(1),
 81};
 82
 83#define SPX5_PORTS             65
 84#define SPX5_PORTS_ALL         70 /* Total number of ports */
 85
 86#define SPX5_PORT_CPU_0        0 /* CPU Port 0 */
 87#define SPX5_PORT_CPU_1        1 /* CPU Port 1 */
 88#define SPX5_PORT_VD0          2 /* VD0/Port used for IPMC */
 89#define SPX5_PORT_VD1          3 /* VD1/Port used for AFI/OAM */
 90#define SPX5_PORT_VD2          4 /* VD2/Port used for IPinIP*/
 91
 92#define PGID_UC_FLOOD          0
 93#define PGID_MC_FLOOD          1
 94#define PGID_IPV4_MC_DATA      2
 95#define PGID_IPV4_MC_CTRL      3
 96#define PGID_IPV6_MC_DATA      4
 97#define PGID_IPV6_MC_CTRL      5
 98#define PGID_BCAST             6
 99#define PGID_CPU               7
100#define PGID_MCAST_START       8
101
102#define PGID_TABLE_SIZE	       3290
103
104#define IFH_LEN                9 /* 36 bytes */
105#define NULL_VID               0
106#define SPX5_MACT_PULL_DELAY   (2 * HZ)
107#define SPX5_STATS_CHECK_DELAY (1 * HZ)
108#define SPX5_PRIOS             8     /* Number of priority queues */
109#define SPX5_BUFFER_CELL_SZ    184   /* Cell size  */
110#define SPX5_BUFFER_MEMORY     4194280 /* 22795 words * 184 bytes */
111
112#define XTR_QUEUE     0
113#define INJ_QUEUE     0
114
115#define FDMA_XTR_CHANNEL		6
116#define FDMA_INJ_CHANNEL		0
117#define FDMA_DCB_MAX			64
118#define FDMA_RX_DCB_MAX_DBS		15
119#define FDMA_TX_DCB_MAX_DBS		1
120
121#define SPARX5_PHC_COUNT		3
122#define SPARX5_PHC_PORT			0
123
124#define IFH_REW_OP_NOOP			0x0
125#define IFH_REW_OP_ONE_STEP_PTP		0x3
126#define IFH_REW_OP_TWO_STEP_PTP		0x4
127
128#define IFH_PDU_TYPE_NONE		0x0
129#define IFH_PDU_TYPE_PTP		0x5
130#define IFH_PDU_TYPE_IPV4_UDP_PTP	0x6
131#define IFH_PDU_TYPE_IPV6_UDP_PTP	0x7
132
133#define SPX5_DSM_CAL_LEN               64
134#define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13
135#define SPX5_DSM_CAL_EMPTY             0xFFFF
136
137#define SPARX5_MAX_PTP_ID	512
138
139struct sparx5;
140
141struct sparx5_calendar_data {
142	u32 schedule[SPX5_DSM_CAL_LEN];
143	u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
144	u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
145	u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
146	u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
147	u32 new_slots[SPX5_DSM_CAL_LEN];
148	u32 temp_sched[SPX5_DSM_CAL_LEN];
149	u32 indices[SPX5_DSM_CAL_LEN];
150	u32 short_list[SPX5_DSM_CAL_LEN];
151	u32 long_list[SPX5_DSM_CAL_LEN];
152};
153
154/* Frame DMA receive state:
155 * For each DB, there is a SKB, and the skb data pointer is mapped in
156 * the DB. Once a frame is received the skb is given to the upper layers
157 * and a new skb is added to the dcb.
158 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused.
159 */
160struct sparx5_rx {
161	struct fdma fdma;
162	struct page_pool *page_pool;
163	union {
164		struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS];
165		struct page *page[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS];
166	};
167	dma_addr_t dma;
168	struct napi_struct napi;
169	struct net_device *ndev;
170	u64 packets;
171	u8 page_order;
172};
173
174/* Used to store information about TX buffers. */
175struct sparx5_tx_buf {
176	struct net_device *dev;
177	struct sk_buff *skb;
178	dma_addr_t dma_addr;
179	bool used;
180	bool ptp;
181};
182
183/* Frame DMA transmit state:
184 * DCBs are chained using the DCBs nextptr field.
185 */
186struct sparx5_tx {
187	struct fdma fdma;
188	struct sparx5_tx_buf *dbs;
189	u64 packets;
190	u64 dropped;
191};
192
193struct sparx5_port_config {
194	phy_interface_t portmode;
195	u32 bandwidth;
196	int speed;
197	int duplex;
198	enum phy_media media;
199	bool inband;
200	bool power_down;
201	bool autoneg;
202	bool serdes_reset;
203	u32 pause;
204	u32 pause_adv;
205	phy_interface_t phy_mode;
206	u32 sd_sgpio;
207};
208
209struct sparx5_port {
210	struct net_device *ndev;
211	struct sparx5 *sparx5;
212	struct device_node *of_node;
213	struct phy *serdes;
214	struct sparx5_port_config conf;
215	struct phylink_config phylink_config;
216	struct phylink *phylink;
217	struct phylink_pcs phylink_pcs;
218	struct flow_stats mirror_stats;
219	u16 portno;
220	/* Ingress default VLAN (pvid) */
221	u16 pvid;
222	/* Egress default VLAN (vid) */
223	u16 vid;
224	bool signd_internal;
225	bool signd_active_high;
226	bool signd_enable;
227	bool flow_control;
228	enum sparx5_port_max_tags max_vlan_tags;
229	enum sparx5_vlan_port_type vlan_type;
230	u32 custom_etype;
231	bool vlan_aware;
232	struct hrtimer inj_timer;
233	/* ptp */
234	u8 ptp_cmd;
235	u16 ts_id;
236	struct sk_buff_head tx_skbs;
237	bool is_mrouter;
238	struct list_head tc_templates; /* list of TC templates on this port */
239};
240
241enum sparx5_core_clockfreq {
242	SPX5_CORE_CLOCK_DEFAULT,  /* Defaults to the highest supported frequency */
243	SPX5_CORE_CLOCK_250MHZ,   /* 250MHZ core clock frequency */
244	SPX5_CORE_CLOCK_328MHZ,   /* 328MHZ core clock frequency */
245	SPX5_CORE_CLOCK_500MHZ,   /* 500MHZ core clock frequency */
246	SPX5_CORE_CLOCK_625MHZ,   /* 625MHZ core clock frequency */
247};
248
249struct sparx5_phc {
250	struct ptp_clock *clock;
251	struct ptp_clock_info info;
252	struct kernel_hwtstamp_config hwtstamp_config;
253	struct sparx5 *sparx5;
254	u8 index;
255};
256
257struct sparx5_skb_cb {
258	u8 rew_op;
259	u8 pdu_type;
260	u8 pdu_w16_offset;
261	u16 ts_id;
262	unsigned long jiffies;
263};
264
265struct sparx5_mdb_entry {
266	struct list_head list;
267	DECLARE_BITMAP(port_mask, SPX5_PORTS);
268	unsigned char addr[ETH_ALEN];
269	bool cpu_copy;
270	u16 vid;
271	u16 pgid_idx;
272};
273
274struct sparx5_mall_mirror_entry {
275	u32 idx;
276	struct sparx5_port *port;
277};
278
279struct sparx5_mall_entry {
280	struct list_head list;
281	struct sparx5_port *port;
282	unsigned long cookie;
283	enum flow_action_id type;
284	bool ingress;
285	union {
286		struct sparx5_mall_mirror_entry mirror;
287	};
288};
289
290#define SPARX5_PTP_TIMEOUT		msecs_to_jiffies(10)
291#define SPARX5_SKB_CB(skb) \
292	((struct sparx5_skb_cb *)((skb)->cb))
293
294struct sparx5_regs {
295	const unsigned int *tsize;
296	const unsigned int *gaddr;
297	const unsigned int *gcnt;
298	const unsigned int *gsize;
299	const unsigned int *raddr;
300	const unsigned int *rcnt;
301	const unsigned int *fpos;
302	const unsigned int *fsize;
303};
304
305struct sparx5_consts {
306	u32 n_ports;             /* Number of front ports */
307	u32 n_ports_all;         /* Number of front ports + internal ports */
308	u32 n_hsch_l1_elems;     /* Number of HSCH layer 1 elements */
309	u32 n_hsch_queues;       /* Number of HSCH queues */
310	u32 n_lb_groups;         /* Number of leacky bucket groupd */
311	u32 n_pgids;             /* Number of PGID's */
312	u32 n_sio_clks;          /* Number of serial IO clocks */
313	u32 n_own_upsids;        /* Number of own UPSID's */
314	u32 n_auto_cals;         /* Number of auto calendars */
315	u32 n_filters;           /* Number of PSFP filters */
316	u32 n_gates;             /* Number of PSFP gates */
317	u32 n_sdlbs;             /* Number of service dual leaky buckets */
318	u32 n_dsm_cal_taxis;     /* Number of DSM calendar taxis */
319	u32 buf_size;            /* Amount of QLIM watermark memory */
320	u32 qres_max_prio_idx;   /* Maximum QRES prio index */
321	u32 qres_max_colour_idx; /* Maximum QRES colour index */
322	u32 tod_pin;             /* PTP TOD pin */
323	const struct sparx5_vcap_inst *vcaps_cfg;
324	const struct vcap_info *vcaps;
325	const struct vcap_statistics *vcap_stats;
326};
327
328struct sparx5_ops {
329	bool (*is_port_2g5)(int portno);
330	bool (*is_port_5g)(int portno);
331	bool (*is_port_10g)(int portno);
332	bool (*is_port_25g)(int portno);
333	bool (*is_port_rgmii)(int portno);
334	u32  (*get_port_dev_index)(struct sparx5 *sparx5, int port);
335	u32  (*get_port_dev_bit)(struct sparx5 *sparx5, int port);
336	u32  (*get_hsch_max_group_rate)(int grp);
337	struct sparx5_sdlb_group *(*get_sdlb_group)(int idx);
338	int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port,
339			    struct sparx5_port_config *conf);
340
341	irqreturn_t (*ptp_irq_handler)(int irq, void *args);
342	int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi,
343				 struct sparx5_calendar_data *data);
344	int (*port_config_rgmii)(struct sparx5_port *port,
345				 struct sparx5_port_config *conf);
346	int (*fdma_init)(struct sparx5 *sparx5);
347	int (*fdma_deinit)(struct sparx5 *sparx5);
348	int (*fdma_poll)(struct napi_struct *napi, int weight);
349	int (*fdma_xmit)(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb,
350			 struct net_device *dev);
351};
352
353struct sparx5_main_io_resource {
354	enum sparx5_target id;
355	phys_addr_t offset;
356	int range;
357};
358
359struct sparx5_match_data {
360	const struct sparx5_regs *regs;
361	const struct sparx5_consts *consts;
362	const struct sparx5_ops *ops;
363	const struct sparx5_main_io_resource *iomap;
364	int ioranges;
365	int iomap_size;
366};
367
368struct sparx5 {
369	struct platform_device *pdev;
370	struct device *dev;
371	u32 chip_id;
372	enum spx5_target_chiptype target_ct;
373	u32 features;
374	void __iomem *regs[NUM_TARGETS];
375	int port_count;
376	struct mutex lock; /* MAC reg lock */
377	/* port structures are in net device */
378	struct sparx5_port *ports[SPX5_PORTS];
379	enum sparx5_core_clockfreq coreclock;
380	/* Statistics */
381	u32 num_stats;
382	u32 num_ethtool_stats;
383	const char * const *stats_layout;
384	u64 *stats;
385	/* Workqueue for reading stats */
386	struct mutex queue_stats_lock;
387	struct delayed_work stats_work;
388	struct workqueue_struct *stats_queue;
389	/* Notifiers */
390	struct notifier_block netdevice_nb;
391	struct notifier_block switchdev_nb;
392	struct notifier_block switchdev_blocking_nb;
393	/* Switch state */
394	u8 base_mac[ETH_ALEN];
395	/* Associated bridge device (when bridged) */
396	struct net_device *hw_bridge_dev;
397	/* Bridged interfaces */
398	DECLARE_BITMAP(bridge_mask, SPX5_PORTS);
399	DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS);
400	DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS);
401	DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS);
402	/* SW MAC table */
403	struct list_head mact_entries;
404	/* mac table list (mact_entries) mutex */
405	struct mutex mact_lock;
406	/* SW MDB table */
407	struct list_head mdb_entries;
408	/* mdb list mutex */
409	struct mutex mdb_lock;
410	struct delayed_work mact_work;
411	struct workqueue_struct *mact_queue;
412	/* Board specifics */
413	bool sd_sgpio_remapping;
414	/* Register based inj/xtr */
415	int xtr_irq;
416	/* Frame DMA */
417	int fdma_irq;
418	spinlock_t tx_lock; /* lock for frame transmission */
419	struct sparx5_rx rx;
420	struct sparx5_tx tx;
421	/* PTP */
422	bool ptp;
423	struct sparx5_phc phc[SPARX5_PHC_COUNT];
424	spinlock_t ptp_clock_lock; /* lock for phc */
425	spinlock_t ptp_ts_id_lock; /* lock for ts_id */
426	struct mutex ptp_lock; /* lock for ptp interface state */
427	u16 ptp_skbs;
428	int ptp_irq;
429	/* VCAP */
430	struct vcap_control *vcap_ctrl;
431	/* PGID allocation map */
432	u8 pgid_map[PGID_TABLE_SIZE];
433	struct list_head mall_entries;
434	/* Common root for debugfs */
435	struct dentry *debugfs_root;
436	const struct sparx5_match_data *data;
437};
438
439/* sparx5_main.c */
440bool is_sparx5(struct sparx5 *sparx5);
441bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature);
442
443/* sparx5_switchdev.c */
444int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
445void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
446
447/* sparx5_packet.c */
448struct frame_info {
449	int src_port;
450	u32 timestamp;
451};
452
453void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
454void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info);
455irqreturn_t sparx5_xtr_handler(int irq, void *_priv);
456netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev);
457int sparx5_manual_injection_mode(struct sparx5 *sparx5);
458void sparx5_port_inj_timer_setup(struct sparx5_port *port);
459
460/* sparx5_fdma.c */
461int sparx5_fdma_init(struct sparx5 *sparx5);
462int sparx5_fdma_deinit(struct sparx5 *sparx5);
463int sparx5_fdma_start(struct sparx5 *sparx5);
464int sparx5_fdma_stop(struct sparx5 *sparx5);
465int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight);
466int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb,
467		     struct net_device *dev);
468irqreturn_t sparx5_fdma_handler(int irq, void *args);
469void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma);
470void sparx5_fdma_injection_mode(struct sparx5 *sparx5);
471
472/* sparx5_mactable.c */
473void sparx5_mact_pull_work(struct work_struct *work);
474int sparx5_mact_learn(struct sparx5 *sparx5, int port,
475		      const unsigned char mac[ETH_ALEN], u16 vid);
476bool sparx5_mact_getnext(struct sparx5 *sparx5,
477			 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2);
478int sparx5_mact_find(struct sparx5 *sparx5,
479		     const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2);
480int sparx5_mact_forget(struct sparx5 *sparx5,
481		       const unsigned char mac[ETH_ALEN], u16 vid);
482int sparx5_add_mact_entry(struct sparx5 *sparx5,
483			  struct net_device *dev,
484			  u16 portno,
485			  const unsigned char *addr, u16 vid);
486int sparx5_del_mact_entry(struct sparx5 *sparx5,
487			  const unsigned char *addr,
488			  u16 vid);
489int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr);
490int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr);
491void sparx5_set_ageing(struct sparx5 *sparx5, int msecs);
492void sparx5_mact_init(struct sparx5 *sparx5);
493
494/* sparx5_vlan.c */
495void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable);
496void sparx5_pgid_clear(struct sparx5 *spx5, int pgid);
497void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]);
498void sparx5_update_fwd(struct sparx5 *sparx5);
499void sparx5_vlan_init(struct sparx5 *sparx5);
500void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno);
501int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid,
502			bool untagged);
503int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid);
504void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port);
505
506/* sparx5_calendar.c */
507int sparx5_config_auto_calendar(struct sparx5 *sparx5);
508int sparx5_config_dsm_calendar(struct sparx5 *sparx5);
509int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
510			     struct sparx5_calendar_data *data);
511u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed);
512enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno);
513
514
515/* sparx5_ethtool.c */
516void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
517int sparx_stats_init(struct sparx5 *sparx5);
518
519/* sparx5_dcb.c */
520#ifdef CONFIG_SPARX5_DCB
521int sparx5_dcb_init(struct sparx5 *sparx5);
522#else
523static inline int sparx5_dcb_init(struct sparx5 *sparx5)
524{
525	return 0;
526}
527#endif
528
529/* sparx5_netdev.c */
530void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr,
531				   u64 timestamp);
532void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op);
533void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr,
534				  u32 pdu_type);
535void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr,
536					u32 pdu_w16_offset);
537void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno);
538bool sparx5_netdevice_check(const struct net_device *dev);
539struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
540int sparx5_register_netdevs(struct sparx5 *sparx5);
541void sparx5_destroy_netdevs(struct sparx5 *sparx5);
542void sparx5_unregister_netdevs(struct sparx5 *sparx5);
543
544/* sparx5_ptp.c */
545int sparx5_ptp_init(struct sparx5 *sparx5);
546void sparx5_ptp_deinit(struct sparx5 *sparx5);
547int sparx5_ptp_hwtstamp_set(struct sparx5_port *port,
548			    struct kernel_hwtstamp_config *cfg,
549			    struct netlink_ext_ack *extack);
550void sparx5_ptp_hwtstamp_get(struct sparx5_port *port,
551			     struct kernel_hwtstamp_config *cfg);
552void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb,
553			 u64 timestamp);
554int sparx5_ptp_txtstamp_request(struct sparx5_port *port,
555				struct sk_buff *skb);
556void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
557				 struct sk_buff *skb);
558irqreturn_t sparx5_ptp_irq_handler(int irq, void *args);
559int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
560void sparx5_get_hwtimestamp(struct sparx5 *sparx5,
561			    struct timespec64 *ts,
562			    u32 nsec);
563
564/* sparx5_vcap_impl.c */
565int sparx5_vcap_init(struct sparx5 *sparx5);
566void sparx5_vcap_destroy(struct sparx5 *sparx5);
567
568/* sparx5_pgid.c */
569enum sparx5_pgid_type {
570	SPX5_PGID_FREE,
571	SPX5_PGID_RESERVED,
572	SPX5_PGID_MULTICAST,
573};
574
575void sparx5_pgid_init(struct sparx5 *spx5);
576int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx);
577int sparx5_pgid_free(struct sparx5 *spx5, u16 idx);
578int sparx5_get_pgid(struct sparx5 *sparx5, int pgid);
579
580/* sparx5_pool.c */
581struct sparx5_pool_entry {
582	u16 ref_cnt;
583	u32 idx; /* tc index */
584};
585
586u32 sparx5_pool_idx_to_id(u32 idx);
587int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id);
588int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id);
589int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx,
590			     u32 *id);
591
592/* sparx5_port.c */
593int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port,
594			struct sparx5_port_config *conf);
595int sparx5_get_internal_port(struct sparx5 *sparx5, int port);
596
597/* sparx5_sdlb.c */
598#define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF
599#define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1)
600#define SPX5_SDLB_GROUP_RATE_MAX 25000000000ULL
601#define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET 13
602#define SPX5_SDLB_CNT 4096
603#define SPX5_SDLB_GROUP_CNT 10
604#define SPX5_CLK_PER_100PS_DEFAULT 16
605
606struct sparx5_sdlb_group {
607	u64 max_rate;
608	u32 min_burst;
609	u32 frame_size;
610	u32 pup_interval;
611	u32 nsets;
612};
613
614extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT];
615struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx);
616int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval,
617			      u64 rate);
618
619u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5);
620int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst);
621int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group);
622
623int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx);
624int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx);
625
626void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst,
627			    u32 frame_size, u32 idx);
628
629/* sparx5_police.c */
630enum {
631	/* More policer types will be added later */
632	SPX5_POL_SERVICE
633};
634
635struct sparx5_policer {
636	u32 type;
637	u32 idx;
638	u64 rate;
639	u32 burst;
640	u32 group;
641	u8 event_mask;
642};
643
644int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol);
645
646/* sparx5_psfp.c */
647#define SPX5_PSFP_GCE_CNT 4
648#define SPX5_PSFP_SG_CNT 1024
649#define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS (1 * NSEC_PER_USEC)
650#define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS ((1 * NSEC_PER_SEC) - 1)
651#define SPX5_PSFP_SG_MAX_IPV (SPX5_PRIOS - 1)
652#define SPX5_PSFP_SG_OPEN (SPX5_PSFP_SG_CNT - 1)
653#define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT 1000000
654#define SPX5_PSFP_SF_MAX_SDU 16383
655
656struct sparx5_psfp_fm {
657	struct sparx5_policer pol;
658};
659
660struct sparx5_psfp_gce {
661	bool gate_state;            /* StreamGateState */
662	u32 interval;               /* TimeInterval */
663	u32 ipv;                    /* InternalPriorityValue */
664	u32 maxoctets;              /* IntervalOctetMax */
665};
666
667struct sparx5_psfp_sg {
668	bool gate_state;            /* PSFPAdminGateStates */
669	bool gate_enabled;          /* PSFPGateEnabled */
670	u32 ipv;                    /* PSFPAdminIPV */
671	struct timespec64 basetime; /* PSFPAdminBaseTime */
672	u32 cycletime;              /* PSFPAdminCycleTime */
673	u32 cycletimeext;           /* PSFPAdminCycleTimeExtension */
674	u32 num_entries;            /* PSFPAdminControlListLength */
675	struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT];
676};
677
678struct sparx5_psfp_sf {
679	bool sblock_osize_ena;
680	bool sblock_osize;
681	u32 max_sdu;
682	u32 sgid; /* Gate id */
683	u32 fmid; /* Flow meter id */
684};
685
686int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx,
687		       struct sparx5_psfp_fm *fm, u32 *id);
688int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id);
689
690int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx,
691		       struct sparx5_psfp_sg *sg, u32 *id);
692int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id);
693
694int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf,
695		       u32 *id);
696int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id);
697
698u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx);
699u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx);
700u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid);
701void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid);
702
703void sparx5_psfp_init(struct sparx5 *sparx5);
704
705/* sparx5_qos.c */
706void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time,
707			  const ktime_t org_base_time, ktime_t *new_base_time);
708
709/* sparx5_mirror.c */
710int sparx5_mirror_add(struct sparx5_mall_entry *entry);
711void sparx5_mirror_del(struct sparx5_mall_entry *entry);
712void sparx5_mirror_stats(struct sparx5_mall_entry *entry,
713			 struct flow_stats *fstats);
714
715/* Clock period in picoseconds */
716static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
717{
718	switch (cclock) {
719	case SPX5_CORE_CLOCK_250MHZ:
720		return 4000;
721	case SPX5_CORE_CLOCK_328MHZ:
722		return 3048;
723	case SPX5_CORE_CLOCK_500MHZ:
724		return 2000;
725	case SPX5_CORE_CLOCK_625MHZ:
726	default:
727		return 1600;
728	}
729}
730
731static inline bool sparx5_is_baser(phy_interface_t interface)
732{
733	return interface == PHY_INTERFACE_MODE_5GBASER ||
734		   interface == PHY_INTERFACE_MODE_10GBASER ||
735		   interface == PHY_INTERFACE_MODE_25GBASER;
736}
737
738extern const struct phylink_mac_ops sparx5_phylink_mac_ops;
739extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops;
740extern const struct ethtool_ops sparx5_ethtool_ops;
741extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops;
742
743/* Calculate raw offset */
744static inline __pure int spx5_offset(int id, int tinst, int tcnt,
745				     int gbase, int ginst,
746				     int gcnt, int gwidth,
747				     int raddr, int rinst,
748				     int rcnt, int rwidth)
749{
750	WARN_ON((tinst) >= tcnt);
751	WARN_ON((ginst) >= gcnt);
752	WARN_ON((rinst) >= rcnt);
753	return gbase + ((ginst) * gwidth) +
754		raddr + ((rinst) * rwidth);
755}
756
757/* Read, Write and modify registers content.
758 * The register definition macros start at the id
759 */
760static inline void __iomem *spx5_addr(void __iomem *base[],
761				      int id, int tinst, int tcnt,
762				      int gbase, int ginst,
763				      int gcnt, int gwidth,
764				      int raddr, int rinst,
765				      int rcnt, int rwidth)
766{
767	WARN_ON((tinst) >= tcnt);
768	WARN_ON((ginst) >= gcnt);
769	WARN_ON((rinst) >= rcnt);
770	return base[id + (tinst)] +
771		gbase + ((ginst) * gwidth) +
772		raddr + ((rinst) * rwidth);
773}
774
775static inline void __iomem *spx5_inst_addr(void __iomem *base,
776					   int gbase, int ginst,
777					   int gcnt, int gwidth,
778					   int raddr, int rinst,
779					   int rcnt, int rwidth)
780{
781	WARN_ON((ginst) >= gcnt);
782	WARN_ON((rinst) >= rcnt);
783	return base +
784		gbase + ((ginst) * gwidth) +
785		raddr + ((rinst) * rwidth);
786}
787
788static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt,
789			  int gbase, int ginst, int gcnt, int gwidth,
790			  int raddr, int rinst, int rcnt, int rwidth)
791{
792	return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
793			       gcnt, gwidth, raddr, rinst, rcnt, rwidth));
794}
795
796static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt,
797			       int gbase, int ginst, int gcnt, int gwidth,
798			       int raddr, int rinst, int rcnt, int rwidth)
799{
800	return readl(spx5_inst_addr(iomem, gbase, ginst,
801				     gcnt, gwidth, raddr, rinst, rcnt, rwidth));
802}
803
804static inline void spx5_wr(u32 val, struct sparx5 *sparx5,
805			   int id, int tinst, int tcnt,
806			   int gbase, int ginst, int gcnt, int gwidth,
807			   int raddr, int rinst, int rcnt, int rwidth)
808{
809	writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt,
810			      gbase, ginst, gcnt, gwidth,
811			      raddr, rinst, rcnt, rwidth));
812}
813
814static inline void spx5_inst_wr(u32 val, void __iomem *iomem,
815				int id, int tinst, int tcnt,
816				int gbase, int ginst, int gcnt, int gwidth,
817				int raddr, int rinst, int rcnt, int rwidth)
818{
819	writel(val, spx5_inst_addr(iomem,
820				   gbase, ginst, gcnt, gwidth,
821				   raddr, rinst, rcnt, rwidth));
822}
823
824static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5,
825			    int id, int tinst, int tcnt,
826			    int gbase, int ginst, int gcnt, int gwidth,
827			    int raddr, int rinst, int rcnt, int rwidth)
828{
829	u32 nval;
830
831	nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
832			       gcnt, gwidth, raddr, rinst, rcnt, rwidth));
833	nval = (nval & ~mask) | (val & mask);
834	writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
835			       gcnt, gwidth, raddr, rinst, rcnt, rwidth));
836}
837
838static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
839				 int id, int tinst, int tcnt,
840				 int gbase, int ginst, int gcnt, int gwidth,
841				 int raddr, int rinst, int rcnt, int rwidth)
842{
843	u32 nval;
844
845	nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
846				    rinst, rcnt, rwidth));
847	nval = (nval & ~mask) | (val & mask);
848	writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
849				    rinst, rcnt, rwidth));
850}
851
852static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst)
853{
854	return sparx5->regs[id + tinst];
855}
856
857static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5,
858					 int id, int tinst, int tcnt,
859					 int gbase, int ginst, int gcnt, int gwidth,
860					 int raddr, int rinst, int rcnt, int rwidth)
861{
862	return spx5_addr(sparx5->regs, id, tinst, tcnt,
863			 gbase, ginst, gcnt, gwidth,
864			 raddr, rinst, rcnt, rwidth);
865}
866
867#endif	/* __SPARX5_MAIN_H__ */