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sparx5_main.c
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linux-6.19.14/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 * 6 * The Sparx5 Chip Register Model can be browsed at this location: 7 * https://github.com/microchip-ung/sparx-5_reginfo 8 */ 9#include <linux/module.h> 10#include <linux/device.h> 11#include <linux/netdevice.h> 12#include <linux/platform_device.h> 13#include <linux/interrupt.h> 14#include <linux/of.h> 15#include <linux/of_net.h> 16#include <linux/of_mdio.h> 17#include <net/switchdev.h> 18#include <linux/etherdevice.h> 19#include <linux/io.h> 20#include <linux/printk.h> 21#include <linux/iopoll.h> 22#include <linux/mfd/syscon.h> 23#include <linux/regmap.h> 24#include <linux/types.h> 25#include <linux/reset.h> 26 27#include "lan969x/lan969x.h" /* for lan969x match data */ 28 29#include "sparx5_main_regs.h" 30#include "sparx5_main.h" 31#include "sparx5_port.h" 32#include "sparx5_qos.h" 33#include "sparx5_vcap_ag_api.h" 34#include "sparx5_vcap_impl.h" 35 36const struct sparx5_regs *regs; 37 38#define IO_RANGES 3 39 40struct initial_port_config { 41 u32 portno; 42 struct device_node *node; 43 struct sparx5_port_config conf; 44 struct phy *serdes; 45}; 46 47struct sparx5_ram_config { 48 void __iomem *init_reg; 49 u32 init_val; 50}; 51 52static const struct sparx5_main_io_resource sparx5_main_iomap[] = { 53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ 63 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */ 64 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */ 65 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */ 66 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */ 67 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */ 68 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */ 69 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */ 70 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */ 71 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */ 72 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */ 73 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */ 74 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */ 75 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */ 76 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */ 77 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */ 78 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */ 79 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */ 80 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */ 81 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */ 82 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */ 83 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */ 84 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */ 85 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */ 86 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */ 87 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */ 88 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */ 89 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */ 90 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */ 91 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */ 92 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */ 93 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */ 94 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */ 95 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */ 96 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */ 97 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */ 98 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */ 99 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */ 100 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */ 101 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */ 102 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */ 103 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */ 104 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */ 105 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */ 106 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */ 107 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */ 108 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */ 109 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */ 110 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */ 111 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */ 112 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */ 113 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */ 114 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */ 115 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */ 116 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */ 117 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */ 118 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */ 119 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */ 120 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */ 121 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */ 122 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */ 123 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */ 124 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */ 125 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */ 126 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */ 127 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */ 128 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */ 129 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */ 130 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */ 131 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */ 132 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */ 133 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */ 134 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */ 135 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */ 136 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */ 137 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */ 138 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */ 139 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */ 140 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */ 141 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */ 142 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */ 143 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */ 144 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */ 145 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */ 146 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */ 147 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */ 148 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */ 149 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */ 150 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */ 151 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */ 152 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */ 153 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */ 154 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */ 155 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */ 156 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */ 157 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */ 158 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */ 159 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */ 160 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */ 161 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */ 162 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */ 163 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */ 164 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */ 165 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */ 166 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */ 167 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */ 168 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */ 169 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */ 170 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */ 171 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */ 172 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */ 173 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */ 174 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */ 175 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */ 176 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */ 177 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */ 178 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */ 179 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */ 180 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */ 181 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */ 182 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */ 183 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */ 184 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */ 185 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */ 186 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */ 187 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */ 188 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */ 189 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */ 190 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */ 191 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */ 192 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */ 193 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */ 194 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */ 195 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */ 196 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */ 197 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */ 198 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */ 199 { TARGET_VCAP_ES2, 0x110d0000, 2 }, /* 0x6110d0000 */ 200 { TARGET_VCAP_ES0, 0x110e0000, 2 }, /* 0x6110e0000 */ 201 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */ 202 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */ 203 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */ 204 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */ 205 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */ 206 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */ 207 { TARGET_ANA_AC_SDLB, 0x11500000, 2 }, /* 0x611500000 */ 208 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */ 209 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */ 210 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */ 211 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */ 212 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ 213}; 214 215bool is_sparx5(struct sparx5 *sparx5) 216{ 217 switch (sparx5->target_ct) { 218 case SPX5_TARGET_CT_7546: 219 case SPX5_TARGET_CT_7549: 220 case SPX5_TARGET_CT_7552: 221 case SPX5_TARGET_CT_7556: 222 case SPX5_TARGET_CT_7558: 223 case SPX5_TARGET_CT_7546TSN: 224 case SPX5_TARGET_CT_7549TSN: 225 case SPX5_TARGET_CT_7552TSN: 226 case SPX5_TARGET_CT_7556TSN: 227 case SPX5_TARGET_CT_7558TSN: 228 return true; 229 default: 230 return false; 231 } 232} 233 234static void sparx5_init_features(struct sparx5 *sparx5) 235{ 236 switch (sparx5->target_ct) { 237 case SPX5_TARGET_CT_7546: 238 case SPX5_TARGET_CT_7549: 239 case SPX5_TARGET_CT_7552: 240 case SPX5_TARGET_CT_7556: 241 case SPX5_TARGET_CT_7558: 242 case SPX5_TARGET_CT_7546TSN: 243 case SPX5_TARGET_CT_7549TSN: 244 case SPX5_TARGET_CT_7552TSN: 245 case SPX5_TARGET_CT_7556TSN: 246 case SPX5_TARGET_CT_7558TSN: 247 case SPX5_TARGET_CT_LAN9691VAO: 248 case SPX5_TARGET_CT_LAN9694TSN: 249 case SPX5_TARGET_CT_LAN9694RED: 250 case SPX5_TARGET_CT_LAN9692VAO: 251 case SPX5_TARGET_CT_LAN9696TSN: 252 case SPX5_TARGET_CT_LAN9696RED: 253 case SPX5_TARGET_CT_LAN9693VAO: 254 case SPX5_TARGET_CT_LAN9698TSN: 255 case SPX5_TARGET_CT_LAN9698RED: 256 sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); 257 break; 258 default: 259 break; 260 } 261} 262 263bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) 264{ 265 return sparx5->features & feature; 266} 267 268static int sparx5_create_targets(struct sparx5 *sparx5) 269{ 270 const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; 271 int iomap_size = sparx5->data->iomap_size; 272 int ioranges = sparx5->data->ioranges; 273 struct resource *iores[IO_RANGES]; 274 void __iomem *iomem[IO_RANGES]; 275 void __iomem *begin[IO_RANGES]; 276 int range_id[IO_RANGES]; 277 int idx, jdx; 278 279 for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) { 280 const struct sparx5_main_io_resource *io = &iomap[jdx]; 281 282 if (idx == io->range) { 283 range_id[idx] = jdx; 284 idx++; 285 } 286 } 287 for (idx = 0; idx < ioranges; idx++) { 288 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, 289 idx); 290 if (!iores[idx]) { 291 dev_err(sparx5->dev, "Invalid resource\n"); 292 return -EINVAL; 293 } 294 iomem[idx] = devm_ioremap(sparx5->dev, 295 iores[idx]->start, 296 resource_size(iores[idx])); 297 if (!iomem[idx]) { 298 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", 299 iores[idx]->name); 300 return -ENOMEM; 301 } 302 begin[idx] = iomem[idx] - iomap[range_id[idx]].offset; 303 } 304 for (jdx = 0; jdx < iomap_size; jdx++) { 305 const struct sparx5_main_io_resource *io = &iomap[jdx]; 306 307 sparx5->regs[io->id] = begin[io->range] + io->offset; 308 } 309 return 0; 310} 311 312static int sparx5_create_port(struct sparx5 *sparx5, 313 struct initial_port_config *config) 314{ 315 struct sparx5_port *spx5_port; 316 const struct sparx5_ops *ops; 317 struct net_device *ndev; 318 struct phylink *phylink; 319 int err; 320 321 ops = sparx5->data->ops; 322 323 ndev = sparx5_create_netdev(sparx5, config->portno); 324 if (IS_ERR(ndev)) { 325 dev_err(sparx5->dev, "Could not create net device: %02u\n", 326 config->portno); 327 return PTR_ERR(ndev); 328 } 329 spx5_port = netdev_priv(ndev); 330 spx5_port->of_node = config->node; 331 spx5_port->serdes = config->serdes; 332 spx5_port->pvid = NULL_VID; 333 spx5_port->signd_internal = true; 334 spx5_port->signd_active_high = true; 335 spx5_port->signd_enable = true; 336 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; 337 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; 338 spx5_port->custom_etype = 0x8880; /* Vitesse */ 339 spx5_port->phylink_pcs.poll = true; 340 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; 341 spx5_port->is_mrouter = false; 342 INIT_LIST_HEAD(&spx5_port->tc_templates); 343 sparx5->ports[config->portno] = spx5_port; 344 345 err = sparx5_port_init(sparx5, spx5_port, &config->conf); 346 if (err) { 347 dev_err(sparx5->dev, "port init failed\n"); 348 return err; 349 } 350 spx5_port->conf = config->conf; 351 352 /* Setup VLAN */ 353 sparx5_vlan_port_setup(sparx5, spx5_port->portno); 354 355 /* Create a phylink for PHY management. Also handles SFPs */ 356 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; 357 spx5_port->phylink_config.type = PHYLINK_NETDEV; 358 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 359 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | 360 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; 361 362 if (ops->is_port_rgmii(spx5_port->portno)) 363 phy_interface_set_rgmii(spx5_port->phylink_config.supported_interfaces); 364 365 __set_bit(PHY_INTERFACE_MODE_SGMII, 366 spx5_port->phylink_config.supported_interfaces); 367 __set_bit(PHY_INTERFACE_MODE_QSGMII, 368 spx5_port->phylink_config.supported_interfaces); 369 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 370 spx5_port->phylink_config.supported_interfaces); 371 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 372 spx5_port->phylink_config.supported_interfaces); 373 374 if (spx5_port->conf.bandwidth == SPEED_5000 || 375 spx5_port->conf.bandwidth == SPEED_10000 || 376 spx5_port->conf.bandwidth == SPEED_25000) 377 __set_bit(PHY_INTERFACE_MODE_5GBASER, 378 spx5_port->phylink_config.supported_interfaces); 379 380 if (spx5_port->conf.bandwidth == SPEED_10000 || 381 spx5_port->conf.bandwidth == SPEED_25000) 382 __set_bit(PHY_INTERFACE_MODE_10GBASER, 383 spx5_port->phylink_config.supported_interfaces); 384 385 if (spx5_port->conf.bandwidth == SPEED_25000) 386 __set_bit(PHY_INTERFACE_MODE_25GBASER, 387 spx5_port->phylink_config.supported_interfaces); 388 389 phylink = phylink_create(&spx5_port->phylink_config, 390 of_fwnode_handle(config->node), 391 config->conf.phy_mode, 392 &sparx5_phylink_mac_ops); 393 if (IS_ERR(phylink)) 394 return PTR_ERR(phylink); 395 396 spx5_port->phylink = phylink; 397 398 spx5_port->ndev->dev.of_node = spx5_port->of_node; 399 400 return 0; 401} 402 403static int sparx5_init_ram(struct sparx5 *s5) 404{ 405 const struct sparx5_ram_config spx5_ram_cfg[] = { 406 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET}, 407 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT}, 408 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 409 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 410 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 411 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 412 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 413 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 414 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 415 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT} 416 }; 417 const struct sparx5_ram_config *cfg; 418 u32 value, pending, jdx, idx; 419 420 for (jdx = 0; jdx < 10; jdx++) { 421 pending = ARRAY_SIZE(spx5_ram_cfg); 422 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { 423 cfg = &spx5_ram_cfg[idx]; 424 if (jdx == 0) { 425 writel(cfg->init_val, cfg->init_reg); 426 } else { 427 value = readl(cfg->init_reg); 428 if ((value & cfg->init_val) != cfg->init_val) 429 pending--; 430 } 431 } 432 if (!pending) 433 break; 434 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 435 } 436 437 if (pending > 0) { 438 /* Still initializing, should be complete in 439 * less than 1ms 440 */ 441 dev_err(s5->dev, "Memory initialization error\n"); 442 return -EINVAL; 443 } 444 return 0; 445} 446 447static int sparx5_init_switchcore(struct sparx5 *sparx5) 448{ 449 u32 value; 450 int err = 0; 451 452 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), 453 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 454 sparx5, 455 EACL_POL_EACL_CFG); 456 457 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), 458 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 459 sparx5, 460 EACL_POL_EACL_CFG); 461 462 /* Initialize memories, if not done already */ 463 value = spx5_rd(sparx5, HSCH_RESET_CFG); 464 if (!(value & HSCH_RESET_CFG_CORE_ENA)) { 465 err = sparx5_init_ram(sparx5); 466 if (err) 467 return err; 468 } 469 470 /* Reset counters */ 471 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); 472 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); 473 474 /* Enable switch-core and queue system */ 475 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); 476 477 return 0; 478} 479 480static int sparx5_init_coreclock(struct sparx5 *sparx5) 481{ 482 enum sparx5_core_clockfreq freq = sparx5->coreclock; 483 u32 clk_div, clk_period, pol_upd_int, idx; 484 485 /* Verify if core clock frequency is supported on target. 486 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported 487 * freq. is used 488 */ 489 switch (sparx5->target_ct) { 490 case SPX5_TARGET_CT_7546: 491 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 492 freq = SPX5_CORE_CLOCK_250MHZ; 493 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) 494 freq = 0; /* Not supported */ 495 break; 496 case SPX5_TARGET_CT_7549: 497 case SPX5_TARGET_CT_7552: 498 case SPX5_TARGET_CT_7556: 499 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 500 freq = SPX5_CORE_CLOCK_500MHZ; 501 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) 502 freq = 0; /* Not supported */ 503 break; 504 case SPX5_TARGET_CT_7558: 505 case SPX5_TARGET_CT_7558TSN: 506 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 507 freq = SPX5_CORE_CLOCK_625MHZ; 508 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) 509 freq = 0; /* Not supported */ 510 break; 511 case SPX5_TARGET_CT_7546TSN: 512 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 513 freq = SPX5_CORE_CLOCK_625MHZ; 514 break; 515 case SPX5_TARGET_CT_7549TSN: 516 case SPX5_TARGET_CT_7552TSN: 517 case SPX5_TARGET_CT_7556TSN: 518 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 519 freq = SPX5_CORE_CLOCK_625MHZ; 520 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) 521 freq = 0; /* Not supported */ 522 break; 523 case SPX5_TARGET_CT_LAN9694: 524 case SPX5_TARGET_CT_LAN9691VAO: 525 case SPX5_TARGET_CT_LAN9694TSN: 526 case SPX5_TARGET_CT_LAN9694RED: 527 case SPX5_TARGET_CT_LAN9696: 528 case SPX5_TARGET_CT_LAN9692VAO: 529 case SPX5_TARGET_CT_LAN9696TSN: 530 case SPX5_TARGET_CT_LAN9696RED: 531 case SPX5_TARGET_CT_LAN9698: 532 case SPX5_TARGET_CT_LAN9693VAO: 533 case SPX5_TARGET_CT_LAN9698TSN: 534 case SPX5_TARGET_CT_LAN9698RED: 535 freq = SPX5_CORE_CLOCK_328MHZ; 536 break; 537 default: 538 dev_err(sparx5->dev, "Target (%#04x) not supported\n", 539 sparx5->target_ct); 540 return -ENODEV; 541 } 542 543 if (is_sparx5(sparx5)) { 544 switch (freq) { 545 case SPX5_CORE_CLOCK_250MHZ: 546 clk_div = 10; 547 pol_upd_int = 312; 548 break; 549 case SPX5_CORE_CLOCK_500MHZ: 550 clk_div = 5; 551 pol_upd_int = 624; 552 break; 553 case SPX5_CORE_CLOCK_625MHZ: 554 clk_div = 4; 555 pol_upd_int = 780; 556 break; 557 default: 558 dev_err(sparx5->dev, 559 "%d coreclock not supported on (%#04x)\n", 560 sparx5->coreclock, sparx5->target_ct); 561 return -EINVAL; 562 } 563 564 /* Configure the LCPLL */ 565 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 566 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 567 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 568 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 569 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 570 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 571 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 572 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 573 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 574 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 575 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 576 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 577 sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); 578 } else { 579 pol_upd_int = 820; // SPX5_CORE_CLOCK_328MHZ 580 } 581 582 /* Update state with chosen frequency */ 583 sparx5->coreclock = freq; 584 clk_period = sparx5_clk_period(freq); 585 586 if (is_sparx5(sparx5)) 587 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), 588 HSCH_SYS_CLK_PER_100PS, 589 sparx5, 590 HSCH_SYS_CLK_PER); 591 592 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 593 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, 594 sparx5, 595 ANA_AC_POL_BDLB_DLB_CTRL); 596 597 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 598 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, 599 sparx5, 600 ANA_AC_POL_SLB_DLB_CTRL); 601 602 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), 603 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, 604 sparx5, 605 LRN_AUTOAGE_CFG_1); 606 607 for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) 608 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), 609 GCB_SIO_CLOCK_SYS_CLK_PERIOD, 610 sparx5, 611 GCB_SIO_CLOCK(idx)); 612 613 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET 614 ((256 * 1000) / clk_period), 615 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, 616 sparx5, 617 HSCH_TAS_STATEMACHINE_CFG); 618 619 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), 620 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, 621 sparx5, 622 ANA_AC_POL_POL_UPD_INT_CFG); 623 624 return 0; 625} 626 627static u32 qlim_wm(struct sparx5 *sparx5, int fraction) 628{ 629 return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) * 630 fraction / 100; 631} 632 633static int sparx5_qlim_set(struct sparx5 *sparx5) 634{ 635 const struct sparx5_consts *consts = sparx5->data->consts; 636 u32 res, dp, prio; 637 638 for (res = 0; res < 2; res++) { 639 for (prio = 0; prio < 8; prio++) 640 spx5_wr(0xFFF, sparx5, 641 QRES_RES_CFG(prio + 642 consts->qres_max_prio_idx + 643 res * 1024)); 644 645 for (dp = 0; dp < 4; dp++) 646 spx5_wr(0xFFF, sparx5, 647 QRES_RES_CFG(dp + 648 consts->qres_max_colour_idx + 649 res * 1024)); 650 } 651 652 /* Set 80,90,95,100% of memory size for top watermarks */ 653 spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 654 spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 655 spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 656 spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 657 658 return 0; 659} 660 661/* Some boards needs to map the SGPIO for signal detect explicitly to the 662 * port module 663 */ 664static void sparx5_board_init(struct sparx5 *sparx5) 665{ 666 int idx; 667 668 if (!sparx5->sd_sgpio_remapping) 669 return; 670 671 /* Enable SGPIO Signal Detect remapping */ 672 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 673 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 674 sparx5, 675 GCB_HW_SGPIO_SD_CFG); 676 677 /* Refer to LOS SGPIO */ 678 for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) 679 if (sparx5->ports[idx]) 680 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) 681 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, 682 sparx5, 683 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx)); 684} 685 686static int sparx5_start(struct sparx5 *sparx5) 687{ 688 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 689 const struct sparx5_consts *consts = sparx5->data->consts; 690 const struct sparx5_ops *ops = sparx5->data->ops; 691 char queue_name[32]; 692 u32 idx; 693 int err; 694 695 /* Setup own UPSIDs */ 696 for (idx = 0; idx < consts->n_own_upsids; idx++) { 697 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); 698 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); 699 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); 700 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); 701 } 702 703 /* Enable CPU ports */ 704 for (idx = consts->n_ports; idx < consts->n_ports_all; idx++) 705 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), 706 QFWD_SWITCH_PORT_MODE_PORT_ENA, 707 sparx5, 708 QFWD_SWITCH_PORT_MODE(idx)); 709 710 /* Init masks */ 711 sparx5_update_fwd(sparx5); 712 713 /* Init flood masks */ 714 for (int pgid = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); 715 pgid <= sparx5_get_pgid(sparx5, PGID_BCAST); pgid++) 716 sparx5_pgid_clear(sparx5, pgid); 717 718 /* CPU copy CPU pgids */ 719 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, 720 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); 721 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, 722 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST))); 723 724 /* Recalc injected frame FCS */ 725 for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); 726 idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++) 727 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), 728 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, 729 sparx5, ANA_CL_FILTER_CTRL(idx)); 730 731 /* Init MAC table, ageing */ 732 sparx5_mact_init(sparx5); 733 734 /* Init PGID table arbitrator */ 735 sparx5_pgid_init(sparx5); 736 737 /* Setup VLANs */ 738 sparx5_vlan_init(sparx5); 739 740 /* Add host mode BC address (points only to CPU) */ 741 sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast, 742 NULL_VID); 743 744 /* Enable queue limitation watermarks */ 745 sparx5_qlim_set(sparx5); 746 747 err = sparx5_config_auto_calendar(sparx5); 748 if (err) 749 return err; 750 751 err = sparx5_config_dsm_calendar(sparx5); 752 if (err) 753 return err; 754 755 /* Init stats */ 756 err = sparx_stats_init(sparx5); 757 if (err) 758 return err; 759 760 /* Init mact_sw struct */ 761 mutex_init(&sparx5->mact_lock); 762 INIT_LIST_HEAD(&sparx5->mact_entries); 763 snprintf(queue_name, sizeof(queue_name), "%s-mact", 764 dev_name(sparx5->dev)); 765 sparx5->mact_queue = create_singlethread_workqueue(queue_name); 766 if (!sparx5->mact_queue) 767 return -ENOMEM; 768 769 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); 770 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, 771 SPX5_MACT_PULL_DELAY); 772 773 mutex_init(&sparx5->mdb_lock); 774 INIT_LIST_HEAD(&sparx5->mdb_entries); 775 776 err = sparx5_register_netdevs(sparx5); 777 if (err) 778 return err; 779 780 sparx5_board_init(sparx5); 781 err = sparx5_register_notifier_blocks(sparx5); 782 if (err) 783 return err; 784 785 err = sparx5_vcap_init(sparx5); 786 if (err) { 787 sparx5_unregister_notifier_blocks(sparx5); 788 return err; 789 } 790 791 /* Start Frame DMA with fallback to register based INJ/XTR */ 792 err = -ENXIO; 793 if (sparx5->fdma_irq >= 0) { 794 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0 || 795 !is_sparx5(sparx5)) 796 err = devm_request_irq(sparx5->dev, 797 sparx5->fdma_irq, 798 sparx5_fdma_handler, 799 0, 800 "sparx5-fdma", sparx5); 801 if (!err) { 802 err = ops->fdma_init(sparx5); 803 if (!err) 804 sparx5_fdma_start(sparx5); 805 } 806 if (err) 807 sparx5->fdma_irq = -ENXIO; 808 } else { 809 sparx5->fdma_irq = -ENXIO; 810 } 811 if (err && sparx5->xtr_irq >= 0) { 812 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, 813 sparx5_xtr_handler, IRQF_SHARED, 814 "sparx5-xtr", sparx5); 815 if (!err) 816 err = sparx5_manual_injection_mode(sparx5); 817 if (err) 818 sparx5->xtr_irq = -ENXIO; 819 } else { 820 sparx5->xtr_irq = -ENXIO; 821 } 822 823 if (sparx5->ptp_irq >= 0 && 824 sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) { 825 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, 826 NULL, ops->ptp_irq_handler, 827 IRQF_ONESHOT, "sparx5-ptp", 828 sparx5); 829 if (err) 830 sparx5->ptp_irq = -ENXIO; 831 832 sparx5->ptp = 1; 833 } 834 835 return err; 836} 837 838static void sparx5_cleanup_ports(struct sparx5 *sparx5) 839{ 840 sparx5_unregister_netdevs(sparx5); 841 sparx5_destroy_netdevs(sparx5); 842} 843 844static int mchp_sparx5_probe(struct platform_device *pdev) 845{ 846 struct initial_port_config *configs, *config; 847 struct device_node *np = pdev->dev.of_node; 848 struct device_node *ports, *portnp; 849 const struct sparx5_ops *ops; 850 struct reset_control *reset; 851 struct sparx5 *sparx5; 852 int idx = 0, err = 0; 853 854 if (!np && !pdev->dev.platform_data) 855 return -ENODEV; 856 857 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); 858 if (!sparx5) 859 return -ENOMEM; 860 861 platform_set_drvdata(pdev, sparx5); 862 sparx5->pdev = pdev; 863 sparx5->dev = &pdev->dev; 864 spin_lock_init(&sparx5->tx_lock); 865 866 sparx5->data = device_get_match_data(sparx5->dev); 867 if (!sparx5->data) 868 return -EINVAL; 869 870 regs = sparx5->data->regs; 871 ops = sparx5->data->ops; 872 873 /* Do switch core reset if available */ 874 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 875 if (IS_ERR(reset)) 876 return dev_err_probe(&pdev->dev, PTR_ERR(reset), 877 "Failed to get switch reset controller.\n"); 878 reset_control_reset(reset); 879 880 /* Default values, some from DT */ 881 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; 882 883 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL); 884 885 ports = of_get_child_by_name(np, "ethernet-ports"); 886 if (!ports) { 887 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); 888 return -ENODEV; 889 } 890 sparx5->port_count = of_get_child_count(ports); 891 892 configs = kcalloc(sparx5->port_count, 893 sizeof(struct initial_port_config), GFP_KERNEL); 894 if (!configs) { 895 err = -ENOMEM; 896 goto cleanup_pnode; 897 } 898 899 for_each_available_child_of_node(ports, portnp) { 900 struct sparx5_port_config *conf; 901 struct phy *serdes = NULL; 902 u32 portno; 903 904 err = of_property_read_u32(portnp, "reg", &portno); 905 if (err) { 906 dev_err(sparx5->dev, "port reg property error\n"); 907 continue; 908 } 909 config = &configs[idx]; 910 conf = &config->conf; 911 conf->speed = SPEED_UNKNOWN; 912 conf->bandwidth = SPEED_UNKNOWN; 913 err = of_get_phy_mode(portnp, &conf->phy_mode); 914 if (err) { 915 dev_err(sparx5->dev, "port %u: missing phy-mode\n", 916 portno); 917 continue; 918 } 919 err = of_property_read_u32(portnp, "microchip,bandwidth", 920 &conf->bandwidth); 921 if (err) { 922 dev_err(sparx5->dev, "port %u: missing bandwidth\n", 923 portno); 924 continue; 925 } 926 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); 927 if (err) 928 conf->sd_sgpio = ~0; 929 else 930 sparx5->sd_sgpio_remapping = true; 931 /* There is no SerDes node for RGMII ports. */ 932 if (!ops->is_port_rgmii(portno)) { 933 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); 934 if (IS_ERR(serdes)) { 935 err = dev_err_probe(sparx5->dev, 936 PTR_ERR(serdes), 937 "port %u: missing serdes\n", 938 portno); 939 of_node_put(portnp); 940 goto cleanup_config; 941 } 942 } 943 config->portno = portno; 944 config->node = portnp; 945 config->serdes = serdes; 946 947 conf->media = PHY_MEDIA_DAC; 948 conf->serdes_reset = true; 949 conf->portmode = conf->phy_mode; 950 conf->power_down = true; 951 idx++; 952 } 953 954 err = sparx5_create_targets(sparx5); 955 if (err) 956 goto cleanup_config; 957 958 if (of_get_mac_address(np, sparx5->base_mac)) { 959 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); 960 eth_random_addr(sparx5->base_mac); 961 sparx5->base_mac[5] = 0; 962 } 963 964 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); 965 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); 966 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp"); 967 968 /* Read chip ID to check CPU interface */ 969 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); 970 971 sparx5->target_ct = (enum spx5_target_chiptype) 972 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); 973 974 /* Initialize the features based on the target */ 975 sparx5_init_features(sparx5); 976 977 /* Initialize Switchcore and internal RAMs */ 978 err = sparx5_init_switchcore(sparx5); 979 if (err) { 980 dev_err(sparx5->dev, "Switchcore initialization error\n"); 981 goto cleanup_config; 982 } 983 984 /* Initialize the LC-PLL (core clock) and set affected registers */ 985 err = sparx5_init_coreclock(sparx5); 986 if (err) { 987 dev_err(sparx5->dev, "LC-PLL initialization error\n"); 988 goto cleanup_config; 989 } 990 991 for (idx = 0; idx < sparx5->port_count; ++idx) { 992 config = &configs[idx]; 993 if (!config->node) 994 continue; 995 996 err = sparx5_create_port(sparx5, config); 997 if (err) { 998 dev_err(sparx5->dev, "port create error\n"); 999 goto cleanup_ports; 1000 } 1001 } 1002 1003 err = sparx5_start(sparx5); 1004 if (err) { 1005 dev_err(sparx5->dev, "Start failed\n"); 1006 goto cleanup_ports; 1007 } 1008 1009 err = sparx5_qos_init(sparx5); 1010 if (err) { 1011 dev_err(sparx5->dev, "Failed to initialize QoS\n"); 1012 goto cleanup_ports; 1013 } 1014 1015 err = sparx5_ptp_init(sparx5); 1016 if (err) { 1017 dev_err(sparx5->dev, "PTP failed\n"); 1018 goto cleanup_ports; 1019 } 1020 1021 INIT_LIST_HEAD(&sparx5->mall_entries); 1022 1023 goto cleanup_config; 1024 1025cleanup_ports: 1026 sparx5_cleanup_ports(sparx5); 1027 if (sparx5->mact_queue) 1028 destroy_workqueue(sparx5->mact_queue); 1029cleanup_config: 1030 kfree(configs); 1031cleanup_pnode: 1032 of_node_put(ports); 1033 return err; 1034} 1035 1036static void mchp_sparx5_remove(struct platform_device *pdev) 1037{ 1038 struct sparx5 *sparx5 = platform_get_drvdata(pdev); 1039 const struct sparx5_ops *ops = sparx5->data->ops; 1040 1041 debugfs_remove_recursive(sparx5->debugfs_root); 1042 if (sparx5->xtr_irq) { 1043 disable_irq(sparx5->xtr_irq); 1044 sparx5->xtr_irq = -ENXIO; 1045 } 1046 if (sparx5->fdma_irq) { 1047 disable_irq(sparx5->fdma_irq); 1048 sparx5->fdma_irq = -ENXIO; 1049 } 1050 sparx5_ptp_deinit(sparx5); 1051 ops->fdma_deinit(sparx5); 1052 sparx5_cleanup_ports(sparx5); 1053 sparx5_vcap_destroy(sparx5); 1054 /* Unregister netdevs */ 1055 sparx5_unregister_notifier_blocks(sparx5); 1056 destroy_workqueue(sparx5->mact_queue); 1057} 1058 1059static const struct sparx5_regs sparx5_regs = { 1060 .tsize = sparx5_tsize, 1061 .gaddr = sparx5_gaddr, 1062 .gcnt = sparx5_gcnt, 1063 .gsize = sparx5_gsize, 1064 .raddr = sparx5_raddr, 1065 .rcnt = sparx5_rcnt, 1066 .fpos = sparx5_fpos, 1067 .fsize = sparx5_fsize, 1068}; 1069 1070static const struct sparx5_consts sparx5_consts = { 1071 .n_ports = 65, 1072 .n_ports_all = 70, 1073 .n_hsch_l1_elems = 64, 1074 .n_hsch_queues = 8, 1075 .n_lb_groups = 10, 1076 .n_pgids = 2113, /* (2048 + n_ports) */ 1077 .n_sio_clks = 3, 1078 .n_own_upsids = 3, 1079 .n_auto_cals = 7, 1080 .n_filters = 1024, 1081 .n_gates = 1024, 1082 .n_sdlbs = 4096, 1083 .n_dsm_cal_taxis = 8, 1084 .buf_size = 4194280, 1085 .qres_max_prio_idx = 630, 1086 .qres_max_colour_idx = 638, 1087 .tod_pin = 4, 1088 .vcaps = sparx5_vcaps, 1089 .vcaps_cfg = sparx5_vcap_inst_cfg, 1090 .vcap_stats = &sparx5_vcap_stats, 1091}; 1092 1093static const struct sparx5_ops sparx5_ops = { 1094 .is_port_2g5 = &sparx5_port_is_2g5, 1095 .is_port_5g = &sparx5_port_is_5g, 1096 .is_port_10g = &sparx5_port_is_10g, 1097 .is_port_25g = &sparx5_port_is_25g, 1098 .is_port_rgmii = &sparx5_port_is_rgmii, 1099 .get_port_dev_index = &sparx5_port_dev_mapping, 1100 .get_port_dev_bit = &sparx5_port_dev_mapping, 1101 .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, 1102 .get_sdlb_group = &sparx5_get_sdlb_group, 1103 .set_port_mux = &sparx5_port_mux_set, 1104 .ptp_irq_handler = &sparx5_ptp_irq_handler, 1105 .dsm_calendar_calc = &sparx5_dsm_calendar_calc, 1106 .fdma_init = &sparx5_fdma_init, 1107 .fdma_deinit = &sparx5_fdma_deinit, 1108 .fdma_poll = &sparx5_fdma_napi_callback, 1109 .fdma_xmit = &sparx5_fdma_xmit, 1110}; 1111 1112static const struct sparx5_match_data sparx5_desc = { 1113 .iomap = sparx5_main_iomap, 1114 .iomap_size = ARRAY_SIZE(sparx5_main_iomap), 1115 .ioranges = 3, 1116 .regs = &sparx5_regs, 1117 .consts = &sparx5_consts, 1118 .ops = &sparx5_ops, 1119}; 1120 1121static const struct of_device_id mchp_sparx5_match[] = { 1122 { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, 1123#ifdef CONFIG_LAN969X_SWITCH 1124 { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc }, 1125#endif 1126 { } 1127}; 1128MODULE_DEVICE_TABLE(of, mchp_sparx5_match); 1129 1130static struct platform_driver mchp_sparx5_driver = { 1131 .probe = mchp_sparx5_probe, 1132 .remove = mchp_sparx5_remove, 1133 .driver = { 1134 .name = "sparx5-switch", 1135 .of_match_table = mchp_sparx5_match, 1136 }, 1137}; 1138 1139module_platform_driver(mchp_sparx5_driver); 1140 1141MODULE_DESCRIPTION("Microchip Sparx5 switch driver"); 1142MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); 1143MODULE_LICENSE("Dual MIT/GPL");
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