lan969x_vcap_ag_api.c

   1// SPDX-License-Identifier: BSD-3-Clause
   2/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries.
   3 * Microchip VCAP API
   4 */
   5
   6/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200.
   7 * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391
   8 */
   9
  10#include <linux/types.h>
  11#include <linux/kernel.h>
  12
  13#include "lan969x.h"
  14
  15/* keyfields */
  16static const struct vcap_field is0_normal_7tuple_keyfield[] = {
  17	[VCAP_KF_TYPE] = {
  18		.type = VCAP_FIELD_BIT,
  19		.offset = 0,
  20		.width = 1,
  21	},
  22	[VCAP_KF_LOOKUP_FIRST_IS] = {
  23		.type = VCAP_FIELD_BIT,
  24		.offset = 1,
  25		.width = 1,
  26	},
  27	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
  28		.type = VCAP_FIELD_U32,
  29		.offset = 2,
  30		.width = 2,
  31	},
  32	[VCAP_KF_LOOKUP_GEN_IDX] = {
  33		.type = VCAP_FIELD_U32,
  34		.offset = 4,
  35		.width = 10,
  36	},
  37	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
  38		.type = VCAP_FIELD_U32,
  39		.offset = 14,
  40		.width = 2,
  41	},
  42	[VCAP_KF_IF_IGR_PORT_MASK] = {
  43		.type = VCAP_FIELD_U72,
  44		.offset = 16,
  45		.width = 65,
  46	},
  47	[VCAP_KF_L2_MC_IS] = {
  48		.type = VCAP_FIELD_BIT,
  49		.offset = 81,
  50		.width = 1,
  51	},
  52	[VCAP_KF_L2_BC_IS] = {
  53		.type = VCAP_FIELD_BIT,
  54		.offset = 82,
  55		.width = 1,
  56	},
  57	[VCAP_KF_8021Q_VLAN_TAGS] = {
  58		.type = VCAP_FIELD_U32,
  59		.offset = 83,
  60		.width = 3,
  61	},
  62	[VCAP_KF_8021Q_TPID0] = {
  63		.type = VCAP_FIELD_U32,
  64		.offset = 86,
  65		.width = 3,
  66	},
  67	[VCAP_KF_8021Q_PCP0] = {
  68		.type = VCAP_FIELD_U32,
  69		.offset = 89,
  70		.width = 3,
  71	},
  72	[VCAP_KF_8021Q_DEI0] = {
  73		.type = VCAP_FIELD_BIT,
  74		.offset = 92,
  75		.width = 1,
  76	},
  77	[VCAP_KF_8021Q_VID0] = {
  78		.type = VCAP_FIELD_U32,
  79		.offset = 93,
  80		.width = 12,
  81	},
  82	[VCAP_KF_8021Q_TPID1] = {
  83		.type = VCAP_FIELD_U32,
  84		.offset = 105,
  85		.width = 3,
  86	},
  87	[VCAP_KF_8021Q_PCP1] = {
  88		.type = VCAP_FIELD_U32,
  89		.offset = 108,
  90		.width = 3,
  91	},
  92	[VCAP_KF_8021Q_DEI1] = {
  93		.type = VCAP_FIELD_BIT,
  94		.offset = 111,
  95		.width = 1,
  96	},
  97	[VCAP_KF_8021Q_VID1] = {
  98		.type = VCAP_FIELD_U32,
  99		.offset = 112,
 100		.width = 12,
 101	},
 102	[VCAP_KF_8021Q_TPID2] = {
 103		.type = VCAP_FIELD_U32,
 104		.offset = 124,
 105		.width = 3,
 106	},
 107	[VCAP_KF_8021Q_PCP2] = {
 108		.type = VCAP_FIELD_U32,
 109		.offset = 127,
 110		.width = 3,
 111	},
 112	[VCAP_KF_8021Q_DEI2] = {
 113		.type = VCAP_FIELD_BIT,
 114		.offset = 130,
 115		.width = 1,
 116	},
 117	[VCAP_KF_8021Q_VID2] = {
 118		.type = VCAP_FIELD_U32,
 119		.offset = 131,
 120		.width = 12,
 121	},
 122	[VCAP_KF_L2_DMAC] = {
 123		.type = VCAP_FIELD_U48,
 124		.offset = 144,
 125		.width = 48,
 126	},
 127	[VCAP_KF_L2_SMAC] = {
 128		.type = VCAP_FIELD_U48,
 129		.offset = 192,
 130		.width = 48,
 131	},
 132	[VCAP_KF_IP_MC_IS] = {
 133		.type = VCAP_FIELD_BIT,
 134		.offset = 240,
 135		.width = 1,
 136	},
 137	[VCAP_KF_ETYPE_LEN_IS] = {
 138		.type = VCAP_FIELD_BIT,
 139		.offset = 241,
 140		.width = 1,
 141	},
 142	[VCAP_KF_ETYPE] = {
 143		.type = VCAP_FIELD_U32,
 144		.offset = 242,
 145		.width = 16,
 146	},
 147	[VCAP_KF_IP_SNAP_IS] = {
 148		.type = VCAP_FIELD_BIT,
 149		.offset = 258,
 150		.width = 1,
 151	},
 152	[VCAP_KF_IP4_IS] = {
 153		.type = VCAP_FIELD_BIT,
 154		.offset = 259,
 155		.width = 1,
 156	},
 157	[VCAP_KF_L3_FRAGMENT_TYPE] = {
 158		.type = VCAP_FIELD_U32,
 159		.offset = 260,
 160		.width = 2,
 161	},
 162	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
 163		.type = VCAP_FIELD_BIT,
 164		.offset = 262,
 165		.width = 1,
 166	},
 167	[VCAP_KF_L3_OPTIONS_IS] = {
 168		.type = VCAP_FIELD_BIT,
 169		.offset = 263,
 170		.width = 1,
 171	},
 172	[VCAP_KF_L3_DSCP] = {
 173		.type = VCAP_FIELD_U32,
 174		.offset = 264,
 175		.width = 6,
 176	},
 177	[VCAP_KF_L3_IP6_DIP] = {
 178		.type = VCAP_FIELD_U128,
 179		.offset = 270,
 180		.width = 128,
 181	},
 182	[VCAP_KF_L3_IP6_SIP] = {
 183		.type = VCAP_FIELD_U128,
 184		.offset = 398,
 185		.width = 128,
 186	},
 187	[VCAP_KF_TCP_UDP_IS] = {
 188		.type = VCAP_FIELD_BIT,
 189		.offset = 526,
 190		.width = 1,
 191	},
 192	[VCAP_KF_TCP_IS] = {
 193		.type = VCAP_FIELD_BIT,
 194		.offset = 527,
 195		.width = 1,
 196	},
 197	[VCAP_KF_L4_SPORT] = {
 198		.type = VCAP_FIELD_U32,
 199		.offset = 528,
 200		.width = 16,
 201	},
 202	[VCAP_KF_L4_RNG] = {
 203		.type = VCAP_FIELD_U32,
 204		.offset = 544,
 205		.width = 8,
 206	},
 207};
 208
 209static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = {
 210	[VCAP_KF_TYPE] = {
 211		.type = VCAP_FIELD_U32,
 212		.offset = 0,
 213		.width = 2,
 214	},
 215	[VCAP_KF_LOOKUP_FIRST_IS] = {
 216		.type = VCAP_FIELD_BIT,
 217		.offset = 2,
 218		.width = 1,
 219	},
 220	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
 221		.type = VCAP_FIELD_U32,
 222		.offset = 3,
 223		.width = 2,
 224	},
 225	[VCAP_KF_LOOKUP_GEN_IDX] = {
 226		.type = VCAP_FIELD_U32,
 227		.offset = 5,
 228		.width = 10,
 229	},
 230	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
 231		.type = VCAP_FIELD_U32,
 232		.offset = 15,
 233		.width = 2,
 234	},
 235	[VCAP_KF_IF_IGR_PORT_MASK] = {
 236		.type = VCAP_FIELD_U72,
 237		.offset = 17,
 238		.width = 65,
 239	},
 240	[VCAP_KF_L2_MC_IS] = {
 241		.type = VCAP_FIELD_BIT,
 242		.offset = 82,
 243		.width = 1,
 244	},
 245	[VCAP_KF_L2_BC_IS] = {
 246		.type = VCAP_FIELD_BIT,
 247		.offset = 83,
 248		.width = 1,
 249	},
 250	[VCAP_KF_8021Q_VLAN_TAGS] = {
 251		.type = VCAP_FIELD_U32,
 252		.offset = 84,
 253		.width = 3,
 254	},
 255	[VCAP_KF_8021Q_TPID0] = {
 256		.type = VCAP_FIELD_U32,
 257		.offset = 87,
 258		.width = 3,
 259	},
 260	[VCAP_KF_8021Q_PCP0] = {
 261		.type = VCAP_FIELD_U32,
 262		.offset = 90,
 263		.width = 3,
 264	},
 265	[VCAP_KF_8021Q_DEI0] = {
 266		.type = VCAP_FIELD_BIT,
 267		.offset = 93,
 268		.width = 1,
 269	},
 270	[VCAP_KF_8021Q_VID0] = {
 271		.type = VCAP_FIELD_U32,
 272		.offset = 94,
 273		.width = 12,
 274	},
 275	[VCAP_KF_8021Q_TPID1] = {
 276		.type = VCAP_FIELD_U32,
 277		.offset = 106,
 278		.width = 3,
 279	},
 280	[VCAP_KF_8021Q_PCP1] = {
 281		.type = VCAP_FIELD_U32,
 282		.offset = 109,
 283		.width = 3,
 284	},
 285	[VCAP_KF_8021Q_DEI1] = {
 286		.type = VCAP_FIELD_BIT,
 287		.offset = 112,
 288		.width = 1,
 289	},
 290	[VCAP_KF_8021Q_VID1] = {
 291		.type = VCAP_FIELD_U32,
 292		.offset = 113,
 293		.width = 12,
 294	},
 295	[VCAP_KF_8021Q_TPID2] = {
 296		.type = VCAP_FIELD_U32,
 297		.offset = 125,
 298		.width = 3,
 299	},
 300	[VCAP_KF_8021Q_PCP2] = {
 301		.type = VCAP_FIELD_U32,
 302		.offset = 128,
 303		.width = 3,
 304	},
 305	[VCAP_KF_8021Q_DEI2] = {
 306		.type = VCAP_FIELD_BIT,
 307		.offset = 131,
 308		.width = 1,
 309	},
 310	[VCAP_KF_8021Q_VID2] = {
 311		.type = VCAP_FIELD_U32,
 312		.offset = 132,
 313		.width = 12,
 314	},
 315	[VCAP_KF_IP_MC_IS] = {
 316		.type = VCAP_FIELD_BIT,
 317		.offset = 145,
 318		.width = 1,
 319	},
 320	[VCAP_KF_IP4_IS] = {
 321		.type = VCAP_FIELD_BIT,
 322		.offset = 146,
 323		.width = 1,
 324	},
 325	[VCAP_KF_L3_FRAGMENT_TYPE] = {
 326		.type = VCAP_FIELD_U32,
 327		.offset = 147,
 328		.width = 2,
 329	},
 330	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
 331		.type = VCAP_FIELD_BIT,
 332		.offset = 149,
 333		.width = 1,
 334	},
 335	[VCAP_KF_L3_OPTIONS_IS] = {
 336		.type = VCAP_FIELD_BIT,
 337		.offset = 150,
 338		.width = 1,
 339	},
 340	[VCAP_KF_L3_DSCP] = {
 341		.type = VCAP_FIELD_U32,
 342		.offset = 151,
 343		.width = 6,
 344	},
 345	[VCAP_KF_L3_IP4_DIP] = {
 346		.type = VCAP_FIELD_U32,
 347		.offset = 157,
 348		.width = 32,
 349	},
 350	[VCAP_KF_L3_IP4_SIP] = {
 351		.type = VCAP_FIELD_U32,
 352		.offset = 189,
 353		.width = 32,
 354	},
 355	[VCAP_KF_L3_IP_PROTO] = {
 356		.type = VCAP_FIELD_U32,
 357		.offset = 221,
 358		.width = 8,
 359	},
 360	[VCAP_KF_TCP_UDP_IS] = {
 361		.type = VCAP_FIELD_BIT,
 362		.offset = 229,
 363		.width = 1,
 364	},
 365	[VCAP_KF_TCP_IS] = {
 366		.type = VCAP_FIELD_BIT,
 367		.offset = 230,
 368		.width = 1,
 369	},
 370	[VCAP_KF_L4_RNG] = {
 371		.type = VCAP_FIELD_U32,
 372		.offset = 231,
 373		.width = 8,
 374	},
 375	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {
 376		.type = VCAP_FIELD_U32,
 377		.offset = 239,
 378		.width = 32,
 379	},
 380};
 381
 382static const struct vcap_field is2_mac_etype_keyfield[] = {
 383	[VCAP_KF_TYPE] = {
 384		.type = VCAP_FIELD_U32,
 385		.offset = 0,
 386		.width = 4,
 387	},
 388	[VCAP_KF_LOOKUP_FIRST_IS] = {
 389		.type = VCAP_FIELD_BIT,
 390		.offset = 4,
 391		.width = 1,
 392	},
 393	[VCAP_KF_LOOKUP_PAG] = {
 394		.type = VCAP_FIELD_U32,
 395		.offset = 5,
 396		.width = 8,
 397	},
 398	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
 399		.type = VCAP_FIELD_BIT,
 400		.offset = 13,
 401		.width = 1,
 402	},
 403	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
 404		.type = VCAP_FIELD_U32,
 405		.offset = 14,
 406		.width = 4,
 407	},
 408	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
 409		.type = VCAP_FIELD_U32,
 410		.offset = 18,
 411		.width = 2,
 412	},
 413	[VCAP_KF_IF_IGR_PORT_MASK] = {
 414		.type = VCAP_FIELD_U32,
 415		.offset = 20,
 416		.width = 32,
 417	},
 418	[VCAP_KF_L2_MC_IS] = {
 419		.type = VCAP_FIELD_BIT,
 420		.offset = 52,
 421		.width = 1,
 422	},
 423	[VCAP_KF_L2_BC_IS] = {
 424		.type = VCAP_FIELD_BIT,
 425		.offset = 53,
 426		.width = 1,
 427	},
 428	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
 429		.type = VCAP_FIELD_BIT,
 430		.offset = 54,
 431		.width = 1,
 432	},
 433	[VCAP_KF_ISDX_GT0_IS] = {
 434		.type = VCAP_FIELD_BIT,
 435		.offset = 56,
 436		.width = 1,
 437	},
 438	[VCAP_KF_ISDX_CLS] = {
 439		.type = VCAP_FIELD_U32,
 440		.offset = 57,
 441		.width = 10,
 442	},
 443	[VCAP_KF_8021Q_VID_CLS] = {
 444		.type = VCAP_FIELD_U32,
 445		.offset = 67,
 446		.width = 13,
 447	},
 448	[VCAP_KF_8021Q_DEI_CLS] = {
 449		.type = VCAP_FIELD_BIT,
 450		.offset = 80,
 451		.width = 1,
 452	},
 453	[VCAP_KF_8021Q_PCP_CLS] = {
 454		.type = VCAP_FIELD_U32,
 455		.offset = 81,
 456		.width = 3,
 457	},
 458	[VCAP_KF_L2_FWD_IS] = {
 459		.type = VCAP_FIELD_BIT,
 460		.offset = 84,
 461		.width = 1,
 462	},
 463	[VCAP_KF_L3_RT_IS] = {
 464		.type = VCAP_FIELD_BIT,
 465		.offset = 87,
 466		.width = 1,
 467	},
 468	[VCAP_KF_L3_DST_IS] = {
 469		.type = VCAP_FIELD_BIT,
 470		.offset = 88,
 471		.width = 1,
 472	},
 473	[VCAP_KF_L2_DMAC] = {
 474		.type = VCAP_FIELD_U48,
 475		.offset = 89,
 476		.width = 48,
 477	},
 478	[VCAP_KF_L2_SMAC] = {
 479		.type = VCAP_FIELD_U48,
 480		.offset = 137,
 481		.width = 48,
 482	},
 483	[VCAP_KF_ETYPE_LEN_IS] = {
 484		.type = VCAP_FIELD_BIT,
 485		.offset = 185,
 486		.width = 1,
 487	},
 488	[VCAP_KF_ETYPE] = {
 489		.type = VCAP_FIELD_U32,
 490		.offset = 186,
 491		.width = 16,
 492	},
 493	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
 494		.type = VCAP_FIELD_U64,
 495		.offset = 202,
 496		.width = 64,
 497	},
 498	[VCAP_KF_L4_RNG] = {
 499		.type = VCAP_FIELD_U32,
 500		.offset = 266,
 501		.width = 16,
 502	},
 503	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
 504		.type = VCAP_FIELD_BIT,
 505		.offset = 282,
 506		.width = 1,
 507	},
 508	[VCAP_KF_OAM_Y1731_IS] = {
 509		.type = VCAP_FIELD_BIT,
 510		.offset = 283,
 511		.width = 1,
 512	},
 513};
 514
 515static const struct vcap_field is2_arp_keyfield[] = {
 516	[VCAP_KF_TYPE] = {
 517		.type = VCAP_FIELD_U32,
 518		.offset = 0,
 519		.width = 4,
 520	},
 521	[VCAP_KF_LOOKUP_FIRST_IS] = {
 522		.type = VCAP_FIELD_BIT,
 523		.offset = 4,
 524		.width = 1,
 525	},
 526	[VCAP_KF_LOOKUP_PAG] = {
 527		.type = VCAP_FIELD_U32,
 528		.offset = 5,
 529		.width = 8,
 530	},
 531	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
 532		.type = VCAP_FIELD_BIT,
 533		.offset = 13,
 534		.width = 1,
 535	},
 536	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
 537		.type = VCAP_FIELD_U32,
 538		.offset = 14,
 539		.width = 4,
 540	},
 541	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
 542		.type = VCAP_FIELD_U32,
 543		.offset = 18,
 544		.width = 2,
 545	},
 546	[VCAP_KF_IF_IGR_PORT_MASK] = {
 547		.type = VCAP_FIELD_U32,
 548		.offset = 20,
 549		.width = 32,
 550	},
 551	[VCAP_KF_L2_MC_IS] = {
 552		.type = VCAP_FIELD_BIT,
 553		.offset = 52,
 554		.width = 1,
 555	},
 556	[VCAP_KF_L2_BC_IS] = {
 557		.type = VCAP_FIELD_BIT,
 558		.offset = 53,
 559		.width = 1,
 560	},
 561	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
 562		.type = VCAP_FIELD_BIT,
 563		.offset = 54,
 564		.width = 1,
 565	},
 566	[VCAP_KF_ISDX_GT0_IS] = {
 567		.type = VCAP_FIELD_BIT,
 568		.offset = 56,
 569		.width = 1,
 570	},
 571	[VCAP_KF_ISDX_CLS] = {
 572		.type = VCAP_FIELD_U32,
 573		.offset = 57,
 574		.width = 10,
 575	},
 576	[VCAP_KF_8021Q_VID_CLS] = {
 577		.type = VCAP_FIELD_U32,
 578		.offset = 67,
 579		.width = 13,
 580	},
 581	[VCAP_KF_8021Q_DEI_CLS] = {
 582		.type = VCAP_FIELD_BIT,
 583		.offset = 80,
 584		.width = 1,
 585	},
 586	[VCAP_KF_8021Q_PCP_CLS] = {
 587		.type = VCAP_FIELD_U32,
 588		.offset = 81,
 589		.width = 3,
 590	},
 591	[VCAP_KF_L2_FWD_IS] = {
 592		.type = VCAP_FIELD_BIT,
 593		.offset = 84,
 594		.width = 1,
 595	},
 596	[VCAP_KF_L2_SMAC] = {
 597		.type = VCAP_FIELD_U48,
 598		.offset = 85,
 599		.width = 48,
 600	},
 601	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
 602		.type = VCAP_FIELD_BIT,
 603		.offset = 133,
 604		.width = 1,
 605	},
 606	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
 607		.type = VCAP_FIELD_BIT,
 608		.offset = 134,
 609		.width = 1,
 610	},
 611	[VCAP_KF_ARP_LEN_OK_IS] = {
 612		.type = VCAP_FIELD_BIT,
 613		.offset = 135,
 614		.width = 1,
 615	},
 616	[VCAP_KF_ARP_TGT_MATCH_IS] = {
 617		.type = VCAP_FIELD_BIT,
 618		.offset = 136,
 619		.width = 1,
 620	},
 621	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
 622		.type = VCAP_FIELD_BIT,
 623		.offset = 137,
 624		.width = 1,
 625	},
 626	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
 627		.type = VCAP_FIELD_BIT,
 628		.offset = 138,
 629		.width = 1,
 630	},
 631	[VCAP_KF_ARP_OPCODE] = {
 632		.type = VCAP_FIELD_U32,
 633		.offset = 139,
 634		.width = 2,
 635	},
 636	[VCAP_KF_L3_IP4_DIP] = {
 637		.type = VCAP_FIELD_U32,
 638		.offset = 141,
 639		.width = 32,
 640	},
 641	[VCAP_KF_L3_IP4_SIP] = {
 642		.type = VCAP_FIELD_U32,
 643		.offset = 173,
 644		.width = 32,
 645	},
 646	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
 647		.type = VCAP_FIELD_BIT,
 648		.offset = 205,
 649		.width = 1,
 650	},
 651	[VCAP_KF_L4_RNG] = {
 652		.type = VCAP_FIELD_U32,
 653		.offset = 206,
 654		.width = 16,
 655	},
 656};
 657
 658static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {
 659	[VCAP_KF_TYPE] = {
 660		.type = VCAP_FIELD_U32,
 661		.offset = 0,
 662		.width = 4,
 663	},
 664	[VCAP_KF_LOOKUP_FIRST_IS] = {
 665		.type = VCAP_FIELD_BIT,
 666		.offset = 4,
 667		.width = 1,
 668	},
 669	[VCAP_KF_LOOKUP_PAG] = {
 670		.type = VCAP_FIELD_U32,
 671		.offset = 5,
 672		.width = 8,
 673	},
 674	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
 675		.type = VCAP_FIELD_BIT,
 676		.offset = 13,
 677		.width = 1,
 678	},
 679	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
 680		.type = VCAP_FIELD_U32,
 681		.offset = 14,
 682		.width = 4,
 683	},
 684	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
 685		.type = VCAP_FIELD_U32,
 686		.offset = 18,
 687		.width = 2,
 688	},
 689	[VCAP_KF_IF_IGR_PORT_MASK] = {
 690		.type = VCAP_FIELD_U32,
 691		.offset = 20,
 692		.width = 32,
 693	},
 694	[VCAP_KF_L2_MC_IS] = {
 695		.type = VCAP_FIELD_BIT,
 696		.offset = 52,
 697		.width = 1,
 698	},
 699	[VCAP_KF_L2_BC_IS] = {
 700		.type = VCAP_FIELD_BIT,
 701		.offset = 53,
 702		.width = 1,
 703	},
 704	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
 705		.type = VCAP_FIELD_BIT,
 706		.offset = 54,
 707		.width = 1,
 708	},
 709	[VCAP_KF_ISDX_GT0_IS] = {
 710		.type = VCAP_FIELD_BIT,
 711		.offset = 56,
 712		.width = 1,
 713	},
 714	[VCAP_KF_ISDX_CLS] = {
 715		.type = VCAP_FIELD_U32,
 716		.offset = 57,
 717		.width = 10,
 718	},
 719	[VCAP_KF_8021Q_VID_CLS] = {
 720		.type = VCAP_FIELD_U32,
 721		.offset = 67,
 722		.width = 13,
 723	},
 724	[VCAP_KF_8021Q_DEI_CLS] = {
 725		.type = VCAP_FIELD_BIT,
 726		.offset = 80,
 727		.width = 1,
 728	},
 729	[VCAP_KF_8021Q_PCP_CLS] = {
 730		.type = VCAP_FIELD_U32,
 731		.offset = 81,
 732		.width = 3,
 733	},
 734	[VCAP_KF_L2_FWD_IS] = {
 735		.type = VCAP_FIELD_BIT,
 736		.offset = 84,
 737		.width = 1,
 738	},
 739	[VCAP_KF_L3_RT_IS] = {
 740		.type = VCAP_FIELD_BIT,
 741		.offset = 87,
 742		.width = 1,
 743	},
 744	[VCAP_KF_L3_DST_IS] = {
 745		.type = VCAP_FIELD_BIT,
 746		.offset = 88,
 747		.width = 1,
 748	},
 749	[VCAP_KF_IP4_IS] = {
 750		.type = VCAP_FIELD_BIT,
 751		.offset = 89,
 752		.width = 1,
 753	},
 754	[VCAP_KF_L3_FRAGMENT_TYPE] = {
 755		.type = VCAP_FIELD_U32,
 756		.offset = 90,
 757		.width = 2,
 758	},
 759	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
 760		.type = VCAP_FIELD_BIT,
 761		.offset = 92,
 762		.width = 1,
 763	},
 764	[VCAP_KF_L3_OPTIONS_IS] = {
 765		.type = VCAP_FIELD_BIT,
 766		.offset = 93,
 767		.width = 1,
 768	},
 769	[VCAP_KF_L3_TTL_GT0] = {
 770		.type = VCAP_FIELD_BIT,
 771		.offset = 94,
 772		.width = 1,
 773	},
 774	[VCAP_KF_L3_TOS] = {
 775		.type = VCAP_FIELD_U32,
 776		.offset = 95,
 777		.width = 8,
 778	},
 779	[VCAP_KF_L3_IP4_DIP] = {
 780		.type = VCAP_FIELD_U32,
 781		.offset = 103,
 782		.width = 32,
 783	},
 784	[VCAP_KF_L3_IP4_SIP] = {
 785		.type = VCAP_FIELD_U32,
 786		.offset = 135,
 787		.width = 32,
 788	},
 789	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
 790		.type = VCAP_FIELD_BIT,
 791		.offset = 167,
 792		.width = 1,
 793	},
 794	[VCAP_KF_TCP_IS] = {
 795		.type = VCAP_FIELD_BIT,
 796		.offset = 168,
 797		.width = 1,
 798	},
 799	[VCAP_KF_L4_DPORT] = {
 800		.type = VCAP_FIELD_U32,
 801		.offset = 169,
 802		.width = 16,
 803	},
 804	[VCAP_KF_L4_SPORT] = {
 805		.type = VCAP_FIELD_U32,
 806		.offset = 185,
 807		.width = 16,
 808	},
 809	[VCAP_KF_L4_RNG] = {
 810		.type = VCAP_FIELD_U32,
 811		.offset = 201,
 812		.width = 16,
 813	},
 814	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
 815		.type = VCAP_FIELD_BIT,
 816		.offset = 217,
 817		.width = 1,
 818	},
 819	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
 820		.type = VCAP_FIELD_BIT,
 821		.offset = 218,
 822		.width = 1,
 823	},
 824	[VCAP_KF_L4_FIN] = {
 825		.type = VCAP_FIELD_BIT,
 826		.offset = 219,
 827		.width = 1,
 828	},
 829	[VCAP_KF_L4_SYN] = {
 830		.type = VCAP_FIELD_BIT,
 831		.offset = 220,
 832		.width = 1,
 833	},
 834	[VCAP_KF_L4_RST] = {
 835		.type = VCAP_FIELD_BIT,
 836		.offset = 221,
 837		.width = 1,
 838	},
 839	[VCAP_KF_L4_PSH] = {
 840		.type = VCAP_FIELD_BIT,
 841		.offset = 222,
 842		.width = 1,
 843	},
 844	[VCAP_KF_L4_ACK] = {
 845		.type = VCAP_FIELD_BIT,
 846		.offset = 223,
 847		.width = 1,
 848	},
 849	[VCAP_KF_L4_URG] = {
 850		.type = VCAP_FIELD_BIT,
 851		.offset = 224,
 852		.width = 1,
 853	},
 854	[VCAP_KF_L4_PAYLOAD] = {
 855		.type = VCAP_FIELD_U64,
 856		.offset = 225,
 857		.width = 64,
 858	},
 859};
 860
 861static const struct vcap_field is2_ip4_other_keyfield[] = {
 862	[VCAP_KF_TYPE] = {
 863		.type = VCAP_FIELD_U32,
 864		.offset = 0,
 865		.width = 4,
 866	},
 867	[VCAP_KF_LOOKUP_FIRST_IS] = {
 868		.type = VCAP_FIELD_BIT,
 869		.offset = 4,
 870		.width = 1,
 871	},
 872	[VCAP_KF_LOOKUP_PAG] = {
 873		.type = VCAP_FIELD_U32,
 874		.offset = 5,
 875		.width = 8,
 876	},
 877	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
 878		.type = VCAP_FIELD_BIT,
 879		.offset = 13,
 880		.width = 1,
 881	},
 882	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
 883		.type = VCAP_FIELD_U32,
 884		.offset = 14,
 885		.width = 4,
 886	},
 887	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
 888		.type = VCAP_FIELD_U32,
 889		.offset = 18,
 890		.width = 2,
 891	},
 892	[VCAP_KF_IF_IGR_PORT_MASK] = {
 893		.type = VCAP_FIELD_U32,
 894		.offset = 20,
 895		.width = 32,
 896	},
 897	[VCAP_KF_L2_MC_IS] = {
 898		.type = VCAP_FIELD_BIT,
 899		.offset = 52,
 900		.width = 1,
 901	},
 902	[VCAP_KF_L2_BC_IS] = {
 903		.type = VCAP_FIELD_BIT,
 904		.offset = 53,
 905		.width = 1,
 906	},
 907	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
 908		.type = VCAP_FIELD_BIT,
 909		.offset = 54,
 910		.width = 1,
 911	},
 912	[VCAP_KF_ISDX_GT0_IS] = {
 913		.type = VCAP_FIELD_BIT,
 914		.offset = 56,
 915		.width = 1,
 916	},
 917	[VCAP_KF_ISDX_CLS] = {
 918		.type = VCAP_FIELD_U32,
 919		.offset = 57,
 920		.width = 10,
 921	},
 922	[VCAP_KF_8021Q_VID_CLS] = {
 923		.type = VCAP_FIELD_U32,
 924		.offset = 67,
 925		.width = 13,
 926	},
 927	[VCAP_KF_8021Q_DEI_CLS] = {
 928		.type = VCAP_FIELD_BIT,
 929		.offset = 80,
 930		.width = 1,
 931	},
 932	[VCAP_KF_8021Q_PCP_CLS] = {
 933		.type = VCAP_FIELD_U32,
 934		.offset = 81,
 935		.width = 3,
 936	},
 937	[VCAP_KF_L2_FWD_IS] = {
 938		.type = VCAP_FIELD_BIT,
 939		.offset = 84,
 940		.width = 1,
 941	},
 942	[VCAP_KF_L3_RT_IS] = {
 943		.type = VCAP_FIELD_BIT,
 944		.offset = 87,
 945		.width = 1,
 946	},
 947	[VCAP_KF_L3_DST_IS] = {
 948		.type = VCAP_FIELD_BIT,
 949		.offset = 88,
 950		.width = 1,
 951	},
 952	[VCAP_KF_IP4_IS] = {
 953		.type = VCAP_FIELD_BIT,
 954		.offset = 89,
 955		.width = 1,
 956	},
 957	[VCAP_KF_L3_FRAGMENT_TYPE] = {
 958		.type = VCAP_FIELD_U32,
 959		.offset = 90,
 960		.width = 2,
 961	},
 962	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
 963		.type = VCAP_FIELD_BIT,
 964		.offset = 92,
 965		.width = 1,
 966	},
 967	[VCAP_KF_L3_OPTIONS_IS] = {
 968		.type = VCAP_FIELD_BIT,
 969		.offset = 93,
 970		.width = 1,
 971	},
 972	[VCAP_KF_L3_TTL_GT0] = {
 973		.type = VCAP_FIELD_BIT,
 974		.offset = 94,
 975		.width = 1,
 976	},
 977	[VCAP_KF_L3_TOS] = {
 978		.type = VCAP_FIELD_U32,
 979		.offset = 95,
 980		.width = 8,
 981	},
 982	[VCAP_KF_L3_IP4_DIP] = {
 983		.type = VCAP_FIELD_U32,
 984		.offset = 103,
 985		.width = 32,
 986	},
 987	[VCAP_KF_L3_IP4_SIP] = {
 988		.type = VCAP_FIELD_U32,
 989		.offset = 135,
 990		.width = 32,
 991	},
 992	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
 993		.type = VCAP_FIELD_BIT,
 994		.offset = 167,
 995		.width = 1,
 996	},
 997	[VCAP_KF_L3_IP_PROTO] = {
 998		.type = VCAP_FIELD_U32,
 999		.offset = 168,
1000		.width = 8,
1001	},
1002	[VCAP_KF_L4_RNG] = {
1003		.type = VCAP_FIELD_U32,
1004		.offset = 176,
1005		.width = 16,
1006	},
1007	[VCAP_KF_L3_PAYLOAD] = {
1008		.type = VCAP_FIELD_U112,
1009		.offset = 192,
1010		.width = 96,
1011	},
1012};
1013
1014static const struct vcap_field is2_ip6_std_keyfield[] = {
1015	[VCAP_KF_TYPE] = {
1016		.type = VCAP_FIELD_U32,
1017		.offset = 0,
1018		.width = 4,
1019	},
1020	[VCAP_KF_LOOKUP_FIRST_IS] = {
1021		.type = VCAP_FIELD_BIT,
1022		.offset = 4,
1023		.width = 1,
1024	},
1025	[VCAP_KF_LOOKUP_PAG] = {
1026		.type = VCAP_FIELD_U32,
1027		.offset = 5,
1028		.width = 8,
1029	},
1030	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1031		.type = VCAP_FIELD_BIT,
1032		.offset = 13,
1033		.width = 1,
1034	},
1035	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1036		.type = VCAP_FIELD_U32,
1037		.offset = 14,
1038		.width = 4,
1039	},
1040	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1041		.type = VCAP_FIELD_U32,
1042		.offset = 18,
1043		.width = 2,
1044	},
1045	[VCAP_KF_IF_IGR_PORT_MASK] = {
1046		.type = VCAP_FIELD_U32,
1047		.offset = 20,
1048		.width = 32,
1049	},
1050	[VCAP_KF_L2_MC_IS] = {
1051		.type = VCAP_FIELD_BIT,
1052		.offset = 52,
1053		.width = 1,
1054	},
1055	[VCAP_KF_L2_BC_IS] = {
1056		.type = VCAP_FIELD_BIT,
1057		.offset = 53,
1058		.width = 1,
1059	},
1060	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1061		.type = VCAP_FIELD_BIT,
1062		.offset = 54,
1063		.width = 1,
1064	},
1065	[VCAP_KF_ISDX_GT0_IS] = {
1066		.type = VCAP_FIELD_BIT,
1067		.offset = 56,
1068		.width = 1,
1069	},
1070	[VCAP_KF_ISDX_CLS] = {
1071		.type = VCAP_FIELD_U32,
1072		.offset = 57,
1073		.width = 10,
1074	},
1075	[VCAP_KF_8021Q_VID_CLS] = {
1076		.type = VCAP_FIELD_U32,
1077		.offset = 67,
1078		.width = 13,
1079	},
1080	[VCAP_KF_8021Q_DEI_CLS] = {
1081		.type = VCAP_FIELD_BIT,
1082		.offset = 80,
1083		.width = 1,
1084	},
1085	[VCAP_KF_8021Q_PCP_CLS] = {
1086		.type = VCAP_FIELD_U32,
1087		.offset = 81,
1088		.width = 3,
1089	},
1090	[VCAP_KF_L2_FWD_IS] = {
1091		.type = VCAP_FIELD_BIT,
1092		.offset = 84,
1093		.width = 1,
1094	},
1095	[VCAP_KF_L3_RT_IS] = {
1096		.type = VCAP_FIELD_BIT,
1097		.offset = 87,
1098		.width = 1,
1099	},
1100	[VCAP_KF_L3_TTL_GT0] = {
1101		.type = VCAP_FIELD_BIT,
1102		.offset = 89,
1103		.width = 1,
1104	},
1105	[VCAP_KF_L3_IP6_SIP] = {
1106		.type = VCAP_FIELD_U128,
1107		.offset = 90,
1108		.width = 128,
1109	},
1110	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1111		.type = VCAP_FIELD_BIT,
1112		.offset = 218,
1113		.width = 1,
1114	},
1115	[VCAP_KF_L3_IP_PROTO] = {
1116		.type = VCAP_FIELD_U32,
1117		.offset = 219,
1118		.width = 8,
1119	},
1120	[VCAP_KF_L4_RNG] = {
1121		.type = VCAP_FIELD_U32,
1122		.offset = 227,
1123		.width = 16,
1124	},
1125	[VCAP_KF_L3_PAYLOAD] = {
1126		.type = VCAP_FIELD_U48,
1127		.offset = 243,
1128		.width = 40,
1129	},
1130};
1131
1132static const struct vcap_field is2_ip_7tuple_keyfield[] = {
1133	[VCAP_KF_TYPE] = {
1134		.type = VCAP_FIELD_U32,
1135		.offset = 0,
1136		.width = 2,
1137	},
1138	[VCAP_KF_LOOKUP_FIRST_IS] = {
1139		.type = VCAP_FIELD_BIT,
1140		.offset = 2,
1141		.width = 1,
1142	},
1143	[VCAP_KF_LOOKUP_PAG] = {
1144		.type = VCAP_FIELD_U32,
1145		.offset = 3,
1146		.width = 8,
1147	},
1148	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1149		.type = VCAP_FIELD_BIT,
1150		.offset = 11,
1151		.width = 1,
1152	},
1153	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1154		.type = VCAP_FIELD_U32,
1155		.offset = 12,
1156		.width = 4,
1157	},
1158	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1159		.type = VCAP_FIELD_U32,
1160		.offset = 16,
1161		.width = 2,
1162	},
1163	[VCAP_KF_IF_IGR_PORT_MASK] = {
1164		.type = VCAP_FIELD_U72,
1165		.offset = 18,
1166		.width = 65,
1167	},
1168	[VCAP_KF_L2_MC_IS] = {
1169		.type = VCAP_FIELD_BIT,
1170		.offset = 83,
1171		.width = 1,
1172	},
1173	[VCAP_KF_L2_BC_IS] = {
1174		.type = VCAP_FIELD_BIT,
1175		.offset = 84,
1176		.width = 1,
1177	},
1178	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1179		.type = VCAP_FIELD_BIT,
1180		.offset = 85,
1181		.width = 1,
1182	},
1183	[VCAP_KF_ISDX_GT0_IS] = {
1184		.type = VCAP_FIELD_BIT,
1185		.offset = 87,
1186		.width = 1,
1187	},
1188	[VCAP_KF_ISDX_CLS] = {
1189		.type = VCAP_FIELD_U32,
1190		.offset = 88,
1191		.width = 10,
1192	},
1193	[VCAP_KF_8021Q_VID_CLS] = {
1194		.type = VCAP_FIELD_U32,
1195		.offset = 98,
1196		.width = 13,
1197	},
1198	[VCAP_KF_8021Q_DEI_CLS] = {
1199		.type = VCAP_FIELD_BIT,
1200		.offset = 111,
1201		.width = 1,
1202	},
1203	[VCAP_KF_8021Q_PCP_CLS] = {
1204		.type = VCAP_FIELD_U32,
1205		.offset = 112,
1206		.width = 3,
1207	},
1208	[VCAP_KF_L2_FWD_IS] = {
1209		.type = VCAP_FIELD_BIT,
1210		.offset = 115,
1211		.width = 1,
1212	},
1213	[VCAP_KF_L3_RT_IS] = {
1214		.type = VCAP_FIELD_BIT,
1215		.offset = 118,
1216		.width = 1,
1217	},
1218	[VCAP_KF_L3_DST_IS] = {
1219		.type = VCAP_FIELD_BIT,
1220		.offset = 119,
1221		.width = 1,
1222	},
1223	[VCAP_KF_L2_DMAC] = {
1224		.type = VCAP_FIELD_U48,
1225		.offset = 120,
1226		.width = 48,
1227	},
1228	[VCAP_KF_L2_SMAC] = {
1229		.type = VCAP_FIELD_U48,
1230		.offset = 168,
1231		.width = 48,
1232	},
1233	[VCAP_KF_IP4_IS] = {
1234		.type = VCAP_FIELD_BIT,
1235		.offset = 218,
1236		.width = 1,
1237	},
1238	[VCAP_KF_L3_TTL_GT0] = {
1239		.type = VCAP_FIELD_BIT,
1240		.offset = 219,
1241		.width = 1,
1242	},
1243	[VCAP_KF_L3_TOS] = {
1244		.type = VCAP_FIELD_U32,
1245		.offset = 220,
1246		.width = 8,
1247	},
1248	[VCAP_KF_L3_IP6_DIP] = {
1249		.type = VCAP_FIELD_U128,
1250		.offset = 228,
1251		.width = 128,
1252	},
1253	[VCAP_KF_L3_IP6_SIP] = {
1254		.type = VCAP_FIELD_U128,
1255		.offset = 356,
1256		.width = 128,
1257	},
1258	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1259		.type = VCAP_FIELD_BIT,
1260		.offset = 484,
1261		.width = 1,
1262	},
1263	[VCAP_KF_TCP_UDP_IS] = {
1264		.type = VCAP_FIELD_BIT,
1265		.offset = 485,
1266		.width = 1,
1267	},
1268	[VCAP_KF_TCP_IS] = {
1269		.type = VCAP_FIELD_BIT,
1270		.offset = 486,
1271		.width = 1,
1272	},
1273	[VCAP_KF_L4_DPORT] = {
1274		.type = VCAP_FIELD_U32,
1275		.offset = 487,
1276		.width = 16,
1277	},
1278	[VCAP_KF_L4_SPORT] = {
1279		.type = VCAP_FIELD_U32,
1280		.offset = 503,
1281		.width = 16,
1282	},
1283	[VCAP_KF_L4_RNG] = {
1284		.type = VCAP_FIELD_U32,
1285		.offset = 519,
1286		.width = 16,
1287	},
1288	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
1289		.type = VCAP_FIELD_BIT,
1290		.offset = 535,
1291		.width = 1,
1292	},
1293	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
1294		.type = VCAP_FIELD_BIT,
1295		.offset = 536,
1296		.width = 1,
1297	},
1298	[VCAP_KF_L4_FIN] = {
1299		.type = VCAP_FIELD_BIT,
1300		.offset = 537,
1301		.width = 1,
1302	},
1303	[VCAP_KF_L4_SYN] = {
1304		.type = VCAP_FIELD_BIT,
1305		.offset = 538,
1306		.width = 1,
1307	},
1308	[VCAP_KF_L4_RST] = {
1309		.type = VCAP_FIELD_BIT,
1310		.offset = 539,
1311		.width = 1,
1312	},
1313	[VCAP_KF_L4_PSH] = {
1314		.type = VCAP_FIELD_BIT,
1315		.offset = 540,
1316		.width = 1,
1317	},
1318	[VCAP_KF_L4_ACK] = {
1319		.type = VCAP_FIELD_BIT,
1320		.offset = 541,
1321		.width = 1,
1322	},
1323	[VCAP_KF_L4_URG] = {
1324		.type = VCAP_FIELD_BIT,
1325		.offset = 542,
1326		.width = 1,
1327	},
1328	[VCAP_KF_L4_PAYLOAD] = {
1329		.type = VCAP_FIELD_U64,
1330		.offset = 543,
1331		.width = 64,
1332	},
1333};
1334
1335static const struct vcap_field es0_isdx_keyfield[] = {
1336	[VCAP_KF_TYPE] = {
1337		.type = VCAP_FIELD_BIT,
1338		.offset = 0,
1339		.width = 1,
1340	},
1341	[VCAP_KF_IF_EGR_PORT_NO] = {
1342		.type = VCAP_FIELD_U32,
1343		.offset = 1,
1344		.width = 6,
1345	},
1346	[VCAP_KF_8021Q_VID_CLS] = {
1347		.type = VCAP_FIELD_U32,
1348		.offset = 7,
1349		.width = 13,
1350	},
1351	[VCAP_KF_COSID_CLS] = {
1352		.type = VCAP_FIELD_U32,
1353		.offset = 20,
1354		.width = 3,
1355	},
1356	[VCAP_KF_8021Q_TPID] = {
1357		.type = VCAP_FIELD_U32,
1358		.offset = 23,
1359		.width = 3,
1360	},
1361	[VCAP_KF_L3_DPL_CLS] = {
1362		.type = VCAP_FIELD_BIT,
1363		.offset = 26,
1364		.width = 1,
1365	},
1366	[VCAP_KF_ISDX_GT0_IS] = {
1367		.type = VCAP_FIELD_BIT,
1368		.offset = 27,
1369		.width = 1,
1370	},
1371	[VCAP_KF_PROT_ACTIVE] = {
1372		.type = VCAP_FIELD_BIT,
1373		.offset = 28,
1374		.width = 1,
1375	},
1376	[VCAP_KF_ISDX_CLS] = {
1377		.type = VCAP_FIELD_U32,
1378		.offset = 38,
1379		.width = 10,
1380	},
1381};
1382
1383static const struct vcap_field es2_mac_etype_keyfield[] = {
1384	[VCAP_KF_TYPE] = {
1385		.type = VCAP_FIELD_U32,
1386		.offset = 0,
1387		.width = 3,
1388	},
1389	[VCAP_KF_LOOKUP_FIRST_IS] = {
1390		.type = VCAP_FIELD_BIT,
1391		.offset = 3,
1392		.width = 1,
1393	},
1394	[VCAP_KF_L2_MC_IS] = {
1395		.type = VCAP_FIELD_BIT,
1396		.offset = 13,
1397		.width = 1,
1398	},
1399	[VCAP_KF_L2_BC_IS] = {
1400		.type = VCAP_FIELD_BIT,
1401		.offset = 14,
1402		.width = 1,
1403	},
1404	[VCAP_KF_ISDX_GT0_IS] = {
1405		.type = VCAP_FIELD_BIT,
1406		.offset = 15,
1407		.width = 1,
1408	},
1409	[VCAP_KF_ISDX_CLS] = {
1410		.type = VCAP_FIELD_U32,
1411		.offset = 16,
1412		.width = 10,
1413	},
1414	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1415		.type = VCAP_FIELD_BIT,
1416		.offset = 26,
1417		.width = 1,
1418	},
1419	[VCAP_KF_8021Q_VID_CLS] = {
1420		.type = VCAP_FIELD_U32,
1421		.offset = 28,
1422		.width = 13,
1423	},
1424	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
1425		.type = VCAP_FIELD_U32,
1426		.offset = 41,
1427		.width = 3,
1428	},
1429	[VCAP_KF_IF_EGR_PORT_MASK] = {
1430		.type = VCAP_FIELD_U32,
1431		.offset = 44,
1432		.width = 32,
1433	},
1434	[VCAP_KF_IF_IGR_PORT_SEL] = {
1435		.type = VCAP_FIELD_BIT,
1436		.offset = 76,
1437		.width = 1,
1438	},
1439	[VCAP_KF_IF_IGR_PORT] = {
1440		.type = VCAP_FIELD_U32,
1441		.offset = 77,
1442		.width = 7,
1443	},
1444	[VCAP_KF_8021Q_PCP_CLS] = {
1445		.type = VCAP_FIELD_U32,
1446		.offset = 84,
1447		.width = 3,
1448	},
1449	[VCAP_KF_8021Q_DEI_CLS] = {
1450		.type = VCAP_FIELD_BIT,
1451		.offset = 87,
1452		.width = 1,
1453	},
1454	[VCAP_KF_COSID_CLS] = {
1455		.type = VCAP_FIELD_U32,
1456		.offset = 88,
1457		.width = 3,
1458	},
1459	[VCAP_KF_L3_DPL_CLS] = {
1460		.type = VCAP_FIELD_BIT,
1461		.offset = 91,
1462		.width = 1,
1463	},
1464	[VCAP_KF_L3_RT_IS] = {
1465		.type = VCAP_FIELD_BIT,
1466		.offset = 92,
1467		.width = 1,
1468	},
1469	[VCAP_KF_L2_DMAC] = {
1470		.type = VCAP_FIELD_U48,
1471		.offset = 96,
1472		.width = 48,
1473	},
1474	[VCAP_KF_L2_SMAC] = {
1475		.type = VCAP_FIELD_U48,
1476		.offset = 144,
1477		.width = 48,
1478	},
1479	[VCAP_KF_ETYPE_LEN_IS] = {
1480		.type = VCAP_FIELD_BIT,
1481		.offset = 192,
1482		.width = 1,
1483	},
1484	[VCAP_KF_ETYPE] = {
1485		.type = VCAP_FIELD_U32,
1486		.offset = 193,
1487		.width = 16,
1488	},
1489	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
1490		.type = VCAP_FIELD_U64,
1491		.offset = 209,
1492		.width = 64,
1493	},
1494	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
1495		.type = VCAP_FIELD_BIT,
1496		.offset = 273,
1497		.width = 1,
1498	},
1499	[VCAP_KF_OAM_Y1731_IS] = {
1500		.type = VCAP_FIELD_BIT,
1501		.offset = 274,
1502		.width = 1,
1503	},
1504};
1505
1506static const struct vcap_field es2_arp_keyfield[] = {
1507	[VCAP_KF_TYPE] = {
1508		.type = VCAP_FIELD_U32,
1509		.offset = 0,
1510		.width = 3,
1511	},
1512	[VCAP_KF_LOOKUP_FIRST_IS] = {
1513		.type = VCAP_FIELD_BIT,
1514		.offset = 3,
1515		.width = 1,
1516	},
1517	[VCAP_KF_L2_MC_IS] = {
1518		.type = VCAP_FIELD_BIT,
1519		.offset = 13,
1520		.width = 1,
1521	},
1522	[VCAP_KF_L2_BC_IS] = {
1523		.type = VCAP_FIELD_BIT,
1524		.offset = 14,
1525		.width = 1,
1526	},
1527	[VCAP_KF_ISDX_GT0_IS] = {
1528		.type = VCAP_FIELD_BIT,
1529		.offset = 15,
1530		.width = 1,
1531	},
1532	[VCAP_KF_ISDX_CLS] = {
1533		.type = VCAP_FIELD_U32,
1534		.offset = 16,
1535		.width = 10,
1536	},
1537	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1538		.type = VCAP_FIELD_BIT,
1539		.offset = 26,
1540		.width = 1,
1541	},
1542	[VCAP_KF_8021Q_VID_CLS] = {
1543		.type = VCAP_FIELD_U32,
1544		.offset = 28,
1545		.width = 13,
1546	},
1547	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
1548		.type = VCAP_FIELD_U32,
1549		.offset = 41,
1550		.width = 3,
1551	},
1552	[VCAP_KF_IF_EGR_PORT_MASK] = {
1553		.type = VCAP_FIELD_U32,
1554		.offset = 44,
1555		.width = 32,
1556	},
1557	[VCAP_KF_IF_IGR_PORT_SEL] = {
1558		.type = VCAP_FIELD_BIT,
1559		.offset = 76,
1560		.width = 1,
1561	},
1562	[VCAP_KF_IF_IGR_PORT] = {
1563		.type = VCAP_FIELD_U32,
1564		.offset = 77,
1565		.width = 7,
1566	},
1567	[VCAP_KF_8021Q_PCP_CLS] = {
1568		.type = VCAP_FIELD_U32,
1569		.offset = 84,
1570		.width = 3,
1571	},
1572	[VCAP_KF_8021Q_DEI_CLS] = {
1573		.type = VCAP_FIELD_BIT,
1574		.offset = 87,
1575		.width = 1,
1576	},
1577	[VCAP_KF_COSID_CLS] = {
1578		.type = VCAP_FIELD_U32,
1579		.offset = 88,
1580		.width = 3,
1581	},
1582	[VCAP_KF_L3_DPL_CLS] = {
1583		.type = VCAP_FIELD_BIT,
1584		.offset = 91,
1585		.width = 1,
1586	},
1587	[VCAP_KF_L2_SMAC] = {
1588		.type = VCAP_FIELD_U48,
1589		.offset = 95,
1590		.width = 48,
1591	},
1592	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
1593		.type = VCAP_FIELD_BIT,
1594		.offset = 143,
1595		.width = 1,
1596	},
1597	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
1598		.type = VCAP_FIELD_BIT,
1599		.offset = 144,
1600		.width = 1,
1601	},
1602	[VCAP_KF_ARP_LEN_OK_IS] = {
1603		.type = VCAP_FIELD_BIT,
1604		.offset = 145,
1605		.width = 1,
1606	},
1607	[VCAP_KF_ARP_TGT_MATCH_IS] = {
1608		.type = VCAP_FIELD_BIT,
1609		.offset = 146,
1610		.width = 1,
1611	},
1612	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
1613		.type = VCAP_FIELD_BIT,
1614		.offset = 147,
1615		.width = 1,
1616	},
1617	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
1618		.type = VCAP_FIELD_BIT,
1619		.offset = 148,
1620		.width = 1,
1621	},
1622	[VCAP_KF_ARP_OPCODE] = {
1623		.type = VCAP_FIELD_U32,
1624		.offset = 149,
1625		.width = 2,
1626	},
1627	[VCAP_KF_L3_IP4_DIP] = {
1628		.type = VCAP_FIELD_U32,
1629		.offset = 151,
1630		.width = 32,
1631	},
1632	[VCAP_KF_L3_IP4_SIP] = {
1633		.type = VCAP_FIELD_U32,
1634		.offset = 183,
1635		.width = 32,
1636	},
1637	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1638		.type = VCAP_FIELD_BIT,
1639		.offset = 215,
1640		.width = 1,
1641	},
1642};
1643
1644static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = {
1645	[VCAP_KF_TYPE] = {
1646		.type = VCAP_FIELD_U32,
1647		.offset = 0,
1648		.width = 3,
1649	},
1650	[VCAP_KF_LOOKUP_FIRST_IS] = {
1651		.type = VCAP_FIELD_BIT,
1652		.offset = 3,
1653		.width = 1,
1654	},
1655	[VCAP_KF_L2_MC_IS] = {
1656		.type = VCAP_FIELD_BIT,
1657		.offset = 13,
1658		.width = 1,
1659	},
1660	[VCAP_KF_L2_BC_IS] = {
1661		.type = VCAP_FIELD_BIT,
1662		.offset = 14,
1663		.width = 1,
1664	},
1665	[VCAP_KF_ISDX_GT0_IS] = {
1666		.type = VCAP_FIELD_BIT,
1667		.offset = 15,
1668		.width = 1,
1669	},
1670	[VCAP_KF_ISDX_CLS] = {
1671		.type = VCAP_FIELD_U32,
1672		.offset = 16,
1673		.width = 10,
1674	},
1675	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1676		.type = VCAP_FIELD_BIT,
1677		.offset = 26,
1678		.width = 1,
1679	},
1680	[VCAP_KF_8021Q_VID_CLS] = {
1681		.type = VCAP_FIELD_U32,
1682		.offset = 28,
1683		.width = 13,
1684	},
1685	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
1686		.type = VCAP_FIELD_U32,
1687		.offset = 41,
1688		.width = 3,
1689	},
1690	[VCAP_KF_IF_EGR_PORT_MASK] = {
1691		.type = VCAP_FIELD_U32,
1692		.offset = 44,
1693		.width = 32,
1694	},
1695	[VCAP_KF_IF_IGR_PORT_SEL] = {
1696		.type = VCAP_FIELD_BIT,
1697		.offset = 76,
1698		.width = 1,
1699	},
1700	[VCAP_KF_IF_IGR_PORT] = {
1701		.type = VCAP_FIELD_U32,
1702		.offset = 77,
1703		.width = 7,
1704	},
1705	[VCAP_KF_8021Q_PCP_CLS] = {
1706		.type = VCAP_FIELD_U32,
1707		.offset = 84,
1708		.width = 3,
1709	},
1710	[VCAP_KF_8021Q_DEI_CLS] = {
1711		.type = VCAP_FIELD_BIT,
1712		.offset = 87,
1713		.width = 1,
1714	},
1715	[VCAP_KF_COSID_CLS] = {
1716		.type = VCAP_FIELD_U32,
1717		.offset = 88,
1718		.width = 3,
1719	},
1720	[VCAP_KF_L3_DPL_CLS] = {
1721		.type = VCAP_FIELD_BIT,
1722		.offset = 91,
1723		.width = 1,
1724	},
1725	[VCAP_KF_L3_RT_IS] = {
1726		.type = VCAP_FIELD_BIT,
1727		.offset = 92,
1728		.width = 1,
1729	},
1730	[VCAP_KF_IP4_IS] = {
1731		.type = VCAP_FIELD_BIT,
1732		.offset = 96,
1733		.width = 1,
1734	},
1735	[VCAP_KF_L3_FRAGMENT_TYPE] = {
1736		.type = VCAP_FIELD_U32,
1737		.offset = 97,
1738		.width = 2,
1739	},
1740	[VCAP_KF_L3_OPTIONS_IS] = {
1741		.type = VCAP_FIELD_BIT,
1742		.offset = 99,
1743		.width = 1,
1744	},
1745	[VCAP_KF_L3_TTL_GT0] = {
1746		.type = VCAP_FIELD_BIT,
1747		.offset = 100,
1748		.width = 1,
1749	},
1750	[VCAP_KF_L3_TOS] = {
1751		.type = VCAP_FIELD_U32,
1752		.offset = 101,
1753		.width = 8,
1754	},
1755	[VCAP_KF_L3_IP4_DIP] = {
1756		.type = VCAP_FIELD_U32,
1757		.offset = 109,
1758		.width = 32,
1759	},
1760	[VCAP_KF_L3_IP4_SIP] = {
1761		.type = VCAP_FIELD_U32,
1762		.offset = 141,
1763		.width = 32,
1764	},
1765	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1766		.type = VCAP_FIELD_BIT,
1767		.offset = 173,
1768		.width = 1,
1769	},
1770	[VCAP_KF_TCP_IS] = {
1771		.type = VCAP_FIELD_BIT,
1772		.offset = 174,
1773		.width = 1,
1774	},
1775	[VCAP_KF_L4_DPORT] = {
1776		.type = VCAP_FIELD_U32,
1777		.offset = 175,
1778		.width = 16,
1779	},
1780	[VCAP_KF_L4_SPORT] = {
1781		.type = VCAP_FIELD_U32,
1782		.offset = 191,
1783		.width = 16,
1784	},
1785	[VCAP_KF_L4_RNG] = {
1786		.type = VCAP_FIELD_U32,
1787		.offset = 207,
1788		.width = 16,
1789	},
1790	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
1791		.type = VCAP_FIELD_BIT,
1792		.offset = 223,
1793		.width = 1,
1794	},
1795	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
1796		.type = VCAP_FIELD_BIT,
1797		.offset = 224,
1798		.width = 1,
1799	},
1800	[VCAP_KF_L4_FIN] = {
1801		.type = VCAP_FIELD_BIT,
1802		.offset = 225,
1803		.width = 1,
1804	},
1805	[VCAP_KF_L4_SYN] = {
1806		.type = VCAP_FIELD_BIT,
1807		.offset = 226,
1808		.width = 1,
1809	},
1810	[VCAP_KF_L4_RST] = {
1811		.type = VCAP_FIELD_BIT,
1812		.offset = 227,
1813		.width = 1,
1814	},
1815	[VCAP_KF_L4_PSH] = {
1816		.type = VCAP_FIELD_BIT,
1817		.offset = 228,
1818		.width = 1,
1819	},
1820	[VCAP_KF_L4_ACK] = {
1821		.type = VCAP_FIELD_BIT,
1822		.offset = 229,
1823		.width = 1,
1824	},
1825	[VCAP_KF_L4_URG] = {
1826		.type = VCAP_FIELD_BIT,
1827		.offset = 230,
1828		.width = 1,
1829	},
1830	[VCAP_KF_L4_PAYLOAD] = {
1831		.type = VCAP_FIELD_U64,
1832		.offset = 231,
1833		.width = 64,
1834	},
1835};
1836
1837static const struct vcap_field es2_ip4_other_keyfield[] = {
1838	[VCAP_KF_TYPE] = {
1839		.type = VCAP_FIELD_U32,
1840		.offset = 0,
1841		.width = 3,
1842	},
1843	[VCAP_KF_LOOKUP_FIRST_IS] = {
1844		.type = VCAP_FIELD_BIT,
1845		.offset = 3,
1846		.width = 1,
1847	},
1848	[VCAP_KF_L2_MC_IS] = {
1849		.type = VCAP_FIELD_BIT,
1850		.offset = 13,
1851		.width = 1,
1852	},
1853	[VCAP_KF_L2_BC_IS] = {
1854		.type = VCAP_FIELD_BIT,
1855		.offset = 14,
1856		.width = 1,
1857	},
1858	[VCAP_KF_ISDX_GT0_IS] = {
1859		.type = VCAP_FIELD_BIT,
1860		.offset = 15,
1861		.width = 1,
1862	},
1863	[VCAP_KF_ISDX_CLS] = {
1864		.type = VCAP_FIELD_U32,
1865		.offset = 16,
1866		.width = 10,
1867	},
1868	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1869		.type = VCAP_FIELD_BIT,
1870		.offset = 26,
1871		.width = 1,
1872	},
1873	[VCAP_KF_8021Q_VID_CLS] = {
1874		.type = VCAP_FIELD_U32,
1875		.offset = 28,
1876		.width = 13,
1877	},
1878	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
1879		.type = VCAP_FIELD_U32,
1880		.offset = 41,
1881		.width = 3,
1882	},
1883	[VCAP_KF_IF_EGR_PORT_MASK] = {
1884		.type = VCAP_FIELD_U32,
1885		.offset = 44,
1886		.width = 32,
1887	},
1888	[VCAP_KF_IF_IGR_PORT_SEL] = {
1889		.type = VCAP_FIELD_BIT,
1890		.offset = 76,
1891		.width = 1,
1892	},
1893	[VCAP_KF_IF_IGR_PORT] = {
1894		.type = VCAP_FIELD_U32,
1895		.offset = 77,
1896		.width = 7,
1897	},
1898	[VCAP_KF_8021Q_PCP_CLS] = {
1899		.type = VCAP_FIELD_U32,
1900		.offset = 84,
1901		.width = 3,
1902	},
1903	[VCAP_KF_8021Q_DEI_CLS] = {
1904		.type = VCAP_FIELD_BIT,
1905		.offset = 87,
1906		.width = 1,
1907	},
1908	[VCAP_KF_COSID_CLS] = {
1909		.type = VCAP_FIELD_U32,
1910		.offset = 88,
1911		.width = 3,
1912	},
1913	[VCAP_KF_L3_DPL_CLS] = {
1914		.type = VCAP_FIELD_BIT,
1915		.offset = 91,
1916		.width = 1,
1917	},
1918	[VCAP_KF_L3_RT_IS] = {
1919		.type = VCAP_FIELD_BIT,
1920		.offset = 92,
1921		.width = 1,
1922	},
1923	[VCAP_KF_IP4_IS] = {
1924		.type = VCAP_FIELD_BIT,
1925		.offset = 96,
1926		.width = 1,
1927	},
1928	[VCAP_KF_L3_FRAGMENT_TYPE] = {
1929		.type = VCAP_FIELD_U32,
1930		.offset = 97,
1931		.width = 2,
1932	},
1933	[VCAP_KF_L3_OPTIONS_IS] = {
1934		.type = VCAP_FIELD_BIT,
1935		.offset = 99,
1936		.width = 1,
1937	},
1938	[VCAP_KF_L3_TTL_GT0] = {
1939		.type = VCAP_FIELD_BIT,
1940		.offset = 100,
1941		.width = 1,
1942	},
1943	[VCAP_KF_L3_TOS] = {
1944		.type = VCAP_FIELD_U32,
1945		.offset = 101,
1946		.width = 8,
1947	},
1948	[VCAP_KF_L3_IP4_DIP] = {
1949		.type = VCAP_FIELD_U32,
1950		.offset = 109,
1951		.width = 32,
1952	},
1953	[VCAP_KF_L3_IP4_SIP] = {
1954		.type = VCAP_FIELD_U32,
1955		.offset = 141,
1956		.width = 32,
1957	},
1958	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1959		.type = VCAP_FIELD_BIT,
1960		.offset = 173,
1961		.width = 1,
1962	},
1963	[VCAP_KF_L3_IP_PROTO] = {
1964		.type = VCAP_FIELD_U32,
1965		.offset = 174,
1966		.width = 8,
1967	},
1968	[VCAP_KF_L3_PAYLOAD] = {
1969		.type = VCAP_FIELD_U112,
1970		.offset = 182,
1971		.width = 96,
1972	},
1973};
1974
1975static const struct vcap_field es2_ip_7tuple_keyfield[] = {
1976	[VCAP_KF_LOOKUP_FIRST_IS] = {
1977		.type = VCAP_FIELD_BIT,
1978		.offset = 0,
1979		.width = 1,
1980	},
1981	[VCAP_KF_L2_MC_IS] = {
1982		.type = VCAP_FIELD_BIT,
1983		.offset = 10,
1984		.width = 1,
1985	},
1986	[VCAP_KF_L2_BC_IS] = {
1987		.type = VCAP_FIELD_BIT,
1988		.offset = 11,
1989		.width = 1,
1990	},
1991	[VCAP_KF_ISDX_GT0_IS] = {
1992		.type = VCAP_FIELD_BIT,
1993		.offset = 12,
1994		.width = 1,
1995	},
1996	[VCAP_KF_ISDX_CLS] = {
1997		.type = VCAP_FIELD_U32,
1998		.offset = 13,
1999		.width = 10,
2000	},
2001	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
2002		.type = VCAP_FIELD_BIT,
2003		.offset = 23,
2004		.width = 1,
2005	},
2006	[VCAP_KF_8021Q_VID_CLS] = {
2007		.type = VCAP_FIELD_U32,
2008		.offset = 25,
2009		.width = 13,
2010	},
2011	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
2012		.type = VCAP_FIELD_U32,
2013		.offset = 38,
2014		.width = 3,
2015	},
2016	[VCAP_KF_IF_EGR_PORT_MASK] = {
2017		.type = VCAP_FIELD_U32,
2018		.offset = 41,
2019		.width = 32,
2020	},
2021	[VCAP_KF_IF_IGR_PORT_SEL] = {
2022		.type = VCAP_FIELD_BIT,
2023		.offset = 73,
2024		.width = 1,
2025	},
2026	[VCAP_KF_IF_IGR_PORT] = {
2027		.type = VCAP_FIELD_U32,
2028		.offset = 74,
2029		.width = 7,
2030	},
2031	[VCAP_KF_8021Q_PCP_CLS] = {
2032		.type = VCAP_FIELD_U32,
2033		.offset = 81,
2034		.width = 3,
2035	},
2036	[VCAP_KF_8021Q_DEI_CLS] = {
2037		.type = VCAP_FIELD_BIT,
2038		.offset = 84,
2039		.width = 1,
2040	},
2041	[VCAP_KF_COSID_CLS] = {
2042		.type = VCAP_FIELD_U32,
2043		.offset = 85,
2044		.width = 3,
2045	},
2046	[VCAP_KF_L3_DPL_CLS] = {
2047		.type = VCAP_FIELD_BIT,
2048		.offset = 88,
2049		.width = 1,
2050	},
2051	[VCAP_KF_L3_RT_IS] = {
2052		.type = VCAP_FIELD_BIT,
2053		.offset = 89,
2054		.width = 1,
2055	},
2056	[VCAP_KF_L2_DMAC] = {
2057		.type = VCAP_FIELD_U48,
2058		.offset = 93,
2059		.width = 48,
2060	},
2061	[VCAP_KF_L2_SMAC] = {
2062		.type = VCAP_FIELD_U48,
2063		.offset = 141,
2064		.width = 48,
2065	},
2066	[VCAP_KF_IP4_IS] = {
2067		.type = VCAP_FIELD_BIT,
2068		.offset = 191,
2069		.width = 1,
2070	},
2071	[VCAP_KF_L3_TTL_GT0] = {
2072		.type = VCAP_FIELD_BIT,
2073		.offset = 192,
2074		.width = 1,
2075	},
2076	[VCAP_KF_L3_TOS] = {
2077		.type = VCAP_FIELD_U32,
2078		.offset = 193,
2079		.width = 8,
2080	},
2081	[VCAP_KF_L3_IP6_DIP] = {
2082		.type = VCAP_FIELD_U128,
2083		.offset = 201,
2084		.width = 128,
2085	},
2086	[VCAP_KF_L3_IP6_SIP] = {
2087		.type = VCAP_FIELD_U128,
2088		.offset = 329,
2089		.width = 128,
2090	},
2091	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
2092		.type = VCAP_FIELD_BIT,
2093		.offset = 457,
2094		.width = 1,
2095	},
2096	[VCAP_KF_TCP_UDP_IS] = {
2097		.type = VCAP_FIELD_BIT,
2098		.offset = 458,
2099		.width = 1,
2100	},
2101	[VCAP_KF_TCP_IS] = {
2102		.type = VCAP_FIELD_BIT,
2103		.offset = 459,
2104		.width = 1,
2105	},
2106	[VCAP_KF_L4_DPORT] = {
2107		.type = VCAP_FIELD_U32,
2108		.offset = 460,
2109		.width = 16,
2110	},
2111	[VCAP_KF_L4_SPORT] = {
2112		.type = VCAP_FIELD_U32,
2113		.offset = 476,
2114		.width = 16,
2115	},
2116	[VCAP_KF_L4_RNG] = {
2117		.type = VCAP_FIELD_U32,
2118		.offset = 492,
2119		.width = 16,
2120	},
2121	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
2122		.type = VCAP_FIELD_BIT,
2123		.offset = 508,
2124		.width = 1,
2125	},
2126	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
2127		.type = VCAP_FIELD_BIT,
2128		.offset = 509,
2129		.width = 1,
2130	},
2131	[VCAP_KF_L4_FIN] = {
2132		.type = VCAP_FIELD_BIT,
2133		.offset = 510,
2134		.width = 1,
2135	},
2136	[VCAP_KF_L4_SYN] = {
2137		.type = VCAP_FIELD_BIT,
2138		.offset = 511,
2139		.width = 1,
2140	},
2141	[VCAP_KF_L4_RST] = {
2142		.type = VCAP_FIELD_BIT,
2143		.offset = 512,
2144		.width = 1,
2145	},
2146	[VCAP_KF_L4_PSH] = {
2147		.type = VCAP_FIELD_BIT,
2148		.offset = 513,
2149		.width = 1,
2150	},
2151	[VCAP_KF_L4_ACK] = {
2152		.type = VCAP_FIELD_BIT,
2153		.offset = 514,
2154		.width = 1,
2155	},
2156	[VCAP_KF_L4_URG] = {
2157		.type = VCAP_FIELD_BIT,
2158		.offset = 515,
2159		.width = 1,
2160	},
2161	[VCAP_KF_L4_PAYLOAD] = {
2162		.type = VCAP_FIELD_U64,
2163		.offset = 516,
2164		.width = 64,
2165	},
2166};
2167
2168static const struct vcap_field es2_ip6_std_keyfield[] = {
2169	[VCAP_KF_TYPE] = {
2170		.type = VCAP_FIELD_U32,
2171		.offset = 0,
2172		.width = 3,
2173	},
2174	[VCAP_KF_LOOKUP_FIRST_IS] = {
2175		.type = VCAP_FIELD_BIT,
2176		.offset = 3,
2177		.width = 1,
2178	},
2179	[VCAP_KF_L2_MC_IS] = {
2180		.type = VCAP_FIELD_BIT,
2181		.offset = 13,
2182		.width = 1,
2183	},
2184	[VCAP_KF_L2_BC_IS] = {
2185		.type = VCAP_FIELD_BIT,
2186		.offset = 14,
2187		.width = 1,
2188	},
2189	[VCAP_KF_ISDX_GT0_IS] = {
2190		.type = VCAP_FIELD_BIT,
2191		.offset = 15,
2192		.width = 1,
2193	},
2194	[VCAP_KF_ISDX_CLS] = {
2195		.type = VCAP_FIELD_U32,
2196		.offset = 16,
2197		.width = 10,
2198	},
2199	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
2200		.type = VCAP_FIELD_BIT,
2201		.offset = 26,
2202		.width = 1,
2203	},
2204	[VCAP_KF_8021Q_VID_CLS] = {
2205		.type = VCAP_FIELD_U32,
2206		.offset = 28,
2207		.width = 13,
2208	},
2209	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
2210		.type = VCAP_FIELD_U32,
2211		.offset = 41,
2212		.width = 3,
2213	},
2214	[VCAP_KF_IF_EGR_PORT_MASK] = {
2215		.type = VCAP_FIELD_U32,
2216		.offset = 44,
2217		.width = 32,
2218	},
2219	[VCAP_KF_IF_IGR_PORT_SEL] = {
2220		.type = VCAP_FIELD_BIT,
2221		.offset = 76,
2222		.width = 1,
2223	},
2224	[VCAP_KF_IF_IGR_PORT] = {
2225		.type = VCAP_FIELD_U32,
2226		.offset = 77,
2227		.width = 7,
2228	},
2229	[VCAP_KF_8021Q_PCP_CLS] = {
2230		.type = VCAP_FIELD_U32,
2231		.offset = 84,
2232		.width = 3,
2233	},
2234	[VCAP_KF_8021Q_DEI_CLS] = {
2235		.type = VCAP_FIELD_BIT,
2236		.offset = 87,
2237		.width = 1,
2238	},
2239	[VCAP_KF_COSID_CLS] = {
2240		.type = VCAP_FIELD_U32,
2241		.offset = 88,
2242		.width = 3,
2243	},
2244	[VCAP_KF_L3_DPL_CLS] = {
2245		.type = VCAP_FIELD_BIT,
2246		.offset = 91,
2247		.width = 1,
2248	},
2249	[VCAP_KF_L3_RT_IS] = {
2250		.type = VCAP_FIELD_BIT,
2251		.offset = 92,
2252		.width = 1,
2253	},
2254	[VCAP_KF_L3_TTL_GT0] = {
2255		.type = VCAP_FIELD_BIT,
2256		.offset = 96,
2257		.width = 1,
2258	},
2259	[VCAP_KF_L3_IP6_SIP] = {
2260		.type = VCAP_FIELD_U128,
2261		.offset = 97,
2262		.width = 128,
2263	},
2264	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
2265		.type = VCAP_FIELD_BIT,
2266		.offset = 225,
2267		.width = 1,
2268	},
2269	[VCAP_KF_L3_IP_PROTO] = {
2270		.type = VCAP_FIELD_U32,
2271		.offset = 226,
2272		.width = 8,
2273	},
2274	[VCAP_KF_L4_RNG] = {
2275		.type = VCAP_FIELD_U32,
2276		.offset = 234,
2277		.width = 16,
2278	},
2279	[VCAP_KF_L3_PAYLOAD] = {
2280		.type = VCAP_FIELD_U48,
2281		.offset = 250,
2282		.width = 40,
2283	},
2284};
2285
2286/* keyfield_set */
2287static const struct vcap_set is0_keyfield_set[] = {
2288	[VCAP_KFS_NORMAL_7TUPLE] = {
2289		.type_id = 0,
2290		.sw_per_item = 12,
2291		.sw_cnt = 1,
2292	},
2293	[VCAP_KFS_NORMAL_5TUPLE_IP4] = {
2294		.type_id = 2,
2295		.sw_per_item = 6,
2296		.sw_cnt = 2,
2297	},
2298};
2299
2300static const struct vcap_set is2_keyfield_set[] = {
2301	[VCAP_KFS_MAC_ETYPE] = {
2302		.type_id = 0,
2303		.sw_per_item = 6,
2304		.sw_cnt = 2,
2305	},
2306	[VCAP_KFS_ARP] = {
2307		.type_id = 3,
2308		.sw_per_item = 6,
2309		.sw_cnt = 2,
2310	},
2311	[VCAP_KFS_IP4_TCP_UDP] = {
2312		.type_id = 4,
2313		.sw_per_item = 6,
2314		.sw_cnt = 2,
2315	},
2316	[VCAP_KFS_IP4_OTHER] = {
2317		.type_id = 5,
2318		.sw_per_item = 6,
2319		.sw_cnt = 2,
2320	},
2321	[VCAP_KFS_IP6_STD] = {
2322		.type_id = 6,
2323		.sw_per_item = 6,
2324		.sw_cnt = 2,
2325	},
2326	[VCAP_KFS_IP_7TUPLE] = {
2327		.type_id = 1,
2328		.sw_per_item = 12,
2329		.sw_cnt = 1,
2330	},
2331};
2332
2333static const struct vcap_set es0_keyfield_set[] = {
2334	[VCAP_KFS_ISDX] = {
2335		.type_id = 0,
2336		.sw_per_item = 1,
2337		.sw_cnt = 1,
2338	},
2339};
2340
2341static const struct vcap_set es2_keyfield_set[] = {
2342	[VCAP_KFS_MAC_ETYPE] = {
2343		.type_id = 0,
2344		.sw_per_item = 6,
2345		.sw_cnt = 2,
2346	},
2347	[VCAP_KFS_ARP] = {
2348		.type_id = 1,
2349		.sw_per_item = 6,
2350		.sw_cnt = 2,
2351	},
2352	[VCAP_KFS_IP4_TCP_UDP] = {
2353		.type_id = 2,
2354		.sw_per_item = 6,
2355		.sw_cnt = 2,
2356	},
2357	[VCAP_KFS_IP4_OTHER] = {
2358		.type_id = 3,
2359		.sw_per_item = 6,
2360		.sw_cnt = 2,
2361	},
2362	[VCAP_KFS_IP_7TUPLE] = {
2363		.type_id = -1,
2364		.sw_per_item = 12,
2365		.sw_cnt = 1,
2366	},
2367	[VCAP_KFS_IP6_STD] = {
2368		.type_id = 4,
2369		.sw_per_item = 6,
2370		.sw_cnt = 2,
2371	},
2372};
2373
2374/* keyfield_set map */
2375static const struct vcap_field *is0_keyfield_set_map[] = {
2376	[VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield,
2377	[VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield,
2378};
2379
2380static const struct vcap_field *is2_keyfield_set_map[] = {
2381	[VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,
2382	[VCAP_KFS_ARP] = is2_arp_keyfield,
2383	[VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,
2384	[VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,
2385	[VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,
2386	[VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield,
2387};
2388
2389static const struct vcap_field *es0_keyfield_set_map[] = {
2390	[VCAP_KFS_ISDX] = es0_isdx_keyfield,
2391};
2392
2393static const struct vcap_field *es2_keyfield_set_map[] = {
2394	[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,
2395	[VCAP_KFS_ARP] = es2_arp_keyfield,
2396	[VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield,
2397	[VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield,
2398	[VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield,
2399	[VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield,
2400};
2401
2402/* keyfield_set map sizes */
2403static int is0_keyfield_set_map_size[] = {
2404	[VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield),
2405	[VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield),
2406};
2407
2408static int is2_keyfield_set_map_size[] = {
2409	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),
2410	[VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),
2411	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),
2412	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),
2413	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),
2414	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield),
2415};
2416
2417static int es0_keyfield_set_map_size[] = {
2418	[VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield),
2419};
2420
2421static int es2_keyfield_set_map_size[] = {
2422	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),
2423	[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),
2424	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield),
2425	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield),
2426	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield),
2427	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield),
2428};
2429
2430/* actionfields */
2431static const struct vcap_field is0_classification_actionfield[] = {
2432	[VCAP_AF_TYPE] = {
2433		.type = VCAP_FIELD_BIT,
2434		.offset = 0,
2435		.width = 1,
2436	},
2437	[VCAP_AF_DSCP_ENA] = {
2438		.type = VCAP_FIELD_BIT,
2439		.offset = 1,
2440		.width = 1,
2441	},
2442	[VCAP_AF_DSCP_VAL] = {
2443		.type = VCAP_FIELD_U32,
2444		.offset = 2,
2445		.width = 6,
2446	},
2447	[VCAP_AF_QOS_ENA] = {
2448		.type = VCAP_FIELD_BIT,
2449		.offset = 12,
2450		.width = 1,
2451	},
2452	[VCAP_AF_QOS_VAL] = {
2453		.type = VCAP_FIELD_U32,
2454		.offset = 13,
2455		.width = 3,
2456	},
2457	[VCAP_AF_DP_ENA] = {
2458		.type = VCAP_FIELD_BIT,
2459		.offset = 16,
2460		.width = 1,
2461	},
2462	[VCAP_AF_DP_VAL] = {
2463		.type = VCAP_FIELD_U32,
2464		.offset = 17,
2465		.width = 2,
2466	},
2467	[VCAP_AF_DEI_ENA] = {
2468		.type = VCAP_FIELD_BIT,
2469		.offset = 19,
2470		.width = 1,
2471	},
2472	[VCAP_AF_DEI_VAL] = {
2473		.type = VCAP_FIELD_BIT,
2474		.offset = 20,
2475		.width = 1,
2476	},
2477	[VCAP_AF_PCP_ENA] = {
2478		.type = VCAP_FIELD_BIT,
2479		.offset = 21,
2480		.width = 1,
2481	},
2482	[VCAP_AF_PCP_VAL] = {
2483		.type = VCAP_FIELD_U32,
2484		.offset = 22,
2485		.width = 3,
2486	},
2487	[VCAP_AF_MAP_LOOKUP_SEL] = {
2488		.type = VCAP_FIELD_U32,
2489		.offset = 25,
2490		.width = 2,
2491	},
2492	[VCAP_AF_MAP_KEY] = {
2493		.type = VCAP_FIELD_U32,
2494		.offset = 27,
2495		.width = 3,
2496	},
2497	[VCAP_AF_MAP_IDX] = {
2498		.type = VCAP_FIELD_U32,
2499		.offset = 30,
2500		.width = 7,
2501	},
2502	[VCAP_AF_CLS_VID_SEL] = {
2503		.type = VCAP_FIELD_U32,
2504		.offset = 37,
2505		.width = 3,
2506	},
2507	[VCAP_AF_VID_VAL] = {
2508		.type = VCAP_FIELD_U32,
2509		.offset = 43,
2510		.width = 13,
2511	},
2512	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
2513		.type = VCAP_FIELD_BIT,
2514		.offset = 66,
2515		.width = 1,
2516	},
2517	[VCAP_AF_ISDX_VAL] = {
2518		.type = VCAP_FIELD_U32,
2519		.offset = 67,
2520		.width = 10,
2521	},
2522	[VCAP_AF_PAG_OVERRIDE_MASK] = {
2523		.type = VCAP_FIELD_U32,
2524		.offset = 107,
2525		.width = 8,
2526	},
2527	[VCAP_AF_PAG_VAL] = {
2528		.type = VCAP_FIELD_U32,
2529		.offset = 115,
2530		.width = 8,
2531	},
2532	[VCAP_AF_NXT_IDX_CTRL] = {
2533		.type = VCAP_FIELD_U32,
2534		.offset = 167,
2535		.width = 3,
2536	},
2537	[VCAP_AF_NXT_IDX] = {
2538		.type = VCAP_FIELD_U32,
2539		.offset = 170,
2540		.width = 10,
2541	},
2542};
2543
2544static const struct vcap_field is0_full_actionfield[] = {
2545	[VCAP_AF_DSCP_ENA] = {
2546		.type = VCAP_FIELD_BIT,
2547		.offset = 0,
2548		.width = 1,
2549	},
2550	[VCAP_AF_DSCP_VAL] = {
2551		.type = VCAP_FIELD_U32,
2552		.offset = 1,
2553		.width = 6,
2554	},
2555	[VCAP_AF_QOS_ENA] = {
2556		.type = VCAP_FIELD_BIT,
2557		.offset = 11,
2558		.width = 1,
2559	},
2560	[VCAP_AF_QOS_VAL] = {
2561		.type = VCAP_FIELD_U32,
2562		.offset = 12,
2563		.width = 3,
2564	},
2565	[VCAP_AF_DP_ENA] = {
2566		.type = VCAP_FIELD_BIT,
2567		.offset = 15,
2568		.width = 1,
2569	},
2570	[VCAP_AF_DP_VAL] = {
2571		.type = VCAP_FIELD_U32,
2572		.offset = 16,
2573		.width = 2,
2574	},
2575	[VCAP_AF_DEI_ENA] = {
2576		.type = VCAP_FIELD_BIT,
2577		.offset = 18,
2578		.width = 1,
2579	},
2580	[VCAP_AF_DEI_VAL] = {
2581		.type = VCAP_FIELD_BIT,
2582		.offset = 19,
2583		.width = 1,
2584	},
2585	[VCAP_AF_PCP_ENA] = {
2586		.type = VCAP_FIELD_BIT,
2587		.offset = 20,
2588		.width = 1,
2589	},
2590	[VCAP_AF_PCP_VAL] = {
2591		.type = VCAP_FIELD_U32,
2592		.offset = 21,
2593		.width = 3,
2594	},
2595	[VCAP_AF_MAP_LOOKUP_SEL] = {
2596		.type = VCAP_FIELD_U32,
2597		.offset = 24,
2598		.width = 2,
2599	},
2600	[VCAP_AF_MAP_KEY] = {
2601		.type = VCAP_FIELD_U32,
2602		.offset = 26,
2603		.width = 3,
2604	},
2605	[VCAP_AF_MAP_IDX] = {
2606		.type = VCAP_FIELD_U32,
2607		.offset = 29,
2608		.width = 7,
2609	},
2610	[VCAP_AF_CLS_VID_SEL] = {
2611		.type = VCAP_FIELD_U32,
2612		.offset = 36,
2613		.width = 3,
2614	},
2615	[VCAP_AF_VID_VAL] = {
2616		.type = VCAP_FIELD_U32,
2617		.offset = 42,
2618		.width = 13,
2619	},
2620	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
2621		.type = VCAP_FIELD_BIT,
2622		.offset = 65,
2623		.width = 1,
2624	},
2625	[VCAP_AF_ISDX_VAL] = {
2626		.type = VCAP_FIELD_U32,
2627		.offset = 66,
2628		.width = 10,
2629	},
2630	[VCAP_AF_MASK_MODE] = {
2631		.type = VCAP_FIELD_U32,
2632		.offset = 76,
2633		.width = 3,
2634	},
2635	[VCAP_AF_PORT_MASK] = {
2636		.type = VCAP_FIELD_U48,
2637		.offset = 79,
2638		.width = 37,
2639	},
2640	[VCAP_AF_PAG_OVERRIDE_MASK] = {
2641		.type = VCAP_FIELD_U32,
2642		.offset = 174,
2643		.width = 8,
2644	},
2645	[VCAP_AF_PAG_VAL] = {
2646		.type = VCAP_FIELD_U32,
2647		.offset = 182,
2648		.width = 8,
2649	},
2650	[VCAP_AF_NXT_IDX_CTRL] = {
2651		.type = VCAP_FIELD_U32,
2652		.offset = 266,
2653		.width = 3,
2654	},
2655	[VCAP_AF_NXT_IDX] = {
2656		.type = VCAP_FIELD_U32,
2657		.offset = 269,
2658		.width = 10,
2659	},
2660};
2661
2662static const struct vcap_field is0_class_reduced_actionfield[] = {
2663	[VCAP_AF_TYPE] = {
2664		.type = VCAP_FIELD_BIT,
2665		.offset = 0,
2666		.width = 1,
2667	},
2668	[VCAP_AF_QOS_ENA] = {
2669		.type = VCAP_FIELD_BIT,
2670		.offset = 5,
2671		.width = 1,
2672	},
2673	[VCAP_AF_QOS_VAL] = {
2674		.type = VCAP_FIELD_U32,
2675		.offset = 6,
2676		.width = 3,
2677	},
2678	[VCAP_AF_DP_ENA] = {
2679		.type = VCAP_FIELD_BIT,
2680		.offset = 9,
2681		.width = 1,
2682	},
2683	[VCAP_AF_DP_VAL] = {
2684		.type = VCAP_FIELD_U32,
2685		.offset = 10,
2686		.width = 2,
2687	},
2688	[VCAP_AF_MAP_LOOKUP_SEL] = {
2689		.type = VCAP_FIELD_U32,
2690		.offset = 12,
2691		.width = 2,
2692	},
2693	[VCAP_AF_MAP_KEY] = {
2694		.type = VCAP_FIELD_U32,
2695		.offset = 14,
2696		.width = 3,
2697	},
2698	[VCAP_AF_CLS_VID_SEL] = {
2699		.type = VCAP_FIELD_U32,
2700		.offset = 17,
2701		.width = 3,
2702	},
2703	[VCAP_AF_VID_VAL] = {
2704		.type = VCAP_FIELD_U32,
2705		.offset = 23,
2706		.width = 13,
2707	},
2708	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
2709		.type = VCAP_FIELD_BIT,
2710		.offset = 46,
2711		.width = 1,
2712	},
2713	[VCAP_AF_ISDX_VAL] = {
2714		.type = VCAP_FIELD_U32,
2715		.offset = 47,
2716		.width = 10,
2717	},
2718	[VCAP_AF_NXT_IDX_CTRL] = {
2719		.type = VCAP_FIELD_U32,
2720		.offset = 89,
2721		.width = 3,
2722	},
2723	[VCAP_AF_NXT_IDX] = {
2724		.type = VCAP_FIELD_U32,
2725		.offset = 92,
2726		.width = 10,
2727	},
2728};
2729
2730static const struct vcap_field is2_base_type_actionfield[] = {
2731	[VCAP_AF_PIPELINE_FORCE_ENA] = {
2732		.type = VCAP_FIELD_BIT,
2733		.offset = 1,
2734		.width = 1,
2735	},
2736	[VCAP_AF_PIPELINE_PT] = {
2737		.type = VCAP_FIELD_U32,
2738		.offset = 2,
2739		.width = 5,
2740	},
2741	[VCAP_AF_HIT_ME_ONCE] = {
2742		.type = VCAP_FIELD_BIT,
2743		.offset = 7,
2744		.width = 1,
2745	},
2746	[VCAP_AF_INTR_ENA] = {
2747		.type = VCAP_FIELD_BIT,
2748		.offset = 8,
2749		.width = 1,
2750	},
2751	[VCAP_AF_CPU_COPY_ENA] = {
2752		.type = VCAP_FIELD_BIT,
2753		.offset = 9,
2754		.width = 1,
2755	},
2756	[VCAP_AF_CPU_QUEUE_NUM] = {
2757		.type = VCAP_FIELD_U32,
2758		.offset = 10,
2759		.width = 3,
2760	},
2761	[VCAP_AF_LRN_DIS] = {
2762		.type = VCAP_FIELD_BIT,
2763		.offset = 15,
2764		.width = 1,
2765	},
2766	[VCAP_AF_RT_DIS] = {
2767		.type = VCAP_FIELD_BIT,
2768		.offset = 16,
2769		.width = 1,
2770	},
2771	[VCAP_AF_POLICE_ENA] = {
2772		.type = VCAP_FIELD_BIT,
2773		.offset = 17,
2774		.width = 1,
2775	},
2776	[VCAP_AF_POLICE_IDX] = {
2777		.type = VCAP_FIELD_U32,
2778		.offset = 18,
2779		.width = 5,
2780	},
2781	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
2782		.type = VCAP_FIELD_BIT,
2783		.offset = 23,
2784		.width = 1,
2785	},
2786	[VCAP_AF_MASK_MODE] = {
2787		.type = VCAP_FIELD_U32,
2788		.offset = 27,
2789		.width = 3,
2790	},
2791	[VCAP_AF_PORT_MASK] = {
2792		.type = VCAP_FIELD_U48,
2793		.offset = 30,
2794		.width = 37,
2795	},
2796	[VCAP_AF_MIRROR_PROBE] = {
2797		.type = VCAP_FIELD_U32,
2798		.offset = 78,
2799		.width = 2,
2800	},
2801	[VCAP_AF_MATCH_ID] = {
2802		.type = VCAP_FIELD_U32,
2803		.offset = 131,
2804		.width = 16,
2805	},
2806	[VCAP_AF_MATCH_ID_MASK] = {
2807		.type = VCAP_FIELD_U32,
2808		.offset = 147,
2809		.width = 16,
2810	},
2811	[VCAP_AF_CNT_ID] = {
2812		.type = VCAP_FIELD_U32,
2813		.offset = 163,
2814		.width = 10,
2815	},
2816};
2817
2818static const struct vcap_field es0_es0_actionfield[] = {
2819	[VCAP_AF_PUSH_OUTER_TAG] = {
2820		.type = VCAP_FIELD_U32,
2821		.offset = 0,
2822		.width = 2,
2823	},
2824	[VCAP_AF_PUSH_INNER_TAG] = {
2825		.type = VCAP_FIELD_BIT,
2826		.offset = 2,
2827		.width = 1,
2828	},
2829	[VCAP_AF_TAG_A_TPID_SEL] = {
2830		.type = VCAP_FIELD_U32,
2831		.offset = 3,
2832		.width = 3,
2833	},
2834	[VCAP_AF_TAG_A_VID_SEL] = {
2835		.type = VCAP_FIELD_U32,
2836		.offset = 6,
2837		.width = 2,
2838	},
2839	[VCAP_AF_TAG_A_PCP_SEL] = {
2840		.type = VCAP_FIELD_U32,
2841		.offset = 8,
2842		.width = 3,
2843	},
2844	[VCAP_AF_TAG_A_DEI_SEL] = {
2845		.type = VCAP_FIELD_U32,
2846		.offset = 11,
2847		.width = 3,
2848	},
2849	[VCAP_AF_TAG_B_TPID_SEL] = {
2850		.type = VCAP_FIELD_U32,
2851		.offset = 14,
2852		.width = 3,
2853	},
2854	[VCAP_AF_TAG_B_VID_SEL] = {
2855		.type = VCAP_FIELD_U32,
2856		.offset = 17,
2857		.width = 2,
2858	},
2859	[VCAP_AF_TAG_B_PCP_SEL] = {
2860		.type = VCAP_FIELD_U32,
2861		.offset = 19,
2862		.width = 3,
2863	},
2864	[VCAP_AF_TAG_B_DEI_SEL] = {
2865		.type = VCAP_FIELD_U32,
2866		.offset = 22,
2867		.width = 3,
2868	},
2869	[VCAP_AF_TAG_C_TPID_SEL] = {
2870		.type = VCAP_FIELD_U32,
2871		.offset = 25,
2872		.width = 3,
2873	},
2874	[VCAP_AF_TAG_C_PCP_SEL] = {
2875		.type = VCAP_FIELD_U32,
2876		.offset = 28,
2877		.width = 3,
2878	},
2879	[VCAP_AF_TAG_C_DEI_SEL] = {
2880		.type = VCAP_FIELD_U32,
2881		.offset = 31,
2882		.width = 3,
2883	},
2884	[VCAP_AF_VID_A_VAL] = {
2885		.type = VCAP_FIELD_U32,
2886		.offset = 34,
2887		.width = 12,
2888	},
2889	[VCAP_AF_PCP_A_VAL] = {
2890		.type = VCAP_FIELD_U32,
2891		.offset = 46,
2892		.width = 3,
2893	},
2894	[VCAP_AF_DEI_A_VAL] = {
2895		.type = VCAP_FIELD_BIT,
2896		.offset = 49,
2897		.width = 1,
2898	},
2899	[VCAP_AF_VID_B_VAL] = {
2900		.type = VCAP_FIELD_U32,
2901		.offset = 50,
2902		.width = 12,
2903	},
2904	[VCAP_AF_PCP_B_VAL] = {
2905		.type = VCAP_FIELD_U32,
2906		.offset = 62,
2907		.width = 3,
2908	},
2909	[VCAP_AF_DEI_B_VAL] = {
2910		.type = VCAP_FIELD_BIT,
2911		.offset = 65,
2912		.width = 1,
2913	},
2914	[VCAP_AF_VID_C_VAL] = {
2915		.type = VCAP_FIELD_U32,
2916		.offset = 66,
2917		.width = 12,
2918	},
2919	[VCAP_AF_PCP_C_VAL] = {
2920		.type = VCAP_FIELD_U32,
2921		.offset = 78,
2922		.width = 3,
2923	},
2924	[VCAP_AF_DEI_C_VAL] = {
2925		.type = VCAP_FIELD_BIT,
2926		.offset = 81,
2927		.width = 1,
2928	},
2929	[VCAP_AF_POP_VAL] = {
2930		.type = VCAP_FIELD_U32,
2931		.offset = 82,
2932		.width = 2,
2933	},
2934	[VCAP_AF_UNTAG_VID_ENA] = {
2935		.type = VCAP_FIELD_BIT,
2936		.offset = 84,
2937		.width = 1,
2938	},
2939	[VCAP_AF_PUSH_CUSTOMER_TAG] = {
2940		.type = VCAP_FIELD_U32,
2941		.offset = 85,
2942		.width = 2,
2943	},
2944	[VCAP_AF_TAG_C_VID_SEL] = {
2945		.type = VCAP_FIELD_U32,
2946		.offset = 87,
2947		.width = 2,
2948	},
2949	[VCAP_AF_DSCP_SEL] = {
2950		.type = VCAP_FIELD_U32,
2951		.offset = 127,
2952		.width = 3,
2953	},
2954	[VCAP_AF_DSCP_VAL] = {
2955		.type = VCAP_FIELD_U32,
2956		.offset = 130,
2957		.width = 6,
2958	},
2959	[VCAP_AF_ESDX] = {
2960		.type = VCAP_FIELD_U32,
2961		.offset = 319,
2962		.width = 10,
2963	},
2964	[VCAP_AF_FWD_SEL] = {
2965		.type = VCAP_FIELD_U32,
2966		.offset = 438,
2967		.width = 2,
2968	},
2969	[VCAP_AF_CPU_QU] = {
2970		.type = VCAP_FIELD_U32,
2971		.offset = 440,
2972		.width = 3,
2973	},
2974	[VCAP_AF_PIPELINE_PT] = {
2975		.type = VCAP_FIELD_U32,
2976		.offset = 443,
2977		.width = 2,
2978	},
2979	[VCAP_AF_PIPELINE_ACT] = {
2980		.type = VCAP_FIELD_BIT,
2981		.offset = 445,
2982		.width = 1,
2983	},
2984	[VCAP_AF_SWAP_MACS_ENA] = {
2985		.type = VCAP_FIELD_BIT,
2986		.offset = 454,
2987		.width = 1,
2988	},
2989	[VCAP_AF_LOOP_ENA] = {
2990		.type = VCAP_FIELD_BIT,
2991		.offset = 455,
2992		.width = 1,
2993	},
2994};
2995
2996static const struct vcap_field es2_base_type_actionfield[] = {
2997	[VCAP_AF_HIT_ME_ONCE] = {
2998		.type = VCAP_FIELD_BIT,
2999		.offset = 0,
3000		.width = 1,
3001	},
3002	[VCAP_AF_INTR_ENA] = {
3003		.type = VCAP_FIELD_BIT,
3004		.offset = 1,
3005		.width = 1,
3006	},
3007	[VCAP_AF_FWD_MODE] = {
3008		.type = VCAP_FIELD_U32,
3009		.offset = 2,
3010		.width = 2,
3011	},
3012	[VCAP_AF_COPY_QUEUE_NUM] = {
3013		.type = VCAP_FIELD_U32,
3014		.offset = 4,
3015		.width = 14,
3016	},
3017	[VCAP_AF_COPY_PORT_NUM] = {
3018		.type = VCAP_FIELD_U32,
3019		.offset = 18,
3020		.width = 6,
3021	},
3022	[VCAP_AF_MIRROR_PROBE_ID] = {
3023		.type = VCAP_FIELD_U32,
3024		.offset = 24,
3025		.width = 2,
3026	},
3027	[VCAP_AF_CPU_COPY_ENA] = {
3028		.type = VCAP_FIELD_BIT,
3029		.offset = 26,
3030		.width = 1,
3031	},
3032	[VCAP_AF_CPU_QUEUE_NUM] = {
3033		.type = VCAP_FIELD_U32,
3034		.offset = 27,
3035		.width = 3,
3036	},
3037	[VCAP_AF_POLICE_ENA] = {
3038		.type = VCAP_FIELD_BIT,
3039		.offset = 30,
3040		.width = 1,
3041	},
3042	[VCAP_AF_POLICE_REMARK] = {
3043		.type = VCAP_FIELD_BIT,
3044		.offset = 31,
3045		.width = 1,
3046	},
3047	[VCAP_AF_POLICE_IDX] = {
3048		.type = VCAP_FIELD_U32,
3049		.offset = 32,
3050		.width = 5,
3051	},
3052	[VCAP_AF_ES2_REW_CMD] = {
3053		.type = VCAP_FIELD_U32,
3054		.offset = 37,
3055		.width = 3,
3056	},
3057	[VCAP_AF_CNT_ID] = {
3058		.type = VCAP_FIELD_U32,
3059		.offset = 40,
3060		.width = 9,
3061	},
3062	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
3063		.type = VCAP_FIELD_BIT,
3064		.offset = 49,
3065		.width = 1,
3066	},
3067};
3068
3069/* actionfield_set */
3070static const struct vcap_set is0_actionfield_set[] = {
3071	[VCAP_AFS_CLASSIFICATION] = {
3072		.type_id = 1,
3073		.sw_per_item = 2,
3074		.sw_cnt = 6,
3075	},
3076	[VCAP_AFS_FULL] = {
3077		.type_id = -1,
3078		.sw_per_item = 3,
3079		.sw_cnt = 4,
3080	},
3081	[VCAP_AFS_CLASS_REDUCED] = {
3082		.type_id = 1,
3083		.sw_per_item = 1,
3084		.sw_cnt = 12,
3085	},
3086};
3087
3088static const struct vcap_set is2_actionfield_set[] = {
3089	[VCAP_AFS_BASE_TYPE] = {
3090		.type_id = -1,
3091		.sw_per_item = 3,
3092		.sw_cnt = 4,
3093	},
3094};
3095
3096static const struct vcap_set es0_actionfield_set[] = {
3097	[VCAP_AFS_ES0] = {
3098		.type_id = -1,
3099		.sw_per_item = 1,
3100		.sw_cnt = 1,
3101	},
3102};
3103
3104static const struct vcap_set es2_actionfield_set[] = {
3105	[VCAP_AFS_BASE_TYPE] = {
3106		.type_id = -1,
3107		.sw_per_item = 3,
3108		.sw_cnt = 4,
3109	},
3110};
3111
3112/* actionfield_set map */
3113static const struct vcap_field *is0_actionfield_set_map[] = {
3114	[VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield,
3115	[VCAP_AFS_FULL] = is0_full_actionfield,
3116	[VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield,
3117};
3118
3119static const struct vcap_field *is2_actionfield_set_map[] = {
3120	[VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,
3121};
3122
3123static const struct vcap_field *es0_actionfield_set_map[] = {
3124	[VCAP_AFS_ES0] = es0_es0_actionfield,
3125};
3126
3127static const struct vcap_field *es2_actionfield_set_map[] = {
3128	[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,
3129};
3130
3131/* actionfield_set map size */
3132static int is0_actionfield_set_map_size[] = {
3133	[VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield),
3134	[VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield),
3135	[VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield),
3136};
3137
3138static int is2_actionfield_set_map_size[] = {
3139	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),
3140};
3141
3142static int es0_actionfield_set_map_size[] = {
3143	[VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield),
3144};
3145
3146static int es2_actionfield_set_map_size[] = {
3147	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),
3148};
3149
3150/* Type Groups */
3151static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = {
3152	{
3153		.offset = 0,
3154		.width = 5,
3155		.value = 16,
3156	},
3157	{
3158		.offset = 52,
3159		.width = 1,
3160		.value = 0,
3161	},
3162	{
3163		.offset = 104,
3164		.width = 2,
3165		.value = 0,
3166	},
3167	{
3168		.offset = 156,
3169		.width = 3,
3170		.value = 0,
3171	},
3172	{
3173		.offset = 208,
3174		.width = 2,
3175		.value = 0,
3176	},
3177	{
3178		.offset = 260,
3179		.width = 1,
3180		.value = 0,
3181	},
3182	{
3183		.offset = 312,
3184		.width = 4,
3185		.value = 0,
3186	},
3187	{
3188		.offset = 364,
3189		.width = 1,
3190		.value = 0,
3191	},
3192	{
3193		.offset = 416,
3194		.width = 2,
3195		.value = 0,
3196	},
3197	{
3198		.offset = 468,
3199		.width = 3,
3200		.value = 0,
3201	},
3202	{
3203		.offset = 520,
3204		.width = 2,
3205		.value = 0,
3206	},
3207	{
3208		.offset = 572,
3209		.width = 1,
3210		.value = 0,
3211	},
3212	{}
3213};
3214
3215static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = {
3216	{
3217		.offset = 0,
3218		.width = 4,
3219		.value = 8,
3220	},
3221	{
3222		.offset = 52,
3223		.width = 1,
3224		.value = 0,
3225	},
3226	{
3227		.offset = 104,
3228		.width = 2,
3229		.value = 0,
3230	},
3231	{
3232		.offset = 156,
3233		.width = 3,
3234		.value = 0,
3235	},
3236	{
3237		.offset = 208,
3238		.width = 2,
3239		.value = 0,
3240	},
3241	{
3242		.offset = 260,
3243		.width = 1,
3244		.value = 0,
3245	},
3246	{}
3247};
3248
3249static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = {
3250	{}
3251};
3252
3253static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = {
3254	{}
3255};
3256
3257static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = {
3258	{}
3259};
3260
3261static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = {
3262	{
3263		.offset = 0,
3264		.width = 3,
3265		.value = 4,
3266	},
3267	{
3268		.offset = 156,
3269		.width = 1,
3270		.value = 0,
3271	},
3272	{
3273		.offset = 312,
3274		.width = 2,
3275		.value = 0,
3276	},
3277	{
3278		.offset = 468,
3279		.width = 1,
3280		.value = 0,
3281	},
3282	{}
3283};
3284
3285static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = {
3286	{
3287		.offset = 0,
3288		.width = 2,
3289		.value = 2,
3290	},
3291	{
3292		.offset = 156,
3293		.width = 1,
3294		.value = 0,
3295	},
3296	{}
3297};
3298
3299static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = {
3300	{}
3301};
3302
3303static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {
3304	{}
3305};
3306
3307static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = {
3308	{}
3309};
3310
3311static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {
3312	{
3313		.offset = 0,
3314		.width = 3,
3315		.value = 4,
3316	},
3317	{
3318		.offset = 156,
3319		.width = 1,
3320		.value = 0,
3321	},
3322	{
3323		.offset = 312,
3324		.width = 2,
3325		.value = 0,
3326	},
3327	{
3328		.offset = 468,
3329		.width = 1,
3330		.value = 0,
3331	},
3332	{}
3333};
3334
3335static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = {
3336	{
3337		.offset = 0,
3338		.width = 2,
3339		.value = 2,
3340	},
3341	{
3342		.offset = 156,
3343		.width = 1,
3344		.value = 0,
3345	},
3346	{}
3347};
3348
3349static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = {
3350	{}
3351};
3352
3353static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = {
3354	{}
3355};
3356
3357static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = {
3358	[12] = is0_x12_keyfield_set_typegroups,
3359	[6] = is0_x6_keyfield_set_typegroups,
3360	[3] = is0_x3_keyfield_set_typegroups,
3361	[2] = is0_x2_keyfield_set_typegroups,
3362	[1] = is0_x1_keyfield_set_typegroups,
3363	[13] = NULL,
3364};
3365
3366static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {
3367	[12] = is2_x12_keyfield_set_typegroups,
3368	[6] = is2_x6_keyfield_set_typegroups,
3369	[3] = is2_x3_keyfield_set_typegroups,
3370	[1] = is2_x1_keyfield_set_typegroups,
3371	[13] = NULL,
3372};
3373
3374static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = {
3375	[1] = es0_x1_keyfield_set_typegroups,
3376	[2] = NULL,
3377};
3378
3379static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {
3380	[12] = es2_x12_keyfield_set_typegroups,
3381	[6] = es2_x6_keyfield_set_typegroups,
3382	[3] = es2_x3_keyfield_set_typegroups,
3383	[1] = es2_x1_keyfield_set_typegroups,
3384	[13] = NULL,
3385};
3386
3387static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = {
3388	{
3389		.offset = 0,
3390		.width = 3,
3391		.value = 4,
3392	},
3393	{
3394		.offset = 103,
3395		.width = 2,
3396		.value = 0,
3397	},
3398	{
3399		.offset = 206,
3400		.width = 2,
3401		.value = 0,
3402	},
3403	{}
3404};
3405
3406static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = {
3407	{
3408		.offset = 0,
3409		.width = 2,
3410		.value = 2,
3411	},
3412	{
3413		.offset = 103,
3414		.width = 1,
3415		.value = 0,
3416	},
3417	{}
3418};
3419
3420static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = {
3421	{
3422		.offset = 0,
3423		.width = 1,
3424		.value = 1,
3425	},
3426	{}
3427};
3428
3429static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = {
3430	{
3431		.offset = 0,
3432		.width = 2,
3433		.value = 2,
3434	},
3435	{
3436		.offset = 95,
3437		.width = 1,
3438		.value = 0,
3439	},
3440	{
3441		.offset = 190,
3442		.width = 1,
3443		.value = 0,
3444	},
3445	{}
3446};
3447
3448static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {
3449	{}
3450};
3451
3452static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = {
3453	{}
3454};
3455
3456static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {
3457	{
3458		.offset = 0,
3459		.width = 2,
3460		.value = 2,
3461	},
3462	{
3463		.offset = 19,
3464		.width = 1,
3465		.value = 0,
3466	},
3467	{
3468		.offset = 38,
3469		.width = 1,
3470		.value = 0,
3471	},
3472	{}
3473};
3474
3475static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = {
3476	{}
3477};
3478
3479static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = {
3480	[3] = is0_x3_actionfield_set_typegroups,
3481	[2] = is0_x2_actionfield_set_typegroups,
3482	[1] = is0_x1_actionfield_set_typegroups,
3483	[13] = NULL,
3484};
3485
3486static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {
3487	[3] = is2_x3_actionfield_set_typegroups,
3488	[1] = is2_x1_actionfield_set_typegroups,
3489	[13] = NULL,
3490};
3491
3492static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = {
3493	[1] = es0_x1_actionfield_set_typegroups,
3494	[2] = NULL,
3495};
3496
3497static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
3498	[3] = es2_x3_actionfield_set_typegroups,
3499	[1] = es2_x1_actionfield_set_typegroups,
3500	[13] = NULL,
3501};
3502
3503/* Keyfieldset names */
3504static const char * const vcap_keyfield_set_names[] = {
3505	[VCAP_KFS_NO_VALUE]                      =  "(None)",
3506	[VCAP_KFS_ARP]                           =  "VCAP_KFS_ARP",
3507	[VCAP_KFS_ETAG]                          =  "VCAP_KFS_ETAG",
3508	[VCAP_KFS_IP4_OTHER]                     =  "VCAP_KFS_IP4_OTHER",
3509	[VCAP_KFS_IP4_TCP_UDP]                   =  "VCAP_KFS_IP4_TCP_UDP",
3510	[VCAP_KFS_IP4_VID]                       =  "VCAP_KFS_IP4_VID",
3511	[VCAP_KFS_IP6_OTHER]                     =  "VCAP_KFS_IP6_OTHER",
3512	[VCAP_KFS_IP6_STD]                       =  "VCAP_KFS_IP6_STD",
3513	[VCAP_KFS_IP6_TCP_UDP]                   =  "VCAP_KFS_IP6_TCP_UDP",
3514	[VCAP_KFS_IP6_VID]                       =  "VCAP_KFS_IP6_VID",
3515	[VCAP_KFS_IP_7TUPLE]                     =  "VCAP_KFS_IP_7TUPLE",
3516	[VCAP_KFS_ISDX]                          =  "VCAP_KFS_ISDX",
3517	[VCAP_KFS_LL_FULL]                       =  "VCAP_KFS_LL_FULL",
3518	[VCAP_KFS_MAC_ETYPE]                     =  "VCAP_KFS_MAC_ETYPE",
3519	[VCAP_KFS_MAC_LLC]                       =  "VCAP_KFS_MAC_LLC",
3520	[VCAP_KFS_MAC_SNAP]                      =  "VCAP_KFS_MAC_SNAP",
3521	[VCAP_KFS_NORMAL_5TUPLE_IP4]             =  "VCAP_KFS_NORMAL_5TUPLE_IP4",
3522	[VCAP_KFS_NORMAL_7TUPLE]                 =  "VCAP_KFS_NORMAL_7TUPLE",
3523	[VCAP_KFS_OAM]                           =  "VCAP_KFS_OAM",
3524	[VCAP_KFS_PURE_5TUPLE_IP4]               =  "VCAP_KFS_PURE_5TUPLE_IP4",
3525	[VCAP_KFS_SMAC_SIP4]                     =  "VCAP_KFS_SMAC_SIP4",
3526	[VCAP_KFS_SMAC_SIP6]                     =  "VCAP_KFS_SMAC_SIP6",
3527};
3528
3529/* Actionfieldset names */
3530static const char * const vcap_actionfield_set_names[] = {
3531	[VCAP_AFS_NO_VALUE]                      =  "(None)",
3532	[VCAP_AFS_BASE_TYPE]                     =  "VCAP_AFS_BASE_TYPE",
3533	[VCAP_AFS_CLASSIFICATION]                =  "VCAP_AFS_CLASSIFICATION",
3534	[VCAP_AFS_CLASS_REDUCED]                 =  "VCAP_AFS_CLASS_REDUCED",
3535	[VCAP_AFS_ES0]                           =  "VCAP_AFS_ES0",
3536	[VCAP_AFS_FULL]                          =  "VCAP_AFS_FULL",
3537	[VCAP_AFS_SMAC_SIP]                      =  "VCAP_AFS_SMAC_SIP",
3538};
3539
3540/* Keyfield names */
3541static const char * const vcap_keyfield_names[] = {
3542	[VCAP_KF_NO_VALUE]                       =  "(None)",
3543	[VCAP_KF_8021BR_ECID_BASE]               =  "8021BR_ECID_BASE",
3544	[VCAP_KF_8021BR_ECID_EXT]                =  "8021BR_ECID_EXT",
3545	[VCAP_KF_8021BR_E_TAGGED]                =  "8021BR_E_TAGGED",
3546	[VCAP_KF_8021BR_GRP]                     =  "8021BR_GRP",
3547	[VCAP_KF_8021BR_IGR_ECID_BASE]           =  "8021BR_IGR_ECID_BASE",
3548	[VCAP_KF_8021BR_IGR_ECID_EXT]            =  "8021BR_IGR_ECID_EXT",
3549	[VCAP_KF_8021Q_DEI0]                     =  "8021Q_DEI0",
3550	[VCAP_KF_8021Q_DEI1]                     =  "8021Q_DEI1",
3551	[VCAP_KF_8021Q_DEI2]                     =  "8021Q_DEI2",
3552	[VCAP_KF_8021Q_DEI_CLS]                  =  "8021Q_DEI_CLS",
3553	[VCAP_KF_8021Q_PCP0]                     =  "8021Q_PCP0",
3554	[VCAP_KF_8021Q_PCP1]                     =  "8021Q_PCP1",
3555	[VCAP_KF_8021Q_PCP2]                     =  "8021Q_PCP2",
3556	[VCAP_KF_8021Q_PCP_CLS]                  =  "8021Q_PCP_CLS",
3557	[VCAP_KF_8021Q_TPID]                     =  "8021Q_TPID",
3558	[VCAP_KF_8021Q_TPID0]                    =  "8021Q_TPID0",
3559	[VCAP_KF_8021Q_TPID1]                    =  "8021Q_TPID1",
3560	[VCAP_KF_8021Q_TPID2]                    =  "8021Q_TPID2",
3561	[VCAP_KF_8021Q_VID0]                     =  "8021Q_VID0",
3562	[VCAP_KF_8021Q_VID1]                     =  "8021Q_VID1",
3563	[VCAP_KF_8021Q_VID2]                     =  "8021Q_VID2",
3564	[VCAP_KF_8021Q_VID_CLS]                  =  "8021Q_VID_CLS",
3565	[VCAP_KF_8021Q_VLAN_TAGGED_IS]           =  "8021Q_VLAN_TAGGED_IS",
3566	[VCAP_KF_8021Q_VLAN_TAGS]                =  "8021Q_VLAN_TAGS",
3567	[VCAP_KF_ACL_GRP_ID]                     =  "ACL_GRP_ID",
3568	[VCAP_KF_ARP_ADDR_SPACE_OK_IS]           =  "ARP_ADDR_SPACE_OK_IS",
3569	[VCAP_KF_ARP_LEN_OK_IS]                  =  "ARP_LEN_OK_IS",
3570	[VCAP_KF_ARP_OPCODE]                     =  "ARP_OPCODE",
3571	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS]          =  "ARP_OPCODE_UNKNOWN_IS",
3572	[VCAP_KF_ARP_PROTO_SPACE_OK_IS]          =  "ARP_PROTO_SPACE_OK_IS",
3573	[VCAP_KF_ARP_SENDER_MATCH_IS]            =  "ARP_SENDER_MATCH_IS",
3574	[VCAP_KF_ARP_TGT_MATCH_IS]               =  "ARP_TGT_MATCH_IS",
3575	[VCAP_KF_COSID_CLS]                      =  "COSID_CLS",
3576	[VCAP_KF_ES0_ISDX_KEY_ENA]               =  "ES0_ISDX_KEY_ENA",
3577	[VCAP_KF_ETYPE]                          =  "ETYPE",
3578	[VCAP_KF_ETYPE_LEN_IS]                   =  "ETYPE_LEN_IS",
3579	[VCAP_KF_HOST_MATCH]                     =  "HOST_MATCH",
3580	[VCAP_KF_IF_EGR_PORT_MASK]               =  "IF_EGR_PORT_MASK",
3581	[VCAP_KF_IF_EGR_PORT_MASK_RNG]           =  "IF_EGR_PORT_MASK_RNG",
3582	[VCAP_KF_IF_EGR_PORT_NO]                 =  "IF_EGR_PORT_NO",
3583	[VCAP_KF_IF_IGR_PORT]                    =  "IF_IGR_PORT",
3584	[VCAP_KF_IF_IGR_PORT_MASK]               =  "IF_IGR_PORT_MASK",
3585	[VCAP_KF_IF_IGR_PORT_MASK_L3]            =  "IF_IGR_PORT_MASK_L3",
3586	[VCAP_KF_IF_IGR_PORT_MASK_RNG]           =  "IF_IGR_PORT_MASK_RNG",
3587	[VCAP_KF_IF_IGR_PORT_MASK_SEL]           =  "IF_IGR_PORT_MASK_SEL",
3588	[VCAP_KF_IF_IGR_PORT_SEL]                =  "IF_IGR_PORT_SEL",
3589	[VCAP_KF_IP4_IS]                         =  "IP4_IS",
3590	[VCAP_KF_IP_MC_IS]                       =  "IP_MC_IS",
3591	[VCAP_KF_IP_PAYLOAD_5TUPLE]              =  "IP_PAYLOAD_5TUPLE",
3592	[VCAP_KF_IP_SNAP_IS]                     =  "IP_SNAP_IS",
3593	[VCAP_KF_ISDX_CLS]                       =  "ISDX_CLS",
3594	[VCAP_KF_ISDX_GT0_IS]                    =  "ISDX_GT0_IS",
3595	[VCAP_KF_L2_BC_IS]                       =  "L2_BC_IS",
3596	[VCAP_KF_L2_DMAC]                        =  "L2_DMAC",
3597	[VCAP_KF_L2_FRM_TYPE]                    =  "L2_FRM_TYPE",
3598	[VCAP_KF_L2_FWD_IS]                      =  "L2_FWD_IS",
3599	[VCAP_KF_L2_LLC]                         =  "L2_LLC",
3600	[VCAP_KF_L2_MC_IS]                       =  "L2_MC_IS",
3601	[VCAP_KF_L2_PAYLOAD0]                    =  "L2_PAYLOAD0",
3602	[VCAP_KF_L2_PAYLOAD1]                    =  "L2_PAYLOAD1",
3603	[VCAP_KF_L2_PAYLOAD2]                    =  "L2_PAYLOAD2",
3604	[VCAP_KF_L2_PAYLOAD_ETYPE]               =  "L2_PAYLOAD_ETYPE",
3605	[VCAP_KF_L2_SMAC]                        =  "L2_SMAC",
3606	[VCAP_KF_L2_SNAP]                        =  "L2_SNAP",
3607	[VCAP_KF_L3_DIP_EQ_SIP_IS]               =  "L3_DIP_EQ_SIP_IS",
3608	[VCAP_KF_L3_DPL_CLS]                     =  "L3_DPL_CLS",
3609	[VCAP_KF_L3_DSCP]                        =  "L3_DSCP",
3610	[VCAP_KF_L3_DST_IS]                      =  "L3_DST_IS",
3611	[VCAP_KF_L3_FRAGMENT]                    =  "L3_FRAGMENT",
3612	[VCAP_KF_L3_FRAGMENT_TYPE]               =  "L3_FRAGMENT_TYPE",
3613	[VCAP_KF_L3_FRAG_INVLD_L4_LEN]           =  "L3_FRAG_INVLD_L4_LEN",
3614	[VCAP_KF_L3_FRAG_OFS_GT0]                =  "L3_FRAG_OFS_GT0",
3615	[VCAP_KF_L3_IP4_DIP]                     =  "L3_IP4_DIP",
3616	[VCAP_KF_L3_IP4_SIP]                     =  "L3_IP4_SIP",
3617	[VCAP_KF_L3_IP6_DIP]                     =  "L3_IP6_DIP",
3618	[VCAP_KF_L3_IP6_SIP]                     =  "L3_IP6_SIP",
3619	[VCAP_KF_L3_IP_PROTO]                    =  "L3_IP_PROTO",
3620	[VCAP_KF_L3_OPTIONS_IS]                  =  "L3_OPTIONS_IS",
3621	[VCAP_KF_L3_PAYLOAD]                     =  "L3_PAYLOAD",
3622	[VCAP_KF_L3_RT_IS]                       =  "L3_RT_IS",
3623	[VCAP_KF_L3_TOS]                         =  "L3_TOS",
3624	[VCAP_KF_L3_TTL_GT0]                     =  "L3_TTL_GT0",
3625	[VCAP_KF_L4_1588_DOM]                    =  "L4_1588_DOM",
3626	[VCAP_KF_L4_1588_VER]                    =  "L4_1588_VER",
3627	[VCAP_KF_L4_ACK]                         =  "L4_ACK",
3628	[VCAP_KF_L4_DPORT]                       =  "L4_DPORT",
3629	[VCAP_KF_L4_FIN]                         =  "L4_FIN",
3630	[VCAP_KF_L4_PAYLOAD]                     =  "L4_PAYLOAD",
3631	[VCAP_KF_L4_PSH]                         =  "L4_PSH",
3632	[VCAP_KF_L4_RNG]                         =  "L4_RNG",
3633	[VCAP_KF_L4_RST]                         =  "L4_RST",
3634	[VCAP_KF_L4_SEQUENCE_EQ0_IS]             =  "L4_SEQUENCE_EQ0_IS",
3635	[VCAP_KF_L4_SPORT]                       =  "L4_SPORT",
3636	[VCAP_KF_L4_SPORT_EQ_DPORT_IS]           =  "L4_SPORT_EQ_DPORT_IS",
3637	[VCAP_KF_L4_SYN]                         =  "L4_SYN",
3638	[VCAP_KF_L4_URG]                         =  "L4_URG",
3639	[VCAP_KF_LOOKUP_FIRST_IS]                =  "LOOKUP_FIRST_IS",
3640	[VCAP_KF_LOOKUP_GEN_IDX]                 =  "LOOKUP_GEN_IDX",
3641	[VCAP_KF_LOOKUP_GEN_IDX_SEL]             =  "LOOKUP_GEN_IDX_SEL",
3642	[VCAP_KF_LOOKUP_PAG]                     =  "LOOKUP_PAG",
3643	[VCAP_KF_MIRROR_PROBE]                   =  "MIRROR_PROBE",
3644	[VCAP_KF_OAM_CCM_CNTS_EQ0]               =  "OAM_CCM_CNTS_EQ0",
3645	[VCAP_KF_OAM_DETECTED]                   =  "OAM_DETECTED",
3646	[VCAP_KF_OAM_FLAGS]                      =  "OAM_FLAGS",
3647	[VCAP_KF_OAM_MEL_FLAGS]                  =  "OAM_MEL_FLAGS",
3648	[VCAP_KF_OAM_MEPID]                      =  "OAM_MEPID",
3649	[VCAP_KF_OAM_OPCODE]                     =  "OAM_OPCODE",
3650	[VCAP_KF_OAM_VER]                        =  "OAM_VER",
3651	[VCAP_KF_OAM_Y1731_IS]                   =  "OAM_Y1731_IS",
3652	[VCAP_KF_PROT_ACTIVE]                    =  "PROT_ACTIVE",
3653	[VCAP_KF_TCP_IS]                         =  "TCP_IS",
3654	[VCAP_KF_TCP_UDP_IS]                     =  "TCP_UDP_IS",
3655	[VCAP_KF_TYPE]                           =  "TYPE",
3656};
3657
3658/* Actionfield names */
3659static const char * const vcap_actionfield_names[] = {
3660	[VCAP_AF_NO_VALUE]                       =  "(None)",
3661	[VCAP_AF_ACL_ID]                         =  "ACL_ID",
3662	[VCAP_AF_CLS_VID_SEL]                    =  "CLS_VID_SEL",
3663	[VCAP_AF_CNT_ID]                         =  "CNT_ID",
3664	[VCAP_AF_COPY_PORT_NUM]                  =  "COPY_PORT_NUM",
3665	[VCAP_AF_COPY_QUEUE_NUM]                 =  "COPY_QUEUE_NUM",
3666	[VCAP_AF_CPU_COPY_ENA]                   =  "CPU_COPY_ENA",
3667	[VCAP_AF_CPU_QU]                         =  "CPU_QU",
3668	[VCAP_AF_CPU_QUEUE_NUM]                  =  "CPU_QUEUE_NUM",
3669	[VCAP_AF_DEI_A_VAL]                      =  "DEI_A_VAL",
3670	[VCAP_AF_DEI_B_VAL]                      =  "DEI_B_VAL",
3671	[VCAP_AF_DEI_C_VAL]                      =  "DEI_C_VAL",
3672	[VCAP_AF_DEI_ENA]                        =  "DEI_ENA",
3673	[VCAP_AF_DEI_VAL]                        =  "DEI_VAL",
3674	[VCAP_AF_DP_ENA]                         =  "DP_ENA",
3675	[VCAP_AF_DP_VAL]                         =  "DP_VAL",
3676	[VCAP_AF_DSCP_ENA]                       =  "DSCP_ENA",
3677	[VCAP_AF_DSCP_SEL]                       =  "DSCP_SEL",
3678	[VCAP_AF_DSCP_VAL]                       =  "DSCP_VAL",
3679	[VCAP_AF_ES2_REW_CMD]                    =  "ES2_REW_CMD",
3680	[VCAP_AF_ESDX]                           =  "ESDX",
3681	[VCAP_AF_FWD_KILL_ENA]                   =  "FWD_KILL_ENA",
3682	[VCAP_AF_FWD_MODE]                       =  "FWD_MODE",
3683	[VCAP_AF_FWD_SEL]                        =  "FWD_SEL",
3684	[VCAP_AF_HIT_ME_ONCE]                    =  "HIT_ME_ONCE",
3685	[VCAP_AF_HOST_MATCH]                     =  "HOST_MATCH",
3686	[VCAP_AF_IGNORE_PIPELINE_CTRL]           =  "IGNORE_PIPELINE_CTRL",
3687	[VCAP_AF_INTR_ENA]                       =  "INTR_ENA",
3688	[VCAP_AF_ISDX_ADD_REPLACE_SEL]           =  "ISDX_ADD_REPLACE_SEL",
3689	[VCAP_AF_ISDX_ENA]                       =  "ISDX_ENA",
3690	[VCAP_AF_ISDX_VAL]                       =  "ISDX_VAL",
3691	[VCAP_AF_LOOP_ENA]                       =  "LOOP_ENA",
3692	[VCAP_AF_LRN_DIS]                        =  "LRN_DIS",
3693	[VCAP_AF_MAP_IDX]                        =  "MAP_IDX",
3694	[VCAP_AF_MAP_KEY]                        =  "MAP_KEY",
3695	[VCAP_AF_MAP_LOOKUP_SEL]                 =  "MAP_LOOKUP_SEL",
3696	[VCAP_AF_MASK_MODE]                      =  "MASK_MODE",
3697	[VCAP_AF_MATCH_ID]                       =  "MATCH_ID",
3698	[VCAP_AF_MATCH_ID_MASK]                  =  "MATCH_ID_MASK",
3699	[VCAP_AF_MIRROR_ENA]                     =  "MIRROR_ENA",
3700	[VCAP_AF_MIRROR_PROBE]                   =  "MIRROR_PROBE",
3701	[VCAP_AF_MIRROR_PROBE_ID]                =  "MIRROR_PROBE_ID",
3702	[VCAP_AF_NXT_IDX]                        =  "NXT_IDX",
3703	[VCAP_AF_NXT_IDX_CTRL]                   =  "NXT_IDX_CTRL",
3704	[VCAP_AF_PAG_OVERRIDE_MASK]              =  "PAG_OVERRIDE_MASK",
3705	[VCAP_AF_PAG_VAL]                        =  "PAG_VAL",
3706	[VCAP_AF_PCP_A_VAL]                      =  "PCP_A_VAL",
3707	[VCAP_AF_PCP_B_VAL]                      =  "PCP_B_VAL",
3708	[VCAP_AF_PCP_C_VAL]                      =  "PCP_C_VAL",
3709	[VCAP_AF_PCP_ENA]                        =  "PCP_ENA",
3710	[VCAP_AF_PCP_VAL]                        =  "PCP_VAL",
3711	[VCAP_AF_PIPELINE_ACT]                   =  "PIPELINE_ACT",
3712	[VCAP_AF_PIPELINE_FORCE_ENA]             =  "PIPELINE_FORCE_ENA",
3713	[VCAP_AF_PIPELINE_PT]                    =  "PIPELINE_PT",
3714	[VCAP_AF_POLICE_ENA]                     =  "POLICE_ENA",
3715	[VCAP_AF_POLICE_IDX]                     =  "POLICE_IDX",
3716	[VCAP_AF_POLICE_REMARK]                  =  "POLICE_REMARK",
3717	[VCAP_AF_POLICE_VCAP_ONLY]               =  "POLICE_VCAP_ONLY",
3718	[VCAP_AF_POP_VAL]                        =  "POP_VAL",
3719	[VCAP_AF_PORT_MASK]                      =  "PORT_MASK",
3720	[VCAP_AF_PUSH_CUSTOMER_TAG]              =  "PUSH_CUSTOMER_TAG",
3721	[VCAP_AF_PUSH_INNER_TAG]                 =  "PUSH_INNER_TAG",
3722	[VCAP_AF_PUSH_OUTER_TAG]                 =  "PUSH_OUTER_TAG",
3723	[VCAP_AF_QOS_ENA]                        =  "QOS_ENA",
3724	[VCAP_AF_QOS_VAL]                        =  "QOS_VAL",
3725	[VCAP_AF_REW_OP]                         =  "REW_OP",
3726	[VCAP_AF_RT_DIS]                         =  "RT_DIS",
3727	[VCAP_AF_SWAP_MACS_ENA]                  =  "SWAP_MACS_ENA",
3728	[VCAP_AF_TAG_A_DEI_SEL]                  =  "TAG_A_DEI_SEL",
3729	[VCAP_AF_TAG_A_PCP_SEL]                  =  "TAG_A_PCP_SEL",
3730	[VCAP_AF_TAG_A_TPID_SEL]                 =  "TAG_A_TPID_SEL",
3731	[VCAP_AF_TAG_A_VID_SEL]                  =  "TAG_A_VID_SEL",
3732	[VCAP_AF_TAG_B_DEI_SEL]                  =  "TAG_B_DEI_SEL",
3733	[VCAP_AF_TAG_B_PCP_SEL]                  =  "TAG_B_PCP_SEL",
3734	[VCAP_AF_TAG_B_TPID_SEL]                 =  "TAG_B_TPID_SEL",
3735	[VCAP_AF_TAG_B_VID_SEL]                  =  "TAG_B_VID_SEL",
3736	[VCAP_AF_TAG_C_DEI_SEL]                  =  "TAG_C_DEI_SEL",
3737	[VCAP_AF_TAG_C_PCP_SEL]                  =  "TAG_C_PCP_SEL",
3738	[VCAP_AF_TAG_C_TPID_SEL]                 =  "TAG_C_TPID_SEL",
3739	[VCAP_AF_TAG_C_VID_SEL]                  =  "TAG_C_VID_SEL",
3740	[VCAP_AF_TYPE]                           =  "TYPE",
3741	[VCAP_AF_UNTAG_VID_ENA]                  =  "UNTAG_VID_ENA",
3742	[VCAP_AF_VID_A_VAL]                      =  "VID_A_VAL",
3743	[VCAP_AF_VID_B_VAL]                      =  "VID_B_VAL",
3744	[VCAP_AF_VID_C_VAL]                      =  "VID_C_VAL",
3745	[VCAP_AF_VID_VAL]                        =  "VID_VAL",
3746};
3747
3748/* VCAPs */
3749const struct vcap_info lan969x_vcaps[] = {
3750	[VCAP_TYPE_IS0] = {
3751		.name = "is0",
3752		.rows = 256,
3753		.sw_count = 12,
3754		.sw_width = 52,
3755		.sticky_width = 1,
3756		.act_width = 103,
3757		.default_cnt = 70,
3758		.require_cnt_dis = 0,
3759		.version = 1,
3760		.keyfield_set = is0_keyfield_set,
3761		.keyfield_set_size = ARRAY_SIZE(is0_keyfield_set),
3762		.actionfield_set = is0_actionfield_set,
3763		.actionfield_set_size = ARRAY_SIZE(is0_actionfield_set),
3764		.keyfield_set_map = is0_keyfield_set_map,
3765		.keyfield_set_map_size = is0_keyfield_set_map_size,
3766		.actionfield_set_map = is0_actionfield_set_map,
3767		.actionfield_set_map_size = is0_actionfield_set_map_size,
3768		.keyfield_set_typegroups = is0_keyfield_set_typegroups,
3769		.actionfield_set_typegroups = is0_actionfield_set_typegroups,
3770	},
3771	[VCAP_TYPE_IS2] = {
3772		.name = "is2",
3773		.rows = 256,
3774		.sw_count = 12,
3775		.sw_width = 52,
3776		.sticky_width = 1,
3777		.act_width = 103,
3778		.default_cnt = 38,
3779		.require_cnt_dis = 0,
3780		.version = 1,
3781		.keyfield_set = is2_keyfield_set,
3782		.keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),
3783		.actionfield_set = is2_actionfield_set,
3784		.actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),
3785		.keyfield_set_map = is2_keyfield_set_map,
3786		.keyfield_set_map_size = is2_keyfield_set_map_size,
3787		.actionfield_set_map = is2_actionfield_set_map,
3788		.actionfield_set_map_size = is2_actionfield_set_map_size,
3789		.keyfield_set_typegroups = is2_keyfield_set_typegroups,
3790		.actionfield_set_typegroups = is2_actionfield_set_typegroups,
3791	},
3792	[VCAP_TYPE_ES0] = {
3793		.name = "es0",
3794		.rows = 1536,
3795		.sw_count = 1,
3796		.sw_width = 51,
3797		.sticky_width = 1,
3798		.act_width = 469,
3799		.default_cnt = 35,
3800		.require_cnt_dis = 0,
3801		.version = 1,
3802		.keyfield_set = es0_keyfield_set,
3803		.keyfield_set_size = ARRAY_SIZE(es0_keyfield_set),
3804		.actionfield_set = es0_actionfield_set,
3805		.actionfield_set_size = ARRAY_SIZE(es0_actionfield_set),
3806		.keyfield_set_map = es0_keyfield_set_map,
3807		.keyfield_set_map_size = es0_keyfield_set_map_size,
3808		.actionfield_set_map = es0_actionfield_set_map,
3809		.actionfield_set_map_size = es0_actionfield_set_map_size,
3810		.keyfield_set_typegroups = es0_keyfield_set_typegroups,
3811		.actionfield_set_typegroups = es0_actionfield_set_typegroups,
3812	},
3813	[VCAP_TYPE_ES2] = {
3814		.name = "es2",
3815		.rows = 256,
3816		.sw_count = 12,
3817		.sw_width = 52,
3818		.sticky_width = 1,
3819		.act_width = 19,
3820		.default_cnt = 39,
3821		.require_cnt_dis = 0,
3822		.version = 1,
3823		.keyfield_set = es2_keyfield_set,
3824		.keyfield_set_size = ARRAY_SIZE(es2_keyfield_set),
3825		.actionfield_set = es2_actionfield_set,
3826		.actionfield_set_size = ARRAY_SIZE(es2_actionfield_set),
3827		.keyfield_set_map = es2_keyfield_set_map,
3828		.keyfield_set_map_size = es2_keyfield_set_map_size,
3829		.actionfield_set_map = es2_actionfield_set_map,
3830		.actionfield_set_map_size = es2_actionfield_set_map_size,
3831		.keyfield_set_typegroups = es2_keyfield_set_typegroups,
3832		.actionfield_set_typegroups = es2_actionfield_set_typegroups,
3833	},
3834};
3835
3836const struct vcap_statistics lan969x_vcap_stats = {
3837	.name = "lan969x",
3838	.count = 4,
3839	.keyfield_set_names = vcap_keyfield_set_names,
3840	.actionfield_set_names = vcap_actionfield_set_names,
3841	.keyfield_names = vcap_keyfield_names,
3842	.actionfield_names = vcap_actionfield_names,
3843};