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spectrum.c
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linux-6.19.14/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/types.h> 7#include <linux/pci.h> 8#include <linux/netdevice.h> 9#include <linux/etherdevice.h> 10#include <linux/ethtool.h> 11#include <linux/slab.h> 12#include <linux/device.h> 13#include <linux/skbuff.h> 14#include <linux/if_vlan.h> 15#include <linux/if_bridge.h> 16#include <linux/workqueue.h> 17#include <linux/jiffies.h> 18#include <linux/bitops.h> 19#include <linux/list.h> 20#include <linux/notifier.h> 21#include <linux/dcbnl.h> 22#include <linux/inetdevice.h> 23#include <linux/netlink.h> 24#include <linux/jhash.h> 25#include <linux/log2.h> 26#include <linux/refcount.h> 27#include <linux/rhashtable.h> 28#include <net/switchdev.h> 29#include <net/pkt_cls.h> 30#include <net/netevent.h> 31#include <net/addrconf.h> 32#include <linux/ptp_classify.h> 33 34#include "spectrum.h" 35#include "pci.h" 36#include "core.h" 37#include "core_env.h" 38#include "reg.h" 39#include "port.h" 40#include "trap.h" 41#include "txheader.h" 42#include "spectrum_cnt.h" 43#include "spectrum_dpipe.h" 44#include "spectrum_acl_flex_actions.h" 45#include "spectrum_span.h" 46#include "spectrum_ptp.h" 47#include "spectrum_trap.h" 48 49#define MLXSW_SP_FWREV_MINOR 2010 50#define MLXSW_SP_FWREV_SUBMINOR 1006 51 52#define MLXSW_SP1_FWREV_MAJOR 13 53#define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 54 55static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 56 .major = MLXSW_SP1_FWREV_MAJOR, 57 .minor = MLXSW_SP_FWREV_MINOR, 58 .subminor = MLXSW_SP_FWREV_SUBMINOR, 59 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 60}; 61 62#define MLXSW_SP1_FW_FILENAME \ 63 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 64 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 65 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 66 67#define MLXSW_SP2_FWREV_MAJOR 29 68 69static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = { 70 .major = MLXSW_SP2_FWREV_MAJOR, 71 .minor = MLXSW_SP_FWREV_MINOR, 72 .subminor = MLXSW_SP_FWREV_SUBMINOR, 73}; 74 75#define MLXSW_SP2_FW_FILENAME \ 76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \ 77 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 78 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 79 80#define MLXSW_SP3_FWREV_MAJOR 30 81 82static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = { 83 .major = MLXSW_SP3_FWREV_MAJOR, 84 .minor = MLXSW_SP_FWREV_MINOR, 85 .subminor = MLXSW_SP_FWREV_SUBMINOR, 86}; 87 88#define MLXSW_SP3_FW_FILENAME \ 89 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \ 90 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 91 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 92 93#define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \ 94 "mellanox/lc_ini_bundle_" \ 95 __stringify(MLXSW_SP_FWREV_MINOR) "_" \ 96 __stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin" 97 98static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 99static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 100static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3"; 101static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4"; 102 103static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = { 104 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00 105}; 106static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = { 107 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00 108}; 109 110int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 111 unsigned int counter_index, bool clear, 112 u64 *packets, u64 *bytes) 113{ 114 enum mlxsw_reg_mgpc_opcode op = clear ? MLXSW_REG_MGPC_OPCODE_CLEAR : 115 MLXSW_REG_MGPC_OPCODE_NOP; 116 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 117 int err; 118 119 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, op, 120 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 121 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 122 if (err) 123 return err; 124 if (packets) 125 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 126 if (bytes) 127 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 128 return 0; 129} 130 131static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 132 unsigned int counter_index) 133{ 134 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 135 136 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 137 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 138 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 139} 140 141int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 142 unsigned int *p_counter_index) 143{ 144 int err; 145 146 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 147 p_counter_index); 148 if (err) 149 return err; 150 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 151 if (err) 152 goto err_counter_clear; 153 return 0; 154 155err_counter_clear: 156 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 157 *p_counter_index); 158 return err; 159} 160 161void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 162 unsigned int counter_index) 163{ 164 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 165 counter_index); 166} 167 168static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb) 169{ 170 unsigned int type; 171 172 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 173 return false; 174 175 type = ptp_classify_raw(skb); 176 return !!ptp_parse_header(skb, type); 177} 178 179static void mlxsw_sp_txhdr_info_data_init(struct mlxsw_core *mlxsw_core, 180 struct sk_buff *skb, 181 struct mlxsw_txhdr_info *txhdr_info) 182{ 183 /* Resource validation was done as part of PTP init. */ 184 u16 max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID); 185 186 txhdr_info->data = true; 187 txhdr_info->max_fid = max_fid; 188} 189 190static struct sk_buff * 191mlxsw_sp_vlan_tag_push(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb) 192{ 193 /* In some Spectrum ASICs, in order for PTP event packets to have their 194 * correction field correctly set on the egress port they must be 195 * transmitted as data packets. Such packets ingress the ASIC via the 196 * CPU port and must have a VLAN tag, as the CPU port is not configured 197 * with a PVID. Push the default VLAN (4095), which is configured as 198 * egress untagged on all the ports. 199 */ 200 if (skb_vlan_tagged(skb)) 201 return skb; 202 203 return vlan_insert_tag_set_proto(skb, htons(ETH_P_8021Q), 204 MLXSW_SP_DEFAULT_VID); 205} 206 207static struct sk_buff * 208mlxsw_sp_txhdr_preparations(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 209 struct mlxsw_txhdr_info *txhdr_info) 210{ 211 if (likely(!mlxsw_sp_skb_requires_ts(skb))) 212 return skb; 213 214 if (!mlxsw_sp->ptp_ops->tx_as_data) 215 return skb; 216 217 /* Special handling for PTP events that require a time stamp and cannot 218 * be transmitted as regular control packets. 219 */ 220 mlxsw_sp_txhdr_info_data_init(mlxsw_sp->core, skb, txhdr_info); 221 return mlxsw_sp_vlan_tag_push(mlxsw_sp, skb); 222} 223 224enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 225{ 226 switch (state) { 227 case BR_STATE_FORWARDING: 228 return MLXSW_REG_SPMS_STATE_FORWARDING; 229 case BR_STATE_LEARNING: 230 return MLXSW_REG_SPMS_STATE_LEARNING; 231 case BR_STATE_LISTENING: 232 case BR_STATE_DISABLED: 233 case BR_STATE_BLOCKING: 234 return MLXSW_REG_SPMS_STATE_DISCARDING; 235 default: 236 BUG(); 237 } 238} 239 240int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 241 u8 state) 242{ 243 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 244 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 245 char *spms_pl; 246 int err; 247 248 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 249 if (!spms_pl) 250 return -ENOMEM; 251 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 252 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 253 254 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 255 kfree(spms_pl); 256 return err; 257} 258 259static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 260{ 261 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 262 int err; 263 264 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 265 if (err) 266 return err; 267 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 268 return 0; 269} 270 271int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 272 bool is_up) 273{ 274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 275 char paos_pl[MLXSW_REG_PAOS_LEN]; 276 277 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 278 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 279 MLXSW_PORT_ADMIN_STATUS_DOWN); 280 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 281} 282 283static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 284 const unsigned char *addr) 285{ 286 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 287 char ppad_pl[MLXSW_REG_PPAD_LEN]; 288 289 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 290 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 291 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 292} 293 294static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 295{ 296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 297 298 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac, 299 mlxsw_sp_port->local_port); 300 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, 301 mlxsw_sp_port->dev->dev_addr); 302} 303 304static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 305{ 306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 307 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 308 309 mtu += MLXSW_PORT_ETH_FRAME_HDR; 310 311 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 312 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 313} 314 315static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, 316 u16 local_port, u8 swid) 317{ 318 char pspa_pl[MLXSW_REG_PSPA_LEN]; 319 320 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port); 321 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 322} 323 324int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 325{ 326 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 327 char svpe_pl[MLXSW_REG_SVPE_LEN]; 328 329 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 330 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 331} 332 333int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 334 bool learn_enable) 335{ 336 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 337 char *spvmlr_pl; 338 int err; 339 340 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 341 if (!spvmlr_pl) 342 return -ENOMEM; 343 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 344 learn_enable); 345 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 346 kfree(spvmlr_pl); 347 return err; 348} 349 350int mlxsw_sp_port_security_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 351{ 352 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 353 char spfsr_pl[MLXSW_REG_SPFSR_LEN]; 354 int err; 355 356 if (mlxsw_sp_port->security == enable) 357 return 0; 358 359 mlxsw_reg_spfsr_pack(spfsr_pl, mlxsw_sp_port->local_port, enable); 360 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spfsr), spfsr_pl); 361 if (err) 362 return err; 363 364 mlxsw_sp_port->security = enable; 365 return 0; 366} 367 368int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type) 369{ 370 switch (ethtype) { 371 case ETH_P_8021Q: 372 *p_sver_type = 0; 373 break; 374 case ETH_P_8021AD: 375 *p_sver_type = 1; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382} 383 384int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port, 385 u16 ethtype) 386{ 387 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 388 char spevet_pl[MLXSW_REG_SPEVET_LEN]; 389 u8 sver_type; 390 int err; 391 392 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 393 if (err) 394 return err; 395 396 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type); 397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl); 398} 399 400static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 401 u16 vid, u16 ethtype) 402{ 403 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 404 char spvid_pl[MLXSW_REG_SPVID_LEN]; 405 u8 sver_type; 406 int err; 407 408 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 409 if (err) 410 return err; 411 412 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid, 413 sver_type); 414 415 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 416} 417 418static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 419 bool allow) 420{ 421 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 422 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 423 424 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 425 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 426} 427 428int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 429 u16 ethtype) 430{ 431 int err; 432 433 if (!vid) { 434 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 435 if (err) 436 return err; 437 } else { 438 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype); 439 if (err) 440 return err; 441 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 442 if (err) 443 goto err_port_allow_untagged_set; 444 } 445 446 mlxsw_sp_port->pvid = vid; 447 return 0; 448 449err_port_allow_untagged_set: 450 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype); 451 return err; 452} 453 454static int 455mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 456{ 457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 458 char sspr_pl[MLXSW_REG_SSPR_LEN]; 459 460 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 461 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 462} 463 464static int 465mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp, 466 u16 local_port, char *pmlp_pl, 467 struct mlxsw_sp_port_mapping *port_mapping) 468{ 469 bool separate_rxtx; 470 u8 first_lane; 471 u8 slot_index; 472 u8 module; 473 u8 width; 474 int i; 475 476 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 477 slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0); 478 width = mlxsw_reg_pmlp_width_get(pmlp_pl); 479 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl); 480 first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 481 482 if (width && !is_power_of_2(width)) { 483 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n", 484 local_port); 485 return -EINVAL; 486 } 487 488 for (i = 0; i < width; i++) { 489 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) { 490 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n", 491 local_port); 492 return -EINVAL; 493 } 494 if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) { 495 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n", 496 local_port); 497 return -EINVAL; 498 } 499 if (separate_rxtx && 500 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != 501 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) { 502 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n", 503 local_port); 504 return -EINVAL; 505 } 506 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) { 507 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n", 508 local_port); 509 return -EINVAL; 510 } 511 } 512 513 port_mapping->module = module; 514 port_mapping->slot_index = slot_index; 515 port_mapping->width = width; 516 port_mapping->module_width = width; 517 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 518 return 0; 519} 520 521static int 522mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port, 523 struct mlxsw_sp_port_mapping *port_mapping) 524{ 525 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 526 int err; 527 528 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 529 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 530 if (err) 531 return err; 532 return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 533 pmlp_pl, port_mapping); 534} 535 536static int 537mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port, 538 const struct mlxsw_sp_port_mapping *port_mapping) 539{ 540 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 541 int i, err; 542 543 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index, 544 port_mapping->module); 545 546 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 547 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width); 548 for (i = 0; i < port_mapping->width; i++) { 549 mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i, 550 port_mapping->slot_index); 551 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module); 552 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */ 553 } 554 555 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 556 if (err) 557 goto err_pmlp_write; 558 return 0; 559 560err_pmlp_write: 561 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index, 562 port_mapping->module); 563 return err; 564} 565 566static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port, 567 u8 slot_index, u8 module) 568{ 569 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 570 571 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 572 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 573 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 574 mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module); 575} 576 577static int mlxsw_sp_port_open(struct net_device *dev) 578{ 579 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 580 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 581 int err; 582 583 err = mlxsw_env_module_port_up(mlxsw_sp->core, 584 mlxsw_sp_port->mapping.slot_index, 585 mlxsw_sp_port->mapping.module); 586 if (err) 587 return err; 588 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 589 if (err) 590 goto err_port_admin_status_set; 591 netif_start_queue(dev); 592 return 0; 593 594err_port_admin_status_set: 595 mlxsw_env_module_port_down(mlxsw_sp->core, 596 mlxsw_sp_port->mapping.slot_index, 597 mlxsw_sp_port->mapping.module); 598 return err; 599} 600 601static int mlxsw_sp_port_stop(struct net_device *dev) 602{ 603 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 605 606 netif_stop_queue(dev); 607 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 608 mlxsw_env_module_port_down(mlxsw_sp->core, 609 mlxsw_sp_port->mapping.slot_index, 610 mlxsw_sp_port->mapping.module); 611 return 0; 612} 613 614static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 615 struct net_device *dev) 616{ 617 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 618 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 619 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 620 struct mlxsw_txhdr_info txhdr_info = { 621 .tx_info.local_port = mlxsw_sp_port->local_port, 622 .tx_info.is_emad = false, 623 }; 624 u64 len; 625 int err; 626 627 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb)); 628 629 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &txhdr_info.tx_info)) 630 return NETDEV_TX_BUSY; 631 632 if (eth_skb_pad(skb)) { 633 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 634 return NETDEV_TX_OK; 635 } 636 637 skb = mlxsw_sp_txhdr_preparations(mlxsw_sp, skb, &txhdr_info); 638 if (!skb) { 639 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 640 return NETDEV_TX_OK; 641 } 642 643 /* TX header is consumed by HW on the way so we shouldn't count its 644 * bytes as being sent. 645 */ 646 len = skb->len - MLXSW_TXHDR_LEN; 647 648 /* Due to a race we might fail here because of a full queue. In that 649 * unlikely case we simply drop the packet. 650 */ 651 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &txhdr_info); 652 653 if (!err) { 654 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 655 u64_stats_update_begin(&pcpu_stats->syncp); 656 pcpu_stats->tx_packets++; 657 pcpu_stats->tx_bytes += len; 658 u64_stats_update_end(&pcpu_stats->syncp); 659 } else { 660 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 661 dev_kfree_skb_any(skb); 662 } 663 return NETDEV_TX_OK; 664} 665 666static void mlxsw_sp_set_rx_mode(struct net_device *dev) 667{ 668} 669 670static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 671{ 672 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 673 struct sockaddr *addr = p; 674 int err; 675 676 if (!is_valid_ether_addr(addr->sa_data)) 677 return -EADDRNOTAVAIL; 678 679 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 680 if (err) 681 return err; 682 eth_hw_addr_set(dev, addr->sa_data); 683 return 0; 684} 685 686static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 687{ 688 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 689 struct mlxsw_sp_hdroom orig_hdroom; 690 struct mlxsw_sp_hdroom hdroom; 691 int err; 692 693 orig_hdroom = *mlxsw_sp_port->hdroom; 694 695 hdroom = orig_hdroom; 696 hdroom.mtu = mtu; 697 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom); 698 699 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom); 700 if (err) { 701 netdev_err(dev, "Failed to configure port's headroom\n"); 702 return err; 703 } 704 705 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 706 if (err) 707 goto err_port_mtu_set; 708 WRITE_ONCE(dev->mtu, mtu); 709 return 0; 710 711err_port_mtu_set: 712 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom); 713 return err; 714} 715 716static int 717mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 718 struct rtnl_link_stats64 *stats) 719{ 720 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 721 struct mlxsw_sp_port_pcpu_stats *p; 722 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 723 u32 tx_dropped = 0; 724 unsigned int start; 725 int i; 726 727 for_each_possible_cpu(i) { 728 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 729 do { 730 start = u64_stats_fetch_begin(&p->syncp); 731 rx_packets = p->rx_packets; 732 rx_bytes = p->rx_bytes; 733 tx_packets = p->tx_packets; 734 tx_bytes = p->tx_bytes; 735 } while (u64_stats_fetch_retry(&p->syncp, start)); 736 737 stats->rx_packets += rx_packets; 738 stats->rx_bytes += rx_bytes; 739 stats->tx_packets += tx_packets; 740 stats->tx_bytes += tx_bytes; 741 /* tx_dropped is u32, updated without syncp protection. */ 742 tx_dropped += p->tx_dropped; 743 } 744 stats->tx_dropped = tx_dropped; 745 return 0; 746} 747 748static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 749{ 750 switch (attr_id) { 751 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 752 return true; 753 } 754 755 return false; 756} 757 758static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 759 void *sp) 760{ 761 switch (attr_id) { 762 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 763 return mlxsw_sp_port_get_sw_stats64(dev, sp); 764 } 765 766 return -EINVAL; 767} 768 769int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 770 int prio, char *ppcnt_pl) 771{ 772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 773 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 774 775 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 776 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 777} 778 779static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 780 struct rtnl_link_stats64 *stats) 781{ 782 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 783 int err; 784 785 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 786 0, ppcnt_pl); 787 if (err) 788 goto out; 789 790 stats->tx_packets = 791 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 792 stats->rx_packets = 793 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 794 stats->tx_bytes = 795 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 796 stats->rx_bytes = 797 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 798 stats->multicast = 799 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 800 801 stats->rx_crc_errors = 802 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 803 stats->rx_frame_errors = 804 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 805 806 stats->rx_length_errors = ( 807 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 808 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 809 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 810 811 stats->rx_errors = (stats->rx_crc_errors + 812 stats->rx_frame_errors + stats->rx_length_errors); 813 814out: 815 return err; 816} 817 818static void 819mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 820 struct mlxsw_sp_port_xstats *xstats) 821{ 822 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 823 int err, i; 824 825 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 826 ppcnt_pl); 827 if (!err) 828 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 829 830 for (i = 0; i < TC_MAX_QUEUE; i++) { 831 err = mlxsw_sp_port_get_stats_raw(dev, 832 MLXSW_REG_PPCNT_TC_CONG_CNT, 833 i, ppcnt_pl); 834 if (err) 835 goto tc_cnt; 836 837 xstats->wred_drop[i] = 838 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 839 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl); 840 841tc_cnt: 842 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 843 i, ppcnt_pl); 844 if (err) 845 continue; 846 847 xstats->backlog[i] = 848 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 849 xstats->tail_drop[i] = 850 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 851 } 852 853 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 854 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 855 i, ppcnt_pl); 856 if (err) 857 continue; 858 859 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 860 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 861 } 862} 863 864static void update_stats_cache(struct work_struct *work) 865{ 866 struct mlxsw_sp_port *mlxsw_sp_port = 867 container_of(work, struct mlxsw_sp_port, 868 periodic_hw_stats.update_dw.work); 869 870 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 871 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as 872 * necessary when port goes down. 873 */ 874 goto out; 875 876 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 877 &mlxsw_sp_port->periodic_hw_stats.stats); 878 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 879 &mlxsw_sp_port->periodic_hw_stats.xstats); 880 881out: 882 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 883 MLXSW_HW_STATS_UPDATE_TIME); 884} 885 886/* Return the stats from a cache that is updated periodically, 887 * as this function might get called in an atomic context. 888 */ 889static void 890mlxsw_sp_port_get_stats64(struct net_device *dev, 891 struct rtnl_link_stats64 *stats) 892{ 893 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 894 895 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 896} 897 898static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 899 u16 vid_begin, u16 vid_end, 900 bool is_member, bool untagged) 901{ 902 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 903 char *spvm_pl; 904 int err; 905 906 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 907 if (!spvm_pl) 908 return -ENOMEM; 909 910 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 911 vid_end, is_member, untagged); 912 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 913 kfree(spvm_pl); 914 return err; 915} 916 917int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 918 u16 vid_end, bool is_member, bool untagged) 919{ 920 u16 vid, vid_e; 921 int err; 922 923 for (vid = vid_begin; vid <= vid_end; 924 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 925 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 926 vid_end); 927 928 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 929 is_member, untagged); 930 if (err) 931 return err; 932 } 933 934 return 0; 935} 936 937static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port, 938 bool flush_default) 939{ 940 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 941 942 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 943 &mlxsw_sp_port->vlans_list, list) { 944 if (!flush_default && 945 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID) 946 continue; 947 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 948 } 949} 950 951static void 952mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 953{ 954 if (mlxsw_sp_port_vlan->bridge_port) 955 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 956 else if (mlxsw_sp_port_vlan->fid) 957 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 958} 959 960struct mlxsw_sp_port_vlan * 961mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 962{ 963 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 964 bool untagged = vid == MLXSW_SP_DEFAULT_VID; 965 int err; 966 967 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 968 if (mlxsw_sp_port_vlan) 969 return ERR_PTR(-EEXIST); 970 971 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 972 if (err) 973 return ERR_PTR(err); 974 975 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 976 if (!mlxsw_sp_port_vlan) { 977 err = -ENOMEM; 978 goto err_port_vlan_alloc; 979 } 980 981 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 982 mlxsw_sp_port_vlan->vid = vid; 983 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 984 985 return mlxsw_sp_port_vlan; 986 987err_port_vlan_alloc: 988 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 989 return ERR_PTR(err); 990} 991 992void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 993{ 994 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 995 u16 vid = mlxsw_sp_port_vlan->vid; 996 997 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan); 998 list_del(&mlxsw_sp_port_vlan->list); 999 kfree(mlxsw_sp_port_vlan); 1000 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1001} 1002 1003static int mlxsw_sp_port_add_vid(struct net_device *dev, 1004 __be16 __always_unused proto, u16 vid) 1005{ 1006 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1007 1008 /* VLAN 0 is added to HW filter when device goes up, but it is 1009 * reserved in our case, so simply return. 1010 */ 1011 if (!vid) 1012 return 0; 1013 1014 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid)); 1015} 1016 1017int mlxsw_sp_port_kill_vid(struct net_device *dev, 1018 __be16 __always_unused proto, u16 vid) 1019{ 1020 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1021 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1022 1023 /* VLAN 0 is removed from HW filter when device goes down, but 1024 * it is reserved in our case, so simply return. 1025 */ 1026 if (!vid) 1027 return 0; 1028 1029 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1030 if (!mlxsw_sp_port_vlan) 1031 return 0; 1032 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1033 1034 return 0; 1035} 1036 1037static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1038 struct flow_block_offload *f) 1039{ 1040 switch (f->binder_type) { 1041 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS: 1042 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true); 1043 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS: 1044 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false); 1045 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP: 1046 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f); 1047 case FLOW_BLOCK_BINDER_TYPE_RED_MARK: 1048 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f); 1049 default: 1050 return -EOPNOTSUPP; 1051 } 1052} 1053 1054static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1055 void *type_data) 1056{ 1057 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1058 1059 switch (type) { 1060 case TC_SETUP_BLOCK: 1061 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1062 case TC_SETUP_QDISC_RED: 1063 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1064 case TC_SETUP_QDISC_PRIO: 1065 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1066 case TC_SETUP_QDISC_ETS: 1067 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data); 1068 case TC_SETUP_QDISC_TBF: 1069 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data); 1070 case TC_SETUP_QDISC_FIFO: 1071 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data); 1072 default: 1073 return -EOPNOTSUPP; 1074 } 1075} 1076 1077static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1078{ 1079 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1080 1081 if (!enable) { 1082 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) || 1083 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) { 1084 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1085 return -EINVAL; 1086 } 1087 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block); 1088 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block); 1089 } else { 1090 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block); 1091 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block); 1092 } 1093 return 0; 1094} 1095 1096static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable) 1097{ 1098 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1099 char pplr_pl[MLXSW_REG_PPLR_LEN]; 1100 int err; 1101 1102 if (netif_running(dev)) 1103 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1104 1105 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable); 1106 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr), 1107 pplr_pl); 1108 1109 if (netif_running(dev)) 1110 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 1111 1112 return err; 1113} 1114 1115typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1116 1117static int mlxsw_sp_handle_feature(struct net_device *dev, 1118 netdev_features_t wanted_features, 1119 netdev_features_t feature, 1120 mlxsw_sp_feature_handler feature_handler) 1121{ 1122 netdev_features_t changes = wanted_features ^ dev->features; 1123 bool enable = !!(wanted_features & feature); 1124 int err; 1125 1126 if (!(changes & feature)) 1127 return 0; 1128 1129 err = feature_handler(dev, enable); 1130 if (err) { 1131 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1132 enable ? "Enable" : "Disable", &feature, err); 1133 return err; 1134 } 1135 1136 if (enable) 1137 dev->features |= feature; 1138 else 1139 dev->features &= ~feature; 1140 1141 return 0; 1142} 1143static int mlxsw_sp_set_features(struct net_device *dev, 1144 netdev_features_t features) 1145{ 1146 netdev_features_t oper_features = dev->features; 1147 int err = 0; 1148 1149 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1150 mlxsw_sp_feature_hw_tc); 1151 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK, 1152 mlxsw_sp_feature_loopback); 1153 1154 if (err) { 1155 dev->features = oper_features; 1156 return -EINVAL; 1157 } 1158 1159 return 0; 1160} 1161 1162static int mlxsw_sp_port_hwtstamp_set(struct net_device *dev, 1163 struct kernel_hwtstamp_config *config, 1164 struct netlink_ext_ack *extack) 1165{ 1166 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1167 1168 return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, 1169 config, extack); 1170} 1171 1172static int mlxsw_sp_port_hwtstamp_get(struct net_device *dev, 1173 struct kernel_hwtstamp_config *config) 1174{ 1175 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1176 1177 return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port, 1178 config); 1179} 1180 1181static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port) 1182{ 1183 struct kernel_hwtstamp_config config = {}; 1184 1185 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config, 1186 NULL); 1187} 1188 1189static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1190 .ndo_open = mlxsw_sp_port_open, 1191 .ndo_stop = mlxsw_sp_port_stop, 1192 .ndo_start_xmit = mlxsw_sp_port_xmit, 1193 .ndo_setup_tc = mlxsw_sp_setup_tc, 1194 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1195 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1196 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1197 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1198 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1199 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1200 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1201 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1202 .ndo_set_features = mlxsw_sp_set_features, 1203 .ndo_hwtstamp_get = mlxsw_sp_port_hwtstamp_get, 1204 .ndo_hwtstamp_set = mlxsw_sp_port_hwtstamp_set, 1205}; 1206 1207static int 1208mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port) 1209{ 1210 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1211 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper; 1212 const struct mlxsw_sp_port_type_speed_ops *ops; 1213 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1214 u32 eth_proto_cap_masked; 1215 int err; 1216 1217 ops = mlxsw_sp->port_type_speed_ops; 1218 1219 /* Set advertised speeds to speeds supported by both the driver 1220 * and the device. 1221 */ 1222 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1223 0, false); 1224 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1225 if (err) 1226 return err; 1227 1228 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, 1229 ð_proto_admin, ð_proto_oper); 1230 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap); 1231 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1232 eth_proto_cap_masked, 1233 mlxsw_sp_port->link.autoneg); 1234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1235} 1236 1237int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed) 1238{ 1239 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops; 1240 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1241 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1242 u32 eth_proto_oper; 1243 int err; 1244 1245 port_type_speed_ops = mlxsw_sp->port_type_speed_ops; 1246 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, 1247 mlxsw_sp_port->local_port, 0, 1248 false); 1249 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1250 if (err) 1251 return err; 1252 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL, 1253 ð_proto_oper); 1254 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper); 1255 return 0; 1256} 1257 1258int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 1259 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 1260 bool dwrr, u8 dwrr_weight) 1261{ 1262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1263 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1264 1265 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1266 next_index); 1267 mlxsw_reg_qeec_de_set(qeec_pl, true); 1268 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 1269 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 1270 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1271} 1272 1273int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 1274 enum mlxsw_reg_qeec_hr hr, u8 index, 1275 u8 next_index, u32 maxrate, u8 burst_size) 1276{ 1277 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1278 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1279 1280 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1281 next_index); 1282 mlxsw_reg_qeec_mase_set(qeec_pl, true); 1283 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 1284 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size); 1285 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1286} 1287 1288static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 1289 enum mlxsw_reg_qeec_hr hr, u8 index, 1290 u8 next_index, u32 minrate) 1291{ 1292 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1293 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1294 1295 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1296 next_index); 1297 mlxsw_reg_qeec_mise_set(qeec_pl, true); 1298 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 1299 1300 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1301} 1302 1303int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 1304 u8 switch_prio, u8 tclass) 1305{ 1306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1307 char qtct_pl[MLXSW_REG_QTCT_LEN]; 1308 1309 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 1310 tclass); 1311 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 1312} 1313 1314static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 1315{ 1316 int err, i; 1317 1318 /* Setup the elements hierarcy, so that each TC is linked to 1319 * one subgroup, which are all member in the same group. 1320 */ 1321 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1322 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0); 1323 if (err) 1324 return err; 1325 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1326 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1327 MLXSW_REG_QEEC_HR_SUBGROUP, i, 1328 0, false, 0); 1329 if (err) 1330 return err; 1331 } 1332 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1333 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1334 MLXSW_REG_QEEC_HR_TC, i, i, 1335 false, 0); 1336 if (err) 1337 return err; 1338 1339 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1340 MLXSW_REG_QEEC_HR_TC, 1341 i + 8, i, 1342 true, 100); 1343 if (err) 1344 return err; 1345 } 1346 1347 /* Make sure the max shaper is disabled in all hierarchies that support 1348 * it. Note that this disables ptps (PTP shaper), but that is intended 1349 * for the initial configuration. 1350 */ 1351 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1352 MLXSW_REG_QEEC_HR_PORT, 0, 0, 1353 MLXSW_REG_QEEC_MAS_DIS, 0); 1354 if (err) 1355 return err; 1356 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1357 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1358 MLXSW_REG_QEEC_HR_SUBGROUP, 1359 i, 0, 1360 MLXSW_REG_QEEC_MAS_DIS, 0); 1361 if (err) 1362 return err; 1363 } 1364 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1365 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1366 MLXSW_REG_QEEC_HR_TC, 1367 i, i, 1368 MLXSW_REG_QEEC_MAS_DIS, 0); 1369 if (err) 1370 return err; 1371 1372 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1373 MLXSW_REG_QEEC_HR_TC, 1374 i + 8, i, 1375 MLXSW_REG_QEEC_MAS_DIS, 0); 1376 if (err) 1377 return err; 1378 } 1379 1380 /* Configure the min shaper for multicast TCs. */ 1381 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1382 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 1383 MLXSW_REG_QEEC_HR_TC, 1384 i + 8, i, 1385 MLXSW_REG_QEEC_MIS_MIN); 1386 if (err) 1387 return err; 1388 } 1389 1390 /* Map all priorities to traffic class 0. */ 1391 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1392 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 1393 if (err) 1394 return err; 1395 } 1396 1397 return 0; 1398} 1399 1400static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 1401 bool enable) 1402{ 1403 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1404 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 1405 1406 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 1407 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 1408} 1409 1410static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port) 1411{ 1412 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1413 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1414 u8 module = mlxsw_sp_port->mapping.module; 1415 u64 overheat_counter; 1416 int err; 1417 1418 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index, 1419 module, &overheat_counter); 1420 if (err) 1421 return err; 1422 1423 mlxsw_sp_port->module_overheat_initial_val = overheat_counter; 1424 return 0; 1425} 1426 1427int 1428mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port, 1429 bool is_8021ad_tagged, 1430 bool is_8021q_tagged) 1431{ 1432 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1433 char spvc_pl[MLXSW_REG_SPVC_LEN]; 1434 1435 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port, 1436 is_8021ad_tagged, is_8021q_tagged); 1437 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl); 1438} 1439 1440static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp, 1441 u16 local_port, u8 *port_number, 1442 u8 *split_port_subnumber, 1443 u8 *slot_index) 1444{ 1445 char pllp_pl[MLXSW_REG_PLLP_LEN]; 1446 int err; 1447 1448 mlxsw_reg_pllp_pack(pllp_pl, local_port); 1449 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); 1450 if (err) 1451 return err; 1452 mlxsw_reg_pllp_unpack(pllp_pl, port_number, 1453 split_port_subnumber, slot_index); 1454 return 0; 1455} 1456 1457static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port, 1458 bool split, 1459 struct mlxsw_sp_port_mapping *port_mapping) 1460{ 1461 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1462 struct mlxsw_sp_port *mlxsw_sp_port; 1463 u32 lanes = port_mapping->width; 1464 u8 split_port_subnumber; 1465 struct net_device *dev; 1466 u8 port_number; 1467 u8 slot_index; 1468 bool splittable; 1469 int err; 1470 1471 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping); 1472 if (err) { 1473 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 1474 local_port); 1475 return err; 1476 } 1477 1478 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0); 1479 if (err) { 1480 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 1481 local_port); 1482 goto err_port_swid_set; 1483 } 1484 1485 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number, 1486 &split_port_subnumber, &slot_index); 1487 if (err) { 1488 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n", 1489 local_port); 1490 goto err_port_label_info_get; 1491 } 1492 1493 splittable = lanes > 1 && !split; 1494 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index, 1495 port_number, split, split_port_subnumber, 1496 splittable, lanes, mlxsw_sp->base_mac, 1497 sizeof(mlxsw_sp->base_mac)); 1498 if (err) { 1499 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 1500 local_port); 1501 goto err_core_port_init; 1502 } 1503 1504 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 1505 if (!dev) { 1506 err = -ENOMEM; 1507 goto err_alloc_etherdev; 1508 } 1509 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 1510 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp)); 1511 mlxsw_sp_port = netdev_priv(dev); 1512 mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port, 1513 mlxsw_sp_port, dev); 1514 mlxsw_sp_port->dev = dev; 1515 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1516 mlxsw_sp_port->local_port = local_port; 1517 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; 1518 mlxsw_sp_port->split = split; 1519 mlxsw_sp_port->mapping = *port_mapping; 1520 mlxsw_sp_port->link.autoneg = 1; 1521 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 1522 1523 mlxsw_sp_port->pcpu_stats = 1524 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 1525 if (!mlxsw_sp_port->pcpu_stats) { 1526 err = -ENOMEM; 1527 goto err_alloc_stats; 1528 } 1529 1530 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1531 &update_stats_cache); 1532 1533 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 1534 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 1535 1536 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 1537 if (err) { 1538 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 1539 mlxsw_sp_port->local_port); 1540 goto err_dev_addr_init; 1541 } 1542 1543 netif_carrier_off(dev); 1544 1545 dev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_FILTER | 1546 NETIF_F_HW_TC | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1547 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK | 1548 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1549 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1550 dev->lltx = true; 1551 dev->netns_immutable = true; 1552 1553 dev->min_mtu = ETH_MIN_MTU; 1554 dev->max_mtu = MLXSW_PORT_MAX_MTU - MLXSW_PORT_ETH_FRAME_HDR; 1555 1556 /* Each packet needs to have a Tx header (metadata) on top all other 1557 * headers. 1558 */ 1559 dev->needed_headroom = MLXSW_TXHDR_LEN; 1560 1561 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 1562 if (err) { 1563 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 1564 mlxsw_sp_port->local_port); 1565 goto err_port_system_port_mapping_set; 1566 } 1567 1568 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port); 1569 if (err) { 1570 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 1571 mlxsw_sp_port->local_port); 1572 goto err_port_speed_by_width_set; 1573 } 1574 1575 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port, 1576 &mlxsw_sp_port->max_speed); 1577 if (err) { 1578 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n", 1579 mlxsw_sp_port->local_port); 1580 goto err_max_speed_get; 1581 } 1582 1583 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 1584 if (err) { 1585 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 1586 mlxsw_sp_port->local_port); 1587 goto err_port_mtu_set; 1588 } 1589 1590 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1591 if (err) 1592 goto err_port_admin_status_set; 1593 1594 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 1595 if (err) { 1596 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 1597 mlxsw_sp_port->local_port); 1598 goto err_port_buffers_init; 1599 } 1600 1601 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 1602 if (err) { 1603 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 1604 mlxsw_sp_port->local_port); 1605 goto err_port_ets_init; 1606 } 1607 1608 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 1609 if (err) { 1610 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 1611 mlxsw_sp_port->local_port); 1612 goto err_port_tc_mc_mode; 1613 } 1614 1615 /* ETS and buffers must be initialized before DCB. */ 1616 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 1617 if (err) { 1618 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 1619 mlxsw_sp_port->local_port); 1620 goto err_port_dcb_init; 1621 } 1622 1623 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 1624 if (err) { 1625 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 1626 mlxsw_sp_port->local_port); 1627 goto err_port_fids_init; 1628 } 1629 1630 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 1631 if (err) { 1632 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 1633 mlxsw_sp_port->local_port); 1634 goto err_port_qdiscs_init; 1635 } 1636 1637 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false, 1638 false); 1639 if (err) { 1640 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n", 1641 mlxsw_sp_port->local_port); 1642 goto err_port_vlan_clear; 1643 } 1644 1645 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 1646 if (err) { 1647 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 1648 mlxsw_sp_port->local_port); 1649 goto err_port_nve_init; 1650 } 1651 1652 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 1653 ETH_P_8021Q); 1654 if (err) { 1655 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n", 1656 mlxsw_sp_port->local_port); 1657 goto err_port_pvid_set; 1658 } 1659 1660 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, 1661 MLXSW_SP_DEFAULT_VID); 1662 if (IS_ERR(mlxsw_sp_port_vlan)) { 1663 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 1664 mlxsw_sp_port->local_port); 1665 err = PTR_ERR(mlxsw_sp_port_vlan); 1666 goto err_port_vlan_create; 1667 } 1668 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan; 1669 1670 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat 1671 * only packets with 802.1q header as tagged packets. 1672 */ 1673 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true); 1674 if (err) { 1675 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n", 1676 local_port); 1677 goto err_port_vlan_classification_set; 1678 } 1679 1680 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw, 1681 mlxsw_sp->ptp_ops->shaper_work); 1682 1683 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 1684 1685 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port); 1686 if (err) { 1687 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n", 1688 mlxsw_sp_port->local_port); 1689 goto err_port_overheat_init_val_set; 1690 } 1691 1692 err = register_netdev(dev); 1693 if (err) { 1694 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 1695 mlxsw_sp_port->local_port); 1696 goto err_register_netdev; 1697 } 1698 1699 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 1700 return 0; 1701 1702err_register_netdev: 1703err_port_overheat_init_val_set: 1704 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1705err_port_vlan_classification_set: 1706 mlxsw_sp->ports[local_port] = NULL; 1707 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1708err_port_vlan_create: 1709err_port_pvid_set: 1710 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1711err_port_nve_init: 1712err_port_vlan_clear: 1713 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1714err_port_qdiscs_init: 1715 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1716err_port_fids_init: 1717 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1718err_port_dcb_init: 1719 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1720err_port_tc_mc_mode: 1721err_port_ets_init: 1722 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1723err_port_buffers_init: 1724err_port_admin_status_set: 1725err_port_mtu_set: 1726err_max_speed_get: 1727err_port_speed_by_width_set: 1728err_port_system_port_mapping_set: 1729err_dev_addr_init: 1730 free_percpu(mlxsw_sp_port->pcpu_stats); 1731err_alloc_stats: 1732 free_netdev(dev); 1733err_alloc_etherdev: 1734 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1735err_core_port_init: 1736err_port_label_info_get: 1737 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1738 MLXSW_PORT_SWID_DISABLED_PORT); 1739err_port_swid_set: 1740 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, 1741 port_mapping->slot_index, 1742 port_mapping->module); 1743 return err; 1744} 1745 1746static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1747{ 1748 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 1749 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1750 u8 module = mlxsw_sp_port->mapping.module; 1751 1752 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 1753 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw); 1754 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 1755 mlxsw_sp_port_ptp_clear(mlxsw_sp_port); 1756 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1757 mlxsw_sp->ports[local_port] = NULL; 1758 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); 1759 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1760 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1761 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1762 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1763 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1764 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1765 free_percpu(mlxsw_sp_port->pcpu_stats); 1766 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 1767 free_netdev(mlxsw_sp_port->dev); 1768 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1769 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1770 MLXSW_PORT_SWID_DISABLED_PORT); 1771 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module); 1772} 1773 1774static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp) 1775{ 1776 struct mlxsw_sp_port *mlxsw_sp_port; 1777 int err; 1778 1779 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL); 1780 if (!mlxsw_sp_port) 1781 return -ENOMEM; 1782 1783 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1784 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT; 1785 1786 err = mlxsw_core_cpu_port_init(mlxsw_sp->core, 1787 mlxsw_sp_port, 1788 mlxsw_sp->base_mac, 1789 sizeof(mlxsw_sp->base_mac)); 1790 if (err) { 1791 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n"); 1792 goto err_core_cpu_port_init; 1793 } 1794 1795 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port; 1796 return 0; 1797 1798err_core_cpu_port_init: 1799 kfree(mlxsw_sp_port); 1800 return err; 1801} 1802 1803static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp) 1804{ 1805 struct mlxsw_sp_port *mlxsw_sp_port = 1806 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT]; 1807 1808 mlxsw_core_cpu_port_fini(mlxsw_sp->core); 1809 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL; 1810 kfree(mlxsw_sp_port); 1811} 1812 1813static bool mlxsw_sp_local_port_valid(u16 local_port) 1814{ 1815 return local_port != MLXSW_PORT_CPU_PORT; 1816} 1817 1818static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1819{ 1820 if (!mlxsw_sp_local_port_valid(local_port)) 1821 return false; 1822 return mlxsw_sp->ports[local_port] != NULL; 1823} 1824 1825static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp, 1826 u16 local_port, bool enable) 1827{ 1828 char pmecr_pl[MLXSW_REG_PMECR_LEN]; 1829 1830 mlxsw_reg_pmecr_pack(pmecr_pl, local_port, 1831 enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT : 1832 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT); 1833 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl); 1834} 1835 1836struct mlxsw_sp_port_mapping_event { 1837 struct list_head list; 1838 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 1839}; 1840 1841static void mlxsw_sp_port_mapping_events_work(struct work_struct *work) 1842{ 1843 struct mlxsw_sp_port_mapping_event *event, *next_event; 1844 struct mlxsw_sp_port_mapping_events *events; 1845 struct mlxsw_sp_port_mapping port_mapping; 1846 struct mlxsw_sp *mlxsw_sp; 1847 struct devlink *devlink; 1848 LIST_HEAD(event_queue); 1849 u16 local_port; 1850 int err; 1851 1852 events = container_of(work, struct mlxsw_sp_port_mapping_events, work); 1853 mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events); 1854 devlink = priv_to_devlink(mlxsw_sp->core); 1855 1856 spin_lock_bh(&events->queue_lock); 1857 list_splice_init(&events->queue, &event_queue); 1858 spin_unlock_bh(&events->queue_lock); 1859 1860 list_for_each_entry_safe(event, next_event, &event_queue, list) { 1861 local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl); 1862 err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 1863 event->pmlp_pl, &port_mapping); 1864 if (err) 1865 goto out; 1866 1867 if (WARN_ON_ONCE(!port_mapping.width)) 1868 goto out; 1869 1870 devl_lock(devlink); 1871 1872 if (!mlxsw_sp_port_created(mlxsw_sp, local_port)) 1873 mlxsw_sp_port_create(mlxsw_sp, local_port, 1874 false, &port_mapping); 1875 else 1876 WARN_ON_ONCE(1); 1877 1878 devl_unlock(devlink); 1879 1880 mlxsw_sp->port_mapping[local_port] = port_mapping; 1881 1882out: 1883 kfree(event); 1884 } 1885} 1886 1887static void 1888mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg, 1889 char *pmlp_pl, void *priv) 1890{ 1891 struct mlxsw_sp_port_mapping_events *events; 1892 struct mlxsw_sp_port_mapping_event *event; 1893 struct mlxsw_sp *mlxsw_sp = priv; 1894 u16 local_port; 1895 1896 local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl); 1897 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 1898 return; 1899 1900 events = &mlxsw_sp->port_mapping_events; 1901 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1902 if (!event) 1903 return; 1904 memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl)); 1905 spin_lock(&events->queue_lock); 1906 list_add_tail(&event->list, &events->queue); 1907 spin_unlock(&events->queue_lock); 1908 mlxsw_core_schedule_work(&events->work); 1909} 1910 1911static void 1912__mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp) 1913{ 1914 struct mlxsw_sp_port_mapping_event *event, *next_event; 1915 struct mlxsw_sp_port_mapping_events *events; 1916 1917 events = &mlxsw_sp->port_mapping_events; 1918 1919 /* Caller needs to make sure that no new event is going to appear. */ 1920 cancel_work_sync(&events->work); 1921 list_for_each_entry_safe(event, next_event, &events->queue, list) { 1922 list_del(&event->list); 1923 kfree(event); 1924 } 1925} 1926 1927static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 1928{ 1929 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1930 int i; 1931 1932 for (i = 1; i < max_ports; i++) 1933 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 1934 /* Make sure all scheduled events are processed */ 1935 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 1936 1937 for (i = 1; i < max_ports; i++) 1938 if (mlxsw_sp_port_created(mlxsw_sp, i)) 1939 mlxsw_sp_port_remove(mlxsw_sp, i); 1940 mlxsw_sp_cpu_port_remove(mlxsw_sp); 1941 kfree(mlxsw_sp->ports); 1942 mlxsw_sp->ports = NULL; 1943} 1944 1945static void 1946mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core, 1947 bool (*selector)(void *priv, u16 local_port), 1948 void *priv) 1949{ 1950 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 1951 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core); 1952 int i; 1953 1954 for (i = 1; i < max_ports; i++) 1955 if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i)) 1956 mlxsw_sp_port_remove(mlxsw_sp, i); 1957} 1958 1959static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 1960{ 1961 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1962 struct mlxsw_sp_port_mapping_events *events; 1963 struct mlxsw_sp_port_mapping *port_mapping; 1964 size_t alloc_size; 1965 int i; 1966 int err; 1967 1968 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 1969 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 1970 if (!mlxsw_sp->ports) 1971 return -ENOMEM; 1972 1973 events = &mlxsw_sp->port_mapping_events; 1974 INIT_LIST_HEAD(&events->queue); 1975 spin_lock_init(&events->queue_lock); 1976 INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work); 1977 1978 for (i = 1; i < max_ports; i++) { 1979 err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true); 1980 if (err) 1981 goto err_event_enable; 1982 } 1983 1984 err = mlxsw_sp_cpu_port_create(mlxsw_sp); 1985 if (err) 1986 goto err_cpu_port_create; 1987 1988 for (i = 1; i < max_ports; i++) { 1989 port_mapping = &mlxsw_sp->port_mapping[i]; 1990 if (!port_mapping->width) 1991 continue; 1992 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping); 1993 if (err) 1994 goto err_port_create; 1995 } 1996 return 0; 1997 1998err_port_create: 1999 for (i--; i >= 1; i--) 2000 if (mlxsw_sp_port_created(mlxsw_sp, i)) 2001 mlxsw_sp_port_remove(mlxsw_sp, i); 2002 i = max_ports; 2003 mlxsw_sp_cpu_port_remove(mlxsw_sp); 2004err_cpu_port_create: 2005err_event_enable: 2006 for (i--; i >= 1; i--) 2007 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 2008 /* Make sure all scheduled events are processed */ 2009 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 2010 kfree(mlxsw_sp->ports); 2011 mlxsw_sp->ports = NULL; 2012 return err; 2013} 2014 2015static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp) 2016{ 2017 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2018 struct mlxsw_sp_port_mapping *port_mapping; 2019 int i; 2020 int err; 2021 2022 mlxsw_sp->port_mapping = kcalloc(max_ports, 2023 sizeof(struct mlxsw_sp_port_mapping), 2024 GFP_KERNEL); 2025 if (!mlxsw_sp->port_mapping) 2026 return -ENOMEM; 2027 2028 for (i = 1; i < max_ports; i++) { 2029 port_mapping = &mlxsw_sp->port_mapping[i]; 2030 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping); 2031 if (err) 2032 goto err_port_module_info_get; 2033 } 2034 return 0; 2035 2036err_port_module_info_get: 2037 kfree(mlxsw_sp->port_mapping); 2038 return err; 2039} 2040 2041static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp) 2042{ 2043 kfree(mlxsw_sp->port_mapping); 2044} 2045 2046static int 2047mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, 2048 struct mlxsw_sp_port_mapping *port_mapping, 2049 unsigned int count, const char *pmtdb_pl) 2050{ 2051 struct mlxsw_sp_port_mapping split_port_mapping; 2052 int err, i; 2053 2054 split_port_mapping = *port_mapping; 2055 split_port_mapping.width /= count; 2056 for (i = 0; i < count; i++) { 2057 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2058 2059 if (!mlxsw_sp_local_port_valid(s_local_port)) 2060 continue; 2061 2062 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port, 2063 true, &split_port_mapping); 2064 if (err) 2065 goto err_port_create; 2066 split_port_mapping.lane += split_port_mapping.width; 2067 } 2068 2069 return 0; 2070 2071err_port_create: 2072 for (i--; i >= 0; i--) { 2073 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2074 2075 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2076 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2077 } 2078 return err; 2079} 2080 2081static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 2082 unsigned int count, 2083 const char *pmtdb_pl) 2084{ 2085 struct mlxsw_sp_port_mapping *port_mapping; 2086 int i; 2087 2088 /* Go over original unsplit ports in the gap and recreate them. */ 2089 for (i = 0; i < count; i++) { 2090 u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2091 2092 port_mapping = &mlxsw_sp->port_mapping[local_port]; 2093 if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port)) 2094 continue; 2095 mlxsw_sp_port_create(mlxsw_sp, local_port, 2096 false, port_mapping); 2097 } 2098} 2099 2100static struct mlxsw_sp_port * 2101mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port) 2102{ 2103 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port]) 2104 return mlxsw_sp->ports[local_port]; 2105 return NULL; 2106} 2107 2108static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port, 2109 unsigned int count, 2110 struct netlink_ext_ack *extack) 2111{ 2112 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2113 struct mlxsw_sp_port_mapping port_mapping; 2114 struct mlxsw_sp_port *mlxsw_sp_port; 2115 enum mlxsw_reg_pmtdb_status status; 2116 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2117 int i; 2118 int err; 2119 2120 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2121 if (!mlxsw_sp_port) { 2122 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2123 local_port); 2124 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2125 return -EINVAL; 2126 } 2127 2128 if (mlxsw_sp_port->split) { 2129 NL_SET_ERR_MSG_MOD(extack, "Port is already split"); 2130 return -EINVAL; 2131 } 2132 2133 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2134 mlxsw_sp_port->mapping.module, 2135 mlxsw_sp_port->mapping.module_width / count, 2136 count); 2137 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2138 if (err) { 2139 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2140 return err; 2141 } 2142 2143 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl); 2144 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) { 2145 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration"); 2146 return -EINVAL; 2147 } 2148 2149 port_mapping = mlxsw_sp_port->mapping; 2150 2151 for (i = 0; i < count; i++) { 2152 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2153 2154 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2155 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2156 } 2157 2158 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping, 2159 count, pmtdb_pl); 2160 if (err) { 2161 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 2162 goto err_port_split_create; 2163 } 2164 2165 return 0; 2166 2167err_port_split_create: 2168 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2169 2170 return err; 2171} 2172 2173static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port, 2174 struct netlink_ext_ack *extack) 2175{ 2176 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2177 struct mlxsw_sp_port *mlxsw_sp_port; 2178 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2179 unsigned int count; 2180 int i; 2181 int err; 2182 2183 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2184 if (!mlxsw_sp_port) { 2185 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2186 local_port); 2187 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2188 return -EINVAL; 2189 } 2190 2191 if (!mlxsw_sp_port->split) { 2192 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 2193 return -EINVAL; 2194 } 2195 2196 count = mlxsw_sp_port->mapping.module_width / 2197 mlxsw_sp_port->mapping.width; 2198 2199 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2200 mlxsw_sp_port->mapping.module, 2201 mlxsw_sp_port->mapping.module_width / count, 2202 count); 2203 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2204 if (err) { 2205 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2206 return err; 2207 } 2208 2209 for (i = 0; i < count; i++) { 2210 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2211 2212 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2213 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2214 } 2215 2216 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2217 2218 return 0; 2219} 2220 2221static void 2222mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port) 2223{ 2224 int i; 2225 2226 for (i = 0; i < TC_MAX_QUEUE; i++) 2227 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0; 2228} 2229 2230static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 2231 char *pude_pl, void *priv) 2232{ 2233 struct mlxsw_sp *mlxsw_sp = priv; 2234 struct mlxsw_sp_port *mlxsw_sp_port; 2235 enum mlxsw_reg_pude_oper_status status; 2236 u16 local_port; 2237 2238 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 2239 2240 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 2241 return; 2242 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2243 if (!mlxsw_sp_port) 2244 return; 2245 2246 status = mlxsw_reg_pude_oper_status_get(pude_pl); 2247 if (status == MLXSW_PORT_OPER_STATUS_UP) { 2248 netdev_info(mlxsw_sp_port->dev, "link up\n"); 2249 netif_carrier_on(mlxsw_sp_port->dev); 2250 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0); 2251 } else { 2252 netdev_info(mlxsw_sp_port->dev, "link down\n"); 2253 netif_carrier_off(mlxsw_sp_port->dev); 2254 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port); 2255 } 2256} 2257 2258static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp, 2259 char *mtpptr_pl, bool ingress) 2260{ 2261 u16 local_port; 2262 u8 num_rec; 2263 int i; 2264 2265 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl); 2266 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl); 2267 for (i = 0; i < num_rec; i++) { 2268 u8 domain_number; 2269 u8 message_type; 2270 u16 sequence_id; 2271 u64 timestamp; 2272 2273 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type, 2274 &domain_number, &sequence_id, 2275 ×tamp); 2276 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port, 2277 message_type, domain_number, 2278 sequence_id, timestamp); 2279 } 2280} 2281 2282static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg, 2283 char *mtpptr_pl, void *priv) 2284{ 2285 struct mlxsw_sp *mlxsw_sp = priv; 2286 2287 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true); 2288} 2289 2290static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg, 2291 char *mtpptr_pl, void *priv) 2292{ 2293 struct mlxsw_sp *mlxsw_sp = priv; 2294 2295 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false); 2296} 2297 2298void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 2299 u16 local_port, void *priv) 2300{ 2301 struct mlxsw_sp *mlxsw_sp = priv; 2302 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2303 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 2304 2305 if (unlikely(!mlxsw_sp_port)) { 2306 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 2307 local_port); 2308 return; 2309 } 2310 2311 skb->dev = mlxsw_sp_port->dev; 2312 2313 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 2314 u64_stats_update_begin(&pcpu_stats->syncp); 2315 pcpu_stats->rx_packets++; 2316 pcpu_stats->rx_bytes += skb->len; 2317 u64_stats_update_end(&pcpu_stats->syncp); 2318 2319 skb->protocol = eth_type_trans(skb, skb->dev); 2320 napi_gro_receive(mlxsw_skb_cb(skb)->rx_md_info.napi, skb); 2321} 2322 2323static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port, 2324 void *priv) 2325{ 2326 skb->offload_fwd_mark = 1; 2327 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2328} 2329 2330static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb, 2331 u16 local_port, void *priv) 2332{ 2333 skb->offload_l3_fwd_mark = 1; 2334 skb->offload_fwd_mark = 1; 2335 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2336} 2337 2338void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 2339 u16 local_port) 2340{ 2341 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port); 2342} 2343 2344#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2345 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 2346 _is_ctrl, SP_##_trap_group, DISCARD) 2347 2348#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2349 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 2350 _is_ctrl, SP_##_trap_group, DISCARD) 2351 2352#define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2353 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \ 2354 _is_ctrl, SP_##_trap_group, DISCARD) 2355 2356#define MLXSW_SP_EVENTL(_func, _trap_id) \ 2357 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 2358 2359static const struct mlxsw_listener mlxsw_sp_listener[] = { 2360 /* Events */ 2361 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 2362 /* L2 traps */ 2363 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false), 2364 /* L3 traps */ 2365 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 2366 false), 2367 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 2368 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 2369 false), 2370 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD, 2371 ROUTER_EXP, false), 2372 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD, 2373 ROUTER_EXP, false), 2374 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD, 2375 ROUTER_EXP, false), 2376 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD, 2377 ROUTER_EXP, false), 2378 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_LINK_LOCAL, FORWARD, 2379 ROUTER_EXP, false), 2380 /* Multicast Router Traps */ 2381 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 2382 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 2383}; 2384 2385static const struct mlxsw_listener mlxsw_sp1_listener[] = { 2386 /* Events */ 2387 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0), 2388 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0), 2389}; 2390 2391static const struct mlxsw_listener mlxsw_sp2_listener[] = { 2392 /* Events */ 2393 MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE), 2394}; 2395 2396static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 2397{ 2398 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2399 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 2400 enum mlxsw_reg_qpcr_ir_units ir_units; 2401 int max_cpu_policers; 2402 bool is_bytes; 2403 u8 burst_size; 2404 u32 rate; 2405 int i, err; 2406 2407 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 2408 return -EIO; 2409 2410 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2411 2412 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 2413 for (i = 0; i < max_cpu_policers; i++) { 2414 is_bytes = false; 2415 switch (i) { 2416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2417 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2418 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2419 rate = 1024; 2420 burst_size = 7; 2421 break; 2422 default: 2423 continue; 2424 } 2425 2426 __set_bit(i, mlxsw_sp->trap->policers_usage); 2427 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 2428 burst_size); 2429 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 2430 if (err) 2431 return err; 2432 } 2433 2434 return 0; 2435} 2436 2437static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 2438{ 2439 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2440 enum mlxsw_reg_htgt_trap_group i; 2441 int max_cpu_policers; 2442 int max_trap_groups; 2443 u8 priority, tc; 2444 u16 policer_id; 2445 int err; 2446 2447 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 2448 return -EIO; 2449 2450 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 2451 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2452 2453 for (i = 0; i < max_trap_groups; i++) { 2454 policer_id = i; 2455 switch (i) { 2456 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2457 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2458 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2459 priority = 1; 2460 tc = 1; 2461 break; 2462 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 2463 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 2464 tc = MLXSW_REG_HTGT_DEFAULT_TC; 2465 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 2466 break; 2467 default: 2468 continue; 2469 } 2470 2471 if (max_cpu_policers <= policer_id && 2472 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 2473 return -EIO; 2474 2475 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 2476 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2477 if (err) 2478 return err; 2479 } 2480 2481 return 0; 2482} 2483 2484static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 2485{ 2486 struct mlxsw_sp_trap *trap; 2487 u64 max_policers; 2488 int err; 2489 2490 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS)) 2491 return -EIO; 2492 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS); 2493 trap = kzalloc(struct_size(trap, policers_usage, 2494 BITS_TO_LONGS(max_policers)), GFP_KERNEL); 2495 if (!trap) 2496 return -ENOMEM; 2497 trap->max_policers = max_policers; 2498 mlxsw_sp->trap = trap; 2499 2500 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 2501 if (err) 2502 goto err_cpu_policers_set; 2503 2504 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 2505 if (err) 2506 goto err_trap_groups_set; 2507 2508 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener, 2509 ARRAY_SIZE(mlxsw_sp_listener), 2510 mlxsw_sp); 2511 if (err) 2512 goto err_traps_register; 2513 2514 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners, 2515 mlxsw_sp->listeners_count, mlxsw_sp); 2516 if (err) 2517 goto err_extra_traps_init; 2518 2519 return 0; 2520 2521err_extra_traps_init: 2522 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2523 ARRAY_SIZE(mlxsw_sp_listener), 2524 mlxsw_sp); 2525err_traps_register: 2526err_trap_groups_set: 2527err_cpu_policers_set: 2528 kfree(trap); 2529 return err; 2530} 2531 2532static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 2533{ 2534 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners, 2535 mlxsw_sp->listeners_count, 2536 mlxsw_sp); 2537 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2538 ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp); 2539 kfree(mlxsw_sp->trap); 2540} 2541 2542static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp) 2543{ 2544 char sgcr_pl[MLXSW_REG_SGCR_LEN]; 2545 int err; 2546 2547 if (mlxsw_core_lag_mode(mlxsw_sp->core) != 2548 MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) 2549 return 0; 2550 2551 /* In DDD mode, which we by default use, each LAG entry is 8 PGT 2552 * entries. The LAG table address needs to be 8-aligned, but that ought 2553 * to be the case, since the LAG table is allocated first. 2554 */ 2555 err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base, 2556 mlxsw_sp->max_lag * 8); 2557 if (err) 2558 return err; 2559 if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) { 2560 err = -EINVAL; 2561 goto err_mid_alloc_range; 2562 } 2563 2564 mlxsw_reg_sgcr_pack(sgcr_pl, mlxsw_sp->lag_pgt_base); 2565 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sgcr), sgcr_pl); 2566 if (err) 2567 goto err_mid_alloc_range; 2568 2569 return 0; 2570 2571err_mid_alloc_range: 2572 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, 2573 mlxsw_sp->max_lag * 8); 2574 return err; 2575} 2576 2577static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp) 2578{ 2579 if (mlxsw_core_lag_mode(mlxsw_sp->core) != 2580 MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) 2581 return; 2582 2583 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, 2584 mlxsw_sp->max_lag * 8); 2585} 2586 2587#define MLXSW_SP_LAG_SEED_INIT 0xcafecafe 2588 2589struct mlxsw_sp_lag { 2590 struct net_device *dev; 2591 refcount_t ref_count; 2592 u16 lag_id; 2593}; 2594 2595static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 2596{ 2597 char slcr_pl[MLXSW_REG_SLCR_LEN]; 2598 u32 seed; 2599 int err; 2600 2601 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac), 2602 MLXSW_SP_LAG_SEED_INIT); 2603 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 2604 MLXSW_REG_SLCR_LAG_HASH_DMAC | 2605 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 2606 MLXSW_REG_SLCR_LAG_HASH_VLANID | 2607 MLXSW_REG_SLCR_LAG_HASH_SIP | 2608 MLXSW_REG_SLCR_LAG_HASH_DIP | 2609 MLXSW_REG_SLCR_LAG_HASH_SPORT | 2610 MLXSW_REG_SLCR_LAG_HASH_DPORT | 2611 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 2612 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 2613 if (err) 2614 return err; 2615 2616 err = mlxsw_core_max_lag(mlxsw_sp->core, &mlxsw_sp->max_lag); 2617 if (err) 2618 return err; 2619 2620 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 2621 return -EIO; 2622 2623 err = mlxsw_sp_lag_pgt_init(mlxsw_sp); 2624 if (err) 2625 return err; 2626 2627 mlxsw_sp->lags = kcalloc(mlxsw_sp->max_lag, sizeof(struct mlxsw_sp_lag), 2628 GFP_KERNEL); 2629 if (!mlxsw_sp->lags) { 2630 err = -ENOMEM; 2631 goto err_kcalloc; 2632 } 2633 2634 return 0; 2635 2636err_kcalloc: 2637 mlxsw_sp_lag_pgt_fini(mlxsw_sp); 2638 return err; 2639} 2640 2641static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 2642{ 2643 mlxsw_sp_lag_pgt_fini(mlxsw_sp); 2644 kfree(mlxsw_sp->lags); 2645} 2646 2647static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = { 2648 .clock_init = mlxsw_sp1_ptp_clock_init, 2649 .clock_fini = mlxsw_sp1_ptp_clock_fini, 2650 .init = mlxsw_sp1_ptp_init, 2651 .fini = mlxsw_sp1_ptp_fini, 2652 .receive = mlxsw_sp1_ptp_receive, 2653 .transmitted = mlxsw_sp1_ptp_transmitted, 2654 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get, 2655 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set, 2656 .shaper_work = mlxsw_sp1_ptp_shaper_work, 2657#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2658 .get_ts_info = mlxsw_sp1_ptp_get_ts_info, 2659#endif 2660 .get_stats_count = mlxsw_sp1_get_stats_count, 2661 .get_stats_strings = mlxsw_sp1_get_stats_strings, 2662 .get_stats = mlxsw_sp1_get_stats, 2663}; 2664 2665static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = { 2666 .clock_init = mlxsw_sp2_ptp_clock_init, 2667 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2668 .init = mlxsw_sp2_ptp_init, 2669 .fini = mlxsw_sp2_ptp_fini, 2670 .receive = mlxsw_sp2_ptp_receive, 2671 .transmitted = mlxsw_sp2_ptp_transmitted, 2672 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2673 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2674 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2675#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2676 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2677#endif 2678 .get_stats_count = mlxsw_sp2_get_stats_count, 2679 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2680 .get_stats = mlxsw_sp2_get_stats, 2681 .tx_as_data = true, 2682}; 2683 2684static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = { 2685 .clock_init = mlxsw_sp2_ptp_clock_init, 2686 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2687 .init = mlxsw_sp2_ptp_init, 2688 .fini = mlxsw_sp2_ptp_fini, 2689 .receive = mlxsw_sp2_ptp_receive, 2690 .transmitted = mlxsw_sp2_ptp_transmitted, 2691 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2692 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2693 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2694#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2695 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2696#endif 2697 .get_stats_count = mlxsw_sp2_get_stats_count, 2698 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2699 .get_stats = mlxsw_sp2_get_stats, 2700}; 2701 2702struct mlxsw_sp_sample_trigger_node { 2703 struct mlxsw_sp_sample_trigger trigger; 2704 struct mlxsw_sp_sample_params params; 2705 struct rhash_head ht_node; 2706 struct rcu_head rcu; 2707 refcount_t refcount; 2708}; 2709 2710static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = { 2711 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger), 2712 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node), 2713 .key_len = sizeof(struct mlxsw_sp_sample_trigger), 2714 .automatic_shrinking = true, 2715}; 2716 2717static void 2718mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key, 2719 const struct mlxsw_sp_sample_trigger *trigger) 2720{ 2721 memset(key, 0, sizeof(*key)); 2722 key->type = trigger->type; 2723 key->local_port = trigger->local_port; 2724} 2725 2726/* RCU read lock must be held */ 2727struct mlxsw_sp_sample_params * 2728mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp, 2729 const struct mlxsw_sp_sample_trigger *trigger) 2730{ 2731 struct mlxsw_sp_sample_trigger_node *trigger_node; 2732 struct mlxsw_sp_sample_trigger key; 2733 2734 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2735 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key, 2736 mlxsw_sp_sample_trigger_ht_params); 2737 if (!trigger_node) 2738 return NULL; 2739 2740 return &trigger_node->params; 2741} 2742 2743static int 2744mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp, 2745 const struct mlxsw_sp_sample_trigger *trigger, 2746 const struct mlxsw_sp_sample_params *params) 2747{ 2748 struct mlxsw_sp_sample_trigger_node *trigger_node; 2749 int err; 2750 2751 trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL); 2752 if (!trigger_node) 2753 return -ENOMEM; 2754 2755 trigger_node->trigger = *trigger; 2756 trigger_node->params = *params; 2757 refcount_set(&trigger_node->refcount, 1); 2758 2759 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht, 2760 &trigger_node->ht_node, 2761 mlxsw_sp_sample_trigger_ht_params); 2762 if (err) 2763 goto err_rhashtable_insert; 2764 2765 return 0; 2766 2767err_rhashtable_insert: 2768 kfree(trigger_node); 2769 return err; 2770} 2771 2772static void 2773mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp, 2774 struct mlxsw_sp_sample_trigger_node *trigger_node) 2775{ 2776 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht, 2777 &trigger_node->ht_node, 2778 mlxsw_sp_sample_trigger_ht_params); 2779 kfree_rcu(trigger_node, rcu); 2780} 2781 2782int 2783mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp, 2784 const struct mlxsw_sp_sample_trigger *trigger, 2785 const struct mlxsw_sp_sample_params *params, 2786 struct netlink_ext_ack *extack) 2787{ 2788 struct mlxsw_sp_sample_trigger_node *trigger_node; 2789 struct mlxsw_sp_sample_trigger key; 2790 2791 ASSERT_RTNL(); 2792 2793 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2794 2795 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2796 &key, 2797 mlxsw_sp_sample_trigger_ht_params); 2798 if (!trigger_node) 2799 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key, 2800 params); 2801 2802 if (trigger_node->trigger.local_port) { 2803 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port"); 2804 return -EINVAL; 2805 } 2806 2807 if (trigger_node->params.psample_group != params->psample_group || 2808 trigger_node->params.truncate != params->truncate || 2809 trigger_node->params.rate != params->rate || 2810 trigger_node->params.trunc_size != params->trunc_size) { 2811 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger"); 2812 return -EINVAL; 2813 } 2814 2815 refcount_inc(&trigger_node->refcount); 2816 2817 return 0; 2818} 2819 2820void 2821mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp, 2822 const struct mlxsw_sp_sample_trigger *trigger) 2823{ 2824 struct mlxsw_sp_sample_trigger_node *trigger_node; 2825 struct mlxsw_sp_sample_trigger key; 2826 2827 ASSERT_RTNL(); 2828 2829 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2830 2831 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2832 &key, 2833 mlxsw_sp_sample_trigger_ht_params); 2834 if (!trigger_node) 2835 return; 2836 2837 if (!refcount_dec_and_test(&trigger_node->refcount)) 2838 return; 2839 2840 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node); 2841} 2842 2843static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 2844 unsigned long event, void *ptr); 2845 2846#define MLXSW_SP_DEFAULT_PARSING_DEPTH 96 2847#define MLXSW_SP_INCREASED_PARSING_DEPTH 128 2848#define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789 2849 2850static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp) 2851{ 2852 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 0); 2853 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 2854 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT; 2855 mutex_init(&mlxsw_sp->parsing.lock); 2856} 2857 2858static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp) 2859{ 2860 mutex_destroy(&mlxsw_sp->parsing.lock); 2861 WARN_ON_ONCE(refcount_read(&mlxsw_sp->parsing.parsing_depth_ref)); 2862} 2863 2864struct mlxsw_sp_ipv6_addr_node { 2865 struct in6_addr key; 2866 struct rhash_head ht_node; 2867 u32 kvdl_index; 2868 refcount_t refcount; 2869}; 2870 2871static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = { 2872 .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key), 2873 .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node), 2874 .key_len = sizeof(struct in6_addr), 2875 .automatic_shrinking = true, 2876}; 2877 2878static int 2879mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6, 2880 u32 *p_kvdl_index) 2881{ 2882 struct mlxsw_sp_ipv6_addr_node *node; 2883 char rips_pl[MLXSW_REG_RIPS_LEN]; 2884 int err; 2885 2886 err = mlxsw_sp_kvdl_alloc(mlxsw_sp, 2887 MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2888 p_kvdl_index); 2889 if (err) 2890 return err; 2891 2892 mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6); 2893 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl); 2894 if (err) 2895 goto err_rips_write; 2896 2897 node = kzalloc(sizeof(*node), GFP_KERNEL); 2898 if (!node) { 2899 err = -ENOMEM; 2900 goto err_node_alloc; 2901 } 2902 2903 node->key = *addr6; 2904 node->kvdl_index = *p_kvdl_index; 2905 refcount_set(&node->refcount, 1); 2906 2907 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht, 2908 &node->ht_node, 2909 mlxsw_sp_ipv6_addr_ht_params); 2910 if (err) 2911 goto err_rhashtable_insert; 2912 2913 return 0; 2914 2915err_rhashtable_insert: 2916 kfree(node); 2917err_node_alloc: 2918err_rips_write: 2919 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2920 *p_kvdl_index); 2921 return err; 2922} 2923 2924static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp, 2925 struct mlxsw_sp_ipv6_addr_node *node) 2926{ 2927 u32 kvdl_index = node->kvdl_index; 2928 2929 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node, 2930 mlxsw_sp_ipv6_addr_ht_params); 2931 kfree(node); 2932 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2933 kvdl_index); 2934} 2935 2936int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp, 2937 const struct in6_addr *addr6, 2938 u32 *p_kvdl_index) 2939{ 2940 struct mlxsw_sp_ipv6_addr_node *node; 2941 int err = 0; 2942 2943 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2944 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2945 mlxsw_sp_ipv6_addr_ht_params); 2946 if (node) { 2947 refcount_inc(&node->refcount); 2948 *p_kvdl_index = node->kvdl_index; 2949 goto out_unlock; 2950 } 2951 2952 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index); 2953 2954out_unlock: 2955 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2956 return err; 2957} 2958 2959void 2960mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6) 2961{ 2962 struct mlxsw_sp_ipv6_addr_node *node; 2963 2964 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2965 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2966 mlxsw_sp_ipv6_addr_ht_params); 2967 if (WARN_ON(!node)) 2968 goto out_unlock; 2969 2970 if (!refcount_dec_and_test(&node->refcount)) 2971 goto out_unlock; 2972 2973 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node); 2974 2975out_unlock: 2976 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2977} 2978 2979static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp) 2980{ 2981 int err; 2982 2983 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht, 2984 &mlxsw_sp_ipv6_addr_ht_params); 2985 if (err) 2986 return err; 2987 2988 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock); 2989 return 0; 2990} 2991 2992static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp) 2993{ 2994 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock); 2995 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht); 2996} 2997 2998static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 2999 const struct mlxsw_bus_info *mlxsw_bus_info, 3000 struct netlink_ext_ack *extack) 3001{ 3002 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3003 int err; 3004 3005 mlxsw_sp->core = mlxsw_core; 3006 mlxsw_sp->bus_info = mlxsw_bus_info; 3007 3008 mlxsw_sp_parsing_init(mlxsw_sp); 3009 3010 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3011 if (err) { 3012 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3013 return err; 3014 } 3015 3016 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3017 if (err) { 3018 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3019 return err; 3020 } 3021 3022 err = mlxsw_sp_pgt_init(mlxsw_sp); 3023 if (err) { 3024 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n"); 3025 goto err_pgt_init; 3026 } 3027 3028 /* Initialize before FIDs so that the LAG table is at the start of PGT 3029 * and 8-aligned without overallocation. 3030 */ 3031 err = mlxsw_sp_lag_init(mlxsw_sp); 3032 if (err) { 3033 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3034 goto err_lag_init; 3035 } 3036 3037 err = mlxsw_sp->fid_core_ops->init(mlxsw_sp); 3038 if (err) { 3039 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3040 goto err_fid_core_init; 3041 } 3042 3043 err = mlxsw_sp_policers_init(mlxsw_sp); 3044 if (err) { 3045 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n"); 3046 goto err_policers_init; 3047 } 3048 3049 err = mlxsw_sp_traps_init(mlxsw_sp); 3050 if (err) { 3051 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3052 goto err_traps_init; 3053 } 3054 3055 err = mlxsw_sp_devlink_traps_init(mlxsw_sp); 3056 if (err) { 3057 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n"); 3058 goto err_devlink_traps_init; 3059 } 3060 3061 err = mlxsw_sp_buffers_init(mlxsw_sp); 3062 if (err) { 3063 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3064 goto err_buffers_init; 3065 } 3066 3067 /* Initialize SPAN before router and switchdev, so that those components 3068 * can call mlxsw_sp_span_respin(). 3069 */ 3070 err = mlxsw_sp_span_init(mlxsw_sp); 3071 if (err) { 3072 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3073 goto err_span_init; 3074 } 3075 3076 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3077 if (err) { 3078 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3079 goto err_switchdev_init; 3080 } 3081 3082 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3083 if (err) { 3084 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3085 goto err_counter_pool_init; 3086 } 3087 3088 err = mlxsw_sp_afa_init(mlxsw_sp); 3089 if (err) { 3090 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3091 goto err_afa_init; 3092 } 3093 3094 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp); 3095 if (err) { 3096 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n"); 3097 goto err_ipv6_addr_ht_init; 3098 } 3099 3100 err = mlxsw_sp_nve_init(mlxsw_sp); 3101 if (err) { 3102 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 3103 goto err_nve_init; 3104 } 3105 3106 err = mlxsw_sp_port_range_init(mlxsw_sp); 3107 if (err) { 3108 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize port ranges\n"); 3109 goto err_port_range_init; 3110 } 3111 3112 err = mlxsw_sp_acl_init(mlxsw_sp); 3113 if (err) { 3114 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3115 goto err_acl_init; 3116 } 3117 3118 err = mlxsw_sp_router_init(mlxsw_sp, extack); 3119 if (err) { 3120 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3121 goto err_router_init; 3122 } 3123 3124 if (mlxsw_sp->bus_info->read_clock_capable) { 3125 /* NULL is a valid return value from clock_init */ 3126 mlxsw_sp->clock = 3127 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp, 3128 mlxsw_sp->bus_info->dev); 3129 if (IS_ERR(mlxsw_sp->clock)) { 3130 err = PTR_ERR(mlxsw_sp->clock); 3131 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n"); 3132 goto err_ptp_clock_init; 3133 } 3134 } 3135 3136 if (mlxsw_sp->clock) { 3137 /* NULL is a valid return value from ptp_ops->init */ 3138 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp); 3139 if (IS_ERR(mlxsw_sp->ptp_state)) { 3140 err = PTR_ERR(mlxsw_sp->ptp_state); 3141 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n"); 3142 goto err_ptp_init; 3143 } 3144 } 3145 3146 /* Initialize netdevice notifier after SPAN is initialized, so that the 3147 * event handler can call SPAN respin. 3148 */ 3149 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3150 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3151 &mlxsw_sp->netdevice_nb); 3152 if (err) { 3153 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3154 goto err_netdev_notifier; 3155 } 3156 3157 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3158 if (err) { 3159 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3160 goto err_dpipe_init; 3161 } 3162 3163 err = mlxsw_sp_port_module_info_init(mlxsw_sp); 3164 if (err) { 3165 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n"); 3166 goto err_port_module_info_init; 3167 } 3168 3169 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht, 3170 &mlxsw_sp_sample_trigger_ht_params); 3171 if (err) { 3172 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n"); 3173 goto err_sample_trigger_init; 3174 } 3175 3176 err = mlxsw_sp_ports_create(mlxsw_sp); 3177 if (err) { 3178 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3179 goto err_ports_create; 3180 } 3181 3182 return 0; 3183 3184err_ports_create: 3185 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3186err_sample_trigger_init: 3187 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3188err_port_module_info_init: 3189 mlxsw_sp_dpipe_fini(mlxsw_sp); 3190err_dpipe_init: 3191 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3192 &mlxsw_sp->netdevice_nb); 3193err_netdev_notifier: 3194 if (mlxsw_sp->clock) 3195 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3196err_ptp_init: 3197 if (mlxsw_sp->clock) 3198 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3199err_ptp_clock_init: 3200 mlxsw_sp_router_fini(mlxsw_sp); 3201err_router_init: 3202 mlxsw_sp_acl_fini(mlxsw_sp); 3203err_acl_init: 3204 mlxsw_sp_port_range_fini(mlxsw_sp); 3205err_port_range_init: 3206 mlxsw_sp_nve_fini(mlxsw_sp); 3207err_nve_init: 3208 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3209err_ipv6_addr_ht_init: 3210 mlxsw_sp_afa_fini(mlxsw_sp); 3211err_afa_init: 3212 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3213err_counter_pool_init: 3214 mlxsw_sp_switchdev_fini(mlxsw_sp); 3215err_switchdev_init: 3216 mlxsw_sp_span_fini(mlxsw_sp); 3217err_span_init: 3218 mlxsw_sp_buffers_fini(mlxsw_sp); 3219err_buffers_init: 3220 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3221err_devlink_traps_init: 3222 mlxsw_sp_traps_fini(mlxsw_sp); 3223err_traps_init: 3224 mlxsw_sp_policers_fini(mlxsw_sp); 3225err_policers_init: 3226 mlxsw_sp->fid_core_ops->fini(mlxsw_sp); 3227err_fid_core_init: 3228 mlxsw_sp_lag_fini(mlxsw_sp); 3229err_lag_init: 3230 mlxsw_sp_pgt_fini(mlxsw_sp); 3231err_pgt_init: 3232 mlxsw_sp_kvdl_fini(mlxsw_sp); 3233 mlxsw_sp_parsing_fini(mlxsw_sp); 3234 return err; 3235} 3236 3237static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 3238 const struct mlxsw_bus_info *mlxsw_bus_info, 3239 struct netlink_ext_ack *extack) 3240{ 3241 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3242 3243 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops; 3244 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3245 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3246 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3247 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3248 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops; 3249 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3250 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 3251 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask; 3252 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals; 3253 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops; 3254 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops; 3255 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops; 3256 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops; 3257 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops; 3258 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops; 3259 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops; 3260 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops; 3261 mlxsw_sp->listeners = mlxsw_sp1_listener; 3262 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener); 3263 mlxsw_sp->fid_core_ops = &mlxsw_sp1_fid_core_ops; 3264 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1; 3265 mlxsw_sp->pgt_smpe_index_valid = true; 3266 3267 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3268} 3269 3270static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3271 const struct mlxsw_bus_info *mlxsw_bus_info, 3272 struct netlink_ext_ack *extack) 3273{ 3274 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3275 3276 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3277 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3278 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3279 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3280 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3281 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3282 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3283 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3284 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3285 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3286 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3287 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops; 3288 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3289 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3290 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops; 3291 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3292 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3293 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3294 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3295 mlxsw_sp->listeners = mlxsw_sp2_listener; 3296 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3297 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3298 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2; 3299 mlxsw_sp->pgt_smpe_index_valid = false; 3300 3301 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3302} 3303 3304static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core, 3305 const struct mlxsw_bus_info *mlxsw_bus_info, 3306 struct netlink_ext_ack *extack) 3307{ 3308 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3309 3310 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3311 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3312 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3313 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3314 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3315 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3316 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3317 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3318 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3319 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3320 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3321 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3322 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3323 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3324 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3325 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3326 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3327 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3328 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3329 mlxsw_sp->listeners = mlxsw_sp2_listener; 3330 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3331 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3332 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3; 3333 mlxsw_sp->pgt_smpe_index_valid = false; 3334 3335 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3336} 3337 3338static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core, 3339 const struct mlxsw_bus_info *mlxsw_bus_info, 3340 struct netlink_ext_ack *extack) 3341{ 3342 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3343 3344 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3345 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3346 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3347 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops; 3348 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3349 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3350 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3351 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops; 3352 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3353 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3354 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3355 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3356 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3357 mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops; 3358 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3359 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3360 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3361 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3362 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3363 mlxsw_sp->listeners = mlxsw_sp2_listener; 3364 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3365 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3366 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4; 3367 mlxsw_sp->pgt_smpe_index_valid = false; 3368 3369 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3370} 3371 3372static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3373{ 3374 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3375 3376 mlxsw_sp_ports_remove(mlxsw_sp); 3377 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3378 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3379 mlxsw_sp_dpipe_fini(mlxsw_sp); 3380 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3381 &mlxsw_sp->netdevice_nb); 3382 if (mlxsw_sp->clock) { 3383 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3384 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3385 } 3386 mlxsw_sp_router_fini(mlxsw_sp); 3387 mlxsw_sp_acl_fini(mlxsw_sp); 3388 mlxsw_sp_port_range_fini(mlxsw_sp); 3389 mlxsw_sp_nve_fini(mlxsw_sp); 3390 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3391 mlxsw_sp_afa_fini(mlxsw_sp); 3392 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3393 mlxsw_sp_switchdev_fini(mlxsw_sp); 3394 mlxsw_sp_span_fini(mlxsw_sp); 3395 mlxsw_sp_buffers_fini(mlxsw_sp); 3396 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3397 mlxsw_sp_traps_fini(mlxsw_sp); 3398 mlxsw_sp_policers_fini(mlxsw_sp); 3399 mlxsw_sp->fid_core_ops->fini(mlxsw_sp); 3400 mlxsw_sp_lag_fini(mlxsw_sp); 3401 mlxsw_sp_pgt_fini(mlxsw_sp); 3402 mlxsw_sp_kvdl_fini(mlxsw_sp); 3403 mlxsw_sp_parsing_fini(mlxsw_sp); 3404} 3405 3406static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3407 .used_flood_mode = 1, 3408 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3409 .used_max_ib_mc = 1, 3410 .max_ib_mc = 0, 3411 .used_max_pkey = 1, 3412 .max_pkey = 0, 3413 .used_ubridge = 1, 3414 .ubridge = 1, 3415 .used_kvd_sizes = 1, 3416 .kvd_hash_single_parts = 59, 3417 .kvd_hash_double_parts = 41, 3418 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3419 .swid_config = { 3420 { 3421 .used_type = 1, 3422 .type = MLXSW_PORT_SWID_TYPE_ETH, 3423 } 3424 }, 3425}; 3426 3427static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3428 .used_flood_mode = 1, 3429 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3430 .used_max_ib_mc = 1, 3431 .max_ib_mc = 0, 3432 .used_max_pkey = 1, 3433 .max_pkey = 0, 3434 .used_ubridge = 1, 3435 .ubridge = 1, 3436 .swid_config = { 3437 { 3438 .used_type = 1, 3439 .type = MLXSW_PORT_SWID_TYPE_ETH, 3440 } 3441 }, 3442 .used_cqe_time_stamp_type = 1, 3443 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3444 .lag_mode_prefer_sw = true, 3445 .flood_mode_prefer_cff = true, 3446}; 3447 3448/* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs 3449 * in Spectrum-2/3, to avoid regression in number of free entries in the PGT 3450 * table. 3451 */ 3452#define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128 3453 3454static const struct mlxsw_config_profile mlxsw_sp4_config_profile = { 3455 .used_max_lag = 1, 3456 .max_lag = MLXSW_SP4_CONFIG_PROFILE_MAX_LAG, 3457 .used_flood_mode = 1, 3458 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3459 .used_max_ib_mc = 1, 3460 .max_ib_mc = 0, 3461 .used_max_pkey = 1, 3462 .max_pkey = 0, 3463 .used_ubridge = 1, 3464 .ubridge = 1, 3465 .swid_config = { 3466 { 3467 .used_type = 1, 3468 .type = MLXSW_PORT_SWID_TYPE_ETH, 3469 } 3470 }, 3471 .used_cqe_time_stamp_type = 1, 3472 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3473 .lag_mode_prefer_sw = true, 3474 .flood_mode_prefer_cff = true, 3475}; 3476 3477static void 3478mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3479 struct devlink_resource_size_params *kvd_size_params, 3480 struct devlink_resource_size_params *linear_size_params, 3481 struct devlink_resource_size_params *hash_double_size_params, 3482 struct devlink_resource_size_params *hash_single_size_params) 3483{ 3484 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3485 KVD_SINGLE_MIN_SIZE); 3486 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3487 KVD_DOUBLE_MIN_SIZE); 3488 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3489 u32 linear_size_min = 0; 3490 3491 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3492 MLXSW_SP_KVD_GRANULARITY, 3493 DEVLINK_RESOURCE_UNIT_ENTRY); 3494 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3495 kvd_size - single_size_min - 3496 double_size_min, 3497 MLXSW_SP_KVD_GRANULARITY, 3498 DEVLINK_RESOURCE_UNIT_ENTRY); 3499 devlink_resource_size_params_init(hash_double_size_params, 3500 double_size_min, 3501 kvd_size - single_size_min - 3502 linear_size_min, 3503 MLXSW_SP_KVD_GRANULARITY, 3504 DEVLINK_RESOURCE_UNIT_ENTRY); 3505 devlink_resource_size_params_init(hash_single_size_params, 3506 single_size_min, 3507 kvd_size - double_size_min - 3508 linear_size_min, 3509 MLXSW_SP_KVD_GRANULARITY, 3510 DEVLINK_RESOURCE_UNIT_ENTRY); 3511} 3512 3513static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3514{ 3515 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3516 struct devlink_resource_size_params hash_single_size_params; 3517 struct devlink_resource_size_params hash_double_size_params; 3518 struct devlink_resource_size_params linear_size_params; 3519 struct devlink_resource_size_params kvd_size_params; 3520 u32 kvd_size, single_size, double_size, linear_size; 3521 const struct mlxsw_config_profile *profile; 3522 int err; 3523 3524 profile = &mlxsw_sp1_config_profile; 3525 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3526 return -EIO; 3527 3528 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3529 &linear_size_params, 3530 &hash_double_size_params, 3531 &hash_single_size_params); 3532 3533 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3534 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3535 kvd_size, MLXSW_SP_RESOURCE_KVD, 3536 DEVLINK_RESOURCE_ID_PARENT_TOP, 3537 &kvd_size_params); 3538 if (err) 3539 return err; 3540 3541 linear_size = profile->kvd_linear_size; 3542 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3543 linear_size, 3544 MLXSW_SP_RESOURCE_KVD_LINEAR, 3545 MLXSW_SP_RESOURCE_KVD, 3546 &linear_size_params); 3547 if (err) 3548 return err; 3549 3550 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 3551 if (err) 3552 return err; 3553 3554 double_size = kvd_size - linear_size; 3555 double_size *= profile->kvd_hash_double_parts; 3556 double_size /= profile->kvd_hash_double_parts + 3557 profile->kvd_hash_single_parts; 3558 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3559 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3560 double_size, 3561 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3562 MLXSW_SP_RESOURCE_KVD, 3563 &hash_double_size_params); 3564 if (err) 3565 return err; 3566 3567 single_size = kvd_size - double_size - linear_size; 3568 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3569 single_size, 3570 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3571 MLXSW_SP_RESOURCE_KVD, 3572 &hash_single_size_params); 3573 if (err) 3574 return err; 3575 3576 return 0; 3577} 3578 3579static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3580{ 3581 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3582 struct devlink_resource_size_params kvd_size_params; 3583 u32 kvd_size; 3584 3585 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3586 return -EIO; 3587 3588 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3589 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size, 3590 MLXSW_SP_KVD_GRANULARITY, 3591 DEVLINK_RESOURCE_UNIT_ENTRY); 3592 3593 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3594 kvd_size, MLXSW_SP_RESOURCE_KVD, 3595 DEVLINK_RESOURCE_ID_PARENT_TOP, 3596 &kvd_size_params); 3597} 3598 3599static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core) 3600{ 3601 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3602 struct devlink_resource_size_params span_size_params; 3603 u32 max_span; 3604 3605 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN)) 3606 return -EIO; 3607 3608 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN); 3609 devlink_resource_size_params_init(&span_size_params, max_span, max_span, 3610 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3611 3612 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN, 3613 max_span, MLXSW_SP_RESOURCE_SPAN, 3614 DEVLINK_RESOURCE_ID_PARENT_TOP, 3615 &span_size_params); 3616} 3617 3618static int 3619mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core) 3620{ 3621 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3622 struct devlink_resource_size_params size_params; 3623 u8 max_rif_mac_profiles; 3624 3625 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES)) 3626 max_rif_mac_profiles = 1; 3627 else 3628 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core, 3629 MAX_RIF_MAC_PROFILES); 3630 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles, 3631 max_rif_mac_profiles, 1, 3632 DEVLINK_RESOURCE_UNIT_ENTRY); 3633 3634 return devl_resource_register(devlink, 3635 "rif_mac_profiles", 3636 max_rif_mac_profiles, 3637 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES, 3638 DEVLINK_RESOURCE_ID_PARENT_TOP, 3639 &size_params); 3640} 3641 3642static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core) 3643{ 3644 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3645 struct devlink_resource_size_params size_params; 3646 u64 max_rifs; 3647 3648 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS)) 3649 return -EIO; 3650 3651 max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS); 3652 devlink_resource_size_params_init(&size_params, max_rifs, max_rifs, 3653 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3654 3655 return devl_resource_register(devlink, "rifs", max_rifs, 3656 MLXSW_SP_RESOURCE_RIFS, 3657 DEVLINK_RESOURCE_ID_PARENT_TOP, 3658 &size_params); 3659} 3660 3661static int 3662mlxsw_sp_resources_port_range_register(struct mlxsw_core *mlxsw_core) 3663{ 3664 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3665 struct devlink_resource_size_params size_params; 3666 u64 max; 3667 3668 if (!MLXSW_CORE_RES_VALID(mlxsw_core, ACL_MAX_L4_PORT_RANGE)) 3669 return -EIO; 3670 3671 max = MLXSW_CORE_RES_GET(mlxsw_core, ACL_MAX_L4_PORT_RANGE); 3672 devlink_resource_size_params_init(&size_params, max, max, 1, 3673 DEVLINK_RESOURCE_UNIT_ENTRY); 3674 3675 return devl_resource_register(devlink, "port_range_registers", max, 3676 MLXSW_SP_RESOURCE_PORT_RANGE_REGISTERS, 3677 DEVLINK_RESOURCE_ID_PARENT_TOP, 3678 &size_params); 3679} 3680 3681static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 3682{ 3683 int err; 3684 3685 err = mlxsw_sp1_resources_kvd_register(mlxsw_core); 3686 if (err) 3687 return err; 3688 3689 err = mlxsw_sp_resources_span_register(mlxsw_core); 3690 if (err) 3691 goto err_resources_span_register; 3692 3693 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3694 if (err) 3695 goto err_resources_counter_register; 3696 3697 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3698 if (err) 3699 goto err_policer_resources_register; 3700 3701 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3702 if (err) 3703 goto err_resources_rif_mac_profile_register; 3704 3705 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3706 if (err) 3707 goto err_resources_rifs_register; 3708 3709 err = mlxsw_sp_resources_port_range_register(mlxsw_core); 3710 if (err) 3711 goto err_resources_port_range_register; 3712 3713 return 0; 3714 3715err_resources_port_range_register: 3716err_resources_rifs_register: 3717err_resources_rif_mac_profile_register: 3718err_policer_resources_register: 3719err_resources_counter_register: 3720err_resources_span_register: 3721 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3722 return err; 3723} 3724 3725static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 3726{ 3727 int err; 3728 3729 err = mlxsw_sp2_resources_kvd_register(mlxsw_core); 3730 if (err) 3731 return err; 3732 3733 err = mlxsw_sp_resources_span_register(mlxsw_core); 3734 if (err) 3735 goto err_resources_span_register; 3736 3737 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3738 if (err) 3739 goto err_resources_counter_register; 3740 3741 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3742 if (err) 3743 goto err_policer_resources_register; 3744 3745 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3746 if (err) 3747 goto err_resources_rif_mac_profile_register; 3748 3749 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3750 if (err) 3751 goto err_resources_rifs_register; 3752 3753 err = mlxsw_sp_resources_port_range_register(mlxsw_core); 3754 if (err) 3755 goto err_resources_port_range_register; 3756 3757 return 0; 3758 3759err_resources_port_range_register: 3760err_resources_rifs_register: 3761err_resources_rif_mac_profile_register: 3762err_policer_resources_register: 3763err_resources_counter_register: 3764err_resources_span_register: 3765 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3766 return err; 3767} 3768 3769static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3770 const struct mlxsw_config_profile *profile, 3771 u64 *p_single_size, u64 *p_double_size, 3772 u64 *p_linear_size) 3773{ 3774 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3775 u32 double_size; 3776 int err; 3777 3778 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3779 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3780 return -EIO; 3781 3782 /* The hash part is what left of the kvd without the 3783 * linear part. It is split to the single size and 3784 * double size by the parts ratio from the profile. 3785 * Both sizes must be a multiplications of the 3786 * granularity from the profile. In case the user 3787 * provided the sizes they are obtained via devlink. 3788 */ 3789 err = devl_resource_size_get(devlink, 3790 MLXSW_SP_RESOURCE_KVD_LINEAR, 3791 p_linear_size); 3792 if (err) 3793 *p_linear_size = profile->kvd_linear_size; 3794 3795 err = devl_resource_size_get(devlink, 3796 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3797 p_double_size); 3798 if (err) { 3799 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3800 *p_linear_size; 3801 double_size *= profile->kvd_hash_double_parts; 3802 double_size /= profile->kvd_hash_double_parts + 3803 profile->kvd_hash_single_parts; 3804 *p_double_size = rounddown(double_size, 3805 MLXSW_SP_KVD_GRANULARITY); 3806 } 3807 3808 err = devl_resource_size_get(devlink, 3809 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3810 p_single_size); 3811 if (err) 3812 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3813 *p_double_size - *p_linear_size; 3814 3815 /* Check results are legal. */ 3816 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3817 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3818 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3819 return -EIO; 3820 3821 return 0; 3822} 3823 3824static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core, 3825 struct sk_buff *skb, u16 local_port) 3826{ 3827 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3828 3829 skb_pull(skb, MLXSW_TXHDR_LEN); 3830 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port); 3831} 3832 3833static struct mlxsw_driver mlxsw_sp1_driver = { 3834 .kind = mlxsw_sp1_driver_name, 3835 .priv_size = sizeof(struct mlxsw_sp), 3836 .fw_req_rev = &mlxsw_sp1_fw_rev, 3837 .fw_filename = MLXSW_SP1_FW_FILENAME, 3838 .init = mlxsw_sp1_init, 3839 .fini = mlxsw_sp_fini, 3840 .port_split = mlxsw_sp_port_split, 3841 .port_unsplit = mlxsw_sp_port_unsplit, 3842 .sb_pool_get = mlxsw_sp_sb_pool_get, 3843 .sb_pool_set = mlxsw_sp_sb_pool_set, 3844 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3845 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3846 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3847 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3848 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3849 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3850 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3851 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3852 .trap_init = mlxsw_sp_trap_init, 3853 .trap_fini = mlxsw_sp_trap_fini, 3854 .trap_action_set = mlxsw_sp_trap_action_set, 3855 .trap_group_init = mlxsw_sp_trap_group_init, 3856 .trap_group_set = mlxsw_sp_trap_group_set, 3857 .trap_policer_init = mlxsw_sp_trap_policer_init, 3858 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3859 .trap_policer_set = mlxsw_sp_trap_policer_set, 3860 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3861 .resources_register = mlxsw_sp1_resources_register, 3862 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 3863 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3864 .profile = &mlxsw_sp1_config_profile, 3865 .sdq_supports_cqe_v2 = false, 3866}; 3867 3868static struct mlxsw_driver mlxsw_sp2_driver = { 3869 .kind = mlxsw_sp2_driver_name, 3870 .priv_size = sizeof(struct mlxsw_sp), 3871 .fw_req_rev = &mlxsw_sp2_fw_rev, 3872 .fw_filename = MLXSW_SP2_FW_FILENAME, 3873 .init = mlxsw_sp2_init, 3874 .fini = mlxsw_sp_fini, 3875 .port_split = mlxsw_sp_port_split, 3876 .port_unsplit = mlxsw_sp_port_unsplit, 3877 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3878 .sb_pool_get = mlxsw_sp_sb_pool_get, 3879 .sb_pool_set = mlxsw_sp_sb_pool_set, 3880 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3881 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3882 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3883 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3884 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3885 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3886 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3887 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3888 .trap_init = mlxsw_sp_trap_init, 3889 .trap_fini = mlxsw_sp_trap_fini, 3890 .trap_action_set = mlxsw_sp_trap_action_set, 3891 .trap_group_init = mlxsw_sp_trap_group_init, 3892 .trap_group_set = mlxsw_sp_trap_group_set, 3893 .trap_policer_init = mlxsw_sp_trap_policer_init, 3894 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3895 .trap_policer_set = mlxsw_sp_trap_policer_set, 3896 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3897 .resources_register = mlxsw_sp2_resources_register, 3898 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3899 .profile = &mlxsw_sp2_config_profile, 3900 .sdq_supports_cqe_v2 = true, 3901}; 3902 3903static struct mlxsw_driver mlxsw_sp3_driver = { 3904 .kind = mlxsw_sp3_driver_name, 3905 .priv_size = sizeof(struct mlxsw_sp), 3906 .fw_req_rev = &mlxsw_sp3_fw_rev, 3907 .fw_filename = MLXSW_SP3_FW_FILENAME, 3908 .init = mlxsw_sp3_init, 3909 .fini = mlxsw_sp_fini, 3910 .port_split = mlxsw_sp_port_split, 3911 .port_unsplit = mlxsw_sp_port_unsplit, 3912 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3913 .sb_pool_get = mlxsw_sp_sb_pool_get, 3914 .sb_pool_set = mlxsw_sp_sb_pool_set, 3915 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3916 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3917 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3918 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3919 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3920 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3921 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3922 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3923 .trap_init = mlxsw_sp_trap_init, 3924 .trap_fini = mlxsw_sp_trap_fini, 3925 .trap_action_set = mlxsw_sp_trap_action_set, 3926 .trap_group_init = mlxsw_sp_trap_group_init, 3927 .trap_group_set = mlxsw_sp_trap_group_set, 3928 .trap_policer_init = mlxsw_sp_trap_policer_init, 3929 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3930 .trap_policer_set = mlxsw_sp_trap_policer_set, 3931 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3932 .resources_register = mlxsw_sp2_resources_register, 3933 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3934 .profile = &mlxsw_sp2_config_profile, 3935 .sdq_supports_cqe_v2 = true, 3936}; 3937 3938static struct mlxsw_driver mlxsw_sp4_driver = { 3939 .kind = mlxsw_sp4_driver_name, 3940 .priv_size = sizeof(struct mlxsw_sp), 3941 .init = mlxsw_sp4_init, 3942 .fini = mlxsw_sp_fini, 3943 .port_split = mlxsw_sp_port_split, 3944 .port_unsplit = mlxsw_sp_port_unsplit, 3945 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3946 .sb_pool_get = mlxsw_sp_sb_pool_get, 3947 .sb_pool_set = mlxsw_sp_sb_pool_set, 3948 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3949 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3950 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3951 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3952 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3953 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3954 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3955 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3956 .trap_init = mlxsw_sp_trap_init, 3957 .trap_fini = mlxsw_sp_trap_fini, 3958 .trap_action_set = mlxsw_sp_trap_action_set, 3959 .trap_group_init = mlxsw_sp_trap_group_init, 3960 .trap_group_set = mlxsw_sp_trap_group_set, 3961 .trap_policer_init = mlxsw_sp_trap_policer_init, 3962 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3963 .trap_policer_set = mlxsw_sp_trap_policer_set, 3964 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3965 .resources_register = mlxsw_sp2_resources_register, 3966 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3967 .profile = &mlxsw_sp4_config_profile, 3968 .sdq_supports_cqe_v2 = true, 3969}; 3970 3971bool mlxsw_sp_port_dev_check(const struct net_device *dev) 3972{ 3973 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 3974} 3975 3976static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, 3977 struct netdev_nested_priv *priv) 3978{ 3979 int ret = 0; 3980 3981 if (mlxsw_sp_port_dev_check(lower_dev)) { 3982 priv->data = (void *)netdev_priv(lower_dev); 3983 ret = 1; 3984 } 3985 3986 return ret; 3987} 3988 3989struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 3990{ 3991 struct netdev_nested_priv priv = { 3992 .data = NULL, 3993 }; 3994 3995 if (mlxsw_sp_port_dev_check(dev)) 3996 return netdev_priv(dev); 3997 3998 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv); 3999 4000 return (struct mlxsw_sp_port *)priv.data; 4001} 4002 4003struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4004{ 4005 struct mlxsw_sp_port *mlxsw_sp_port; 4006 4007 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4008 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4009} 4010 4011struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4012{ 4013 struct netdev_nested_priv priv = { 4014 .data = NULL, 4015 }; 4016 4017 if (mlxsw_sp_port_dev_check(dev)) 4018 return netdev_priv(dev); 4019 4020 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4021 &priv); 4022 4023 return (struct mlxsw_sp_port *)priv.data; 4024} 4025 4026int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp) 4027{ 4028 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4029 int err = 0; 4030 4031 mutex_lock(&mlxsw_sp->parsing.lock); 4032 4033 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref)) 4034 goto out_unlock; 4035 4036 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH, 4037 mlxsw_sp->parsing.vxlan_udp_dport); 4038 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4039 if (err) 4040 goto out_unlock; 4041 4042 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH; 4043 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1); 4044 4045out_unlock: 4046 mutex_unlock(&mlxsw_sp->parsing.lock); 4047 return err; 4048} 4049 4050void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp) 4051{ 4052 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4053 4054 mutex_lock(&mlxsw_sp->parsing.lock); 4055 4056 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref)) 4057 goto out_unlock; 4058 4059 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH, 4060 mlxsw_sp->parsing.vxlan_udp_dport); 4061 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4062 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 4063 4064out_unlock: 4065 mutex_unlock(&mlxsw_sp->parsing.lock); 4066} 4067 4068int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp, 4069 __be16 udp_dport) 4070{ 4071 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4072 int err; 4073 4074 mutex_lock(&mlxsw_sp->parsing.lock); 4075 4076 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth, 4077 be16_to_cpu(udp_dport)); 4078 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4079 if (err) 4080 goto out_unlock; 4081 4082 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport); 4083 4084out_unlock: 4085 mutex_unlock(&mlxsw_sp->parsing.lock); 4086 return err; 4087} 4088 4089static void 4090mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port, 4091 struct net_device *lag_dev) 4092{ 4093 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev); 4094 struct net_device *upper_dev; 4095 struct list_head *iter; 4096 4097 if (netif_is_bridge_port(lag_dev)) 4098 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev); 4099 4100 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4101 if (!netif_is_bridge_port(upper_dev)) 4102 continue; 4103 br_dev = netdev_master_upper_dev_get(upper_dev); 4104 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev); 4105 } 4106} 4107 4108static struct mlxsw_sp_lag * 4109mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev, 4110 struct netlink_ext_ack *extack) 4111{ 4112 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4113 struct mlxsw_sp_lag *lag; 4114 u16 lag_id; 4115 int i, err; 4116 4117 for (i = 0; i < mlxsw_sp->max_lag; i++) { 4118 if (!mlxsw_sp->lags[i].dev) 4119 break; 4120 } 4121 4122 if (i == mlxsw_sp->max_lag) { 4123 NL_SET_ERR_MSG_MOD(extack, 4124 "Exceeded number of supported LAG devices"); 4125 return ERR_PTR(-EBUSY); 4126 } 4127 4128 lag_id = i; 4129 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4130 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4131 if (err) 4132 return ERR_PTR(err); 4133 4134 lag = &mlxsw_sp->lags[lag_id]; 4135 lag->lag_id = lag_id; 4136 lag->dev = lag_dev; 4137 refcount_set(&lag->ref_count, 1); 4138 4139 return lag; 4140} 4141 4142static int 4143mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag) 4144{ 4145 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4146 4147 lag->dev = NULL; 4148 4149 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag->lag_id); 4150 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4151} 4152 4153static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4154 u16 lag_id, u8 port_index) 4155{ 4156 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4157 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4158 4159 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4160 lag_id, port_index); 4161 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4162} 4163 4164static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4165 u16 lag_id) 4166{ 4167 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4168 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4169 4170 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4171 lag_id); 4172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4173} 4174 4175static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4176 u16 lag_id) 4177{ 4178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4179 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4180 4181 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4182 lag_id); 4183 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4184} 4185 4186static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4187 u16 lag_id) 4188{ 4189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4190 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4191 4192 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4193 lag_id); 4194 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4195} 4196 4197static struct mlxsw_sp_lag * 4198mlxsw_sp_lag_find(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev) 4199{ 4200 int i; 4201 4202 for (i = 0; i < mlxsw_sp->max_lag; i++) { 4203 if (!mlxsw_sp->lags[i].dev) 4204 continue; 4205 4206 if (mlxsw_sp->lags[i].dev == lag_dev) 4207 return &mlxsw_sp->lags[i]; 4208 } 4209 4210 return NULL; 4211} 4212 4213static struct mlxsw_sp_lag * 4214mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev, 4215 struct netlink_ext_ack *extack) 4216{ 4217 struct mlxsw_sp_lag *lag; 4218 4219 lag = mlxsw_sp_lag_find(mlxsw_sp, lag_dev); 4220 if (lag) { 4221 refcount_inc(&lag->ref_count); 4222 return lag; 4223 } 4224 4225 return mlxsw_sp_lag_create(mlxsw_sp, lag_dev, extack); 4226} 4227 4228static void 4229mlxsw_sp_lag_put(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag) 4230{ 4231 if (!refcount_dec_and_test(&lag->ref_count)) 4232 return; 4233 4234 mlxsw_sp_lag_destroy(mlxsw_sp, lag); 4235} 4236 4237static bool 4238mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4239 struct net_device *lag_dev, 4240 struct netdev_lag_upper_info *lag_upper_info, 4241 struct netlink_ext_ack *extack) 4242{ 4243 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4244 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4245 return false; 4246 } 4247 return true; 4248} 4249 4250static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4251 u16 lag_id, u8 *p_port_index) 4252{ 4253 u64 max_lag_members; 4254 int i; 4255 4256 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4257 MAX_LAG_MEMBERS); 4258 for (i = 0; i < max_lag_members; i++) { 4259 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4260 *p_port_index = i; 4261 return 0; 4262 } 4263 } 4264 return -EBUSY; 4265} 4266 4267static int mlxsw_sp_lag_uppers_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port, 4268 struct net_device *lag_dev, 4269 struct netlink_ext_ack *extack) 4270{ 4271 struct net_device *upper_dev; 4272 struct net_device *master; 4273 struct list_head *iter; 4274 int done = 0; 4275 int err; 4276 4277 master = netdev_master_upper_dev_get(lag_dev); 4278 if (master && netif_is_bridge_master(master)) { 4279 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, lag_dev, master, 4280 extack); 4281 if (err) 4282 return err; 4283 } 4284 4285 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4286 if (!is_vlan_dev(upper_dev)) 4287 continue; 4288 4289 master = netdev_master_upper_dev_get(upper_dev); 4290 if (master && netif_is_bridge_master(master)) { 4291 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4292 upper_dev, master, 4293 extack); 4294 if (err) 4295 goto err_port_bridge_join; 4296 } 4297 4298 ++done; 4299 } 4300 4301 return 0; 4302 4303err_port_bridge_join: 4304 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4305 if (!is_vlan_dev(upper_dev)) 4306 continue; 4307 4308 master = netdev_master_upper_dev_get(upper_dev); 4309 if (!master || !netif_is_bridge_master(master)) 4310 continue; 4311 4312 if (!done--) 4313 break; 4314 4315 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master); 4316 } 4317 4318 master = netdev_master_upper_dev_get(lag_dev); 4319 if (master && netif_is_bridge_master(master)) 4320 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master); 4321 4322 return err; 4323} 4324 4325static void 4326mlxsw_sp_lag_uppers_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4327 struct net_device *lag_dev) 4328{ 4329 struct net_device *upper_dev; 4330 struct net_device *master; 4331 struct list_head *iter; 4332 4333 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4334 if (!is_vlan_dev(upper_dev)) 4335 continue; 4336 4337 master = netdev_master_upper_dev_get(upper_dev); 4338 if (!master) 4339 continue; 4340 4341 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master); 4342 } 4343 4344 master = netdev_master_upper_dev_get(lag_dev); 4345 if (master) 4346 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master); 4347} 4348 4349static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4350 struct net_device *lag_dev, 4351 struct netlink_ext_ack *extack) 4352{ 4353 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4354 struct mlxsw_sp_lag *lag; 4355 u16 lag_id; 4356 u8 port_index; 4357 int err; 4358 4359 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_dev, extack); 4360 if (IS_ERR(lag)) 4361 return PTR_ERR(lag); 4362 4363 lag_id = lag->lag_id; 4364 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4365 if (err) 4366 return err; 4367 4368 err = mlxsw_sp_lag_uppers_bridge_join(mlxsw_sp_port, lag_dev, 4369 extack); 4370 if (err) 4371 goto err_lag_uppers_bridge_join; 4372 4373 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4374 if (err) 4375 goto err_col_port_add; 4376 4377 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4378 mlxsw_sp_port->local_port); 4379 mlxsw_sp_port->lag_id = lag_id; 4380 mlxsw_sp_port->lagged = 1; 4381 4382 err = mlxsw_sp_fid_port_join_lag(mlxsw_sp_port); 4383 if (err) 4384 goto err_fid_port_join_lag; 4385 4386 /* Port is no longer usable as a router interface */ 4387 if (mlxsw_sp_port->default_vlan->fid) 4388 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan); 4389 4390 /* Join a router interface configured on the LAG, if exists */ 4391 err = mlxsw_sp_router_port_join_lag(mlxsw_sp_port, lag_dev, 4392 extack); 4393 if (err) 4394 goto err_router_join; 4395 4396 err = mlxsw_sp_netdevice_enslavement_replay(mlxsw_sp, lag_dev, extack); 4397 if (err) 4398 goto err_replay; 4399 4400 return 0; 4401 4402err_replay: 4403 mlxsw_sp_router_port_leave_lag(mlxsw_sp_port, lag_dev); 4404err_router_join: 4405 mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port); 4406err_fid_port_join_lag: 4407 mlxsw_sp_port->lagged = 0; 4408 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4409 mlxsw_sp_port->local_port); 4410 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4411err_col_port_add: 4412 mlxsw_sp_lag_uppers_bridge_leave(mlxsw_sp_port, lag_dev); 4413err_lag_uppers_bridge_join: 4414 mlxsw_sp_lag_put(mlxsw_sp, lag); 4415 return err; 4416} 4417 4418static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4419 struct net_device *lag_dev) 4420{ 4421 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4422 u16 lag_id = mlxsw_sp_port->lag_id; 4423 struct mlxsw_sp_lag *lag; 4424 4425 if (!mlxsw_sp_port->lagged) 4426 return; 4427 lag = &mlxsw_sp->lags[lag_id]; 4428 4429 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4430 4431 /* Any VLANs configured on the port are no longer valid */ 4432 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false); 4433 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan); 4434 /* Make the LAG and its directly linked uppers leave bridges they 4435 * are memeber in 4436 */ 4437 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev); 4438 4439 mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port); 4440 4441 mlxsw_sp_lag_put(mlxsw_sp, lag); 4442 4443 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4444 mlxsw_sp_port->local_port); 4445 mlxsw_sp_port->lagged = 0; 4446 4447 /* Make sure untagged frames are allowed to ingress */ 4448 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 4449 ETH_P_8021Q); 4450} 4451 4452static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4453 u16 lag_id) 4454{ 4455 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4456 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4457 4458 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4459 mlxsw_sp_port->local_port); 4460 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4461} 4462 4463static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4464 u16 lag_id) 4465{ 4466 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4467 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4468 4469 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4470 mlxsw_sp_port->local_port); 4471 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4472} 4473 4474static int 4475mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port) 4476{ 4477 int err; 4478 4479 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, 4480 mlxsw_sp_port->lag_id); 4481 if (err) 4482 return err; 4483 4484 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4485 if (err) 4486 goto err_dist_port_add; 4487 4488 return 0; 4489 4490err_dist_port_add: 4491 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4492 return err; 4493} 4494 4495static int 4496mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port) 4497{ 4498 int err; 4499 4500 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4501 mlxsw_sp_port->lag_id); 4502 if (err) 4503 return err; 4504 4505 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, 4506 mlxsw_sp_port->lag_id); 4507 if (err) 4508 goto err_col_port_disable; 4509 4510 return 0; 4511 4512err_col_port_disable: 4513 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4514 return err; 4515} 4516 4517static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4518 struct netdev_lag_lower_state_info *info) 4519{ 4520 if (info->tx_enabled) 4521 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port); 4522 else 4523 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4524} 4525 4526static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4527 bool enable) 4528{ 4529 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4530 enum mlxsw_reg_spms_state spms_state; 4531 char *spms_pl; 4532 u16 vid; 4533 int err; 4534 4535 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4536 MLXSW_REG_SPMS_STATE_DISCARDING; 4537 4538 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4539 if (!spms_pl) 4540 return -ENOMEM; 4541 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4542 4543 for (vid = 0; vid < VLAN_N_VID; vid++) 4544 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4545 4546 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4547 kfree(spms_pl); 4548 return err; 4549} 4550 4551static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4552{ 4553 u16 vid = 1; 4554 int err; 4555 4556 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4557 if (err) 4558 return err; 4559 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4560 if (err) 4561 goto err_port_stp_set; 4562 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4563 true, false); 4564 if (err) 4565 goto err_port_vlan_set; 4566 4567 for (; vid <= VLAN_N_VID - 1; vid++) { 4568 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4569 vid, false); 4570 if (err) 4571 goto err_vid_learning_set; 4572 } 4573 4574 return 0; 4575 4576err_vid_learning_set: 4577 for (vid--; vid >= 1; vid--) 4578 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4579err_port_vlan_set: 4580 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4581err_port_stp_set: 4582 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4583 return err; 4584} 4585 4586static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4587{ 4588 u16 vid; 4589 4590 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4591 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4592 vid, true); 4593 4594 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4595 false, false); 4596 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4597 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4598} 4599 4600static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4601{ 4602 unsigned int num_vxlans = 0; 4603 struct net_device *dev; 4604 struct list_head *iter; 4605 4606 netdev_for_each_lower_dev(br_dev, dev, iter) { 4607 if (netif_is_vxlan(dev)) 4608 num_vxlans++; 4609 } 4610 4611 return num_vxlans > 1; 4612} 4613 4614static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev) 4615{ 4616 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0}; 4617 struct net_device *dev; 4618 struct list_head *iter; 4619 4620 netdev_for_each_lower_dev(br_dev, dev, iter) { 4621 u16 pvid; 4622 int err; 4623 4624 if (!netif_is_vxlan(dev)) 4625 continue; 4626 4627 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid); 4628 if (err || !pvid) 4629 continue; 4630 4631 if (test_and_set_bit(pvid, vlans)) 4632 return false; 4633 } 4634 4635 return true; 4636} 4637 4638static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4639 struct netlink_ext_ack *extack) 4640{ 4641 if (br_multicast_enabled(br_dev)) { 4642 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4643 return false; 4644 } 4645 4646 if (!br_vlan_enabled(br_dev) && 4647 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4648 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4649 return false; 4650 } 4651 4652 if (br_vlan_enabled(br_dev) && 4653 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) { 4654 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged"); 4655 return false; 4656 } 4657 4658 return true; 4659} 4660 4661static bool mlxsw_sp_netdev_is_master(struct net_device *upper_dev, 4662 struct net_device *dev) 4663{ 4664 return upper_dev == netdev_master_upper_dev_get(dev); 4665} 4666 4667static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp, 4668 unsigned long event, void *ptr, 4669 bool process_foreign); 4670 4671static int mlxsw_sp_netdevice_validate_uppers(struct mlxsw_sp *mlxsw_sp, 4672 struct net_device *dev, 4673 struct netlink_ext_ack *extack) 4674{ 4675 struct net_device *upper_dev; 4676 struct list_head *iter; 4677 int err; 4678 4679 netdev_for_each_upper_dev_rcu(dev, upper_dev, iter) { 4680 struct netdev_notifier_changeupper_info info = { 4681 .info = { 4682 .dev = dev, 4683 .extack = extack, 4684 }, 4685 .master = mlxsw_sp_netdev_is_master(upper_dev, dev), 4686 .upper_dev = upper_dev, 4687 .linking = true, 4688 4689 /* upper_info is relevant for LAG devices. But we would 4690 * only need this if LAG were a valid upper above 4691 * another upper (e.g. a bridge that is a member of a 4692 * LAG), and that is never a valid configuration. So we 4693 * can keep this as NULL. 4694 */ 4695 .upper_info = NULL, 4696 }; 4697 4698 err = __mlxsw_sp_netdevice_event(mlxsw_sp, 4699 NETDEV_PRECHANGEUPPER, 4700 &info, true); 4701 if (err) 4702 return err; 4703 4704 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, upper_dev, 4705 extack); 4706 if (err) 4707 return err; 4708 } 4709 4710 return 0; 4711} 4712 4713static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4714 struct net_device *dev, 4715 unsigned long event, void *ptr, 4716 bool replay_deslavement) 4717{ 4718 struct netdev_notifier_changeupper_info *info; 4719 struct mlxsw_sp_port *mlxsw_sp_port; 4720 struct netlink_ext_ack *extack; 4721 struct net_device *upper_dev; 4722 struct mlxsw_sp *mlxsw_sp; 4723 int err = 0; 4724 u16 proto; 4725 4726 mlxsw_sp_port = netdev_priv(dev); 4727 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4728 info = ptr; 4729 extack = netdev_notifier_info_to_extack(&info->info); 4730 4731 switch (event) { 4732 case NETDEV_PRECHANGEUPPER: 4733 upper_dev = info->upper_dev; 4734 if (!is_vlan_dev(upper_dev) && 4735 !netif_is_lag_master(upper_dev) && 4736 !netif_is_bridge_master(upper_dev) && 4737 !netif_is_ovs_master(upper_dev) && 4738 !netif_is_macvlan(upper_dev) && 4739 !netif_is_l3_master(upper_dev)) { 4740 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4741 return -EINVAL; 4742 } 4743 if (!info->linking) 4744 break; 4745 if (netif_is_bridge_master(upper_dev) && 4746 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4747 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4748 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4749 return -EOPNOTSUPP; 4750 if (netdev_has_any_upper_dev(upper_dev) && 4751 (!netif_is_bridge_master(upper_dev) || 4752 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4753 upper_dev))) { 4754 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, 4755 upper_dev, 4756 extack); 4757 if (err) 4758 return err; 4759 } 4760 if (netif_is_lag_master(upper_dev) && 4761 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4762 info->upper_info, extack)) 4763 return -EINVAL; 4764 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4765 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4766 return -EINVAL; 4767 } 4768 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4769 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4770 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4771 return -EINVAL; 4772 } 4773 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4774 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4775 return -EINVAL; 4776 } 4777 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4778 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4779 return -EINVAL; 4780 } 4781 if (netif_is_bridge_master(upper_dev)) { 4782 br_vlan_get_proto(upper_dev, &proto); 4783 if (br_vlan_enabled(upper_dev) && 4784 proto != ETH_P_8021Q && proto != ETH_P_8021AD) { 4785 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported"); 4786 return -EOPNOTSUPP; 4787 } 4788 if (vlan_uses_dev(lower_dev) && 4789 br_vlan_enabled(upper_dev) && 4790 proto == ETH_P_8021AD) { 4791 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported"); 4792 return -EOPNOTSUPP; 4793 } 4794 } 4795 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) { 4796 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev); 4797 4798 if (br_vlan_enabled(br_dev)) { 4799 br_vlan_get_proto(br_dev, &proto); 4800 if (proto == ETH_P_8021AD) { 4801 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge"); 4802 return -EOPNOTSUPP; 4803 } 4804 } 4805 } 4806 if (is_vlan_dev(upper_dev) && 4807 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4808 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4809 return -EOPNOTSUPP; 4810 } 4811 if (is_vlan_dev(upper_dev) && mlxsw_sp_port->security) { 4812 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a locked port"); 4813 return -EOPNOTSUPP; 4814 } 4815 break; 4816 case NETDEV_CHANGEUPPER: 4817 upper_dev = info->upper_dev; 4818 if (netif_is_bridge_master(upper_dev)) { 4819 if (info->linking) { 4820 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4821 lower_dev, 4822 upper_dev, 4823 extack); 4824 } else { 4825 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4826 lower_dev, 4827 upper_dev); 4828 if (!replay_deslavement) 4829 break; 4830 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 4831 lower_dev); 4832 } 4833 } else if (netif_is_lag_master(upper_dev)) { 4834 if (info->linking) { 4835 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4836 upper_dev, extack); 4837 } else { 4838 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4839 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4840 upper_dev); 4841 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 4842 dev); 4843 } 4844 } else if (netif_is_ovs_master(upper_dev)) { 4845 if (info->linking) 4846 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4847 else 4848 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4849 } else if (netif_is_macvlan(upper_dev)) { 4850 if (!info->linking) 4851 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4852 } else if (is_vlan_dev(upper_dev)) { 4853 struct net_device *br_dev; 4854 4855 if (!netif_is_bridge_port(upper_dev)) 4856 break; 4857 if (info->linking) 4858 break; 4859 br_dev = netdev_master_upper_dev_get(upper_dev); 4860 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, 4861 br_dev); 4862 } 4863 break; 4864 } 4865 4866 return err; 4867} 4868 4869static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4870 unsigned long event, void *ptr) 4871{ 4872 struct netdev_notifier_changelowerstate_info *info; 4873 struct mlxsw_sp_port *mlxsw_sp_port; 4874 int err; 4875 4876 mlxsw_sp_port = netdev_priv(dev); 4877 info = ptr; 4878 4879 switch (event) { 4880 case NETDEV_CHANGELOWERSTATE: 4881 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4882 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4883 info->lower_state_info); 4884 if (err) 4885 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4886 } 4887 break; 4888 } 4889 4890 return 0; 4891} 4892 4893static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4894 struct net_device *port_dev, 4895 unsigned long event, void *ptr, 4896 bool replay_deslavement) 4897{ 4898 switch (event) { 4899 case NETDEV_PRECHANGEUPPER: 4900 case NETDEV_CHANGEUPPER: 4901 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4902 event, ptr, 4903 replay_deslavement); 4904 case NETDEV_CHANGELOWERSTATE: 4905 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4906 ptr); 4907 } 4908 4909 return 0; 4910} 4911 4912/* Called for LAG or its upper VLAN after the per-LAG-lower processing was done, 4913 * to do any per-LAG / per-LAG-upper processing. 4914 */ 4915static int mlxsw_sp_netdevice_post_lag_event(struct net_device *dev, 4916 unsigned long event, 4917 void *ptr) 4918{ 4919 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(dev); 4920 struct netdev_notifier_changeupper_info *info = ptr; 4921 4922 if (!mlxsw_sp) 4923 return 0; 4924 4925 switch (event) { 4926 case NETDEV_CHANGEUPPER: 4927 if (info->linking) 4928 break; 4929 if (netif_is_bridge_master(info->upper_dev)) 4930 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, dev); 4931 break; 4932 } 4933 return 0; 4934} 4935 4936static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4937 unsigned long event, void *ptr) 4938{ 4939 struct net_device *dev; 4940 struct list_head *iter; 4941 int ret; 4942 4943 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4944 if (mlxsw_sp_port_dev_check(dev)) { 4945 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4946 ptr, false); 4947 if (ret) 4948 return ret; 4949 } 4950 } 4951 4952 return mlxsw_sp_netdevice_post_lag_event(lag_dev, event, ptr); 4953} 4954 4955static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4956 struct net_device *dev, 4957 unsigned long event, void *ptr, 4958 u16 vid, bool replay_deslavement) 4959{ 4960 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4961 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4962 struct netdev_notifier_changeupper_info *info = ptr; 4963 struct netlink_ext_ack *extack; 4964 struct net_device *upper_dev; 4965 int err = 0; 4966 4967 extack = netdev_notifier_info_to_extack(&info->info); 4968 4969 switch (event) { 4970 case NETDEV_PRECHANGEUPPER: 4971 upper_dev = info->upper_dev; 4972 if (!netif_is_bridge_master(upper_dev) && 4973 !netif_is_macvlan(upper_dev) && 4974 !netif_is_l3_master(upper_dev)) { 4975 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4976 return -EINVAL; 4977 } 4978 if (!info->linking) 4979 break; 4980 if (netif_is_bridge_master(upper_dev) && 4981 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4982 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4983 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4984 return -EOPNOTSUPP; 4985 if (netdev_has_any_upper_dev(upper_dev) && 4986 (!netif_is_bridge_master(upper_dev) || 4987 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4988 upper_dev))) { 4989 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, 4990 upper_dev, 4991 extack); 4992 if (err) 4993 return err; 4994 } 4995 break; 4996 case NETDEV_CHANGEUPPER: 4997 upper_dev = info->upper_dev; 4998 if (netif_is_bridge_master(upper_dev)) { 4999 if (info->linking) { 5000 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 5001 vlan_dev, 5002 upper_dev, 5003 extack); 5004 } else { 5005 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 5006 vlan_dev, 5007 upper_dev); 5008 if (!replay_deslavement) 5009 break; 5010 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 5011 vlan_dev); 5012 } 5013 } else if (netif_is_macvlan(upper_dev)) { 5014 if (!info->linking) 5015 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5016 } 5017 break; 5018 } 5019 5020 return err; 5021} 5022 5023static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 5024 struct net_device *lag_dev, 5025 unsigned long event, 5026 void *ptr, u16 vid) 5027{ 5028 struct net_device *dev; 5029 struct list_head *iter; 5030 int ret; 5031 5032 netdev_for_each_lower_dev(lag_dev, dev, iter) { 5033 if (mlxsw_sp_port_dev_check(dev)) { 5034 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 5035 event, ptr, 5036 vid, false); 5037 if (ret) 5038 return ret; 5039 } 5040 } 5041 5042 return mlxsw_sp_netdevice_post_lag_event(vlan_dev, event, ptr); 5043} 5044 5045static int mlxsw_sp_netdevice_bridge_vlan_event(struct mlxsw_sp *mlxsw_sp, 5046 struct net_device *vlan_dev, 5047 struct net_device *br_dev, 5048 unsigned long event, void *ptr, 5049 u16 vid, bool process_foreign) 5050{ 5051 struct netdev_notifier_changeupper_info *info = ptr; 5052 struct netlink_ext_ack *extack; 5053 struct net_device *upper_dev; 5054 5055 if (!process_foreign && !mlxsw_sp_lower_get(vlan_dev)) 5056 return 0; 5057 5058 extack = netdev_notifier_info_to_extack(&info->info); 5059 5060 switch (event) { 5061 case NETDEV_PRECHANGEUPPER: 5062 upper_dev = info->upper_dev; 5063 if (!netif_is_macvlan(upper_dev) && 5064 !netif_is_l3_master(upper_dev)) { 5065 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5066 return -EOPNOTSUPP; 5067 } 5068 break; 5069 case NETDEV_CHANGEUPPER: 5070 upper_dev = info->upper_dev; 5071 if (info->linking) 5072 break; 5073 if (netif_is_macvlan(upper_dev)) 5074 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5075 break; 5076 } 5077 5078 return 0; 5079} 5080 5081static int mlxsw_sp_netdevice_vlan_event(struct mlxsw_sp *mlxsw_sp, 5082 struct net_device *vlan_dev, 5083 unsigned long event, void *ptr, 5084 bool process_foreign) 5085{ 5086 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 5087 u16 vid = vlan_dev_vlan_id(vlan_dev); 5088 5089 if (mlxsw_sp_port_dev_check(real_dev)) 5090 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 5091 event, ptr, vid, 5092 true); 5093 else if (netif_is_lag_master(real_dev)) 5094 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 5095 real_dev, event, 5096 ptr, vid); 5097 else if (netif_is_bridge_master(real_dev)) 5098 return mlxsw_sp_netdevice_bridge_vlan_event(mlxsw_sp, vlan_dev, 5099 real_dev, event, 5100 ptr, vid, 5101 process_foreign); 5102 5103 return 0; 5104} 5105 5106static int mlxsw_sp_netdevice_bridge_event(struct mlxsw_sp *mlxsw_sp, 5107 struct net_device *br_dev, 5108 unsigned long event, void *ptr, 5109 bool process_foreign) 5110{ 5111 struct netdev_notifier_changeupper_info *info = ptr; 5112 struct netlink_ext_ack *extack; 5113 struct net_device *upper_dev; 5114 u16 proto; 5115 5116 if (!process_foreign && !mlxsw_sp_lower_get(br_dev)) 5117 return 0; 5118 5119 extack = netdev_notifier_info_to_extack(&info->info); 5120 5121 switch (event) { 5122 case NETDEV_PRECHANGEUPPER: 5123 upper_dev = info->upper_dev; 5124 if (!is_vlan_dev(upper_dev) && 5125 !netif_is_macvlan(upper_dev) && 5126 !netif_is_l3_master(upper_dev)) { 5127 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5128 return -EOPNOTSUPP; 5129 } 5130 if (!info->linking) 5131 break; 5132 if (br_vlan_enabled(br_dev)) { 5133 br_vlan_get_proto(br_dev, &proto); 5134 if (proto == ETH_P_8021AD) { 5135 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge"); 5136 return -EOPNOTSUPP; 5137 } 5138 } 5139 if (is_vlan_dev(upper_dev) && 5140 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 5141 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 5142 return -EOPNOTSUPP; 5143 } 5144 break; 5145 case NETDEV_CHANGEUPPER: 5146 upper_dev = info->upper_dev; 5147 if (info->linking) 5148 break; 5149 if (is_vlan_dev(upper_dev)) 5150 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 5151 if (netif_is_macvlan(upper_dev)) 5152 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5153 break; 5154 } 5155 5156 return 0; 5157} 5158 5159static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 5160 unsigned long event, void *ptr) 5161{ 5162 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 5163 struct netdev_notifier_changeupper_info *info = ptr; 5164 struct netlink_ext_ack *extack; 5165 struct net_device *upper_dev; 5166 5167 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 5168 return 0; 5169 5170 extack = netdev_notifier_info_to_extack(&info->info); 5171 upper_dev = info->upper_dev; 5172 5173 if (!netif_is_l3_master(upper_dev)) { 5174 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5175 return -EOPNOTSUPP; 5176 } 5177 5178 return 0; 5179} 5180 5181static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 5182 struct net_device *dev, 5183 unsigned long event, void *ptr) 5184{ 5185 struct netdev_notifier_changeupper_info *cu_info; 5186 struct netdev_notifier_info *info = ptr; 5187 struct netlink_ext_ack *extack; 5188 struct net_device *upper_dev; 5189 5190 extack = netdev_notifier_info_to_extack(info); 5191 5192 switch (event) { 5193 case NETDEV_CHANGEUPPER: 5194 cu_info = container_of(info, 5195 struct netdev_notifier_changeupper_info, 5196 info); 5197 upper_dev = cu_info->upper_dev; 5198 if (!netif_is_bridge_master(upper_dev)) 5199 return 0; 5200 if (!mlxsw_sp_lower_get(upper_dev)) 5201 return 0; 5202 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5203 return -EOPNOTSUPP; 5204 if (!netif_running(dev)) 5205 return 0; 5206 if (cu_info->linking) 5207 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 5208 dev, 0, extack); 5209 else 5210 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5211 break; 5212 case NETDEV_PRE_UP: 5213 upper_dev = netdev_master_upper_dev_get(dev); 5214 if (!upper_dev) 5215 return 0; 5216 if (!netif_is_bridge_master(upper_dev)) 5217 return 0; 5218 if (!mlxsw_sp_lower_get(upper_dev)) 5219 return 0; 5220 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0, 5221 extack); 5222 case NETDEV_DOWN: 5223 upper_dev = netdev_master_upper_dev_get(dev); 5224 if (!upper_dev) 5225 return 0; 5226 if (!netif_is_bridge_master(upper_dev)) 5227 return 0; 5228 if (!mlxsw_sp_lower_get(upper_dev)) 5229 return 0; 5230 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5231 break; 5232 } 5233 5234 return 0; 5235} 5236 5237static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp, 5238 unsigned long event, void *ptr, 5239 bool process_foreign) 5240{ 5241 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 5242 struct mlxsw_sp_span_entry *span_entry; 5243 int err = 0; 5244 5245 if (event == NETDEV_UNREGISTER) { 5246 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 5247 if (span_entry) 5248 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 5249 } 5250 5251 if (netif_is_vxlan(dev)) 5252 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 5253 else if (mlxsw_sp_port_dev_check(dev)) 5254 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr, true); 5255 else if (netif_is_lag_master(dev)) 5256 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 5257 else if (is_vlan_dev(dev)) 5258 err = mlxsw_sp_netdevice_vlan_event(mlxsw_sp, dev, event, ptr, 5259 process_foreign); 5260 else if (netif_is_bridge_master(dev)) 5261 err = mlxsw_sp_netdevice_bridge_event(mlxsw_sp, dev, event, ptr, 5262 process_foreign); 5263 else if (netif_is_macvlan(dev)) 5264 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 5265 5266 return err; 5267} 5268 5269static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 5270 unsigned long event, void *ptr) 5271{ 5272 struct mlxsw_sp *mlxsw_sp; 5273 int err; 5274 5275 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 5276 mlxsw_sp_span_respin(mlxsw_sp); 5277 err = __mlxsw_sp_netdevice_event(mlxsw_sp, event, ptr, false); 5278 5279 return notifier_from_errno(err); 5280} 5281 5282static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 5283 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 5284 {0, }, 5285}; 5286 5287static struct pci_driver mlxsw_sp1_pci_driver = { 5288 .name = mlxsw_sp1_driver_name, 5289 .id_table = mlxsw_sp1_pci_id_table, 5290}; 5291 5292static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 5293 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 5294 {0, }, 5295}; 5296 5297static struct pci_driver mlxsw_sp2_pci_driver = { 5298 .name = mlxsw_sp2_driver_name, 5299 .id_table = mlxsw_sp2_pci_id_table, 5300}; 5301 5302static const struct pci_device_id mlxsw_sp3_pci_id_table[] = { 5303 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0}, 5304 {0, }, 5305}; 5306 5307static struct pci_driver mlxsw_sp3_pci_driver = { 5308 .name = mlxsw_sp3_driver_name, 5309 .id_table = mlxsw_sp3_pci_id_table, 5310}; 5311 5312static const struct pci_device_id mlxsw_sp4_pci_id_table[] = { 5313 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4), 0}, 5314 {0, }, 5315}; 5316 5317static struct pci_driver mlxsw_sp4_pci_driver = { 5318 .name = mlxsw_sp4_driver_name, 5319 .id_table = mlxsw_sp4_pci_id_table, 5320}; 5321 5322static int __init mlxsw_sp_module_init(void) 5323{ 5324 int err; 5325 5326 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5327 if (err) 5328 return err; 5329 5330 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5331 if (err) 5332 goto err_sp2_core_driver_register; 5333 5334 err = mlxsw_core_driver_register(&mlxsw_sp3_driver); 5335 if (err) 5336 goto err_sp3_core_driver_register; 5337 5338 err = mlxsw_core_driver_register(&mlxsw_sp4_driver); 5339 if (err) 5340 goto err_sp4_core_driver_register; 5341 5342 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5343 if (err) 5344 goto err_sp1_pci_driver_register; 5345 5346 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5347 if (err) 5348 goto err_sp2_pci_driver_register; 5349 5350 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver); 5351 if (err) 5352 goto err_sp3_pci_driver_register; 5353 5354 err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver); 5355 if (err) 5356 goto err_sp4_pci_driver_register; 5357 5358 return 0; 5359 5360err_sp4_pci_driver_register: 5361 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5362err_sp3_pci_driver_register: 5363 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5364err_sp2_pci_driver_register: 5365 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5366err_sp1_pci_driver_register: 5367 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5368err_sp4_core_driver_register: 5369 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5370err_sp3_core_driver_register: 5371 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5372err_sp2_core_driver_register: 5373 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5374 return err; 5375} 5376 5377static void __exit mlxsw_sp_module_exit(void) 5378{ 5379 mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver); 5380 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5381 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5382 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5383 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5384 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5385 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5386 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5387} 5388 5389module_init(mlxsw_sp_module_init); 5390module_exit(mlxsw_sp_module_exit); 5391 5392MODULE_LICENSE("Dual BSD/GPL"); 5393MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5394MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5395MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5396MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5397MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table); 5398MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table); 5399MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5400MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME); 5401MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME); 5402MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME);
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