resources.h

  1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
  2/* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
  3
  4#ifndef _MLXSW_RESOURCES_H
  5#define _MLXSW_RESOURCES_H
  6
  7#include <linux/kernel.h>
  8#include <linux/types.h>
  9
 10enum mlxsw_res_id {
 11	MLXSW_RES_ID_KVD_SIZE,
 12	MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
 13	MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
 14	MLXSW_RES_ID_PGT_SIZE,
 15	MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
 16	MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
 17	MLXSW_RES_ID_MAX_TRAP_GROUPS,
 18	MLXSW_RES_ID_CQE_V0,
 19	MLXSW_RES_ID_CQE_V1,
 20	MLXSW_RES_ID_CQE_V2,
 21	MLXSW_RES_ID_COUNTER_POOL_SIZE,
 22	MLXSW_RES_ID_COUNTER_BANK_SIZE,
 23	MLXSW_RES_ID_MAX_SPAN,
 24	MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
 25	MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
 26	MLXSW_RES_ID_MAX_SYSTEM_PORT,
 27	MLXSW_RES_ID_FID,
 28	MLXSW_RES_ID_MAX_LAG,
 29	MLXSW_RES_ID_MAX_LAG_MEMBERS,
 30	MLXSW_RES_ID_MAX_NVE_FLOOD_PRF,
 31	MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,
 32	MLXSW_RES_ID_CELL_SIZE,
 33	MLXSW_RES_ID_MAX_HEADROOM_SIZE,
 34	MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
 35	MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
 36	MLXSW_RES_ID_ACL_MAX_REGIONS,
 37	MLXSW_RES_ID_ACL_MAX_GROUPS,
 38	MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
 39	MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS,
 40	MLXSW_RES_ID_ACL_FLEX_KEYS,
 41	MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
 42	MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
 43	MLXSW_RES_ID_ACL_MAX_L4_PORT_RANGE,
 44	MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
 45	MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
 46	MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
 47	MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
 48	MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
 49	MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
 50	MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
 51	MLXSW_RES_ID_ACL_MAX_BF_LOG,
 52	MLXSW_RES_ID_MAX_GLOBAL_POLICERS,
 53	MLXSW_RES_ID_MAX_CPU_POLICERS,
 54	MLXSW_RES_ID_MAX_VRS,
 55	MLXSW_RES_ID_MAX_RIFS,
 56	MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
 57	MLXSW_RES_ID_MAX_RIF_MAC_PROFILES,
 58	MLXSW_RES_ID_MAX_LPM_TREES,
 59	MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4,
 60	MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6,
 61
 62	/* Internal resources.
 63	 * Determined by the SW, not queried from the HW.
 64	 */
 65	MLXSW_RES_ID_KVD_SINGLE_SIZE,
 66	MLXSW_RES_ID_KVD_DOUBLE_SIZE,
 67	MLXSW_RES_ID_KVD_LINEAR_SIZE,
 68
 69	__MLXSW_RES_ID_MAX,
 70};
 71
 72static u16 mlxsw_res_ids[] = {
 73	[MLXSW_RES_ID_KVD_SIZE] = 0x1001,
 74	[MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
 75	[MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
 76	[MLXSW_RES_ID_PGT_SIZE] = 0x1004,
 77	[MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
 78	[MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
 79	[MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
 80	[MLXSW_RES_ID_CQE_V0] = 0x2210,
 81	[MLXSW_RES_ID_CQE_V1] = 0x2211,
 82	[MLXSW_RES_ID_CQE_V2] = 0x2212,
 83	[MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
 84	[MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411,
 85	[MLXSW_RES_ID_MAX_SPAN] = 0x2420,
 86	[MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
 87	[MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
 88	[MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
 89	[MLXSW_RES_ID_FID] = 0x2512,
 90	[MLXSW_RES_ID_MAX_LAG] = 0x2520,
 91	[MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
 92	[MLXSW_RES_ID_MAX_NVE_FLOOD_PRF] = 0x2522,
 93	[MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805,	/* Bytes */
 94	[MLXSW_RES_ID_CELL_SIZE] = 0x2803,	/* Bytes */
 95	[MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811,	/* Bytes */
 96	[MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
 97	[MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
 98	[MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
 99	[MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
100	[MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
101	[MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS] = 0x2908,
102	[MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
103	[MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
104	[MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
105	[MLXSW_RES_ID_ACL_MAX_L4_PORT_RANGE] = 0x2920,
106	[MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
107	[MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
108	[MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
109	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
110	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
111	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
112	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
113	[MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960,
114	[MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10,
115	[MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
116	[MLXSW_RES_ID_MAX_VRS] = 0x2C01,
117	[MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
118	[MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
119	[MLXSW_RES_ID_MAX_RIF_MAC_PROFILES] = 0x2C14,
120	[MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
121	[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02,
122	[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03,
123};
124
125struct mlxsw_res {
126	bool valid[__MLXSW_RES_ID_MAX];
127	u64 values[__MLXSW_RES_ID_MAX];
128};
129
130static inline bool mlxsw_res_valid(struct mlxsw_res *res,
131				   enum mlxsw_res_id res_id)
132{
133	return res->valid[res_id];
134}
135
136#define MLXSW_RES_VALID(res, short_res_id)			\
137	mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
138
139static inline u64 mlxsw_res_get(struct mlxsw_res *res,
140				enum mlxsw_res_id res_id)
141{
142	if (WARN_ON(!res->valid[res_id]))
143		return 0;
144	return res->values[res_id];
145}
146
147#define MLXSW_RES_GET(res, short_res_id)			\
148	mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
149
150static inline void mlxsw_res_set(struct mlxsw_res *res,
151				 enum mlxsw_res_id res_id, u64 value)
152{
153	res->valid[res_id] = true;
154	res->values[res_id] = value;
155}
156
157#define MLXSW_RES_SET(res, short_res_id, value)			\
158	mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
159
160static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
161{
162	int i;
163
164	for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
165		if (mlxsw_res_ids[i] == id) {
166			mlxsw_res_set(res, i, value);
167			return;
168		}
169	}
170}
171
172#endif