mlxbf_gige_main.c

  1// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
  2
  3/* Gigabit Ethernet driver for Mellanox BlueField SoC
  4 *
  5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
  6 */
  7
  8#include <linux/acpi.h>
  9#include <linux/device.h>
 10#include <linux/dma-mapping.h>
 11#include <linux/etherdevice.h>
 12#include <linux/interrupt.h>
 13#include <linux/iopoll.h>
 14#include <linux/module.h>
 15#include <linux/phy.h>
 16#include <linux/platform_device.h>
 17#include <linux/rtnetlink.h>
 18#include <linux/skbuff.h>
 19
 20#include "mlxbf_gige.h"
 21#include "mlxbf_gige_regs.h"
 22
 23/* Allocate SKB whose payload pointer aligns with the Bluefield
 24 * hardware DMA limitation, i.e. DMA operation can't cross
 25 * a 4KB boundary.  A maximum packet size of 2KB is assumed in the
 26 * alignment formula.  The alignment logic overallocates an SKB,
 27 * and then adjusts the headroom so that the SKB data pointer is
 28 * naturally aligned to a 2KB boundary.
 29 */
 30struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
 31				     unsigned int map_len,
 32				     dma_addr_t *buf_dma,
 33				     enum dma_data_direction dir)
 34{
 35	struct sk_buff *skb;
 36	u64 addr, offset;
 37
 38	/* Overallocate the SKB so that any headroom adjustment (to
 39	 * provide 2KB natural alignment) does not exceed payload area
 40	 */
 41	skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2);
 42	if (!skb)
 43		return NULL;
 44
 45	/* Adjust the headroom so that skb->data is naturally aligned to
 46	 * a 2KB boundary, which is the maximum packet size supported.
 47	 */
 48	addr = (long)skb->data;
 49	offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) &
 50		~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1);
 51	offset -= addr;
 52	if (offset)
 53		skb_reserve(skb, offset);
 54
 55	/* Return streaming DMA mapping to caller */
 56	*buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir);
 57	if (dma_mapping_error(priv->dev, *buf_dma)) {
 58		dev_kfree_skb(skb);
 59		*buf_dma = (dma_addr_t)0;
 60		return NULL;
 61	}
 62
 63	return skb;
 64}
 65
 66static void mlxbf_gige_initial_mac(struct mlxbf_gige *priv)
 67{
 68	u8 mac[ETH_ALEN];
 69	u64 local_mac;
 70
 71	eth_zero_addr(mac);
 72	mlxbf_gige_get_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
 73				     &local_mac);
 74	u64_to_ether_addr(local_mac, mac);
 75
 76	if (is_valid_ether_addr(mac)) {
 77		eth_hw_addr_set(priv->netdev, mac);
 78	} else {
 79		/* Provide a random MAC if for some reason the device has
 80		 * not been configured with a valid MAC address already.
 81		 */
 82		eth_hw_addr_random(priv->netdev);
 83	}
 84
 85	local_mac = ether_addr_to_u64(priv->netdev->dev_addr);
 86	mlxbf_gige_set_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
 87				     local_mac);
 88}
 89
 90static void mlxbf_gige_cache_stats(struct mlxbf_gige *priv)
 91{
 92	struct mlxbf_gige_stats *p;
 93
 94	/* Cache stats that will be cleared by clean port operation */
 95	p = &priv->stats;
 96	p->rx_din_dropped_pkts += readq(priv->base +
 97					MLXBF_GIGE_RX_DIN_DROP_COUNTER);
 98	p->rx_filter_passed_pkts += readq(priv->base +
 99					  MLXBF_GIGE_RX_PASS_COUNTER_ALL);
100	p->rx_filter_discard_pkts += readq(priv->base +
101					   MLXBF_GIGE_RX_DISC_COUNTER_ALL);
102}
103
104static int mlxbf_gige_clean_port(struct mlxbf_gige *priv)
105{
106	u64 control;
107	u64 temp;
108	int err;
109
110	/* Set the CLEAN_PORT_EN bit to trigger SW reset */
111	control = readq(priv->base + MLXBF_GIGE_CONTROL);
112	control |= MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
113	writeq(control, priv->base + MLXBF_GIGE_CONTROL);
114
115	/* Ensure completion of "clean port" write before polling status */
116	mb();
117
118	err = readq_poll_timeout_atomic(priv->base + MLXBF_GIGE_STATUS, temp,
119					(temp & MLXBF_GIGE_STATUS_READY),
120					100, 100000);
121
122	/* Clear the CLEAN_PORT_EN bit at end of this loop */
123	control = readq(priv->base + MLXBF_GIGE_CONTROL);
124	control &= ~MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
125	writeq(control, priv->base + MLXBF_GIGE_CONTROL);
126
127	return err;
128}
129
130static int mlxbf_gige_open(struct net_device *netdev)
131{
132	struct mlxbf_gige *priv = netdev_priv(netdev);
133	struct phy_device *phydev = netdev->phydev;
134	u64 control;
135	u64 int_en;
136	int err;
137
138	/* Perform general init of GigE block */
139	control = readq(priv->base + MLXBF_GIGE_CONTROL);
140	control |= MLXBF_GIGE_CONTROL_PORT_EN;
141	writeq(control, priv->base + MLXBF_GIGE_CONTROL);
142
143	mlxbf_gige_cache_stats(priv);
144	err = mlxbf_gige_clean_port(priv);
145	if (err) {
146		dev_err(priv->dev, "open: clean_port failed: %pe\n", ERR_PTR(err));
147		return err;
148	}
149
150	/* Clear driver's valid_polarity to match hardware,
151	 * since the above call to clean_port() resets the
152	 * receive polarity used by hardware.
153	 */
154	priv->valid_polarity = 0;
155
156	phy_start(phydev);
157
158	err = mlxbf_gige_tx_init(priv);
159	if (err) {
160		dev_err(priv->dev, "open: tx_init failed: %pe\n", ERR_PTR(err));
161		goto phy_deinit;
162	}
163	err = mlxbf_gige_rx_init(priv);
164	if (err) {
165		dev_err(priv->dev, "open: rx_init failed: %pe\n", ERR_PTR(err));
166		goto tx_deinit;
167	}
168
169	netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll);
170	napi_enable(&priv->napi);
171	netif_start_queue(netdev);
172
173	err = mlxbf_gige_request_irqs(priv);
174	if (err) {
175		dev_err(priv->dev, "open: request_irqs failed: %pe\n", ERR_PTR(err));
176		goto napi_deinit;
177	}
178
179	mlxbf_gige_enable_mac_rx_filter(priv, MLXBF_GIGE_BCAST_MAC_FILTER_IDX);
180	mlxbf_gige_enable_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX);
181	mlxbf_gige_enable_multicast_rx(priv);
182
183	/* Set bits in INT_EN that we care about */
184	int_en = MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR |
185		 MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS |
186		 MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE |
187		 MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE |
188		 MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR |
189		 MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR |
190		 MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET;
191
192	/* Ensure completion of all initialization before enabling interrupts */
193	mb();
194
195	writeq(int_en, priv->base + MLXBF_GIGE_INT_EN);
196
197	return 0;
198
199napi_deinit:
200	netif_stop_queue(netdev);
201	napi_disable(&priv->napi);
202	netif_napi_del(&priv->napi);
203	mlxbf_gige_rx_deinit(priv);
204
205tx_deinit:
206	mlxbf_gige_tx_deinit(priv);
207
208phy_deinit:
209	phy_stop(phydev);
210	return err;
211}
212
213static int mlxbf_gige_stop(struct net_device *netdev)
214{
215	struct mlxbf_gige *priv = netdev_priv(netdev);
216
217	writeq(0, priv->base + MLXBF_GIGE_INT_EN);
218	netif_stop_queue(netdev);
219	napi_disable(&priv->napi);
220	netif_napi_del(&priv->napi);
221	mlxbf_gige_free_irqs(priv);
222
223	phy_stop(netdev->phydev);
224
225	mlxbf_gige_rx_deinit(priv);
226	mlxbf_gige_tx_deinit(priv);
227	mlxbf_gige_cache_stats(priv);
228	mlxbf_gige_clean_port(priv);
229
230	return 0;
231}
232
233static int mlxbf_gige_eth_ioctl(struct net_device *netdev,
234				struct ifreq *ifr, int cmd)
235{
236	if (!(netif_running(netdev)))
237		return -EINVAL;
238
239	return phy_mii_ioctl(netdev->phydev, ifr, cmd);
240}
241
242static void mlxbf_gige_set_rx_mode(struct net_device *netdev)
243{
244	struct mlxbf_gige *priv = netdev_priv(netdev);
245	bool new_promisc_enabled;
246
247	new_promisc_enabled = netdev->flags & IFF_PROMISC;
248
249	/* Only write to the hardware registers if the new setting
250	 * of promiscuous mode is different from the current one.
251	 */
252	if (new_promisc_enabled != priv->promisc_enabled) {
253		priv->promisc_enabled = new_promisc_enabled;
254
255		if (new_promisc_enabled)
256			mlxbf_gige_enable_promisc(priv);
257		else
258			mlxbf_gige_disable_promisc(priv);
259	}
260}
261
262static void mlxbf_gige_get_stats64(struct net_device *netdev,
263				   struct rtnl_link_stats64 *stats)
264{
265	struct mlxbf_gige *priv = netdev_priv(netdev);
266
267	netdev_stats_to_stats64(stats, &netdev->stats);
268
269	stats->rx_length_errors = priv->stats.rx_truncate_errors;
270	stats->rx_fifo_errors = priv->stats.rx_din_dropped_pkts +
271				readq(priv->base + MLXBF_GIGE_RX_DIN_DROP_COUNTER);
272	stats->rx_crc_errors = priv->stats.rx_mac_errors;
273	stats->rx_errors = stats->rx_length_errors +
274			   stats->rx_fifo_errors +
275			   stats->rx_crc_errors;
276
277	stats->tx_fifo_errors = priv->stats.tx_fifo_full;
278	stats->tx_errors = stats->tx_fifo_errors;
279}
280
281static const struct net_device_ops mlxbf_gige_netdev_ops = {
282	.ndo_open		= mlxbf_gige_open,
283	.ndo_stop		= mlxbf_gige_stop,
284	.ndo_start_xmit		= mlxbf_gige_start_xmit,
285	.ndo_set_mac_address	= eth_mac_addr,
286	.ndo_validate_addr	= eth_validate_addr,
287	.ndo_eth_ioctl		= mlxbf_gige_eth_ioctl,
288	.ndo_set_rx_mode        = mlxbf_gige_set_rx_mode,
289	.ndo_get_stats64        = mlxbf_gige_get_stats64,
290};
291
292static void mlxbf_gige_bf2_adjust_link(struct net_device *netdev)
293{
294	struct phy_device *phydev = netdev->phydev;
295
296	phy_print_status(phydev);
297}
298
299static void mlxbf_gige_bf3_adjust_link(struct net_device *netdev)
300{
301	struct mlxbf_gige *priv = netdev_priv(netdev);
302	struct phy_device *phydev = netdev->phydev;
303	u8 sgmii_mode;
304	u16 ipg_size;
305	u32 val;
306
307	if (phydev->link && phydev->speed != priv->prev_speed) {
308		switch (phydev->speed) {
309		case 1000:
310			ipg_size = MLXBF_GIGE_1G_IPG_SIZE;
311			sgmii_mode = MLXBF_GIGE_1G_SGMII_MODE;
312			break;
313		case 100:
314			ipg_size = MLXBF_GIGE_100M_IPG_SIZE;
315			sgmii_mode = MLXBF_GIGE_100M_SGMII_MODE;
316			break;
317		case 10:
318			ipg_size = MLXBF_GIGE_10M_IPG_SIZE;
319			sgmii_mode = MLXBF_GIGE_10M_SGMII_MODE;
320			break;
321		default:
322			return;
323		}
324
325		val = readl(priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);
326		val &= ~(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK | MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK);
327		val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK, ipg_size);
328		val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK, sgmii_mode);
329		writel(val, priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);
330
331		val = readl(priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);
332		val &= ~MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK;
333		val |= FIELD_PREP(MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK, sgmii_mode);
334		writel(val, priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);
335
336		priv->prev_speed = phydev->speed;
337	}
338
339	phy_print_status(phydev);
340}
341
342static void mlxbf_gige_bf2_set_phy_link_mode(struct phy_device *phydev)
343{
344	/* MAC only supports 1000T full duplex mode */
345	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
346	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
347	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
348	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
349	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
350
351	/* Only symmetric pause with flow control enabled is supported so no
352	 * need to negotiate pause.
353	 */
354	linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
355	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
356}
357
358static void mlxbf_gige_bf3_set_phy_link_mode(struct phy_device *phydev)
359{
360	/* MAC only supports full duplex mode */
361	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
362	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
363	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
364
365	/* Only symmetric pause with flow control enabled is supported so no
366	 * need to negotiate pause.
367	 */
368	linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
369	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
370}
371
372static struct mlxbf_gige_link_cfg mlxbf_gige_link_cfgs[] = {
373	[MLXBF_GIGE_VERSION_BF2] = {
374		.set_phy_link_mode = mlxbf_gige_bf2_set_phy_link_mode,
375		.adjust_link = mlxbf_gige_bf2_adjust_link,
376		.phy_mode = PHY_INTERFACE_MODE_GMII
377	},
378	[MLXBF_GIGE_VERSION_BF3] = {
379		.set_phy_link_mode = mlxbf_gige_bf3_set_phy_link_mode,
380		.adjust_link = mlxbf_gige_bf3_adjust_link,
381		.phy_mode = PHY_INTERFACE_MODE_SGMII
382	}
383};
384
385static int mlxbf_gige_probe(struct platform_device *pdev)
386{
387	struct phy_device *phydev;
388	struct net_device *netdev;
389	struct mlxbf_gige *priv;
390	void __iomem *llu_base;
391	void __iomem *plu_base;
392	void __iomem *base;
393	int addr, phy_irq;
394	unsigned int i;
395	int err;
396
397	base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC);
398	if (IS_ERR(base))
399		return PTR_ERR(base);
400
401	llu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_LLU);
402	if (IS_ERR(llu_base))
403		return PTR_ERR(llu_base);
404
405	plu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_PLU);
406	if (IS_ERR(plu_base))
407		return PTR_ERR(plu_base);
408
409	netdev = devm_alloc_etherdev(&pdev->dev, sizeof(*priv));
410	if (!netdev)
411		return -ENOMEM;
412
413	SET_NETDEV_DEV(netdev, &pdev->dev);
414	netdev->netdev_ops = &mlxbf_gige_netdev_ops;
415	netdev->ethtool_ops = &mlxbf_gige_ethtool_ops;
416	priv = netdev_priv(netdev);
417	priv->netdev = netdev;
418
419	platform_set_drvdata(pdev, priv);
420	priv->dev = &pdev->dev;
421	priv->pdev = pdev;
422
423	spin_lock_init(&priv->lock);
424
425	priv->hw_version = readq(base + MLXBF_GIGE_VERSION);
426
427	/* Attach MDIO device */
428	err = mlxbf_gige_mdio_probe(pdev, priv);
429	if (err) {
430		dev_err(priv->dev, "probe: mdio_probe failed: %pe\n", ERR_PTR(err));
431		return err;
432	}
433
434	priv->base = base;
435	priv->llu_base = llu_base;
436	priv->plu_base = plu_base;
437
438	priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ;
439	priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ;
440
441	for (i = 0; i <= MLXBF_GIGE_MAX_FILTER_IDX; i++)
442		mlxbf_gige_disable_mac_rx_filter(priv, i);
443	mlxbf_gige_disable_multicast_rx(priv);
444	mlxbf_gige_disable_promisc(priv);
445
446	/* Write initial MAC address to hardware */
447	mlxbf_gige_initial_mac(priv);
448
449	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
450	if (err) {
451		dev_err(&pdev->dev, "DMA configuration failed: %pe\n", ERR_PTR(err));
452		goto out;
453	}
454
455	priv->error_irq = platform_get_irq(pdev, MLXBF_GIGE_ERROR_INTR_IDX);
456	priv->rx_irq = platform_get_irq(pdev, MLXBF_GIGE_RECEIVE_PKT_INTR_IDX);
457	priv->llu_plu_irq = platform_get_irq(pdev, MLXBF_GIGE_LLU_PLU_INTR_IDX);
458
459	phy_irq = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(&pdev->dev), "phy", 0);
460	if (phy_irq == -EPROBE_DEFER) {
461		err = -EPROBE_DEFER;
462		goto out;
463	} else if (phy_irq < 0) {
464		phy_irq = PHY_POLL;
465	}
466
467	phydev = phy_find_first(priv->mdiobus);
468	if (!phydev) {
469		err = -ENODEV;
470		goto out;
471	}
472
473	addr = phydev->mdio.addr;
474	priv->mdiobus->irq[addr] = phy_irq;
475	phydev->irq = phy_irq;
476
477	err = phy_connect_direct(netdev, phydev,
478				 mlxbf_gige_link_cfgs[priv->hw_version].adjust_link,
479				 mlxbf_gige_link_cfgs[priv->hw_version].phy_mode);
480	if (err) {
481		dev_err(&pdev->dev, "Could not attach to PHY: %pe\n", ERR_PTR(err));
482		goto out;
483	}
484
485	mlxbf_gige_link_cfgs[priv->hw_version].set_phy_link_mode(phydev);
486
487	/* Display information about attached PHY device */
488	phy_attached_info(phydev);
489
490	err = register_netdev(netdev);
491	if (err) {
492		dev_err(&pdev->dev, "Failed to register netdev: %pe\n", ERR_PTR(err));
493		phy_disconnect(phydev);
494		goto out;
495	}
496
497	return 0;
498
499out:
500	mlxbf_gige_mdio_remove(priv);
501	return err;
502}
503
504static void mlxbf_gige_remove(struct platform_device *pdev)
505{
506	struct mlxbf_gige *priv = platform_get_drvdata(pdev);
507
508	unregister_netdev(priv->netdev);
509	phy_disconnect(priv->netdev->phydev);
510	mlxbf_gige_mdio_remove(priv);
511	platform_set_drvdata(pdev, NULL);
512}
513
514static void mlxbf_gige_shutdown(struct platform_device *pdev)
515{
516	struct mlxbf_gige *priv = platform_get_drvdata(pdev);
517
518	rtnl_lock();
519	netif_device_detach(priv->netdev);
520
521	if (netif_running(priv->netdev))
522		dev_close(priv->netdev);
523
524	rtnl_unlock();
525}
526
527static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = {
528	{ "MLNXBF17", 0 },
529	{},
530};
531MODULE_DEVICE_TABLE(acpi, mlxbf_gige_acpi_match);
532
533static struct platform_driver mlxbf_gige_driver = {
534	.probe = mlxbf_gige_probe,
535	.remove = mlxbf_gige_remove,
536	.shutdown = mlxbf_gige_shutdown,
537	.driver = {
538		.name = KBUILD_MODNAME,
539		.acpi_match_table = ACPI_PTR(mlxbf_gige_acpi_match),
540	},
541};
542
543module_platform_driver(mlxbf_gige_driver);
544
545MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver");
546MODULE_AUTHOR("David Thompson <davthompson@nvidia.com>");
547MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
548MODULE_LICENSE("Dual BSD/GPL");