prm.h

  1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
  2/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */
  3
  4#ifndef MLX5_PRM_H_
  5#define MLX5_PRM_H_
  6
  7#define MLX5_MAX_ACTIONS_DATA_IN_HEADER_MODIFY 512
  8
  9/* Action type of header modification. */
 10enum {
 11	MLX5_MODIFICATION_TYPE_SET = 0x1,
 12	MLX5_MODIFICATION_TYPE_ADD = 0x2,
 13	MLX5_MODIFICATION_TYPE_COPY = 0x3,
 14	MLX5_MODIFICATION_TYPE_INSERT = 0x4,
 15	MLX5_MODIFICATION_TYPE_REMOVE = 0x5,
 16	MLX5_MODIFICATION_TYPE_NOP = 0x6,
 17	MLX5_MODIFICATION_TYPE_REMOVE_WORDS = 0x7,
 18	MLX5_MODIFICATION_TYPE_ADD_FIELD = 0x8,
 19	MLX5_MODIFICATION_TYPE_MAX,
 20};
 21
 22/* The field of packet to be modified. */
 23enum mlx5_modification_field {
 24	MLX5_MODI_OUT_NONE = -1,
 25	MLX5_MODI_OUT_SMAC_47_16 = 1,
 26	MLX5_MODI_OUT_SMAC_15_0,
 27	MLX5_MODI_OUT_ETHERTYPE,
 28	MLX5_MODI_OUT_DMAC_47_16,
 29	MLX5_MODI_OUT_DMAC_15_0,
 30	MLX5_MODI_OUT_IP_DSCP,
 31	MLX5_MODI_OUT_TCP_FLAGS,
 32	MLX5_MODI_OUT_TCP_SPORT,
 33	MLX5_MODI_OUT_TCP_DPORT,
 34	MLX5_MODI_OUT_IPV4_TTL,
 35	MLX5_MODI_OUT_UDP_SPORT,
 36	MLX5_MODI_OUT_UDP_DPORT,
 37	MLX5_MODI_OUT_SIPV6_127_96,
 38	MLX5_MODI_OUT_SIPV6_95_64,
 39	MLX5_MODI_OUT_SIPV6_63_32,
 40	MLX5_MODI_OUT_SIPV6_31_0,
 41	MLX5_MODI_OUT_DIPV6_127_96,
 42	MLX5_MODI_OUT_DIPV6_95_64,
 43	MLX5_MODI_OUT_DIPV6_63_32,
 44	MLX5_MODI_OUT_DIPV6_31_0,
 45	MLX5_MODI_OUT_SIPV4,
 46	MLX5_MODI_OUT_DIPV4,
 47	MLX5_MODI_OUT_FIRST_VID,
 48	MLX5_MODI_IN_SMAC_47_16 = 0x31,
 49	MLX5_MODI_IN_SMAC_15_0,
 50	MLX5_MODI_IN_ETHERTYPE,
 51	MLX5_MODI_IN_DMAC_47_16,
 52	MLX5_MODI_IN_DMAC_15_0,
 53	MLX5_MODI_IN_IP_DSCP,
 54	MLX5_MODI_IN_TCP_FLAGS,
 55	MLX5_MODI_IN_TCP_SPORT,
 56	MLX5_MODI_IN_TCP_DPORT,
 57	MLX5_MODI_IN_IPV4_TTL,
 58	MLX5_MODI_IN_UDP_SPORT,
 59	MLX5_MODI_IN_UDP_DPORT,
 60	MLX5_MODI_IN_SIPV6_127_96,
 61	MLX5_MODI_IN_SIPV6_95_64,
 62	MLX5_MODI_IN_SIPV6_63_32,
 63	MLX5_MODI_IN_SIPV6_31_0,
 64	MLX5_MODI_IN_DIPV6_127_96,
 65	MLX5_MODI_IN_DIPV6_95_64,
 66	MLX5_MODI_IN_DIPV6_63_32,
 67	MLX5_MODI_IN_DIPV6_31_0,
 68	MLX5_MODI_IN_SIPV4,
 69	MLX5_MODI_IN_DIPV4,
 70	MLX5_MODI_OUT_IPV6_HOPLIMIT,
 71	MLX5_MODI_IN_IPV6_HOPLIMIT,
 72	MLX5_MODI_META_DATA_REG_A,
 73	MLX5_MODI_META_DATA_REG_B = 0x50,
 74	MLX5_MODI_META_REG_C_0,
 75	MLX5_MODI_META_REG_C_1,
 76	MLX5_MODI_META_REG_C_2,
 77	MLX5_MODI_META_REG_C_3,
 78	MLX5_MODI_META_REG_C_4,
 79	MLX5_MODI_META_REG_C_5,
 80	MLX5_MODI_META_REG_C_6,
 81	MLX5_MODI_META_REG_C_7,
 82	MLX5_MODI_OUT_TCP_SEQ_NUM,
 83	MLX5_MODI_IN_TCP_SEQ_NUM,
 84	MLX5_MODI_OUT_TCP_ACK_NUM,
 85	MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 86	MLX5_MODI_GTP_TEID = 0x6E,
 87	MLX5_MODI_OUT_IP_ECN = 0x73,
 88	MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75,
 89	MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76,
 90	MLX5_MODI_HASH_RESULT = 0x81,
 91	MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a,
 92	MLX5_MODI_IN_MPLS_LABEL_1,
 93	MLX5_MODI_IN_MPLS_LABEL_2,
 94	MLX5_MODI_IN_MPLS_LABEL_3,
 95	MLX5_MODI_IN_MPLS_LABEL_4,
 96	MLX5_MODI_OUT_IP_PROTOCOL = 0x4A,
 97	MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A,
 98	MLX5_MODI_META_REG_C_8 = 0x8F,
 99	MLX5_MODI_META_REG_C_9 = 0x90,
100	MLX5_MODI_META_REG_C_10 = 0x91,
101	MLX5_MODI_META_REG_C_11 = 0x92,
102	MLX5_MODI_META_REG_C_12 = 0x93,
103	MLX5_MODI_META_REG_C_13 = 0x94,
104	MLX5_MODI_META_REG_C_14 = 0x95,
105	MLX5_MODI_META_REG_C_15 = 0x96,
106	MLX5_MODI_OUT_IPV4_TOTAL_LEN = 0x11D,
107	MLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E,
108	MLX5_MODI_OUT_IPV4_IHL = 0x11F,
109	MLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120,
110	MLX5_MODI_OUT_ESP_SPI = 0x5E,
111	MLX5_MODI_OUT_ESP_SEQ_NUM = 0x82,
112	MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126,
113	MLX5_MODI_INVALID = INT_MAX,
114};
115
116enum {
117	MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
118	MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE = 0x8 << 1,
119	MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,
120	MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE = 0x1B << 1,
121	MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
122};
123
124enum mlx5_ifc_rtc_update_mode {
125	MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0,
126	MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1,
127};
128
129enum mlx5_ifc_rtc_access_mode {
130	MLX5_IFC_RTC_STE_ACCESS_MODE_BY_HASH = 0x0,
131	MLX5_IFC_RTC_STE_ACCESS_MODE_LINEAR = 0x1,
132};
133
134enum mlx5_ifc_rtc_ste_format {
135	MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4,
136	MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5,
137	MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7,
138};
139
140enum mlx5_ifc_rtc_reparse_mode {
141	MLX5_IFC_RTC_REPARSE_NEVER = 0x0,
142	MLX5_IFC_RTC_REPARSE_ALWAYS = 0x1,
143	MLX5_IFC_RTC_REPARSE_BY_STC = 0x2,
144};
145
146#define MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX 16
147
148struct mlx5_ifc_rtc_bits {
149	u8 modify_field_select[0x40];
150	u8 reserved_at_40[0x40];
151	u8 update_index_mode[0x2];
152	u8 reparse_mode[0x2];
153	u8 num_match_ste[0x4];
154	u8 pd[0x18];
155	u8 reserved_at_a0[0x9];
156	u8 access_index_mode[0x3];
157	u8 num_hash_definer[0x4];
158	u8 update_method[0x1];
159	u8 reserved_at_b1[0x2];
160	u8 log_depth[0x5];
161	u8 log_hash_size[0x8];
162	u8 ste_format_0[0x8];
163	u8 table_type[0x8];
164	u8 ste_format_1[0x8];
165	u8 reserved_at_d8[0x8];
166	u8 match_definer_0[0x20];
167	u8 stc_id[0x20];
168	u8 ste_table_base_id[0x20];
169	u8 ste_table_offset[0x20];
170	u8 reserved_at_160[0x8];
171	u8 miss_flow_table_id[0x18];
172	u8 match_definer_1[0x20];
173	u8 reserved_at_1a0[0x260];
174};
175
176enum mlx5_ifc_stc_action_type {
177	MLX5_IFC_STC_ACTION_TYPE_NOP = 0x00,
178	MLX5_IFC_STC_ACTION_TYPE_COPY = 0x05,
179	MLX5_IFC_STC_ACTION_TYPE_SET = 0x06,
180	MLX5_IFC_STC_ACTION_TYPE_ADD = 0x07,
181	MLX5_IFC_STC_ACTION_TYPE_REMOVE_WORDS = 0x08,
182	MLX5_IFC_STC_ACTION_TYPE_HEADER_REMOVE = 0x09,
183	MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT = 0x0b,
184	MLX5_IFC_STC_ACTION_TYPE_TAG = 0x0c,
185	MLX5_IFC_STC_ACTION_TYPE_ACC_MODIFY_LIST = 0x0e,
186	MLX5_IFC_STC_ACTION_TYPE_CRYPTO_IPSEC_ENCRYPTION = 0x10,
187	MLX5_IFC_STC_ACTION_TYPE_CRYPTO_IPSEC_DECRYPTION = 0x11,
188	MLX5_IFC_STC_ACTION_TYPE_ASO = 0x12,
189	MLX5_IFC_STC_ACTION_TYPE_TRAILER = 0x13,
190	MLX5_IFC_STC_ACTION_TYPE_COUNTER = 0x14,
191	MLX5_IFC_STC_ACTION_TYPE_ADD_FIELD = 0x1b,
192	MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE = 0x80,
193	MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR = 0x81,
194	MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT = 0x82,
195	MLX5_IFC_STC_ACTION_TYPE_DROP = 0x83,
196	MLX5_IFC_STC_ACTION_TYPE_ALLOW = 0x84,
197	MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT = 0x85,
198	MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_UPLINK = 0x86,
199};
200
201enum mlx5_ifc_stc_reparse_mode {
202	MLX5_IFC_STC_REPARSE_IGNORE = 0x0,
203	MLX5_IFC_STC_REPARSE_NEVER = 0x1,
204	MLX5_IFC_STC_REPARSE_ALWAYS = 0x2,
205};
206
207struct mlx5_ifc_stc_ste_param_ste_table_bits {
208	u8 ste_obj_id[0x20];
209	u8 match_definer_id[0x20];
210	u8 reserved_at_40[0x3];
211	u8 log_hash_size[0x5];
212	u8 reserved_at_48[0x38];
213};
214
215struct mlx5_ifc_stc_ste_param_tir_bits {
216	u8 reserved_at_0[0x8];
217	u8 tirn[0x18];
218	u8 reserved_at_20[0x60];
219};
220
221struct mlx5_ifc_stc_ste_param_table_bits {
222	u8 reserved_at_0[0x8];
223	u8 table_id[0x18];
224	u8 reserved_at_20[0x60];
225};
226
227struct mlx5_ifc_stc_ste_param_flow_counter_bits {
228	u8 flow_counter_id[0x20];
229};
230
231enum {
232	MLX5_ASO_CT_NUM_PER_OBJ = 1,
233	MLX5_ASO_METER_NUM_PER_OBJ = 2,
234	MLX5_ASO_IPSEC_NUM_PER_OBJ = 1,
235	MLX5_ASO_FIRST_HIT_NUM_PER_OBJ = 512,
236};
237
238struct mlx5_ifc_stc_ste_param_execute_aso_bits {
239	u8 aso_object_id[0x20];
240	u8 return_reg_id[0x4];
241	u8 aso_type[0x4];
242	u8 reserved_at_28[0x18];
243};
244
245struct mlx5_ifc_stc_ste_param_ipsec_encrypt_bits {
246	u8 ipsec_object_id[0x20];
247};
248
249struct mlx5_ifc_stc_ste_param_ipsec_decrypt_bits {
250	u8 ipsec_object_id[0x20];
251};
252
253struct mlx5_ifc_stc_ste_param_trailer_bits {
254	u8 reserved_at_0[0x8];
255	u8 command[0x4];
256	u8 reserved_at_c[0x2];
257	u8 type[0x2];
258	u8 reserved_at_10[0xa];
259	u8 length[0x6];
260};
261
262struct mlx5_ifc_stc_ste_param_header_modify_list_bits {
263	u8 header_modify_pattern_id[0x20];
264	u8 header_modify_argument_id[0x20];
265};
266
267enum mlx5_ifc_header_anchors {
268	MLX5_HEADER_ANCHOR_PACKET_START = 0x0,
269	MLX5_HEADER_ANCHOR_MAC = 0x1,
270	MLX5_HEADER_ANCHOR_FIRST_VLAN_START = 0x2,
271	MLX5_HEADER_ANCHOR_IPV6_IPV4 = 0x07,
272	MLX5_HEADER_ANCHOR_ESP = 0x08,
273	MLX5_HEADER_ANCHOR_TCP_UDP = 0x09,
274	MLX5_HEADER_ANCHOR_TUNNEL_HEADER = 0x0a,
275	MLX5_HEADER_ANCHOR_INNER_MAC = 0x13,
276	MLX5_HEADER_ANCHOR_INNER_IPV6_IPV4 = 0x19,
277	MLX5_HEADER_ANCHOR_INNER_TCP_UDP = 0x1a,
278	MLX5_HEADER_ANCHOR_L4_PAYLOAD = 0x1b,
279	MLX5_HEADER_ANCHOR_INNER_L4_PAYLOAD = 0x1c
280};
281
282struct mlx5_ifc_stc_ste_param_remove_bits {
283	u8 action_type[0x4];
284	u8 decap[0x1];
285	u8 reserved_at_5[0x5];
286	u8 remove_start_anchor[0x6];
287	u8 reserved_at_10[0x2];
288	u8 remove_end_anchor[0x6];
289	u8 reserved_at_18[0x8];
290};
291
292struct mlx5_ifc_stc_ste_param_remove_words_bits {
293	u8 action_type[0x4];
294	u8 reserved_at_4[0x6];
295	u8 remove_start_anchor[0x6];
296	u8 reserved_at_10[0x1];
297	u8 remove_offset[0x7];
298	u8 reserved_at_18[0x2];
299	u8 remove_size[0x6];
300};
301
302struct mlx5_ifc_stc_ste_param_insert_bits {
303	u8 action_type[0x4];
304	u8 encap[0x1];
305	u8 inline_data[0x1];
306	u8 reserved_at_6[0x4];
307	u8 insert_anchor[0x6];
308	u8 reserved_at_10[0x1];
309	u8 insert_offset[0x7];
310	u8 reserved_at_18[0x1];
311	u8 insert_size[0x7];
312	u8 insert_argument[0x20];
313};
314
315struct mlx5_ifc_stc_ste_param_vport_bits {
316	u8 eswitch_owner_vhca_id[0x10];
317	u8 vport_number[0x10];
318	u8 eswitch_owner_vhca_id_valid[0x1];
319	u8 reserved_at_21[0x5f];
320};
321
322union mlx5_ifc_stc_param_bits {
323	struct mlx5_ifc_stc_ste_param_ste_table_bits ste_table;
324	struct mlx5_ifc_stc_ste_param_tir_bits tir;
325	struct mlx5_ifc_stc_ste_param_table_bits table;
326	struct mlx5_ifc_stc_ste_param_flow_counter_bits counter;
327	struct mlx5_ifc_stc_ste_param_header_modify_list_bits modify_header;
328	struct mlx5_ifc_stc_ste_param_execute_aso_bits aso;
329	struct mlx5_ifc_stc_ste_param_remove_bits remove_header;
330	struct mlx5_ifc_stc_ste_param_insert_bits insert_header;
331	struct mlx5_ifc_set_action_in_bits add;
332	struct mlx5_ifc_set_action_in_bits set;
333	struct mlx5_ifc_copy_action_in_bits copy;
334	struct mlx5_ifc_stc_ste_param_vport_bits vport;
335	struct mlx5_ifc_stc_ste_param_ipsec_encrypt_bits ipsec_encrypt;
336	struct mlx5_ifc_stc_ste_param_ipsec_decrypt_bits ipsec_decrypt;
337	struct mlx5_ifc_stc_ste_param_trailer_bits trailer;
338	u8 reserved_at_0[0x80];
339};
340
341enum {
342	MLX5_IFC_MODIFY_STC_FIELD_SELECT_NEW_STC = BIT(0),
343};
344
345struct mlx5_ifc_stc_bits {
346	u8 modify_field_select[0x40];
347	u8 reserved_at_40[0x46];
348	u8 reparse_mode[0x2];
349	u8 table_type[0x8];
350	u8 ste_action_offset[0x8];
351	u8 action_type[0x8];
352	u8 reserved_at_a0[0x60];
353	union mlx5_ifc_stc_param_bits stc_param;
354	u8 reserved_at_180[0x280];
355};
356
357struct mlx5_ifc_ste_bits {
358	u8 modify_field_select[0x40];
359	u8 reserved_at_40[0x48];
360	u8 table_type[0x8];
361	u8 reserved_at_90[0x370];
362};
363
364struct mlx5_ifc_definer_bits {
365	u8 modify_field_select[0x40];
366	u8 reserved_at_40[0x50];
367	u8 format_id[0x10];
368	u8 reserved_at_60[0x60];
369	u8 format_select_dw3[0x8];
370	u8 format_select_dw2[0x8];
371	u8 format_select_dw1[0x8];
372	u8 format_select_dw0[0x8];
373	u8 format_select_dw7[0x8];
374	u8 format_select_dw6[0x8];
375	u8 format_select_dw5[0x8];
376	u8 format_select_dw4[0x8];
377	u8 reserved_at_100[0x18];
378	u8 format_select_dw8[0x8];
379	u8 reserved_at_120[0x20];
380	u8 format_select_byte3[0x8];
381	u8 format_select_byte2[0x8];
382	u8 format_select_byte1[0x8];
383	u8 format_select_byte0[0x8];
384	u8 format_select_byte7[0x8];
385	u8 format_select_byte6[0x8];
386	u8 format_select_byte5[0x8];
387	u8 format_select_byte4[0x8];
388	u8 reserved_at_180[0x40];
389	u8 ctrl[0xa0];
390	u8 match_mask[0x160];
391};
392
393struct mlx5_ifc_header_modify_pattern_in_bits {
394	u8 modify_field_select[0x40];
395
396	u8 reserved_at_40[0x40];
397
398	u8 pattern_length[0x8];
399	u8 reserved_at_88[0x18];
400
401	u8 reserved_at_a0[0x60];
402
403	u8 pattern_data[MLX5_MAX_ACTIONS_DATA_IN_HEADER_MODIFY * 8];
404};
405
406struct mlx5_ifc_create_rtc_in_bits {
407	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
408	struct mlx5_ifc_rtc_bits rtc;
409};
410
411struct mlx5_ifc_create_stc_in_bits {
412	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
413	struct mlx5_ifc_stc_bits stc;
414};
415
416struct mlx5_ifc_create_ste_in_bits {
417	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
418	struct mlx5_ifc_ste_bits ste;
419};
420
421struct mlx5_ifc_create_definer_in_bits {
422	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
423	struct mlx5_ifc_definer_bits definer;
424};
425
426struct mlx5_ifc_create_header_modify_pattern_in_bits {
427	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
428	struct mlx5_ifc_header_modify_pattern_in_bits pattern;
429};
430
431struct mlx5_ifc_generate_wqe_in_bits {
432	u8 opcode[0x10];
433	u8 uid[0x10];
434	u8 reserved_at_20[0x10];
435	u8 op_mode[0x10];
436	u8 reserved_at_40[0x40];
437	u8 reserved_at_80[0x8];
438	u8 pdn[0x18];
439	u8 reserved_at_a0[0x160];
440	u8 wqe_ctrl[0x80];
441	u8 wqe_gta_ctrl[0x180];
442	u8 wqe_gta_data_0[0x200];
443	u8 wqe_gta_data_1[0x200];
444};
445
446struct mlx5_ifc_generate_wqe_out_bits {
447	u8 status[0x8];
448	u8 reserved_at_8[0x18];
449	u8 syndrome[0x20];
450	u8 reserved_at_40[0x1c0];
451	u8 cqe_data[0x200];
452};
453
454enum mlx5_access_aso_opc_mod {
455	ASO_OPC_MOD_IPSEC = 0x0,
456	ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
457	ASO_OPC_MOD_POLICER = 0x2,
458	ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
459	ASO_OPC_MOD_FLOW_HIT = 0x4,
460};
461
462enum {
463	MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION = BIT(0),
464	MLX5_IFC_MODIFY_FLOW_TABLE_RTC_ID = BIT(1),
465};
466
467enum {
468	MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_DEFAULT = 0,
469	MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL = 1,
470};
471
472#endif /* MLX5_PRM_H_ */