definer.h

  1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
  2/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */
  3
  4#ifndef HWS_DEFINER_H_
  5#define HWS_DEFINER_H_
  6
  7/* Max available selecotrs */
  8#define DW_SELECTORS 9
  9#define BYTE_SELECTORS 8
 10
 11/* Selectors based on match TAG */
 12#define DW_SELECTORS_MATCH 6
 13#define DW_SELECTORS_LIMITED 3
 14
 15/* Selectors based on range TAG */
 16#define DW_SELECTORS_RANGE 2
 17#define BYTE_SELECTORS_RANGE 8
 18
 19#define HWS_NUM_OF_FLEX_PARSERS 8
 20
 21enum mlx5hws_definer_fname {
 22	MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_O,
 23	MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_I,
 24	MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_O,
 25	MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_I,
 26	MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_O,
 27	MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_I,
 28	MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_O,
 29	MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_I,
 30	MLX5HWS_DEFINER_FNAME_ETH_TYPE_O,
 31	MLX5HWS_DEFINER_FNAME_ETH_TYPE_I,
 32	MLX5HWS_DEFINER_FNAME_ETH_L3_TYPE_O,
 33	MLX5HWS_DEFINER_FNAME_ETH_L3_TYPE_I,
 34	MLX5HWS_DEFINER_FNAME_VLAN_TYPE_O,
 35	MLX5HWS_DEFINER_FNAME_VLAN_TYPE_I,
 36	MLX5HWS_DEFINER_FNAME_VLAN_FIRST_PRIO_O,
 37	MLX5HWS_DEFINER_FNAME_VLAN_FIRST_PRIO_I,
 38	MLX5HWS_DEFINER_FNAME_VLAN_CFI_O,
 39	MLX5HWS_DEFINER_FNAME_VLAN_CFI_I,
 40	MLX5HWS_DEFINER_FNAME_VLAN_ID_O,
 41	MLX5HWS_DEFINER_FNAME_VLAN_ID_I,
 42	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_TYPE_O,
 43	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_TYPE_I,
 44	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_PRIO_O,
 45	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_PRIO_I,
 46	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_CFI_O,
 47	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_CFI_I,
 48	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_ID_O,
 49	MLX5HWS_DEFINER_FNAME_VLAN_SECOND_ID_I,
 50	MLX5HWS_DEFINER_FNAME_IPV4_IHL_O,
 51	MLX5HWS_DEFINER_FNAME_IPV4_IHL_I,
 52	MLX5HWS_DEFINER_FNAME_IP_DSCP_O,
 53	MLX5HWS_DEFINER_FNAME_IP_DSCP_I,
 54	MLX5HWS_DEFINER_FNAME_IP_ECN_O,
 55	MLX5HWS_DEFINER_FNAME_IP_ECN_I,
 56	MLX5HWS_DEFINER_FNAME_IP_TTL_O,
 57	MLX5HWS_DEFINER_FNAME_IP_TTL_I,
 58	MLX5HWS_DEFINER_FNAME_IPV4_DST_O,
 59	MLX5HWS_DEFINER_FNAME_IPV4_DST_I,
 60	MLX5HWS_DEFINER_FNAME_IPV4_SRC_O,
 61	MLX5HWS_DEFINER_FNAME_IPV4_SRC_I,
 62	MLX5HWS_DEFINER_FNAME_IP_VERSION_O,
 63	MLX5HWS_DEFINER_FNAME_IP_VERSION_I,
 64	MLX5HWS_DEFINER_FNAME_IP_FRAG_O,
 65	MLX5HWS_DEFINER_FNAME_IP_FRAG_I,
 66	MLX5HWS_DEFINER_FNAME_IP_LEN_O,
 67	MLX5HWS_DEFINER_FNAME_IP_LEN_I,
 68	MLX5HWS_DEFINER_FNAME_IP_TOS_O,
 69	MLX5HWS_DEFINER_FNAME_IP_TOS_I,
 70	MLX5HWS_DEFINER_FNAME_IPV6_FLOW_LABEL_O,
 71	MLX5HWS_DEFINER_FNAME_IPV6_FLOW_LABEL_I,
 72	MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_O,
 73	MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_O,
 74	MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_O,
 75	MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_O,
 76	MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_I,
 77	MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_I,
 78	MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_I,
 79	MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_I,
 80	MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_O,
 81	MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_O,
 82	MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_O,
 83	MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_O,
 84	MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_I,
 85	MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_I,
 86	MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_I,
 87	MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_I,
 88	MLX5HWS_DEFINER_FNAME_IP_PROTOCOL_O,
 89	MLX5HWS_DEFINER_FNAME_IP_PROTOCOL_I,
 90	MLX5HWS_DEFINER_FNAME_L4_SPORT_O,
 91	MLX5HWS_DEFINER_FNAME_L4_SPORT_I,
 92	MLX5HWS_DEFINER_FNAME_L4_DPORT_O,
 93	MLX5HWS_DEFINER_FNAME_L4_DPORT_I,
 94	MLX5HWS_DEFINER_FNAME_TCP_FLAGS_I,
 95	MLX5HWS_DEFINER_FNAME_TCP_FLAGS_O,
 96	MLX5HWS_DEFINER_FNAME_TCP_SEQ_NUM,
 97	MLX5HWS_DEFINER_FNAME_TCP_ACK_NUM,
 98	MLX5HWS_DEFINER_FNAME_GTP_TEID,
 99	MLX5HWS_DEFINER_FNAME_GTP_MSG_TYPE,
100	MLX5HWS_DEFINER_FNAME_GTP_EXT_FLAG,
101	MLX5HWS_DEFINER_FNAME_GTP_NEXT_EXT_HDR,
102	MLX5HWS_DEFINER_FNAME_GTP_EXT_HDR_PDU,
103	MLX5HWS_DEFINER_FNAME_GTP_EXT_HDR_QFI,
104	MLX5HWS_DEFINER_FNAME_GTPU_DW0,
105	MLX5HWS_DEFINER_FNAME_GTPU_FIRST_EXT_DW0,
106	MLX5HWS_DEFINER_FNAME_GTPU_DW2,
107	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_0,
108	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_1,
109	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_2,
110	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_3,
111	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_4,
112	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_5,
113	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_6,
114	MLX5HWS_DEFINER_FNAME_FLEX_PARSER_7,
115	MLX5HWS_DEFINER_FNAME_VPORT_REG_C_0,
116	MLX5HWS_DEFINER_FNAME_VXLAN_FLAGS,
117	MLX5HWS_DEFINER_FNAME_VXLAN_VNI,
118	MLX5HWS_DEFINER_FNAME_VXLAN_GPE_FLAGS,
119	MLX5HWS_DEFINER_FNAME_VXLAN_GPE_RSVD0,
120	MLX5HWS_DEFINER_FNAME_VXLAN_GPE_PROTO,
121	MLX5HWS_DEFINER_FNAME_VXLAN_GPE_VNI,
122	MLX5HWS_DEFINER_FNAME_VXLAN_GPE_RSVD1,
123	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_LEN,
124	MLX5HWS_DEFINER_FNAME_GENEVE_OAM,
125	MLX5HWS_DEFINER_FNAME_GENEVE_PROTO,
126	MLX5HWS_DEFINER_FNAME_GENEVE_VNI,
127	MLX5HWS_DEFINER_FNAME_SOURCE_QP,
128	MLX5HWS_DEFINER_FNAME_SOURCE_GVMI,
129	MLX5HWS_DEFINER_FNAME_REG_0,
130	MLX5HWS_DEFINER_FNAME_REG_1,
131	MLX5HWS_DEFINER_FNAME_REG_2,
132	MLX5HWS_DEFINER_FNAME_REG_3,
133	MLX5HWS_DEFINER_FNAME_REG_4,
134	MLX5HWS_DEFINER_FNAME_REG_5,
135	MLX5HWS_DEFINER_FNAME_REG_6,
136	MLX5HWS_DEFINER_FNAME_REG_7,
137	MLX5HWS_DEFINER_FNAME_REG_8,
138	MLX5HWS_DEFINER_FNAME_REG_9,
139	MLX5HWS_DEFINER_FNAME_REG_10,
140	MLX5HWS_DEFINER_FNAME_REG_11,
141	MLX5HWS_DEFINER_FNAME_REG_A,
142	MLX5HWS_DEFINER_FNAME_REG_B,
143	MLX5HWS_DEFINER_FNAME_GRE_KEY_PRESENT,
144	MLX5HWS_DEFINER_FNAME_GRE_C,
145	MLX5HWS_DEFINER_FNAME_GRE_K,
146	MLX5HWS_DEFINER_FNAME_GRE_S,
147	MLX5HWS_DEFINER_FNAME_GRE_PROTOCOL,
148	MLX5HWS_DEFINER_FNAME_GRE_OPT_KEY,
149	MLX5HWS_DEFINER_FNAME_GRE_OPT_SEQ,
150	MLX5HWS_DEFINER_FNAME_GRE_OPT_CHECKSUM,
151	MLX5HWS_DEFINER_FNAME_INTEGRITY_O,
152	MLX5HWS_DEFINER_FNAME_INTEGRITY_I,
153	MLX5HWS_DEFINER_FNAME_ICMP_DW1,
154	MLX5HWS_DEFINER_FNAME_ICMP_DW2,
155	MLX5HWS_DEFINER_FNAME_ICMP_DW3,
156	MLX5HWS_DEFINER_FNAME_IPSEC_SPI,
157	MLX5HWS_DEFINER_FNAME_IPSEC_SEQUENCE_NUMBER,
158	MLX5HWS_DEFINER_FNAME_IPSEC_SYNDROME,
159	MLX5HWS_DEFINER_FNAME_MPLS0_O,
160	MLX5HWS_DEFINER_FNAME_MPLS1_O,
161	MLX5HWS_DEFINER_FNAME_MPLS2_O,
162	MLX5HWS_DEFINER_FNAME_MPLS3_O,
163	MLX5HWS_DEFINER_FNAME_MPLS4_O,
164	MLX5HWS_DEFINER_FNAME_MPLS0_I,
165	MLX5HWS_DEFINER_FNAME_MPLS1_I,
166	MLX5HWS_DEFINER_FNAME_MPLS2_I,
167	MLX5HWS_DEFINER_FNAME_MPLS3_I,
168	MLX5HWS_DEFINER_FNAME_MPLS4_I,
169	MLX5HWS_DEFINER_FNAME_FLEX_PARSER0_OK,
170	MLX5HWS_DEFINER_FNAME_FLEX_PARSER1_OK,
171	MLX5HWS_DEFINER_FNAME_FLEX_PARSER2_OK,
172	MLX5HWS_DEFINER_FNAME_FLEX_PARSER3_OK,
173	MLX5HWS_DEFINER_FNAME_FLEX_PARSER4_OK,
174	MLX5HWS_DEFINER_FNAME_FLEX_PARSER5_OK,
175	MLX5HWS_DEFINER_FNAME_FLEX_PARSER6_OK,
176	MLX5HWS_DEFINER_FNAME_FLEX_PARSER7_OK,
177	MLX5HWS_DEFINER_FNAME_OKS2_MPLS0_O,
178	MLX5HWS_DEFINER_FNAME_OKS2_MPLS1_O,
179	MLX5HWS_DEFINER_FNAME_OKS2_MPLS2_O,
180	MLX5HWS_DEFINER_FNAME_OKS2_MPLS3_O,
181	MLX5HWS_DEFINER_FNAME_OKS2_MPLS4_O,
182	MLX5HWS_DEFINER_FNAME_OKS2_MPLS0_I,
183	MLX5HWS_DEFINER_FNAME_OKS2_MPLS1_I,
184	MLX5HWS_DEFINER_FNAME_OKS2_MPLS2_I,
185	MLX5HWS_DEFINER_FNAME_OKS2_MPLS3_I,
186	MLX5HWS_DEFINER_FNAME_OKS2_MPLS4_I,
187	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_0,
188	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_1,
189	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_2,
190	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_3,
191	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_4,
192	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_5,
193	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_6,
194	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_OK_7,
195	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_0,
196	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_1,
197	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_2,
198	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_3,
199	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_4,
200	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_5,
201	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_6,
202	MLX5HWS_DEFINER_FNAME_GENEVE_OPT_DW_7,
203	MLX5HWS_DEFINER_FNAME_IB_L4_OPCODE,
204	MLX5HWS_DEFINER_FNAME_IB_L4_QPN,
205	MLX5HWS_DEFINER_FNAME_IB_L4_A,
206	MLX5HWS_DEFINER_FNAME_RANDOM_NUM,
207	MLX5HWS_DEFINER_FNAME_PTYPE_L2_O,
208	MLX5HWS_DEFINER_FNAME_PTYPE_L2_I,
209	MLX5HWS_DEFINER_FNAME_PTYPE_L3_O,
210	MLX5HWS_DEFINER_FNAME_PTYPE_L3_I,
211	MLX5HWS_DEFINER_FNAME_PTYPE_L4_O,
212	MLX5HWS_DEFINER_FNAME_PTYPE_L4_I,
213	MLX5HWS_DEFINER_FNAME_PTYPE_L4_EXT_O,
214	MLX5HWS_DEFINER_FNAME_PTYPE_L4_EXT_I,
215	MLX5HWS_DEFINER_FNAME_PTYPE_FRAG_O,
216	MLX5HWS_DEFINER_FNAME_PTYPE_FRAG_I,
217	MLX5HWS_DEFINER_FNAME_TNL_HDR_0,
218	MLX5HWS_DEFINER_FNAME_TNL_HDR_1,
219	MLX5HWS_DEFINER_FNAME_TNL_HDR_2,
220	MLX5HWS_DEFINER_FNAME_TNL_HDR_3,
221	MLX5HWS_DEFINER_FNAME_MAX,
222};
223
224enum mlx5hws_definer_match_criteria {
225	MLX5HWS_DEFINER_MATCH_CRITERIA_EMPTY = 0,
226	MLX5HWS_DEFINER_MATCH_CRITERIA_OUTER = 1 << 0,
227	MLX5HWS_DEFINER_MATCH_CRITERIA_MISC = 1 << 1,
228	MLX5HWS_DEFINER_MATCH_CRITERIA_INNER = 1 << 2,
229	MLX5HWS_DEFINER_MATCH_CRITERIA_MISC2 = 1 << 3,
230	MLX5HWS_DEFINER_MATCH_CRITERIA_MISC3 = 1 << 4,
231	MLX5HWS_DEFINER_MATCH_CRITERIA_MISC4 = 1 << 5,
232	MLX5HWS_DEFINER_MATCH_CRITERIA_MISC5 = 1 << 6,
233	MLX5HWS_DEFINER_MATCH_CRITERIA_MISC6 = 1 << 7,
234};
235
236enum mlx5hws_definer_type {
237	MLX5HWS_DEFINER_TYPE_MATCH,
238	MLX5HWS_DEFINER_TYPE_JUMBO,
239};
240
241enum mlx5hws_definer_match_flag {
242	MLX5HWS_DEFINER_MATCH_FLAG_TNL_VXLAN_GPE = 1 << 0,
243	MLX5HWS_DEFINER_MATCH_FLAG_TNL_GENEVE = 1 << 1,
244	MLX5HWS_DEFINER_MATCH_FLAG_TNL_GTPU = 1 << 2,
245	MLX5HWS_DEFINER_MATCH_FLAG_TNL_GRE = 1 << 3,
246	MLX5HWS_DEFINER_MATCH_FLAG_TNL_VXLAN = 1 << 4,
247	MLX5HWS_DEFINER_MATCH_FLAG_TNL_HEADER_0_1 = 1 << 5,
248
249	MLX5HWS_DEFINER_MATCH_FLAG_TNL_GRE_OPT_KEY = 1 << 6,
250	MLX5HWS_DEFINER_MATCH_FLAG_TNL_HEADER_2 = 1 << 7,
251
252	MLX5HWS_DEFINER_MATCH_FLAG_TNL_MPLS_OVER_GRE = 1 << 8,
253	MLX5HWS_DEFINER_MATCH_FLAG_TNL_MPLS_OVER_UDP = 1 << 9,
254
255	MLX5HWS_DEFINER_MATCH_FLAG_ICMPV4 = 1 << 10,
256	MLX5HWS_DEFINER_MATCH_FLAG_ICMPV6 = 1 << 11,
257	MLX5HWS_DEFINER_MATCH_FLAG_TCP_O = 1 << 12,
258	MLX5HWS_DEFINER_MATCH_FLAG_TCP_I = 1 << 13,
259};
260
261struct mlx5hws_definer_fc {
262	struct mlx5hws_context *ctx;
263	/* Source */
264	u32 s_byte_off;
265	int s_bit_off;
266	u32 s_bit_mask;
267	/* Destination */
268	u32 byte_off;
269	int bit_off;
270	u32 bit_mask;
271	enum mlx5hws_definer_fname fname;
272	void (*tag_set)(struct mlx5hws_definer_fc *fc,
273			void *mach_param,
274			u8 *tag);
275	void (*tag_mask_set)(struct mlx5hws_definer_fc *fc,
276			     void *mach_param,
277			     u8 *tag);
278};
279
280struct mlx5_ifc_definer_hl_eth_l2_bits {
281	u8 dmac_47_16[0x20];
282	u8 dmac_15_0[0x10];
283	u8 l3_ethertype[0x10];
284	u8 reserved_at_40[0x1];
285	u8 sx_sniffer[0x1];
286	u8 functional_lb[0x1];
287	u8 ip_fragmented[0x1];
288	u8 qp_type[0x2];
289	u8 encap_type[0x2];
290	u8 port_number[0x2];
291	u8 l3_type[0x2];
292	u8 l4_type_bwc[0x2];
293	u8 first_vlan_qualifier[0x2];
294	u8 first_priority[0x3];
295	u8 first_cfi[0x1];
296	u8 first_vlan_id[0xc];
297	u8 l4_type[0x4];
298	u8 reserved_at_64[0x2];
299	u8 ipsec_layer[0x2];
300	u8 l2_type[0x2];
301	u8 force_lb[0x1];
302	u8 l2_ok[0x1];
303	u8 l3_ok[0x1];
304	u8 l4_ok[0x1];
305	u8 second_vlan_qualifier[0x2];
306	u8 second_priority[0x3];
307	u8 second_cfi[0x1];
308	u8 second_vlan_id[0xc];
309};
310
311struct mlx5_ifc_definer_hl_eth_l2_src_bits {
312	u8 smac_47_16[0x20];
313	u8 smac_15_0[0x10];
314	u8 loopback_syndrome[0x8];
315	u8 l3_type[0x2];
316	u8 l4_type_bwc[0x2];
317	u8 first_vlan_qualifier[0x2];
318	u8 ip_fragmented[0x1];
319	u8 functional_lb[0x1];
320};
321
322struct mlx5_ifc_definer_hl_ib_l2_bits {
323	u8 sx_sniffer[0x1];
324	u8 force_lb[0x1];
325	u8 functional_lb[0x1];
326	u8 reserved_at_3[0x3];
327	u8 port_number[0x2];
328	u8 sl[0x4];
329	u8 qp_type[0x2];
330	u8 lnh[0x2];
331	u8 dlid[0x10];
332	u8 vl[0x4];
333	u8 lrh_packet_length[0xc];
334	u8 slid[0x10];
335};
336
337struct mlx5_ifc_definer_hl_eth_l3_bits {
338	u8 ip_version[0x4];
339	u8 ihl[0x4];
340	union {
341		u8 tos[0x8];
342		struct {
343			u8 dscp[0x6];
344			u8 ecn[0x2];
345		};
346	};
347	u8 time_to_live_hop_limit[0x8];
348	u8 protocol_next_header[0x8];
349	u8 identification[0x10];
350	union {
351		u8 ipv4_frag[0x10];
352		struct {
353			u8 flags[0x3];
354			u8 fragment_offset[0xd];
355		};
356	};
357	u8 ipv4_total_length[0x10];
358	u8 checksum[0x10];
359	u8 reserved_at_60[0xc];
360	u8 flow_label[0x14];
361	u8 packet_length[0x10];
362	u8 ipv6_payload_length[0x10];
363};
364
365struct mlx5_ifc_definer_hl_eth_l4_bits {
366	u8 source_port[0x10];
367	u8 destination_port[0x10];
368	u8 data_offset[0x4];
369	u8 l4_ok[0x1];
370	u8 l3_ok[0x1];
371	u8 ip_fragmented[0x1];
372	u8 tcp_ns[0x1];
373	union {
374		u8 tcp_flags[0x8];
375		struct {
376			u8 tcp_cwr[0x1];
377			u8 tcp_ece[0x1];
378			u8 tcp_urg[0x1];
379			u8 tcp_ack[0x1];
380			u8 tcp_psh[0x1];
381			u8 tcp_rst[0x1];
382			u8 tcp_syn[0x1];
383			u8 tcp_fin[0x1];
384		};
385	};
386	u8 first_fragment[0x1];
387	u8 reserved_at_31[0xf];
388};
389
390struct mlx5_ifc_definer_hl_src_qp_gvmi_bits {
391	u8 loopback_syndrome[0x8];
392	u8 l3_type[0x2];
393	u8 l4_type_bwc[0x2];
394	u8 first_vlan_qualifier[0x2];
395	u8 reserved_at_e[0x1];
396	u8 functional_lb[0x1];
397	u8 source_gvmi[0x10];
398	u8 force_lb[0x1];
399	u8 ip_fragmented[0x1];
400	u8 source_is_requestor[0x1];
401	u8 reserved_at_23[0x5];
402	u8 source_qp[0x18];
403};
404
405struct mlx5_ifc_definer_hl_ib_l4_bits {
406	u8 opcode[0x8];
407	u8 qp[0x18];
408	u8 se[0x1];
409	u8 migreq[0x1];
410	u8 ackreq[0x1];
411	u8 fecn[0x1];
412	u8 becn[0x1];
413	u8 bth[0x1];
414	u8 deth[0x1];
415	u8 dcceth[0x1];
416	u8 reserved_at_28[0x2];
417	u8 pad_count[0x2];
418	u8 tver[0x4];
419	u8 p_key[0x10];
420	u8 reserved_at_40[0x8];
421	u8 deth_source_qp[0x18];
422};
423
424enum mlx5hws_integrity_ok1_bits {
425	MLX5HWS_DEFINER_OKS1_FIRST_L4_OK = 24,
426	MLX5HWS_DEFINER_OKS1_FIRST_L3_OK = 25,
427	MLX5HWS_DEFINER_OKS1_SECOND_L4_OK = 26,
428	MLX5HWS_DEFINER_OKS1_SECOND_L3_OK = 27,
429	MLX5HWS_DEFINER_OKS1_FIRST_L4_CSUM_OK = 28,
430	MLX5HWS_DEFINER_OKS1_FIRST_IPV4_CSUM_OK = 29,
431	MLX5HWS_DEFINER_OKS1_SECOND_L4_CSUM_OK = 30,
432	MLX5HWS_DEFINER_OKS1_SECOND_IPV4_CSUM_OK = 31,
433};
434
435struct mlx5_ifc_definer_hl_oks1_bits {
436	union {
437		u8 oks1_bits[0x20];
438		struct {
439			u8 second_ipv4_checksum_ok[0x1];
440			u8 second_l4_checksum_ok[0x1];
441			u8 first_ipv4_checksum_ok[0x1];
442			u8 first_l4_checksum_ok[0x1];
443			u8 second_l3_ok[0x1];
444			u8 second_l4_ok[0x1];
445			u8 first_l3_ok[0x1];
446			u8 first_l4_ok[0x1];
447			u8 flex_parser7_steering_ok[0x1];
448			u8 flex_parser6_steering_ok[0x1];
449			u8 flex_parser5_steering_ok[0x1];
450			u8 flex_parser4_steering_ok[0x1];
451			u8 flex_parser3_steering_ok[0x1];
452			u8 flex_parser2_steering_ok[0x1];
453			u8 flex_parser1_steering_ok[0x1];
454			u8 flex_parser0_steering_ok[0x1];
455			u8 second_ipv6_extension_header_vld[0x1];
456			u8 first_ipv6_extension_header_vld[0x1];
457			u8 l3_tunneling_ok[0x1];
458			u8 l2_tunneling_ok[0x1];
459			u8 second_tcp_ok[0x1];
460			u8 second_udp_ok[0x1];
461			u8 second_ipv4_ok[0x1];
462			u8 second_ipv6_ok[0x1];
463			u8 second_l2_ok[0x1];
464			u8 vxlan_ok[0x1];
465			u8 gre_ok[0x1];
466			u8 first_tcp_ok[0x1];
467			u8 first_udp_ok[0x1];
468			u8 first_ipv4_ok[0x1];
469			u8 first_ipv6_ok[0x1];
470			u8 first_l2_ok[0x1];
471		};
472	};
473};
474
475struct mlx5_ifc_definer_hl_oks2_bits {
476	u8 reserved_at_0[0xa];
477	u8 second_mpls_ok[0x1];
478	u8 second_mpls4_s_bit[0x1];
479	u8 second_mpls4_qualifier[0x1];
480	u8 second_mpls3_s_bit[0x1];
481	u8 second_mpls3_qualifier[0x1];
482	u8 second_mpls2_s_bit[0x1];
483	u8 second_mpls2_qualifier[0x1];
484	u8 second_mpls1_s_bit[0x1];
485	u8 second_mpls1_qualifier[0x1];
486	u8 second_mpls0_s_bit[0x1];
487	u8 second_mpls0_qualifier[0x1];
488	u8 first_mpls_ok[0x1];
489	u8 first_mpls4_s_bit[0x1];
490	u8 first_mpls4_qualifier[0x1];
491	u8 first_mpls3_s_bit[0x1];
492	u8 first_mpls3_qualifier[0x1];
493	u8 first_mpls2_s_bit[0x1];
494	u8 first_mpls2_qualifier[0x1];
495	u8 first_mpls1_s_bit[0x1];
496	u8 first_mpls1_qualifier[0x1];
497	u8 first_mpls0_s_bit[0x1];
498	u8 first_mpls0_qualifier[0x1];
499};
500
501struct mlx5_ifc_definer_hl_voq_bits {
502	u8 reserved_at_0[0x18];
503	u8 ecn_ok[0x1];
504	u8 congestion[0x1];
505	u8 profile[0x2];
506	u8 internal_prio[0x4];
507};
508
509struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {
510	u8 source_address[0x20];
511	u8 destination_address[0x20];
512};
513
514struct mlx5_ifc_definer_hl_random_number_bits {
515	u8 random_number[0x10];
516	u8 reserved[0x10];
517};
518
519struct mlx5_ifc_definer_hl_ipv6_addr_bits {
520	u8 ipv6_address_127_96[0x20];
521	u8 ipv6_address_95_64[0x20];
522	u8 ipv6_address_63_32[0x20];
523	u8 ipv6_address_31_0[0x20];
524};
525
526struct mlx5_ifc_definer_tcp_icmp_header_bits {
527	union {
528		struct {
529			u8 icmp_dw1[0x20];
530			u8 icmp_dw2[0x20];
531			u8 icmp_dw3[0x20];
532		};
533		struct {
534			u8 tcp_seq[0x20];
535			u8 tcp_ack[0x20];
536			u8 tcp_win_urg[0x20];
537		};
538	};
539};
540
541struct mlx5_ifc_definer_hl_tunnel_header_bits {
542	u8 tunnel_header_0[0x20];
543	u8 tunnel_header_1[0x20];
544	u8 tunnel_header_2[0x20];
545	u8 tunnel_header_3[0x20];
546};
547
548struct mlx5_ifc_definer_hl_ipsec_bits {
549	u8 spi[0x20];
550	u8 sequence_number[0x20];
551	u8 reserved[0x10];
552	u8 ipsec_syndrome[0x8];
553	u8 next_header[0x8];
554};
555
556struct mlx5_ifc_definer_hl_metadata_bits {
557	u8 metadata_to_cqe[0x20];
558	u8 general_purpose[0x20];
559	u8 acomulated_hash[0x20];
560};
561
562struct mlx5_ifc_definer_hl_flex_parser_bits {
563	u8 flex_parser_7[0x20];
564	u8 flex_parser_6[0x20];
565	u8 flex_parser_5[0x20];
566	u8 flex_parser_4[0x20];
567	u8 flex_parser_3[0x20];
568	u8 flex_parser_2[0x20];
569	u8 flex_parser_1[0x20];
570	u8 flex_parser_0[0x20];
571};
572
573struct mlx5_ifc_definer_hl_registers_bits {
574	u8 register_c_10[0x20];
575	u8 register_c_11[0x20];
576	u8 register_c_8[0x20];
577	u8 register_c_9[0x20];
578	u8 register_c_6[0x20];
579	u8 register_c_7[0x20];
580	u8 register_c_4[0x20];
581	u8 register_c_5[0x20];
582	u8 register_c_2[0x20];
583	u8 register_c_3[0x20];
584	u8 register_c_0[0x20];
585	u8 register_c_1[0x20];
586};
587
588struct mlx5_ifc_definer_hl_mpls_bits {
589	u8 mpls0_label[0x20];
590	u8 mpls1_label[0x20];
591	u8 mpls2_label[0x20];
592	u8 mpls3_label[0x20];
593	u8 mpls4_label[0x20];
594};
595
596struct mlx5_ifc_definer_hl_bits {
597	struct mlx5_ifc_definer_hl_eth_l2_bits eth_l2_outer;
598	struct mlx5_ifc_definer_hl_eth_l2_bits eth_l2_inner;
599	struct mlx5_ifc_definer_hl_eth_l2_src_bits eth_l2_src_outer;
600	struct mlx5_ifc_definer_hl_eth_l2_src_bits eth_l2_src_inner;
601	struct mlx5_ifc_definer_hl_ib_l2_bits ib_l2;
602	struct mlx5_ifc_definer_hl_eth_l3_bits eth_l3_outer;
603	struct mlx5_ifc_definer_hl_eth_l3_bits eth_l3_inner;
604	struct mlx5_ifc_definer_hl_eth_l4_bits eth_l4_outer;
605	struct mlx5_ifc_definer_hl_eth_l4_bits eth_l4_inner;
606	struct mlx5_ifc_definer_hl_src_qp_gvmi_bits source_qp_gvmi;
607	struct mlx5_ifc_definer_hl_ib_l4_bits ib_l4;
608	struct mlx5_ifc_definer_hl_oks1_bits oks1;
609	struct mlx5_ifc_definer_hl_oks2_bits oks2;
610	struct mlx5_ifc_definer_hl_voq_bits voq;
611	u8 reserved_at_480[0x380];
612	struct mlx5_ifc_definer_hl_ipv4_src_dst_bits ipv4_src_dest_outer;
613	struct mlx5_ifc_definer_hl_ipv4_src_dst_bits ipv4_src_dest_inner;
614	struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_dst_outer;
615	struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_dst_inner;
616	struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_src_outer;
617	struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_src_inner;
618	u8 unsupported_dest_ib_l3[0x80];
619	u8 unsupported_source_ib_l3[0x80];
620	u8 unsupported_udp_misc_outer[0x20];
621	u8 unsupported_udp_misc_inner[0x20];
622	struct mlx5_ifc_definer_tcp_icmp_header_bits tcp_icmp;
623	struct mlx5_ifc_definer_hl_tunnel_header_bits tunnel_header;
624	struct mlx5_ifc_definer_hl_mpls_bits mpls_outer;
625	struct mlx5_ifc_definer_hl_mpls_bits mpls_inner;
626	u8 unsupported_config_headers_outer[0x80];
627	u8 unsupported_config_headers_inner[0x80];
628	struct mlx5_ifc_definer_hl_random_number_bits random_number;
629	struct mlx5_ifc_definer_hl_ipsec_bits ipsec;
630	struct mlx5_ifc_definer_hl_metadata_bits metadata;
631	u8 unsupported_utc_timestamp[0x40];
632	u8 unsupported_free_running_timestamp[0x40];
633	struct mlx5_ifc_definer_hl_flex_parser_bits flex_parser;
634	struct mlx5_ifc_definer_hl_registers_bits registers;
635	/* Reserved in case header layout on future HW */
636	u8 unsupported_reserved[0xd40];
637};
638
639enum mlx5hws_definer_gtp {
640	MLX5HWS_DEFINER_GTP_EXT_HDR_BIT = 0x04,
641};
642
643struct mlx5_ifc_header_gtp_bits {
644	u8 version[0x3];
645	u8 proto_type[0x1];
646	u8 reserved1[0x1];
647	union {
648		u8 msg_flags[0x3];
649		struct {
650			u8 ext_hdr_flag[0x1];
651			u8 seq_num_flag[0x1];
652			u8 pdu_flag[0x1];
653		};
654	};
655	u8 msg_type[0x8];
656	u8 msg_len[0x8];
657	u8 teid[0x20];
658};
659
660struct mlx5_ifc_header_opt_gtp_bits {
661	u8 seq_num[0x10];
662	u8 pdu_num[0x8];
663	u8 next_ext_hdr_type[0x8];
664};
665
666struct mlx5_ifc_header_gtp_psc_bits {
667	u8 len[0x8];
668	u8 pdu_type[0x4];
669	u8 flags[0x4];
670	u8 qfi[0x8];
671	u8 reserved2[0x8];
672};
673
674struct mlx5_ifc_header_ipv6_vtc_bits {
675	u8 version[0x4];
676	union {
677		u8 tos[0x8];
678		struct {
679			u8 dscp[0x6];
680			u8 ecn[0x2];
681		};
682	};
683	u8 flow_label[0x14];
684};
685
686struct mlx5_ifc_header_ipv6_routing_ext_bits {
687	u8 next_hdr[0x8];
688	u8 hdr_len[0x8];
689	u8 type[0x8];
690	u8 segments_left[0x8];
691	union {
692		u8 flags[0x20];
693		struct {
694			u8 last_entry[0x8];
695			u8 flag[0x8];
696			u8 tag[0x10];
697		};
698	};
699};
700
701struct mlx5_ifc_header_vxlan_bits {
702	u8 flags[0x8];
703	u8 reserved1[0x18];
704	u8 vni[0x18];
705	u8 reserved2[0x8];
706};
707
708struct mlx5_ifc_header_vxlan_gpe_bits {
709	u8 flags[0x8];
710	u8 rsvd0[0x10];
711	u8 protocol[0x8];
712	u8 vni[0x18];
713	u8 rsvd1[0x8];
714};
715
716struct mlx5_ifc_header_gre_bits {
717	union {
718		u8 c_rsvd0_ver[0x10];
719		struct {
720			u8 gre_c_present[0x1];
721			u8 reserved_at_1[0x1];
722			u8 gre_k_present[0x1];
723			u8 gre_s_present[0x1];
724			u8 reserved_at_4[0x9];
725			u8 version[0x3];
726		};
727	};
728	u8 gre_protocol[0x10];
729	u8 checksum[0x10];
730	u8 reserved_at_30[0x10];
731};
732
733struct mlx5_ifc_header_geneve_bits {
734	union {
735		u8 ver_opt_len_o_c_rsvd[0x10];
736		struct {
737			u8 version[0x2];
738			u8 opt_len[0x6];
739			u8 o_flag[0x1];
740			u8 c_flag[0x1];
741			u8 reserved_at_a[0x6];
742		};
743	};
744	u8 protocol_type[0x10];
745	u8 vni[0x18];
746	u8 reserved_at_38[0x8];
747};
748
749struct mlx5_ifc_header_geneve_opt_bits {
750	u8 class[0x10];
751	u8 type[0x8];
752	u8 reserved[0x3];
753	u8 len[0x5];
754};
755
756struct mlx5_ifc_header_icmp_bits {
757	union {
758		u8 icmp_dw1[0x20];
759		struct {
760			u8 type[0x8];
761			u8 code[0x8];
762			u8 cksum[0x10];
763		};
764	};
765	union {
766		u8 icmp_dw2[0x20];
767		struct {
768			u8 ident[0x10];
769			u8 seq_nb[0x10];
770		};
771	};
772};
773
774struct mlx5hws_definer {
775	enum mlx5hws_definer_type type;
776	u8 dw_selector[DW_SELECTORS];
777	u8 byte_selector[BYTE_SELECTORS];
778	struct mlx5hws_rule_match_tag mask;
779	u32 obj_id;
780};
781
782struct mlx5hws_definer_cache {
783	struct list_head list_head;
784};
785
786struct mlx5hws_definer_cache_item {
787	struct mlx5hws_definer definer;
788	u32 refcount; /* protected by context ctrl lock */
789	struct list_head list_node;
790};
791
792static inline bool
793mlx5hws_definer_is_jumbo(struct mlx5hws_definer *definer)
794{
795	return (definer->type == MLX5HWS_DEFINER_TYPE_JUMBO);
796}
797
798void mlx5hws_definer_create_tag(u32 *match_param,
799				struct mlx5hws_definer_fc *fc,
800				u32 fc_sz,
801				u8 *tag);
802
803int mlx5hws_definer_get_id(struct mlx5hws_definer *definer);
804
805int mlx5hws_definer_mt_init(struct mlx5hws_context *ctx,
806			    struct mlx5hws_match_template *mt);
807
808void mlx5hws_definer_mt_uninit(struct mlx5hws_context *ctx,
809			       struct mlx5hws_match_template *mt);
810
811int mlx5hws_definer_init_cache(struct mlx5hws_definer_cache **cache);
812
813void mlx5hws_definer_uninit_cache(struct mlx5hws_definer_cache *cache);
814
815int mlx5hws_definer_compare(struct mlx5hws_definer *definer_a,
816			    struct mlx5hws_definer *definer_b);
817
818int mlx5hws_definer_get_obj(struct mlx5hws_context *ctx,
819			    struct mlx5hws_definer *definer);
820
821void mlx5hws_definer_free(struct mlx5hws_context *ctx,
822			  struct mlx5hws_definer *definer);
823
824int mlx5hws_definer_calc_layout(struct mlx5hws_context *ctx,
825				struct mlx5hws_match_template *mt,
826				struct mlx5hws_definer *match_definer,
827				bool allow_jumbo);
828
829const char *mlx5hws_definer_fname_to_str(enum mlx5hws_definer_fname fname);
830
831#endif /* HWS_DEFINER_H_ */