qos.c

 1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
 2/* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
 3
 4#include "qos.h"
 5
 6#define MLX5_QOS_DEFAULT_DWRR_UID 0
 7
 8bool mlx5_qos_is_supported(struct mlx5_core_dev *mdev)
 9{
10	if (!MLX5_CAP_GEN(mdev, qos))
11		return false;
12	if (!MLX5_CAP_QOS(mdev, nic_sq_scheduling))
13		return false;
14	if (!MLX5_CAP_QOS(mdev, nic_bw_share))
15		return false;
16	if (!MLX5_CAP_QOS(mdev, nic_rate_limit))
17		return false;
18	return true;
19}
20
21int mlx5_qos_max_leaf_nodes(struct mlx5_core_dev *mdev)
22{
23	return 1 << MLX5_CAP_QOS(mdev, log_max_qos_nic_queue_group);
24}
25
26int mlx5_qos_create_leaf_node(struct mlx5_core_dev *mdev, u32 parent_id,
27			      u32 bw_share, u32 max_avg_bw, u32 *id)
28{
29	u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
30
31	if (!mlx5_qos_element_type_supported(mdev,
32					     SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP,
33					     SCHEDULING_HIERARCHY_NIC))
34		return -EOPNOTSUPP;
35
36	MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
37	MLX5_SET(scheduling_context, sched_ctx, element_type,
38		 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP);
39	MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share);
40	MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw);
41
42	return mlx5_create_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC,
43						  sched_ctx, id);
44}
45
46int mlx5_qos_create_inner_node(struct mlx5_core_dev *mdev, u32 parent_id,
47			       u32 bw_share, u32 max_avg_bw, u32 *id)
48{
49	u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
50	void *attr;
51
52	if (!mlx5_qos_element_type_supported(mdev,
53					     SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR,
54					     SCHEDULING_HIERARCHY_NIC) ||
55	    !mlx5_qos_tsar_type_supported(mdev,
56					  TSAR_ELEMENT_TSAR_TYPE_DWRR,
57					  SCHEDULING_HIERARCHY_NIC))
58		return -EOPNOTSUPP;
59
60	MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
61	MLX5_SET(scheduling_context, sched_ctx, element_type,
62		 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);
63	MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share);
64	MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw);
65
66	attr = MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes);
67	MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR);
68
69	return mlx5_create_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC,
70						  sched_ctx, id);
71}
72
73int mlx5_qos_create_root_node(struct mlx5_core_dev *mdev, u32 *id)
74{
75	return mlx5_qos_create_inner_node(mdev, MLX5_QOS_DEFAULT_DWRR_UID, 0, 0, id);
76}
77
78int mlx5_qos_update_node(struct mlx5_core_dev *mdev,
79			 u32 bw_share, u32 max_avg_bw, u32 id)
80{
81	u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
82	u32 bitmask = 0;
83
84	MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share);
85	MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_avg_bw);
86
87	bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE;
88	bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW;
89
90	return mlx5_modify_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC,
91						  sched_ctx, id, bitmask);
92}
93
94int mlx5_qos_destroy_node(struct mlx5_core_dev *mdev, u32 id)
95{
96	return mlx5_destroy_scheduling_element_cmd(mdev, SCHEDULING_HIERARCHY_NIC, id);
97}