en_stats.h

  1/*
  2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
  3 *
  4 * This software is available to you under a choice of one of two
  5 * licenses.  You may choose to be licensed under the terms of the GNU
  6 * General Public License (GPL) Version 2, available from the file
  7 * COPYING in the main directory of this source tree, or the
  8 * OpenIB.org BSD license below:
  9 *
 10 *     Redistribution and use in source and binary forms, with or
 11 *     without modification, are permitted provided that the following
 12 *     conditions are met:
 13 *
 14 *      - Redistributions of source code must retain the above
 15 *        copyright notice, this list of conditions and the following
 16 *        disclaimer.
 17 *
 18 *      - Redistributions in binary form must reproduce the above
 19 *        copyright notice, this list of conditions and the following
 20 *        disclaimer in the documentation and/or other materials
 21 *        provided with the distribution.
 22 *
 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 30 * SOFTWARE.
 31 */
 32
 33#ifndef __MLX5_EN_STATS_H__
 34#define __MLX5_EN_STATS_H__
 35
 36#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
 37	(*(u64 *)((char *)ptr + dsc[i].offset))
 38#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
 39	be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
 40#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
 41	(*(u32 *)((char *)ptr + dsc[i].offset))
 42#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
 43	be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
 44
 45#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
 46#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
 47#define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
 48#define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
 49#define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
 50#define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
 51#define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
 52#define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
 53
 54#define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
 55#define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
 56#define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
 57#define MLX5E_DECLARE_PTP_RQ_STAT(type, fld) "ptp_rq0_"#fld, offsetof(type, fld)
 58
 59#define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)
 60
 61struct counter_desc {
 62	char		format[ETH_GSTRING_LEN];
 63	size_t		offset; /* Byte offset */
 64};
 65
 66enum {
 67	MLX5E_NDO_UPDATE_STATS = BIT(0x1),
 68};
 69
 70struct mlx5e_priv;
 71struct mlx5e_stats_grp {
 72	u16 update_stats_mask;
 73	int (*get_num_stats)(struct mlx5e_priv *priv);
 74	void (*fill_strings)(struct mlx5e_priv *priv, u8 **data);
 75	void (*fill_stats)(struct mlx5e_priv *priv, u64 **data);
 76	void (*update_stats)(struct mlx5e_priv *priv);
 77};
 78
 79void mlx5e_ethtool_put_stat(u64 **data, u64 val);
 80
 81typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
 82
 83#define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
 84
 85#define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
 86	int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
 87
 88#define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
 89	void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
 90
 91#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
 92	void MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 **data)
 93
 94#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
 95	void MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 **data)
 96
 97#define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
 98
 99#define MLX5E_DECLARE_STATS_GRP(grp) \
100	const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
101
102#define MLX5E_DEFINE_STATS_GRP(grp, mask) \
103MLX5E_DECLARE_STATS_GRP(grp) = { \
104	.get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
105	.fill_stats    = MLX5E_STATS_GRP_OP(grp, fill_stats), \
106	.fill_strings  = MLX5E_STATS_GRP_OP(grp, fill_strings), \
107	.update_stats  = MLX5E_STATS_GRP_OP(grp, update_stats), \
108	.update_stats_mask = mask, \
109}
110
111unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
112void mlx5e_stats_update(struct mlx5e_priv *priv);
113void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
114void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
115void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
116
117void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
118			   struct ethtool_pause_stats *pause_stats);
119void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
120			 struct ethtool_fec_stats *fec_stats,
121			 struct ethtool_fec_hist *hist);
122
123void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
124			     struct ethtool_eth_phy_stats *phy_stats);
125void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
126			     struct ethtool_eth_mac_stats *mac_stats);
127void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
128			      struct ethtool_eth_ctrl_stats *ctrl_stats);
129void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
130			  struct ethtool_rmon_stats *rmon,
131			  const struct ethtool_rmon_hist_range **ranges);
132void mlx5e_stats_ts_get(struct mlx5e_priv *priv,
133			struct ethtool_ts_stats *ts_stats);
134void mlx5e_get_link_ext_stats(struct net_device *dev,
135			      struct ethtool_link_ext_stats *stats);
136
137/* Concrete NIC Stats */
138
139struct mlx5e_sw_stats {
140	u64 rx_packets;
141	u64 rx_bytes;
142	u64 tx_packets;
143	u64 tx_bytes;
144	u64 tx_tso_packets;
145	u64 tx_tso_bytes;
146	u64 tx_tso_inner_packets;
147	u64 tx_tso_inner_bytes;
148	u64 tx_added_vlan_packets;
149	u64 tx_nop;
150	u64 tx_mpwqe_blks;
151	u64 tx_mpwqe_pkts;
152	u64 rx_lro_packets;
153	u64 rx_lro_bytes;
154	u64 rx_gro_packets;
155	u64 rx_gro_bytes;
156	u64 rx_gro_skbs;
157	u64 rx_gro_large_hds;
158	u64 rx_hds_nodata_packets;
159	u64 rx_hds_nodata_bytes;
160	u64 rx_hds_nosplit_packets;
161	u64 rx_hds_nosplit_bytes;
162	u64 rx_mcast_packets;
163	u64 rx_ecn_mark;
164	u64 rx_removed_vlan_packets;
165	u64 rx_csum_unnecessary;
166	u64 rx_csum_none;
167	u64 rx_csum_complete;
168	u64 rx_csum_complete_tail;
169	u64 rx_csum_complete_tail_slow;
170	u64 rx_csum_unnecessary_inner;
171	u64 rx_xdp_drop;
172	u64 rx_xdp_redirect;
173	u64 rx_xdp_tx_xmit;
174	u64 rx_xdp_tx_mpwqe;
175	u64 rx_xdp_tx_inlnw;
176	u64 rx_xdp_tx_nops;
177	u64 rx_xdp_tx_full;
178	u64 rx_xdp_tx_err;
179	u64 rx_xdp_tx_cqe;
180	u64 tx_csum_none;
181	u64 tx_csum_partial;
182	u64 tx_csum_partial_inner;
183	u64 tx_queue_stopped;
184	u64 tx_queue_dropped;
185	u64 tx_xmit_more;
186	u64 tx_recover;
187	u64 tx_cqes;
188	u64 tx_queue_wake;
189	u64 tx_cqe_err;
190	u64 tx_xdp_xmit;
191	u64 tx_xdp_mpwqe;
192	u64 tx_xdp_inlnw;
193	u64 tx_xdp_nops;
194	u64 tx_xdp_full;
195	u64 tx_xdp_err;
196	u64 tx_xdp_cqes;
197	u64 rx_wqe_err;
198	u64 rx_mpwqe_filler_cqes;
199	u64 rx_mpwqe_filler_strides;
200	u64 rx_oversize_pkts_sw_drop;
201	u64 rx_buff_alloc_err;
202	u64 rx_cqe_compress_blks;
203	u64 rx_cqe_compress_pkts;
204	u64 rx_congst_umr;
205#ifdef CONFIG_MLX5_EN_ARFS
206	u64 rx_arfs_add;
207	u64 rx_arfs_request_in;
208	u64 rx_arfs_request_out;
209	u64 rx_arfs_expired;
210	u64 rx_arfs_err;
211#endif
212	u64 rx_recover;
213	u64 ch_events;
214	u64 ch_poll;
215	u64 ch_arm;
216	u64 ch_aff_change;
217	u64 ch_force_irq;
218	u64 ch_eq_rearm;
219	u64 rx_pp_alloc_fast;
220	u64 rx_pp_alloc_slow;
221	u64 rx_pp_alloc_slow_high_order;
222	u64 rx_pp_alloc_empty;
223	u64 rx_pp_alloc_refill;
224	u64 rx_pp_alloc_waive;
225	u64 rx_pp_recycle_cached;
226	u64 rx_pp_recycle_cache_full;
227	u64 rx_pp_recycle_ring;
228	u64 rx_pp_recycle_ring_full;
229	u64 rx_pp_recycle_released_ref;
230#ifdef CONFIG_MLX5_EN_TLS
231	u64 tx_tls_encrypted_packets;
232	u64 tx_tls_encrypted_bytes;
233	u64 tx_tls_ooo;
234	u64 tx_tls_dump_packets;
235	u64 tx_tls_dump_bytes;
236	u64 tx_tls_resync_bytes;
237	u64 tx_tls_skip_no_sync_data;
238	u64 tx_tls_drop_no_sync_data;
239	u64 tx_tls_drop_bypass_req;
240
241	u64 rx_tls_decrypted_packets;
242	u64 rx_tls_decrypted_bytes;
243	u64 rx_tls_resync_req_pkt;
244	u64 rx_tls_resync_req_start;
245	u64 rx_tls_resync_req_end;
246	u64 rx_tls_resync_req_skip;
247	u64 rx_tls_resync_res_ok;
248	u64 rx_tls_resync_res_retry;
249	u64 rx_tls_resync_res_skip;
250	u64 rx_tls_err;
251#endif
252
253	u64 rx_xsk_packets;
254	u64 rx_xsk_bytes;
255	u64 rx_xsk_csum_complete;
256	u64 rx_xsk_csum_unnecessary;
257	u64 rx_xsk_csum_unnecessary_inner;
258	u64 rx_xsk_csum_none;
259	u64 rx_xsk_ecn_mark;
260	u64 rx_xsk_removed_vlan_packets;
261	u64 rx_xsk_xdp_drop;
262	u64 rx_xsk_xdp_redirect;
263	u64 rx_xsk_wqe_err;
264	u64 rx_xsk_mpwqe_filler_cqes;
265	u64 rx_xsk_mpwqe_filler_strides;
266	u64 rx_xsk_oversize_pkts_sw_drop;
267	u64 rx_xsk_buff_alloc_err;
268	u64 rx_xsk_cqe_compress_blks;
269	u64 rx_xsk_cqe_compress_pkts;
270	u64 rx_xsk_congst_umr;
271	u64 tx_xsk_xmit;
272	u64 tx_xsk_mpwqe;
273	u64 tx_xsk_inlnw;
274	u64 tx_xsk_full;
275	u64 tx_xsk_err;
276	u64 tx_xsk_cqes;
277};
278
279struct mlx5e_qcounter_stats {
280	u32 rx_out_of_buffer;
281	u32 rx_if_down_packets;
282};
283
284#define VNIC_ENV_GET(vnic_env_stats, c) \
285	MLX5_GET(query_vnic_env_out, (vnic_env_stats)->query_vnic_env_out, \
286		 vport_env.c)
287
288struct mlx5e_vnic_env_stats {
289	__be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
290};
291
292#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
293						vstats->query_vport_out, c)
294
295struct mlx5e_vport_stats {
296	__be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
297};
298
299#define PPORT_802_3_GET(pstats, c) \
300	MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
301		   counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
302#define PPORT_2863_GET(pstats, c) \
303	MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
304		   counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
305#define PPORT_2819_GET(pstats, c) \
306	MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
307		   counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
308#define PPORT_PHY_STATISTICAL_GET(pstats, c) \
309	MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
310		   counter_set.phys_layer_statistical_cntrs.c##_high)
311#define PPORT_PHY_RECOVERY_GET(pstats, c) \
312	MLX5_GET64(ppcnt_reg, (pstats)->phy_recovery_counters, \
313		   counter_set.phys_layer_recovery_cntrs.c)
314#define PPORT_PER_PRIO_GET(pstats, prio, c) \
315	MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
316		   counter_set.eth_per_prio_grp_data_layout.c##_high)
317#define NUM_PPORT_PRIO				8
318#define PPORT_ETH_EXT_GET(pstats, c) \
319	MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
320		   counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
321
322struct mlx5e_pport_stats {
323	__be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
324	__be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
325	__be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
326	__be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
327	__be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
328	__be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
329	__be64 phy_recovery_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
330	__be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
331	__be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
332	__be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
333};
334
335#define PCIE_PERF_GET(pcie_stats, c) \
336	MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
337		 counter_set.pcie_perf_cntrs_grp_data_layout.c)
338
339#define PCIE_PERF_GET64(pcie_stats, c) \
340	MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
341		   counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
342
343struct mlx5e_pcie_stats {
344	__be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
345};
346
347struct mlx5e_rq_stats {
348	u64 packets;
349	u64 bytes;
350	u64 csum_complete;
351	u64 csum_complete_tail;
352	u64 csum_complete_tail_slow;
353	u64 csum_unnecessary;
354	u64 csum_unnecessary_inner;
355	u64 csum_none;
356	u64 lro_packets;
357	u64 lro_bytes;
358	u64 gro_packets;
359	u64 gro_bytes;
360	u64 gro_skbs;
361	u64 gro_large_hds;
362	u64 hds_nodata_packets;
363	u64 hds_nodata_bytes;
364	u64 hds_nosplit_packets;
365	u64 hds_nosplit_bytes;
366	u64 mcast_packets;
367	u64 ecn_mark;
368	u64 removed_vlan_packets;
369	u64 xdp_drop;
370	u64 xdp_redirect;
371	u64 wqe_err;
372	u64 mpwqe_filler_cqes;
373	u64 mpwqe_filler_strides;
374	u64 oversize_pkts_sw_drop;
375	u64 buff_alloc_err;
376	u64 cqe_compress_blks;
377	u64 cqe_compress_pkts;
378	u64 congst_umr;
379#ifdef CONFIG_MLX5_EN_ARFS
380	u64 arfs_add;
381	u64 arfs_request_in;
382	u64 arfs_request_out;
383	u64 arfs_expired;
384	u64 arfs_err;
385#endif
386	u64 recover;
387	u64 pp_alloc_fast;
388	u64 pp_alloc_slow;
389	u64 pp_alloc_slow_high_order;
390	u64 pp_alloc_empty;
391	u64 pp_alloc_refill;
392	u64 pp_alloc_waive;
393	u64 pp_recycle_cached;
394	u64 pp_recycle_cache_full;
395	u64 pp_recycle_ring;
396	u64 pp_recycle_ring_full;
397	u64 pp_recycle_released_ref;
398#ifdef CONFIG_MLX5_EN_TLS
399	u64 tls_decrypted_packets;
400	u64 tls_decrypted_bytes;
401	u64 tls_resync_req_pkt;
402	u64 tls_resync_req_start;
403	u64 tls_resync_req_end;
404	u64 tls_resync_req_skip;
405	u64 tls_resync_res_ok;
406	u64 tls_resync_res_retry;
407	u64 tls_resync_res_skip;
408	u64 tls_err;
409#endif
410};
411
412struct mlx5e_sq_stats {
413	/* commonly accessed in data path */
414	u64 packets;
415	u64 bytes;
416	u64 xmit_more;
417	u64 tso_packets;
418	u64 tso_bytes;
419	u64 tso_inner_packets;
420	u64 tso_inner_bytes;
421	u64 csum_partial;
422	u64 csum_partial_inner;
423	u64 added_vlan_packets;
424	u64 nop;
425	u64 mpwqe_blks;
426	u64 mpwqe_pkts;
427#ifdef CONFIG_MLX5_EN_TLS
428	u64 tls_encrypted_packets;
429	u64 tls_encrypted_bytes;
430	u64 tls_ooo;
431	u64 tls_dump_packets;
432	u64 tls_dump_bytes;
433	u64 tls_resync_bytes;
434	u64 tls_skip_no_sync_data;
435	u64 tls_drop_no_sync_data;
436	u64 tls_drop_bypass_req;
437#endif
438	/* less likely accessed in data path */
439	u64 csum_none;
440	u64 stopped;
441	u64 dropped;
442	u64 recover;
443	u64 timestamps;
444	/* dirtied @completion */
445	u64 cqes ____cacheline_aligned_in_smp;
446	u64 wake;
447	u64 cqe_err;
448};
449
450struct mlx5e_xdpsq_stats {
451	u64 xmit;
452	u64 mpwqe;
453	u64 inlnw;
454	u64 nops;
455	u64 full;
456	u64 err;
457	/* dirtied @completion */
458	u64 cqes ____cacheline_aligned_in_smp;
459};
460
461struct mlx5e_ch_stats {
462	u64 events;
463	u64 poll;
464	u64 arm;
465	u64 aff_change;
466	u64 force_irq;
467	u64 eq_rearm;
468};
469
470struct mlx5e_ptp_cq_stats {
471	u64 cqe;
472	u64 err_cqe;
473	u64 abort;
474	u64 abort_abs_diff_ns;
475	u64 late_cqe;
476	u64 lost_cqe;
477};
478
479struct mlx5e_rep_stats {
480	u64 vport_rx_packets;
481	u64 vport_tx_packets;
482	u64 vport_rx_bytes;
483	u64 vport_tx_bytes;
484	u64 rx_vport_rdma_unicast_packets;
485	u64 tx_vport_rdma_unicast_packets;
486	u64 rx_vport_rdma_unicast_bytes;
487	u64 tx_vport_rdma_unicast_bytes;
488	u64 rx_vport_rdma_multicast_packets;
489	u64 tx_vport_rdma_multicast_packets;
490	u64 rx_vport_rdma_multicast_bytes;
491	u64 tx_vport_rdma_multicast_bytes;
492	u64 vport_loopback_packets;
493	u64 vport_loopback_bytes;
494	u64 rx_vport_out_of_buffer;
495};
496
497struct mlx5e_stats {
498	struct mlx5e_sw_stats sw;
499	struct mlx5e_qcounter_stats qcnt;
500	struct mlx5e_vnic_env_stats vnic;
501	struct mlx5e_vport_stats vport;
502	struct mlx5e_pport_stats pport;
503	struct mlx5e_pcie_stats pcie;
504	struct mlx5e_rep_stats rep_stats;
505};
506
507static inline void mlx5e_stats_copy_rep_stats(struct rtnl_link_stats64 *vf_vport,
508					      struct mlx5e_rep_stats *rep_stats)
509{
510	memset(vf_vport, 0, sizeof(*vf_vport));
511	vf_vport->rx_packets = rep_stats->vport_rx_packets;
512	vf_vport->tx_packets = rep_stats->vport_tx_packets;
513	vf_vport->rx_bytes = rep_stats->vport_rx_bytes;
514	vf_vport->tx_bytes = rep_stats->vport_tx_bytes;
515	vf_vport->rx_missed_errors = rep_stats->rx_vport_out_of_buffer;
516}
517
518extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
519unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
520
521extern MLX5E_DECLARE_STATS_GRP(sw);
522extern MLX5E_DECLARE_STATS_GRP(qcnt);
523extern MLX5E_DECLARE_STATS_GRP(vnic_env);
524extern MLX5E_DECLARE_STATS_GRP(vport);
525extern MLX5E_DECLARE_STATS_GRP(802_3);
526extern MLX5E_DECLARE_STATS_GRP(2863);
527extern MLX5E_DECLARE_STATS_GRP(2819);
528extern MLX5E_DECLARE_STATS_GRP(phy);
529extern MLX5E_DECLARE_STATS_GRP(eth_ext);
530extern MLX5E_DECLARE_STATS_GRP(pcie);
531extern MLX5E_DECLARE_STATS_GRP(per_prio);
532extern MLX5E_DECLARE_STATS_GRP(pme);
533extern MLX5E_DECLARE_STATS_GRP(channels);
534extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
535extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
536extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
537extern MLX5E_DECLARE_STATS_GRP(ptp);
538extern MLX5E_DECLARE_STATS_GRP(macsec_hw);
539extern MLX5E_DECLARE_STATS_GRP(pcie_cong);
540
541#endif /* __MLX5_EN_STATS_H__ */