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en.h
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linux-6.19.14/drivers/net/ethernet/mellanox/mlx5/core/en.h
1/* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#ifndef __MLX5_EN_H__ 33#define __MLX5_EN_H__ 34 35#include <linux/if_vlan.h> 36#include <linux/etherdevice.h> 37#include <linux/timecounter.h> 38#include <linux/net_tstamp.h> 39#include <linux/crash_dump.h> 40#include <linux/mlx5/driver.h> 41#include <linux/mlx5/qp.h> 42#include <linux/mlx5/cq.h> 43#include <linux/mlx5/port.h> 44#include <linux/mlx5/vport.h> 45#include <linux/mlx5/transobj.h> 46#include <linux/mlx5/fs.h> 47#include <linux/rhashtable.h> 48#include <net/udp_tunnel.h> 49#include <net/switchdev.h> 50#include <net/psp/types.h> 51#include <net/xdp.h> 52#include <linux/dim.h> 53#include <linux/bits.h> 54#include "wq.h" 55#include "mlx5_core.h" 56#include "en_stats.h" 57#include "en/dcbnl.h" 58#include "en/fs.h" 59#include "en/qos.h" 60#include "lib/hv_vhca.h" 61#include "lib/clock.h" 62#include "en/rx_res.h" 63#include "en/selq.h" 64#include "lib/sd.h" 65 66extern const struct net_device_ops mlx5e_netdev_ops; 67struct page_pool; 68 69#define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 70#define MLX5E_METADATA_ETHER_LEN 8 71 72#define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 73 74#define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 75#define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 76 77#define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 78 79#define MLX5_RX_HEADROOM NET_SKB_PAD 80#define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 81 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 82 83#define MLX5E_RX_MAX_HEAD (256) 84#define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8) 85#define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) 86#define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 87#define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 88#define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT (6) 89#define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12) 90#define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16) 91#define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE) 92 93#define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 94 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 95#define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 96 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 97#define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 98 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 99 100/* Keep in sync with mlx5e_mpwrq_log_wqe_sz. 101 * These are theoretical maximums, which can be further restricted by 102 * capabilities. These values are used for static resource allocations and 103 * sanity checks. 104 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE 105 * size actually used at runtime, but it's not a problem when calculating static 106 * array sizes. 107 */ 108#define MLX5_UMR_MAX_FLEX_SPACE \ 109 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \ 110 MLX5_UMR_FLEX_ALIGNMENT)) 111#define MLX5_MPWRQ_MAX_PAGES_PER_WQE \ 112 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt)) 113 114#define MLX5E_MAX_RQ_NUM_MTTS \ 115 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */ 116#define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */ 117#define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 118 119#define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 120#define MLX5E_LOG_MAX_RX_WQE_BULK \ 121 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 122 123#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 124#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 125#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 126 127#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 128#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 129#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd 130 131#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 132 133#define MLX5E_DEFAULT_LRO_TIMEOUT 32 134#define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024 135 136#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 137#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 138#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 139#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 140#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 141#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 142#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 143#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 144 145#define MLX5E_MIN_NUM_CHANNELS 0x1 146#define MLX5E_MAX_NUM_CHANNELS 256 147#define MLX5E_TX_CQ_POLL_BUDGET 128 148#define MLX5E_TX_XSK_POLL_BUDGET 64 149#define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 150 151#define mlx5e_state_dereference(priv, p) \ 152 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 153 154enum mlx5e_devcom_events { 155 MPV_DEVCOM_MASTER_UP, 156 MPV_DEVCOM_MASTER_DOWN, 157 MPV_DEVCOM_IPSEC_MASTER_UP, 158 MPV_DEVCOM_IPSEC_MASTER_DOWN, 159}; 160 161static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 162{ 163 if (mlx5_lag_is_lacp_owner(mdev)) 164 return 1; 165 166 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 167} 168 169static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 170{ 171 switch (wq_type) { 172 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 173 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 174 wq_size / 2); 175 default: 176 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 177 wq_size / 2); 178 } 179} 180 181/* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 182static inline unsigned int 183mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 184{ 185 return is_kdump_kernel() ? 186 MLX5E_MIN_NUM_CHANNELS : 187 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS, 188 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size))); 189} 190 191/* The maximum WQE size can be retrieved by max_wqe_sz_sq in 192 * bytes units. Driver hardens the limitation to 1KB (16 193 * WQEBBs), unless firmware capability is stricter. 194 */ 195static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 196{ 197 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX); 198 199 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, 200 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); 201} 202 203static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev) 204{ 205/* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. 206 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, 207 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) 208 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower 209 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be 210 * cache-aligned. 211 */ 212 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev); 213 214 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); 215#if L1_CACHE_BYTES >= 128 216 wqebbs = ALIGN_DOWN(wqebbs, 2); 217#endif 218 return wqebbs; 219} 220 221struct mlx5e_tx_wqe { 222 struct mlx5_wqe_ctrl_seg ctrl; 223 struct mlx5_wqe_eth_seg eth; 224 struct mlx5_wqe_data_seg data[]; 225}; 226 227struct mlx5e_rx_wqe_ll { 228 struct mlx5_wqe_srq_next_seg next; 229 struct mlx5_wqe_data_seg data[]; 230}; 231 232struct mlx5e_rx_wqe_cyc { 233 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); 234}; 235 236struct mlx5e_umr_wqe_hdr { 237 struct mlx5_wqe_ctrl_seg ctrl; 238 struct mlx5_wqe_umr_ctrl_seg uctrl; 239 struct mlx5_mkey_seg mkc; 240}; 241 242struct mlx5e_umr_wqe { 243 struct mlx5e_umr_wqe_hdr hdr; 244 union { 245 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 246 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 247 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); 248 }; 249}; 250static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr), 251 "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe"); 252 253enum mlx5e_priv_flag { 254 MLX5E_PFLAG_RX_CQE_BASED_MODER, 255 MLX5E_PFLAG_TX_CQE_BASED_MODER, 256 MLX5E_PFLAG_RX_CQE_COMPRESS, 257 MLX5E_PFLAG_RX_STRIDING_RQ, 258 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 259 MLX5E_PFLAG_XDP_TX_MPWQE, 260 MLX5E_PFLAG_SKB_TX_MPWQE, 261 MLX5E_PFLAG_TX_PORT_TS, 262 MLX5E_NUM_PFLAGS, /* Keep last */ 263}; 264 265#define MLX5E_SET_PFLAG(params, pflag, enable) \ 266 do { \ 267 if (enable) \ 268 (params)->pflags |= BIT(pflag); \ 269 else \ 270 (params)->pflags &= ~(BIT(pflag)); \ 271 } while (0) 272 273#define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 274 275enum packet_merge { 276 MLX5E_PACKET_MERGE_NONE, 277 MLX5E_PACKET_MERGE_LRO, 278 MLX5E_PACKET_MERGE_SHAMPO, 279}; 280 281struct mlx5e_packet_merge_param { 282 enum packet_merge type; 283 u32 timeout; 284}; 285 286struct mlx5e_params { 287 u8 log_sq_size; 288 u8 rq_wq_type; 289 u8 log_rq_mtu_frames; 290 u16 num_channels; 291 struct { 292 u16 mode; 293 u8 num_tc; 294 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 295 struct { 296 u64 max_rate[TC_MAX_QUEUE]; 297 u32 hw_id[TC_MAX_QUEUE]; 298 } channel; 299 } mqprio; 300 bool rx_cqe_compress_def; 301 struct dim_cq_moder rx_cq_moderation; 302 struct dim_cq_moder tx_cq_moderation; 303 struct mlx5e_packet_merge_param packet_merge; 304 u8 tx_min_inline_mode; 305 bool vlan_strip_disable; 306 bool scatter_fcs_en; 307 bool rx_dim_enabled; 308 bool tx_dim_enabled; 309 bool rx_moder_use_cqe_mode; 310 bool tx_moder_use_cqe_mode; 311 u32 pflags; 312 struct bpf_prog *xdp_prog; 313 struct mlx5e_xsk *xsk; 314 unsigned int sw_mtu; 315 int hard_mtu; 316 bool ptp_rx; 317 __be32 terminate_lkey_be; 318}; 319 320static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 321{ 322 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 323 params->mqprio.num_tc : 1; 324} 325 326/* Keep this enum consistent with the corresponding strings array 327 * declared in en/reporter_rx.c 328 */ 329enum { 330 MLX5E_RQ_STATE_ENABLED = 0, 331 MLX5E_RQ_STATE_RECOVERING, 332 MLX5E_RQ_STATE_DIM, 333 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 334 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 335 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 336 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 337 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */ 338 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */ 339 MLX5E_NUM_RQ_STATES, /* Must be kept last */ 340}; 341 342struct mlx5e_cq { 343 /* data path - accessed per cqe */ 344 struct mlx5_cqwq wq; 345 346 /* data path - accessed per napi poll */ 347 u16 event_ctr; 348 struct napi_struct *napi; 349 struct mlx5_uars_page *uar; 350 struct mlx5_core_cq mcq; 351 struct mlx5e_ch_stats *ch_stats; 352 353 /* control */ 354 struct net_device *netdev; 355 struct mlx5_core_dev *mdev; 356 struct workqueue_struct *workqueue; 357 struct mlx5_wq_ctrl wq_ctrl; 358} ____cacheline_aligned_in_smp; 359 360struct mlx5e_cq_decomp { 361 /* cqe decompression */ 362 struct mlx5_cqe64 title; 363 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 364 u8 mini_arr_idx; 365 u16 left; 366 u16 wqe_counter; 367 bool last_cqe_title; 368} ____cacheline_aligned_in_smp; 369 370enum mlx5e_dma_map_type { 371 MLX5E_DMA_MAP_SINGLE, 372 MLX5E_DMA_MAP_PAGE 373}; 374 375struct mlx5e_sq_dma { 376 dma_addr_t addr; 377 u32 size; 378 enum mlx5e_dma_map_type type; 379}; 380 381/* Keep this enum consistent with the corresponding strings array 382 * declared in en/reporter_tx.c 383 */ 384enum { 385 MLX5E_SQ_STATE_ENABLED = 0, 386 MLX5E_SQ_STATE_MPWQE, 387 MLX5E_SQ_STATE_RECOVERING, 388 MLX5E_SQ_STATE_IPSEC, 389 MLX5E_SQ_STATE_DIM, 390 MLX5E_SQ_STATE_PENDING_XSK_TX, 391 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 392 MLX5E_NUM_SQ_STATES, /* Must be kept last */ 393}; 394 395struct mlx5e_tx_mpwqe { 396 /* Current MPWQE session */ 397 struct mlx5e_tx_wqe *wqe; 398 u32 bytes_count; 399 u8 ds_count; 400 u8 ds_count_max; 401 u8 pkt_count; 402 u8 inline_on; 403}; 404 405struct mlx5e_skb_fifo { 406 struct sk_buff **fifo; 407 u16 *pc; 408 u16 *cc; 409 u16 mask; 410}; 411 412struct mlx5e_ptpsq; 413 414struct mlx5e_txqsq { 415 /* data path */ 416 417 /* dirtied @completion */ 418 u16 cc; 419 u16 skb_fifo_cc; 420 u32 dma_fifo_cc; 421 struct dim *dim; /* Adaptive Moderation */ 422 423 /* dirtied @xmit */ 424 u16 pc ____cacheline_aligned_in_smp; 425 u16 skb_fifo_pc; 426 u32 dma_fifo_pc; 427 struct mlx5e_tx_mpwqe mpwqe; 428 429 struct mlx5e_cq cq; 430 431 /* read only */ 432 struct mlx5_wq_cyc wq; 433 u32 dma_fifo_mask; 434 struct mlx5e_sq_stats *stats; 435 struct { 436 struct mlx5e_sq_dma *dma_fifo; 437 struct mlx5e_skb_fifo skb_fifo; 438 struct mlx5e_tx_wqe_info *wqe_info; 439 } db; 440 void __iomem *uar_map; 441 struct netdev_queue *txq; 442 u32 sqn; 443 u16 stop_room; 444 u8 max_sq_mpw_wqebbs; 445 u8 min_inline_mode; 446 struct device *pdev; 447 __be32 mkey_be; 448 unsigned long state; 449 unsigned int hw_mtu; 450 struct mlx5_clock *clock; 451 struct net_device *netdev; 452 struct mlx5_core_dev *mdev; 453 struct mlx5e_channel *channel; 454 struct mlx5e_priv *priv; 455 456 /* control path */ 457 struct mlx5_wq_ctrl wq_ctrl; 458 int ch_ix; 459 int txq_ix; 460 u32 rate_limit; 461 struct work_struct recover_work; 462 struct mlx5e_ptpsq *ptpsq; 463 cqe_ts_to_ns ptp_cyc2time; 464} ____cacheline_aligned_in_smp; 465 466struct mlx5e_xdp_info_fifo { 467 union mlx5e_xdp_info *xi; 468 u32 *cc; 469 u32 *pc; 470 u32 mask; 471}; 472 473struct mlx5e_xdpsq; 474struct mlx5e_xmit_data; 475struct xsk_tx_metadata; 476typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 477typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 478 struct mlx5e_xmit_data *, 479 int, 480 struct xsk_tx_metadata *); 481 482struct mlx5e_xdpsq { 483 /* data path */ 484 485 /* dirtied @completion */ 486 u32 xdpi_fifo_cc; 487 u16 cc; 488 489 /* dirtied @xmit */ 490 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 491 u16 pc; 492 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 493 struct mlx5e_tx_mpwqe mpwqe; 494 495 struct mlx5e_cq cq; 496 497 /* read only */ 498 struct xsk_buff_pool *xsk_pool; 499 struct mlx5_wq_cyc wq; 500 struct mlx5e_xdpsq_stats *stats; 501 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 502 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 503 struct { 504 struct mlx5e_xdp_wqe_info *wqe_info; 505 struct mlx5e_xdp_info_fifo xdpi_fifo; 506 } db; 507 void __iomem *uar_map; 508 u32 sqn; 509 struct device *pdev; 510 __be32 mkey_be; 511 u16 stop_room; 512 u8 max_sq_mpw_wqebbs; 513 u8 min_inline_mode; 514 unsigned long state; 515 unsigned int hw_mtu; 516 517 /* control path */ 518 struct mlx5_wq_ctrl wq_ctrl; 519 struct mlx5e_channel *channel; 520} ____cacheline_aligned_in_smp; 521 522struct mlx5e_xdp_buff { 523 struct xdp_buff xdp; 524 struct mlx5_cqe64 *cqe; 525 struct mlx5e_rq *rq; 526}; 527 528struct mlx5e_ktls_resync_resp; 529 530struct mlx5e_icosq { 531 /* data path */ 532 u16 cc; 533 u16 pc; 534 535 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 536 struct mlx5e_cq cq; 537 538 /* write@xmit, read@completion */ 539 struct { 540 struct mlx5e_icosq_wqe_info *wqe_info; 541 } db; 542 543 /* read only */ 544 struct mlx5_wq_cyc wq; 545 void __iomem *uar_map; 546 u32 sqn; 547 u16 reserved_room; 548 unsigned long state; 549 struct mlx5e_ktls_resync_resp *ktls_resync; 550 551 /* control path */ 552 struct mlx5_wq_ctrl wq_ctrl; 553 struct mlx5e_channel *channel; 554 555 struct work_struct recover_work; 556} ____cacheline_aligned_in_smp; 557 558struct mlx5e_frag_page { 559 netmem_ref netmem; 560 u16 frags; 561}; 562 563enum mlx5e_wqe_frag_flag { 564 MLX5E_WQE_FRAG_LAST_IN_PAGE, 565 MLX5E_WQE_FRAG_SKIP_RELEASE, 566}; 567 568struct mlx5e_wqe_frag_info { 569 union { 570 struct mlx5e_frag_page *frag_page; 571 struct xdp_buff **xskp; 572 }; 573 u32 offset; 574 u8 flags; 575}; 576 577union mlx5e_alloc_units { 578 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages); 579 DECLARE_FLEX_ARRAY(struct page *, pages); 580 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs); 581}; 582 583struct mlx5e_mpw_info { 584 u16 consumed_strides; 585 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); 586 struct mlx5e_frag_page linear_page; 587 union mlx5e_alloc_units alloc_units; 588}; 589 590#define MLX5E_MAX_RX_FRAGS 4 591 592struct mlx5e_rq; 593typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 594typedef struct sk_buff * 595(*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 596 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, 597 u32 head_offset, u32 page_idx); 598typedef struct sk_buff * 599(*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 600 struct mlx5_cqe64 *cqe, u32 cqe_bcnt); 601typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 602typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 603typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 604 605int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 606void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 607 608enum mlx5e_rq_flag { 609 MLX5E_RQ_FLAG_XDP_XMIT, 610 MLX5E_RQ_FLAG_XDP_REDIRECT, 611}; 612 613struct mlx5e_rq_frag_info { 614 int frag_size; 615 int frag_stride; 616}; 617 618struct mlx5e_rq_frags_info { 619 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 620 u8 num_frags; 621 u8 log_num_frags; 622 u16 wqe_bulk; 623 u16 refill_unit; 624 u8 wqe_index_mask; 625}; 626 627struct mlx5e_dma_info { 628 dma_addr_t addr; 629 union { 630 struct mlx5e_frag_page *frag_page; 631 struct page *page; 632 }; 633}; 634 635struct mlx5e_shampo_hd { 636 struct mlx5e_frag_page *pages; 637 u32 hd_per_wq; 638 u32 hd_per_page; 639 u16 hd_per_wqe; 640 u8 log_hd_per_page; 641 u8 log_hd_entry_size; 642 unsigned long *bitmap; 643 u16 pi; 644 u16 ci; 645 __be32 mkey_be; 646}; 647 648struct mlx5e_hw_gro_data { 649 struct sk_buff *skb; 650 struct flow_keys fk; 651 int second_ip_id; 652}; 653 654enum mlx5e_mpwrq_umr_mode { 655 MLX5E_MPWRQ_UMR_MODE_ALIGNED, 656 MLX5E_MPWRQ_UMR_MODE_UNALIGNED, 657 MLX5E_MPWRQ_UMR_MODE_OVERSIZED, 658 MLX5E_MPWRQ_UMR_MODE_TRIPLE, 659}; 660 661struct mlx5e_rq { 662 /* data path */ 663 union { 664 struct { 665 struct mlx5_wq_cyc wq; 666 struct mlx5e_wqe_frag_info *frags; 667 union mlx5e_alloc_units *alloc_units; 668 struct mlx5e_rq_frags_info info; 669 mlx5e_fp_skb_from_cqe skb_from_cqe; 670 } wqe; 671 struct { 672 struct mlx5_wq_ll wq; 673 struct mlx5e_umr_wqe_hdr umr_wqe; 674 struct mlx5e_mpw_info *info; 675 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 676 __be32 umr_mkey_be; 677 u16 num_strides; 678 u16 actual_wq_head; 679 u8 log_stride_sz; 680 u8 umr_in_progress; 681 u8 umr_last_bulk; 682 u8 umr_completed; 683 u8 min_wqe_bulk; 684 u8 page_shift; 685 u8 pages_per_wqe; 686 u8 umr_wqebbs; 687 u8 mtts_per_wqe; 688 u8 umr_mode; 689 struct mlx5e_shampo_hd *shampo; 690 } mpwqe; 691 }; 692 struct { 693 u16 headroom; 694 u32 frame0_sz; 695 u8 map_dir; /* dma map direction */ 696 } buff; 697 698 struct device *pdev; 699 struct net_device *netdev; 700 struct mlx5e_rq_stats *stats; 701 struct mlx5e_cq cq; 702 struct mlx5e_cq_decomp cqd; 703 struct kernel_hwtstamp_config *hwtstamp_config; 704 struct mlx5_clock *clock; 705 struct mlx5e_icosq *icosq; 706 struct mlx5e_priv *priv; 707 708 struct mlx5e_hw_gro_data *hw_gro_data; 709 710 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 711 mlx5e_fp_post_rx_wqes post_wqes; 712 mlx5e_fp_dealloc_wqe dealloc_wqe; 713 714 unsigned long state; 715 int ix; 716 unsigned int hw_mtu; 717 718 struct dim *dim; /* Dynamic Interrupt Moderation */ 719 720 /* XDP */ 721 struct bpf_prog __rcu *xdp_prog; 722 struct mlx5e_xdpsq *xdpsq; 723 DECLARE_BITMAP(flags, 8); 724 725 /* page pools */ 726 struct page_pool *page_pool; 727 struct page_pool *hd_page_pool; 728 729 struct mlx5e_xdp_buff mxbuf; 730 731 /* AF_XDP zero-copy */ 732 struct xsk_buff_pool *xsk_pool; 733 734 struct work_struct recover_work; 735 struct work_struct rx_timeout_work; 736 737 /* control */ 738 struct mlx5_wq_ctrl wq_ctrl; 739 __be32 mkey_be; 740 u8 wq_type; 741 u32 rqn; 742 struct mlx5_core_dev *mdev; 743 struct mlx5e_channel *channel; 744 struct mlx5e_dma_info wqe_overflow; 745 746 /* XDP read-mostly */ 747 struct xdp_rxq_info xdp_rxq; 748 cqe_ts_to_ns ptp_cyc2time; 749} ____cacheline_aligned_in_smp; 750 751enum mlx5e_channel_state { 752 MLX5E_CHANNEL_STATE_XSK, 753 MLX5E_CHANNEL_NUM_STATES 754}; 755 756struct mlx5e_channel { 757 /* data path */ 758 struct mlx5e_rq rq; 759 struct mlx5e_xdpsq rq_xdpsq; 760 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC]; 761 struct mlx5e_icosq icosq; /* internal control operations */ 762 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 763 bool xdp; 764 struct napi_struct napi; 765 struct device *pdev; 766 struct net_device *netdev; 767 __be32 mkey_be; 768 u16 qos_sqs_size; 769 u8 num_tc; 770 u8 lag_port; 771 772 /* XDP_REDIRECT */ 773 struct mlx5e_xdpsq *xdpsq; 774 775 /* AF_XDP zero-copy */ 776 struct mlx5e_rq xskrq; 777 struct mlx5e_xdpsq xsksq; 778 779 /* Async ICOSQ */ 780 struct mlx5e_icosq async_icosq; 781 /* async_icosq can be accessed from any CPU - the spinlock protects it. */ 782 spinlock_t async_icosq_lock; 783 784 /* data path - accessed per napi poll */ 785 const struct cpumask *aff_mask; 786 struct mlx5e_ch_stats *stats; 787 788 /* control */ 789 struct mlx5e_priv *priv; 790 struct mlx5_core_dev *mdev; 791 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 792 int ix; 793 int vec_ix; 794 int sd_ix; 795 int cpu; 796 struct mlx5_sq_bfreg *bfreg; 797 /* Sync between icosq recovery and XSK enable/disable. */ 798 struct mutex icosq_recovery_lock; 799 800 /* coalescing configuration */ 801 struct dim_cq_moder rx_cq_moder; 802 struct dim_cq_moder tx_cq_moder; 803}; 804 805struct mlx5e_ptp; 806 807struct mlx5e_channels { 808 struct mlx5e_channel **c; 809 struct mlx5e_ptp *ptp; 810 unsigned int num; 811 struct mlx5e_params params; 812}; 813 814struct mlx5e_channel_stats { 815 struct mlx5e_ch_stats ch; 816 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 817 struct mlx5e_rq_stats rq; 818 struct mlx5e_rq_stats xskrq; 819 struct mlx5e_xdpsq_stats rq_xdpsq; 820 struct mlx5e_xdpsq_stats xdpsq; 821 struct mlx5e_xdpsq_stats xsksq; 822} ____cacheline_aligned_in_smp; 823 824struct mlx5e_ptp_stats { 825 struct mlx5e_ch_stats ch; 826 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; 827 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC]; 828 struct mlx5e_rq_stats rq; 829} ____cacheline_aligned_in_smp; 830 831enum { 832 MLX5E_STATE_OPENED, 833 MLX5E_STATE_DESTROYING, 834 MLX5E_STATE_XDP_TX_ENABLED, 835 MLX5E_STATE_XDP_ACTIVE, 836 MLX5E_STATE_CHANNELS_ACTIVE, 837}; 838 839struct mlx5e_modify_sq_param { 840 int curr_state; 841 int next_state; 842 int rl_update; 843 int rl_index; 844 bool qos_update; 845 u16 qos_queue_group_id; 846}; 847 848#if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 849struct mlx5e_hv_vhca_stats_agent { 850 struct mlx5_hv_vhca_agent *agent; 851 struct delayed_work work; 852 u16 delay; 853 void *buf; 854}; 855#endif 856 857struct mlx5e_xsk { 858 /* XSK buffer pools are stored separately from channels, 859 * because we don't want to lose them when channels are 860 * recreated. The kernel also stores buffer pool, but it doesn't 861 * distinguish between zero-copy and non-zero-copy UMEMs, so 862 * rely on our mechanism. 863 */ 864 struct xsk_buff_pool **pools; 865 u16 refcnt; 866 bool ever_used; 867}; 868 869/* Temporary storage for variables that are allocated when struct mlx5e_priv is 870 * initialized, and used where we can't allocate them because that functions 871 * must not fail. Use with care and make sure the same variable is not used 872 * simultaneously by multiple users. 873 */ 874struct mlx5e_scratchpad { 875 cpumask_var_t cpumask; 876}; 877 878struct mlx5e_trap; 879struct mlx5e_htb; 880 881struct mlx5e_priv { 882 /* priv data path fields - start */ 883 struct mlx5e_selq selq; 884 struct mlx5e_txqsq **txq2sq; 885 struct mlx5e_sq_stats **txq2sq_stats; 886 887#ifdef CONFIG_MLX5_CORE_EN_DCB 888 struct mlx5e_dcbx_dp dcbx_dp; 889#endif 890 /* priv data path fields - end */ 891 892 unsigned long state; 893 struct mutex state_lock; /* Protects Interface state */ 894 struct mlx5e_rq drop_rq; 895 896 struct mlx5e_channels channels; 897 struct mlx5e_rx_res *rx_res; 898 u32 *tx_rates; 899 900 struct mlx5e_flow_steering *fs; 901 902 struct workqueue_struct *wq; 903 struct work_struct update_carrier_work; 904 struct work_struct set_rx_mode_work; 905 struct work_struct tx_timeout_work; 906 struct work_struct update_stats_work; 907 struct work_struct monitor_counters_work; 908 struct mlx5_nb monitor_counters_nb; 909 910 struct mlx5_core_dev *mdev; 911 struct net_device *netdev; 912 struct mlx5e_trap *en_trap; 913 struct mlx5e_stats stats; 914 struct mlx5e_channel_stats **channel_stats; 915 struct mlx5e_channel_stats trap_stats; 916 struct mlx5e_ptp_stats ptp_stats; 917 struct mlx5e_sq_stats **htb_qos_sq_stats; 918 u16 htb_max_qos_sqs; 919 u16 stats_nch; 920 u16 max_nch; 921 u8 max_opened_tc; 922 bool tx_ptp_opened; 923 bool rx_ptp_opened; 924 struct kernel_hwtstamp_config hwtstamp_config; 925 u16 q_counter[MLX5_SD_MAX_GROUP_SZ]; 926 u16 drop_rq_q_counter; 927 struct notifier_block events_nb; 928 struct notifier_block blocking_events_nb; 929 930 struct mlx5e_pcie_cong_event *cong_event; 931 932 struct udp_tunnel_nic_info nic_info; 933#ifdef CONFIG_MLX5_CORE_EN_DCB 934 struct mlx5e_dcbx dcbx; 935#endif 936 937 const struct mlx5e_profile *profile; 938 void *ppriv; 939#ifdef CONFIG_MLX5_MACSEC 940 struct mlx5e_macsec *macsec; 941#endif 942#ifdef CONFIG_MLX5_EN_IPSEC 943 struct mlx5e_ipsec *ipsec; 944#endif 945#ifdef CONFIG_MLX5_EN_PSP 946 struct mlx5e_psp *psp; 947#endif 948#ifdef CONFIG_MLX5_EN_TLS 949 struct mlx5e_tls *tls; 950#endif 951 struct devlink_health_reporter *tx_reporter; 952 struct devlink_health_reporter *rx_reporter; 953 struct mlx5e_xsk xsk; 954#if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 955 struct mlx5e_hv_vhca_stats_agent stats_agent; 956#endif 957 struct mlx5e_scratchpad scratchpad; 958 struct mlx5e_htb *htb; 959 struct mlx5e_mqprio_rl *mqprio_rl; 960 struct dentry *dfs_root; 961 struct mlx5_devcom_comp_dev *devcom; 962 struct ethtool_fec_hist_range *fec_ranges; 963}; 964 965struct mlx5e_dev { 966 struct net_device *netdev; 967 struct devlink_port dl_port; 968}; 969 970struct mlx5e_rx_handlers { 971 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 972 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 973 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 974}; 975 976extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 977 978enum mlx5e_profile_feature { 979 MLX5E_PROFILE_FEATURE_PTP_RX, 980 MLX5E_PROFILE_FEATURE_PTP_TX, 981 MLX5E_PROFILE_FEATURE_QOS_HTB, 982 MLX5E_PROFILE_FEATURE_FS_VLAN, 983 MLX5E_PROFILE_FEATURE_FS_TC, 984}; 985 986struct mlx5e_profile { 987 int (*init)(struct mlx5_core_dev *mdev, 988 struct net_device *netdev); 989 void (*cleanup)(struct mlx5e_priv *priv); 990 int (*init_rx)(struct mlx5e_priv *priv); 991 void (*cleanup_rx)(struct mlx5e_priv *priv); 992 int (*init_tx)(struct mlx5e_priv *priv); 993 void (*cleanup_tx)(struct mlx5e_priv *priv); 994 void (*enable)(struct mlx5e_priv *priv); 995 void (*disable)(struct mlx5e_priv *priv); 996 int (*update_rx)(struct mlx5e_priv *priv); 997 void (*update_stats)(struct mlx5e_priv *priv); 998 void (*update_carrier)(struct mlx5e_priv *priv); 999 int (*max_nch_limit)(struct mlx5_core_dev *mdev); 1000 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv, 1001 u8 lag_port, u8 tc); 1002 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 1003 mlx5e_stats_grp_t *stats_grps; 1004 const struct mlx5e_rx_handlers *rx_handlers; 1005 int max_tc; 1006 u32 features; 1007}; 1008 1009u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev, 1010 struct mlx5e_priv *priv, 1011 const struct mlx5e_profile *profile, 1012 u8 lag_port, u8 tc); 1013 1014#define mlx5e_profile_feature_cap(profile, feature) \ 1015 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) 1016 1017void mlx5e_build_ptys2ethtool_map(void); 1018 1019bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, 1020 enum mlx5e_mpwrq_umr_mode umr_mode); 1021 1022void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len); 1023void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq); 1024void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 1025void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 1026 1027int mlx5e_self_test_num(struct mlx5e_priv *priv); 1028int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 1029void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 1030 u64 *buf); 1031void mlx5e_set_rx_mode_work(struct work_struct *work); 1032 1033int mlx5e_hwtstamp_set(struct mlx5e_priv *priv, 1034 struct kernel_hwtstamp_config *config, 1035 struct netlink_ext_ack *extack); 1036int mlx5e_hwtstamp_get(struct mlx5e_priv *priv, 1037 struct kernel_hwtstamp_config *config); 1038int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 1039 1040int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1041 u16 vid); 1042int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1043 u16 vid); 1044void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1045 1046struct mlx5e_xsk_param; 1047 1048struct mlx5e_rq_param; 1049int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1050 struct mlx5e_xsk_param *xsk, int node, u16 q_counter, 1051 struct mlx5e_rq *rq); 1052#define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ 1053int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1054void mlx5e_close_rq(struct mlx5e_rq *rq); 1055int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter); 1056void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1057 1058bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1059 bool dim_enabled); 1060bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1061 bool dim_enabled, bool keep_dim_state); 1062 1063struct mlx5e_sq_param; 1064int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1065 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1066 struct mlx5e_xdpsq *sq, bool is_redirect); 1067void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1068 1069struct mlx5e_create_cq_param { 1070 struct net_device *netdev; 1071 struct workqueue_struct *wq; 1072 struct napi_struct *napi; 1073 struct mlx5e_ch_stats *ch_stats; 1074 int node; 1075 int ix; 1076 struct mlx5_uars_page *uar; 1077}; 1078 1079struct mlx5e_cq_param; 1080int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder, 1081 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1082 struct mlx5e_cq *cq); 1083void mlx5e_close_cq(struct mlx5e_cq *cq); 1084int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1085 u8 cq_period_mode); 1086int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 1087 u16 cq_period, u16 cq_max_count, u8 cq_period_mode); 1088 1089int mlx5e_open_locked(struct net_device *netdev); 1090int mlx5e_close_locked(struct net_device *netdev); 1091 1092void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); 1093void mlx5e_trigger_napi_sched(struct napi_struct *napi); 1094 1095int mlx5e_open_channels(struct mlx5e_priv *priv, 1096 struct mlx5e_channels *chs); 1097void mlx5e_close_channels(struct mlx5e_channels *chs); 1098 1099/* Function pointer to be used to modify HW or kernel settings while 1100 * switching channels 1101 */ 1102typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1103#define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1104int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1105{ \ 1106 return fn(priv); \ 1107} 1108int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1109int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1110 struct mlx5e_params *new_params, 1111 mlx5e_fp_preactivate preactivate, 1112 void *context, bool reset); 1113int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1114int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1115int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context); 1116void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1117void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1118int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1119 1120int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state); 1121void mlx5e_activate_rq(struct mlx5e_rq *rq); 1122void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1123void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1124void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1125 1126int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1127 struct mlx5e_modify_sq_param *p); 1128int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1129 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1130 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1131 struct mlx5e_sq_stats *sq_stats); 1132void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1133void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1134void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1135void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1136int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1137void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1138struct mlx5e_create_sq_param; 1139int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1140 struct mlx5e_sq_param *param, 1141 struct mlx5e_create_sq_param *csp, 1142 u16 qos_queue_group_id, 1143 u32 *sqn); 1144void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1145void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1146 1147bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, 1148 bool dim_enabled); 1149bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, 1150 bool dim_enabled, bool keep_dim_state); 1151 1152static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1153{ 1154 return MLX5_CAP_ETH(mdev, swp) && 1155 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1156} 1157 1158extern const struct ethtool_ops mlx5e_ethtool_ops; 1159 1160int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1161int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises); 1162void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1163int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, 1164 bool enable_mc_lb); 1165int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb, 1166 bool enable_mc_lb); 1167void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1168 1169/* common netdev helpers */ 1170void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1171void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1172int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1173 struct mlx5e_rq *drop_rq); 1174void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1175 1176int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1177void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1178 1179void mlx5e_update_carrier(struct mlx5e_priv *priv); 1180int mlx5e_close(struct net_device *netdev); 1181int mlx5e_open(struct net_device *netdev); 1182 1183void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1184 1185int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1186int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1187int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1188 mlx5e_fp_preactivate preactivate); 1189void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1190 1191/* ethtool helpers */ 1192void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1193 struct ethtool_drvinfo *drvinfo); 1194void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1195 u32 stringset, u8 *data); 1196int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1197void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1198 struct ethtool_stats *stats, u64 *data); 1199void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1200 struct ethtool_ringparam *param, 1201 struct kernel_ethtool_ringparam *kernel_param); 1202int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1203 struct ethtool_ringparam *param, 1204 struct netlink_ext_ack *extack); 1205void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1206 struct ethtool_channels *ch); 1207int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1208 struct ethtool_channels *ch); 1209int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1210 struct ethtool_coalesce *coal, 1211 struct kernel_ethtool_coalesce *kernel_coal, 1212 struct netlink_ext_ack *extack); 1213int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1214 struct ethtool_coalesce *coal, 1215 struct kernel_ethtool_coalesce *kernel_coal, 1216 struct netlink_ext_ack *extack); 1217int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue, 1218 struct ethtool_coalesce *coal); 1219int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1220 struct ethtool_coalesce *coal); 1221u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1222u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1223int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1224 struct kernel_ethtool_ts_info *info); 1225int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1226 struct ethtool_flash *flash); 1227 1228/* mlx5e generic netdev management API */ 1229static inline bool 1230mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1231{ 1232 return !is_kdump_kernel() && 1233 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1234} 1235 1236int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); 1237int mlx5e_priv_init(struct mlx5e_priv *priv, 1238 const struct mlx5e_profile *profile, 1239 struct net_device *netdev, 1240 struct mlx5_core_dev *mdev); 1241void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1242struct net_device * 1243mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); 1244int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1245void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1246void mlx5e_destroy_netdev(struct net_device *netdev); 1247int mlx5e_netdev_change_profile(struct net_device *netdev, 1248 struct mlx5_core_dev *mdev, 1249 const struct mlx5e_profile *new_profile, 1250 void *new_ppriv); 1251void mlx5e_netdev_attach_nic_profile(struct net_device *netdev, 1252 struct mlx5_core_dev *mdev); 1253void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1254void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1255 1256void mlx5e_set_xdp_feature(struct mlx5e_priv *priv); 1257netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1258 struct net_device *netdev, 1259 netdev_features_t features); 1260int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1261#ifdef CONFIG_MLX5_ESWITCH 1262int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1263int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1264int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1265int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1266#endif 1267int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1268#endif /* __MLX5_EN_H__ */
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