en_tx.c

   1/*
   2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 *
  32 */
  33
  34#include <asm/page.h>
  35#include <linux/mlx4/cq.h>
  36#include <linux/slab.h>
  37#include <linux/mlx4/qp.h>
  38#include <linux/skbuff.h>
  39#include <linux/if_vlan.h>
  40#include <linux/prefetch.h>
  41#include <linux/vmalloc.h>
  42#include <linux/tcp.h>
  43#include <linux/ip.h>
  44#include <linux/ipv6.h>
  45#include <linux/indirect_call_wrapper.h>
  46#include <net/ipv6.h>
  47#include <net/page_pool/helpers.h>
  48
  49#include "mlx4_en.h"
  50
  51int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  52			   struct mlx4_en_tx_ring **pring, u32 size,
  53			   u16 stride, int node, int queue_index)
  54{
  55	struct mlx4_en_dev *mdev = priv->mdev;
  56	struct mlx4_en_tx_ring *ring;
  57	int tmp;
  58	int err;
  59
  60	ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
  61	if (!ring) {
  62		en_err(priv, "Failed allocating TX ring\n");
  63		return -ENOMEM;
  64	}
  65
  66	ring->size = size;
  67	ring->size_mask = size - 1;
  68	ring->sp_stride = stride;
  69	ring->full_size = ring->size - HEADROOM - MLX4_MAX_DESC_TXBBS;
  70
  71	tmp = size * sizeof(struct mlx4_en_tx_info);
  72	ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node);
  73	if (!ring->tx_info) {
  74		err = -ENOMEM;
  75		goto err_ring;
  76	}
  77
  78	en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  79		 ring->tx_info, tmp);
  80
  81	ring->bounce_buf = kmalloc_node(MLX4_TX_BOUNCE_BUFFER_SIZE,
  82					GFP_KERNEL, node);
  83	if (!ring->bounce_buf) {
  84		ring->bounce_buf = kmalloc(MLX4_TX_BOUNCE_BUFFER_SIZE,
  85					   GFP_KERNEL);
  86		if (!ring->bounce_buf) {
  87			err = -ENOMEM;
  88			goto err_info;
  89		}
  90	}
  91	ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE);
  92
  93	/* Allocate HW buffers on provided NUMA node */
  94	set_dev_node(&mdev->dev->persist->pdev->dev, node);
  95	err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
  96	set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
  97	if (err) {
  98		en_err(priv, "Failed allocating hwq resources\n");
  99		goto err_bounce;
 100	}
 101
 102	ring->buf = ring->sp_wqres.buf.direct.buf;
 103
 104	en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
 105	       ring, ring->buf, ring->size, ring->buf_size,
 106	       (unsigned long long) ring->sp_wqres.buf.direct.map);
 107
 108	err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
 109				    MLX4_RESERVE_ETH_BF_QP,
 110				    MLX4_RES_USAGE_DRIVER);
 111	if (err) {
 112		en_err(priv, "failed reserving qp for TX ring\n");
 113		goto err_hwq_res;
 114	}
 115
 116	err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp);
 117	if (err) {
 118		en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 119		goto err_reserve;
 120	}
 121	ring->sp_qp.event = mlx4_en_sqp_event;
 122
 123	err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
 124	if (err) {
 125		en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
 126		ring->bf.uar = &mdev->priv_uar;
 127		ring->bf.uar->map = mdev->uar_map;
 128		ring->bf_enabled = false;
 129		ring->bf_alloced = false;
 130		priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
 131	} else {
 132		ring->bf_alloced = true;
 133		ring->bf_enabled = !!(priv->pflags &
 134				      MLX4_EN_PRIV_FLAGS_BLUEFLAME);
 135	}
 136	ring->doorbell_address = ring->bf.uar->map + MLX4_SEND_DOORBELL;
 137
 138	ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
 139	ring->queue_index = queue_index;
 140
 141	if (queue_index < priv->num_tx_rings_p_up)
 142		cpumask_set_cpu(cpumask_local_spread(queue_index,
 143						     priv->mdev->dev->numa_node),
 144				&ring->sp_affinity_mask);
 145
 146	*pring = ring;
 147	return 0;
 148
 149err_reserve:
 150	mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
 151err_hwq_res:
 152	mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 153err_bounce:
 154	kfree(ring->bounce_buf);
 155	ring->bounce_buf = NULL;
 156err_info:
 157	kvfree(ring->tx_info);
 158	ring->tx_info = NULL;
 159err_ring:
 160	kfree(ring);
 161	*pring = NULL;
 162	return err;
 163}
 164
 165void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 166			     struct mlx4_en_tx_ring **pring)
 167{
 168	struct mlx4_en_dev *mdev = priv->mdev;
 169	struct mlx4_en_tx_ring *ring = *pring;
 170	en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 171
 172	if (ring->bf_alloced)
 173		mlx4_bf_free(mdev->dev, &ring->bf);
 174	mlx4_qp_remove(mdev->dev, &ring->sp_qp);
 175	mlx4_qp_free(mdev->dev, &ring->sp_qp);
 176	mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
 177	mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 178	kfree(ring->bounce_buf);
 179	ring->bounce_buf = NULL;
 180	kvfree(ring->tx_info);
 181	ring->tx_info = NULL;
 182	kfree(ring);
 183	*pring = NULL;
 184}
 185
 186int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 187			     struct mlx4_en_tx_ring *ring,
 188			     int cq, int user_prio)
 189{
 190	struct mlx4_en_dev *mdev = priv->mdev;
 191	int err;
 192
 193	ring->sp_cqn = cq;
 194	ring->prod = 0;
 195	ring->cons = 0xffffffff;
 196	ring->last_nr_txbb = 1;
 197	memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 198	memset(ring->buf, 0, ring->buf_size);
 199	ring->free_tx_desc = mlx4_en_free_tx_desc;
 200
 201	ring->sp_qp_state = MLX4_QP_STATE_RST;
 202	ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8);
 203	ring->mr_key = cpu_to_be32(mdev->mr.key);
 204
 205	mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn,
 206				ring->sp_cqn, user_prio, &ring->sp_context);
 207	if (ring->bf_alloced)
 208		ring->sp_context.usr_page =
 209			cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev,
 210							 ring->bf.uar->index));
 211
 212	err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context,
 213			       &ring->sp_qp, &ring->sp_qp_state);
 214	if (!cpumask_empty(&ring->sp_affinity_mask))
 215		netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask,
 216				    ring->queue_index);
 217
 218	return err;
 219}
 220
 221void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 222				struct mlx4_en_tx_ring *ring)
 223{
 224	struct mlx4_en_dev *mdev = priv->mdev;
 225
 226	mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state,
 227		       MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp);
 228}
 229
 230static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
 231{
 232	u32 used = READ_ONCE(ring->prod) - READ_ONCE(ring->cons);
 233
 234	return used > ring->full_size;
 235}
 236
 237static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
 238			      struct mlx4_en_tx_ring *ring, int index,
 239			      u8 owner)
 240{
 241	__be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 242	struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 243	struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 244	void *end = ring->buf + ring->buf_size;
 245	__be32 *ptr = (__be32 *)tx_desc;
 246	int i;
 247
 248	/* Optimize the common case when there are no wraparounds */
 249	if (likely((void *)tx_desc +
 250		   (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
 251		/* Stamp the freed descriptor */
 252		for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
 253		     i += STAMP_STRIDE) {
 254			*ptr = stamp;
 255			ptr += STAMP_DWORDS;
 256		}
 257	} else {
 258		/* Stamp the freed descriptor */
 259		for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
 260		     i += STAMP_STRIDE) {
 261			*ptr = stamp;
 262			ptr += STAMP_DWORDS;
 263			if ((void *)ptr >= end) {
 264				ptr = ring->buf;
 265				stamp ^= cpu_to_be32(0x80000000);
 266			}
 267		}
 268	}
 269}
 270
 271INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 272						   struct mlx4_en_tx_ring *ring,
 273						   int index, u64 timestamp,
 274						   int napi_mode));
 275
 276u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 277			 struct mlx4_en_tx_ring *ring,
 278			 int index, u64 timestamp,
 279			 int napi_mode)
 280{
 281	struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 282	struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 283	struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 284	void *end = ring->buf + ring->buf_size;
 285	struct sk_buff *skb = tx_info->skb;
 286	int nr_maps = tx_info->nr_maps;
 287	int i;
 288
 289	/* We do not touch skb here, so prefetch skb->users location
 290	 * to speedup consume_skb()
 291	 */
 292	prefetchw(&skb->users);
 293
 294	if (unlikely(timestamp)) {
 295		struct skb_shared_hwtstamps hwts;
 296
 297		mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
 298		skb_tstamp_tx(skb, &hwts);
 299	}
 300
 301	if (!tx_info->inl) {
 302		if (tx_info->linear)
 303			dma_unmap_single(priv->ddev,
 304					 tx_info->map0_dma,
 305					 tx_info->map0_byte_count,
 306					 DMA_TO_DEVICE);
 307		else
 308			dma_unmap_page(priv->ddev,
 309				       tx_info->map0_dma,
 310				       tx_info->map0_byte_count,
 311				       DMA_TO_DEVICE);
 312		/* Optimize the common case when there are no wraparounds */
 313		if (likely((void *)tx_desc +
 314			   (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
 315			for (i = 1; i < nr_maps; i++) {
 316				data++;
 317				dma_unmap_page(priv->ddev,
 318					(dma_addr_t)be64_to_cpu(data->addr),
 319					be32_to_cpu(data->byte_count),
 320					DMA_TO_DEVICE);
 321			}
 322		} else {
 323			if ((void *)data >= end)
 324				data = ring->buf + ((void *)data - end);
 325
 326			for (i = 1; i < nr_maps; i++) {
 327				data++;
 328				/* Check for wraparound before unmapping */
 329				if ((void *) data >= end)
 330					data = ring->buf;
 331				dma_unmap_page(priv->ddev,
 332					(dma_addr_t)be64_to_cpu(data->addr),
 333					be32_to_cpu(data->byte_count),
 334					DMA_TO_DEVICE);
 335			}
 336		}
 337	}
 338	napi_consume_skb(skb, napi_mode);
 339
 340	return tx_info->nr_txbb;
 341}
 342
 343INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
 344						      struct mlx4_en_tx_ring *ring,
 345						      int index, u64 timestamp,
 346						      int napi_mode));
 347
 348u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
 349			    struct mlx4_en_tx_ring *ring,
 350			    int index, u64 timestamp,
 351			    int napi_mode)
 352{
 353	struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 354	struct page_pool *pool = ring->recycle_ring->pp;
 355
 356	/* Note that napi_mode = 0 means ndo_close() path, not budget = 0 */
 357	page_pool_put_full_page(pool, tx_info->page, !!napi_mode);
 358
 359	return tx_info->nr_txbb;
 360}
 361
 362int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 363{
 364	struct mlx4_en_priv *priv = netdev_priv(dev);
 365	int cnt = 0;
 366
 367	/* Skip last polled descriptor */
 368	ring->cons += ring->last_nr_txbb;
 369	en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 370		 ring->cons, ring->prod);
 371
 372	if ((u32) (ring->prod - ring->cons) > ring->size) {
 373		if (netif_msg_tx_err(priv))
 374			en_warn(priv, "Tx consumer passed producer!\n");
 375		return 0;
 376	}
 377
 378	while (ring->cons != ring->prod) {
 379		ring->last_nr_txbb = ring->free_tx_desc(priv, ring,
 380						ring->cons & ring->size_mask,
 381						0, 0 /* Non-NAPI caller */);
 382		ring->cons += ring->last_nr_txbb;
 383		cnt++;
 384	}
 385
 386	if (ring->tx_queue)
 387		netdev_tx_reset_queue(ring->tx_queue);
 388
 389	if (cnt)
 390		en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 391
 392	return cnt;
 393}
 394
 395static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe,
 396				   u16 cqe_index, struct mlx4_en_tx_ring *ring)
 397{
 398	struct mlx4_en_dev *mdev = priv->mdev;
 399	struct mlx4_en_tx_info *tx_info;
 400	struct mlx4_en_tx_desc *tx_desc;
 401	u16 wqe_index;
 402	int desc_size;
 403
 404	en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n",
 405	       ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome);
 406	print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe),
 407		       false);
 408
 409	wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask;
 410	tx_info = &ring->tx_info[wqe_index];
 411	desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE;
 412	en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn,
 413	       wqe_index, desc_size);
 414	tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE);
 415	print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false);
 416
 417	if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state))
 418		return;
 419
 420	en_err(priv, "Scheduling port restart\n");
 421	queue_work(mdev->workqueue, &priv->restart_task);
 422}
 423
 424int mlx4_en_process_tx_cq(struct net_device *dev,
 425			  struct mlx4_en_cq *cq, int napi_budget)
 426{
 427	struct mlx4_en_priv *priv = netdev_priv(dev);
 428	struct mlx4_cq *mcq = &cq->mcq;
 429	struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring];
 430	struct mlx4_cqe *cqe;
 431	u16 index, ring_index, stamp_index;
 432	u32 txbbs_skipped = 0;
 433	u32 txbbs_stamp = 0;
 434	u32 cons_index = mcq->cons_index;
 435	int size = cq->size;
 436	u32 size_mask = ring->size_mask;
 437	struct mlx4_cqe *buf = cq->buf;
 438	u32 packets = 0;
 439	u32 bytes = 0;
 440	int factor = priv->cqe_factor;
 441	int done = 0;
 442	int budget = priv->tx_work_limit;
 443	u32 last_nr_txbb;
 444	u32 ring_cons;
 445
 446	if (unlikely(!priv->port_up))
 447		return 0;
 448	if (unlikely(!napi_budget) && cq->type == TX_XDP)
 449		return 0;
 450
 451	netdev_txq_bql_complete_prefetchw(ring->tx_queue);
 452
 453	index = cons_index & size_mask;
 454	cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 455	last_nr_txbb = READ_ONCE(ring->last_nr_txbb);
 456	ring_cons = READ_ONCE(ring->cons);
 457	ring_index = ring_cons & size_mask;
 458	stamp_index = ring_index;
 459
 460	/* Process all completed CQEs */
 461	while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 462			cons_index & size) && (done < budget)) {
 463		u16 new_index;
 464
 465		/*
 466		 * make sure we read the CQE after we read the
 467		 * ownership bit
 468		 */
 469		dma_rmb();
 470
 471		if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 472			     MLX4_CQE_OPCODE_ERROR))
 473			if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state))
 474				mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index,
 475						       ring);
 476
 477		/* Skip over last polled CQE */
 478		new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 479
 480		do {
 481			u64 timestamp = 0;
 482
 483			txbbs_skipped += last_nr_txbb;
 484			ring_index = (ring_index + last_nr_txbb) & size_mask;
 485
 486			if (unlikely(ring->tx_info[ring_index].ts_requested))
 487				timestamp = mlx4_en_get_cqe_ts(cqe);
 488
 489			/* free next descriptor */
 490			last_nr_txbb = INDIRECT_CALL_2(ring->free_tx_desc,
 491						       mlx4_en_free_tx_desc,
 492						       mlx4_en_recycle_tx_desc,
 493					priv, ring, ring_index,
 494					timestamp, napi_budget);
 495
 496			mlx4_en_stamp_wqe(priv, ring, stamp_index,
 497					  !!((ring_cons + txbbs_stamp) &
 498						ring->size));
 499			stamp_index = ring_index;
 500			txbbs_stamp = txbbs_skipped;
 501			packets++;
 502			bytes += ring->tx_info[ring_index].nr_bytes;
 503		} while ((++done < budget) && (ring_index != new_index));
 504
 505		++cons_index;
 506		index = cons_index & size_mask;
 507		cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 508	}
 509
 510	/*
 511	 * To prevent CQ overflow we first update CQ consumer and only then
 512	 * the ring consumer.
 513	 */
 514	mcq->cons_index = cons_index;
 515	mlx4_cq_set_ci(mcq);
 516	wmb();
 517
 518	/* we want to dirty this cache line once */
 519	WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb);
 520	WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped);
 521
 522	if (cq->type == TX_XDP)
 523		return done;
 524
 525	netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 526
 527	/* Wakeup Tx queue if this stopped, and ring is not full.
 528	 */
 529	if (netif_tx_queue_stopped(ring->tx_queue) &&
 530	    !mlx4_en_is_tx_ring_full(ring)) {
 531		netif_tx_wake_queue(ring->tx_queue);
 532		ring->wake_queue++;
 533	}
 534
 535	return done;
 536}
 537
 538void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 539{
 540	struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 541	struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 542
 543	if (likely(priv->port_up))
 544		napi_schedule_irqoff(&cq->napi);
 545	else
 546		mlx4_en_arm_cq(priv, cq);
 547}
 548
 549/* TX CQ polling - called by NAPI */
 550int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
 551{
 552	struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 553	struct net_device *dev = cq->dev;
 554	struct mlx4_en_priv *priv = netdev_priv(dev);
 555	int work_done;
 556
 557	work_done = mlx4_en_process_tx_cq(dev, cq, budget);
 558	if (work_done >= budget)
 559		return budget;
 560
 561	if (napi_complete_done(napi, work_done))
 562		mlx4_en_arm_cq(priv, cq);
 563
 564	return 0;
 565}
 566
 567static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 568						      struct mlx4_en_tx_ring *ring,
 569						      u32 index,
 570						      unsigned int desc_size)
 571{
 572	u32 copy = (ring->size - index) << LOG_TXBB_SIZE;
 573	int i;
 574
 575	for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 576		if ((i & (TXBB_SIZE - 1)) == 0)
 577			wmb();
 578
 579		*((u32 *) (ring->buf + i)) =
 580			*((u32 *) (ring->bounce_buf + copy + i));
 581	}
 582
 583	for (i = copy - 4; i >= 4 ; i -= 4) {
 584		if ((i & (TXBB_SIZE - 1)) == 0)
 585			wmb();
 586
 587		*((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) =
 588			*((u32 *) (ring->bounce_buf + i));
 589	}
 590
 591	/* Return real descriptor location */
 592	return ring->buf + (index << LOG_TXBB_SIZE);
 593}
 594
 595/* Decide if skb can be inlined in tx descriptor to avoid dma mapping
 596 *
 597 * It seems strange we do not simply use skb_copy_bits().
 598 * This would allow to inline all skbs iff skb->len <= inline_thold
 599 *
 600 * Note that caller already checked skb was not a gso packet
 601 */
 602static bool is_inline(int inline_thold, const struct sk_buff *skb,
 603		      const struct skb_shared_info *shinfo,
 604		      void **pfrag)
 605{
 606	void *ptr;
 607
 608	if (skb->len > inline_thold || !inline_thold)
 609		return false;
 610
 611	if (shinfo->nr_frags == 1) {
 612		ptr = skb_frag_address_safe(&shinfo->frags[0]);
 613		if (unlikely(!ptr))
 614			return false;
 615		*pfrag = ptr;
 616		return true;
 617	}
 618	if (shinfo->nr_frags)
 619		return false;
 620	return true;
 621}
 622
 623static int inline_size(const struct sk_buff *skb)
 624{
 625	if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 626	    <= MLX4_INLINE_ALIGN)
 627		return ALIGN(skb->len + CTRL_SIZE +
 628			     sizeof(struct mlx4_wqe_inline_seg), 16);
 629	else
 630		return ALIGN(skb->len + CTRL_SIZE + 2 *
 631			     sizeof(struct mlx4_wqe_inline_seg), 16);
 632}
 633
 634static int get_real_size(const struct sk_buff *skb,
 635			 const struct skb_shared_info *shinfo,
 636			 struct net_device *dev,
 637			 int *lso_header_size,
 638			 bool *inline_ok,
 639			 void **pfrag,
 640			 int *hopbyhop)
 641{
 642	struct mlx4_en_priv *priv = netdev_priv(dev);
 643	int real_size;
 644
 645	if (shinfo->gso_size) {
 646		*inline_ok = false;
 647		*hopbyhop = 0;
 648		if (skb->encapsulation) {
 649			*lso_header_size = skb_inner_tcp_all_headers(skb);
 650		} else {
 651			/* Detects large IPV6 TCP packets and prepares for removal of
 652			 * HBH header that has been pushed by ip6_xmit(),
 653			 * mainly so that tcpdump can dissect them.
 654			 */
 655			if (ipv6_has_hopopt_jumbo(skb))
 656				*hopbyhop = sizeof(struct hop_jumbo_hdr);
 657			*lso_header_size = skb_tcp_all_headers(skb);
 658		}
 659		real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
 660			ALIGN(*lso_header_size - *hopbyhop + 4, DS_SIZE);
 661		if (unlikely(*lso_header_size != skb_headlen(skb))) {
 662			/* We add a segment for the skb linear buffer only if
 663			 * it contains data */
 664			if (*lso_header_size < skb_headlen(skb))
 665				real_size += DS_SIZE;
 666			else {
 667				if (netif_msg_tx_err(priv))
 668					en_warn(priv, "Non-linear headers\n");
 669				return 0;
 670			}
 671		}
 672	} else {
 673		*lso_header_size = 0;
 674		*inline_ok = is_inline(priv->prof->inline_thold, skb,
 675				       shinfo, pfrag);
 676
 677		if (*inline_ok)
 678			real_size = inline_size(skb);
 679		else
 680			real_size = CTRL_SIZE +
 681				    (shinfo->nr_frags + 1) * DS_SIZE;
 682	}
 683
 684	return real_size;
 685}
 686
 687static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
 688			     const struct sk_buff *skb,
 689			     const struct skb_shared_info *shinfo,
 690			     void *fragptr)
 691{
 692	struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 693	int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl);
 694	unsigned int hlen = skb_headlen(skb);
 695
 696	if (skb->len <= spc) {
 697		if (likely(skb->len >= MIN_PKT_LEN)) {
 698			inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 699		} else {
 700			inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
 701			memset(inl->data + skb->len, 0,
 702			       MIN_PKT_LEN - skb->len);
 703		}
 704		skb_copy_from_linear_data(skb, inl->data, hlen);
 705		if (shinfo->nr_frags)
 706			memcpy(inl->data + hlen, fragptr,
 707			       skb_frag_size(&shinfo->frags[0]));
 708
 709	} else {
 710		inl->byte_count = cpu_to_be32(1 << 31 | spc);
 711		if (hlen <= spc) {
 712			skb_copy_from_linear_data(skb, inl->data, hlen);
 713			if (hlen < spc) {
 714				memcpy(inl->data + hlen,
 715				       fragptr, spc - hlen);
 716				fragptr +=  spc - hlen;
 717			}
 718			inl = (void *)inl->data + spc;
 719			memcpy(inl->data, fragptr, skb->len - spc);
 720		} else {
 721			skb_copy_from_linear_data(skb, inl->data, spc);
 722			inl = (void *)inl->data + spc;
 723			skb_copy_from_linear_data_offset(skb, spc, inl->data,
 724							 hlen - spc);
 725			if (shinfo->nr_frags)
 726				memcpy(inl->data + hlen - spc,
 727				       fragptr,
 728				       skb_frag_size(&shinfo->frags[0]));
 729		}
 730
 731		dma_wmb();
 732		inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 733	}
 734}
 735
 736u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 737			 struct net_device *sb_dev)
 738{
 739	struct mlx4_en_priv *priv = netdev_priv(dev);
 740	u16 rings_p_up = priv->num_tx_rings_p_up;
 741
 742	if (netdev_get_num_tc(dev))
 743		return netdev_pick_tx(dev, skb, NULL);
 744
 745	return netdev_pick_tx(dev, skb, NULL) % rings_p_up;
 746}
 747
 748static void mlx4_bf_copy(void __iomem *dst, const void *src,
 749			 unsigned int bytecnt)
 750{
 751	__iowrite64_copy(dst, src, bytecnt / 8);
 752}
 753
 754void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring)
 755{
 756	wmb();
 757	/* Since there is no iowrite*_native() that writes the
 758	 * value as is, without byteswapping - using the one
 759	 * the doesn't do byteswapping in the relevant arch
 760	 * endianness.
 761	 */
 762#if defined(__LITTLE_ENDIAN)
 763	iowrite32(
 764#else
 765	iowrite32be(
 766#endif
 767		  (__force u32)ring->doorbell_qpn, ring->doorbell_address);
 768}
 769
 770static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring,
 771				  struct mlx4_en_tx_desc *tx_desc,
 772				  union mlx4_wqe_qpn_vlan qpn_vlan,
 773				  int desc_size, int bf_index,
 774				  __be32 op_own, bool bf_ok,
 775				  bool send_doorbell)
 776{
 777	tx_desc->ctrl.qpn_vlan = qpn_vlan;
 778
 779	if (bf_ok) {
 780		op_own |= htonl((bf_index & 0xffff) << 8);
 781		/* Ensure new descriptor hits memory
 782		 * before setting ownership of this descriptor to HW
 783		 */
 784		dma_wmb();
 785		tx_desc->ctrl.owner_opcode = op_own;
 786
 787		wmb();
 788
 789		mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
 790			     desc_size);
 791
 792		wmb();
 793
 794		ring->bf.offset ^= ring->bf.buf_size;
 795	} else {
 796		/* Ensure new descriptor hits memory
 797		 * before setting ownership of this descriptor to HW
 798		 */
 799		dma_wmb();
 800		tx_desc->ctrl.owner_opcode = op_own;
 801		if (send_doorbell)
 802			mlx4_en_xmit_doorbell(ring);
 803		else
 804			ring->xmit_more++;
 805	}
 806}
 807
 808static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv,
 809				  struct skb_shared_info *shinfo,
 810				  struct mlx4_wqe_data_seg *data,
 811				  struct sk_buff *skb,
 812				  int lso_header_size,
 813				  __be32 mr_key,
 814				  struct mlx4_en_tx_info *tx_info)
 815{
 816	struct device *ddev = priv->ddev;
 817	dma_addr_t dma = 0;
 818	u32 byte_count = 0;
 819	int i_frag;
 820
 821	/* Map fragments if any */
 822	for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
 823		const skb_frag_t *frag = &shinfo->frags[i_frag];
 824		byte_count = skb_frag_size(frag);
 825		dma = skb_frag_dma_map(ddev, frag,
 826				       0, byte_count,
 827				       DMA_TO_DEVICE);
 828		if (dma_mapping_error(ddev, dma))
 829			goto tx_drop_unmap;
 830
 831		data->addr = cpu_to_be64(dma);
 832		data->lkey = mr_key;
 833		dma_wmb();
 834		data->byte_count = cpu_to_be32(byte_count);
 835		--data;
 836	}
 837
 838	/* Map linear part if needed */
 839	if (tx_info->linear) {
 840		byte_count = skb_headlen(skb) - lso_header_size;
 841
 842		dma = dma_map_single(ddev, skb->data +
 843				     lso_header_size, byte_count,
 844				     DMA_TO_DEVICE);
 845		if (dma_mapping_error(ddev, dma))
 846			goto tx_drop_unmap;
 847
 848		data->addr = cpu_to_be64(dma);
 849		data->lkey = mr_key;
 850		dma_wmb();
 851		data->byte_count = cpu_to_be32(byte_count);
 852	}
 853	/* tx completion can avoid cache line miss for common cases */
 854	tx_info->map0_dma = dma;
 855	tx_info->map0_byte_count = byte_count;
 856
 857	return true;
 858
 859tx_drop_unmap:
 860	en_err(priv, "DMA mapping error\n");
 861
 862	while (++i_frag < shinfo->nr_frags) {
 863		++data;
 864		dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr),
 865			       be32_to_cpu(data->byte_count),
 866			       DMA_TO_DEVICE);
 867	}
 868
 869	return false;
 870}
 871
 872netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 873{
 874	struct skb_shared_info *shinfo = skb_shinfo(skb);
 875	struct mlx4_en_priv *priv = netdev_priv(dev);
 876	union mlx4_wqe_qpn_vlan	qpn_vlan = {};
 877	struct mlx4_en_tx_ring *ring;
 878	struct mlx4_en_tx_desc *tx_desc;
 879	struct mlx4_wqe_data_seg *data;
 880	struct mlx4_en_tx_info *tx_info;
 881	u32 __maybe_unused ring_cons;
 882	int tx_ind;
 883	int nr_txbb;
 884	int desc_size;
 885	int real_size;
 886	u32 index, bf_index;
 887	struct ipv6hdr *h6;
 888	__be32 op_own;
 889	int lso_header_size;
 890	void *fragptr = NULL;
 891	bool bounce = false;
 892	bool send_doorbell;
 893	bool stop_queue;
 894	bool inline_ok;
 895	u8 data_offset;
 896	int hopbyhop;
 897	bool bf_ok;
 898
 899	tx_ind = skb_get_queue_mapping(skb);
 900	ring = priv->tx_ring[TX][tx_ind];
 901
 902	if (unlikely(!priv->port_up))
 903		goto tx_drop;
 904
 905	real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
 906				  &inline_ok, &fragptr, &hopbyhop);
 907	if (unlikely(!real_size))
 908		goto tx_drop_count;
 909
 910	/* Align descriptor to TXBB size */
 911	desc_size = ALIGN(real_size, TXBB_SIZE);
 912	nr_txbb = desc_size >> LOG_TXBB_SIZE;
 913
 914	bf_ok = ring->bf_enabled;
 915	if (skb_vlan_tag_present(skb)) {
 916		u16 vlan_proto;
 917
 918		qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb));
 919		vlan_proto = be16_to_cpu(skb->vlan_proto);
 920		if (vlan_proto == ETH_P_8021AD)
 921			qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
 922		else if (vlan_proto == ETH_P_8021Q)
 923			qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
 924		else
 925			qpn_vlan.ins_vlan = 0;
 926		bf_ok = false;
 927	}
 928
 929	netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
 930
 931	/* Packet is good - grab an index and transmit it */
 932	index = ring->prod & ring->size_mask;
 933	bf_index = ring->prod;
 934
 935	/* See if we have enough space for whole descriptor TXBB for setting
 936	 * SW ownership on next descriptor; if not, use a bounce buffer. */
 937	if (likely(index + nr_txbb <= ring->size))
 938		tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 939	else {
 940		if (unlikely(nr_txbb > MLX4_MAX_DESC_TXBBS)) {
 941			if (netif_msg_tx_err(priv))
 942				en_warn(priv, "Oversized header or SG list\n");
 943			goto tx_drop_count;
 944		}
 945		tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 946		bounce = true;
 947		bf_ok = false;
 948	}
 949
 950	/* Save skb in tx_info ring */
 951	tx_info = &ring->tx_info[index];
 952	tx_info->skb = skb;
 953	tx_info->nr_txbb = nr_txbb;
 954
 955	if (!lso_header_size) {
 956		data = &tx_desc->data;
 957		data_offset = offsetof(struct mlx4_en_tx_desc, data);
 958	} else {
 959		int lso_align = ALIGN(lso_header_size - hopbyhop + 4, DS_SIZE);
 960
 961		data = (void *)&tx_desc->lso + lso_align;
 962		data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align;
 963	}
 964
 965	/* valid only for none inline segments */
 966	tx_info->data_offset = data_offset;
 967
 968	tx_info->inl = inline_ok;
 969
 970	tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok;
 971
 972	tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
 973	data += tx_info->nr_maps - 1;
 974
 975	if (!tx_info->inl)
 976		if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb,
 977					   lso_header_size, ring->mr_key,
 978					   tx_info))
 979			goto tx_drop_count;
 980
 981	/*
 982	 * For timestamping add flag to skb_shinfo and
 983	 * set flag for further reference
 984	 */
 985	tx_info->ts_requested = 0;
 986	if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
 987		     shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
 988		shinfo->tx_flags |= SKBTX_IN_PROGRESS;
 989		tx_info->ts_requested = 1;
 990	}
 991
 992	/* Prepare ctrl segment apart opcode+ownership, which depends on
 993	 * whether LSO is used */
 994	tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 995	if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 996		if (!skb->encapsulation)
 997			tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 998								 MLX4_WQE_CTRL_TCP_UDP_CSUM);
 999		else
1000			tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
1001		ring->tx_csum++;
1002	}
1003
1004	if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
1005		struct ethhdr *ethh;
1006
1007		/* Copy dst mac address to wqe. This allows loopback in eSwitch,
1008		 * so that VFs and PF can communicate with each other
1009		 */
1010		ethh = (struct ethhdr *)skb->data;
1011		tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
1012		tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
1013	}
1014
1015	/* Handle LSO (TSO) packets */
1016	if (lso_header_size) {
1017		int i;
1018
1019		/* Mark opcode as LSO */
1020		op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
1021			((ring->prod & ring->size) ?
1022				cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1023
1024		lso_header_size -= hopbyhop;
1025		/* Fill in the LSO prefix */
1026		tx_desc->lso.mss_hdr_size = cpu_to_be32(
1027			shinfo->gso_size << 16 | lso_header_size);
1028
1029
1030		if (unlikely(hopbyhop)) {
1031			/* remove the HBH header.
1032			 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
1033			 */
1034			memcpy(tx_desc->lso.header, skb->data, ETH_HLEN + sizeof(*h6));
1035			h6 = (struct ipv6hdr *)((char *)tx_desc->lso.header + ETH_HLEN);
1036			h6->nexthdr = IPPROTO_TCP;
1037			/* Copy the TCP header after the IPv6 one */
1038			memcpy(h6 + 1,
1039			       skb->data + ETH_HLEN + sizeof(*h6) +
1040					sizeof(struct hop_jumbo_hdr),
1041			       tcp_hdrlen(skb));
1042			/* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
1043		} else {
1044			/* Copy headers;
1045			 * note that we already verified that it is linear
1046			 */
1047			memcpy(tx_desc->lso.header, skb->data, lso_header_size);
1048		}
1049		ring->tso_packets++;
1050
1051		i = shinfo->gso_segs;
1052		tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
1053		ring->packets += i;
1054	} else {
1055		/* Normal (Non LSO) packet */
1056		op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1057			((ring->prod & ring->size) ?
1058			 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1059		tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
1060		ring->packets++;
1061	}
1062	ring->bytes += tx_info->nr_bytes;
1063
1064	if (tx_info->inl)
1065		build_inline_wqe(tx_desc, skb, shinfo, fragptr);
1066
1067	if (skb->encapsulation) {
1068		union {
1069			struct iphdr *v4;
1070			struct ipv6hdr *v6;
1071			unsigned char *hdr;
1072		} ip;
1073		u8 proto;
1074
1075		ip.hdr = skb_inner_network_header(skb);
1076		proto = (ip.v4->version == 4) ? ip.v4->protocol :
1077						ip.v6->nexthdr;
1078
1079		if (proto == IPPROTO_TCP || proto == IPPROTO_UDP)
1080			op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
1081		else
1082			op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
1083	}
1084
1085	WRITE_ONCE(ring->prod, ring->prod + nr_txbb);
1086
1087	/* If we used a bounce buffer then copy descriptor back into place */
1088	if (unlikely(bounce))
1089		tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
1090
1091	skb_tx_timestamp(skb);
1092
1093	/* Check available TXBBs And 2K spare for prefetch */
1094	stop_queue = mlx4_en_is_tx_ring_full(ring);
1095	if (unlikely(stop_queue)) {
1096		netif_tx_stop_queue(ring->tx_queue);
1097		ring->queue_stopped++;
1098	}
1099
1100	send_doorbell = __netdev_tx_sent_queue(ring->tx_queue,
1101					       tx_info->nr_bytes,
1102					       netdev_xmit_more());
1103
1104	real_size = (real_size / 16) & 0x3f;
1105
1106	bf_ok &= desc_size <= MAX_BF && send_doorbell;
1107
1108	if (bf_ok)
1109		qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size);
1110	else
1111		qpn_vlan.fence_size = real_size;
1112
1113	mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index,
1114			      op_own, bf_ok, send_doorbell);
1115
1116	if (unlikely(stop_queue)) {
1117		/* If queue was emptied after the if (stop_queue) , and before
1118		 * the netif_tx_stop_queue() - need to wake the queue,
1119		 * or else it will remain stopped forever.
1120		 * Need a memory barrier to make sure ring->cons was not
1121		 * updated before queue was stopped.
1122		 */
1123		smp_rmb();
1124
1125		if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1126			netif_tx_wake_queue(ring->tx_queue);
1127			ring->wake_queue++;
1128		}
1129	}
1130	return NETDEV_TX_OK;
1131
1132tx_drop_count:
1133	ring->tx_dropped++;
1134tx_drop:
1135	dev_kfree_skb_any(skb);
1136	return NETDEV_TX_OK;
1137}
1138
1139#define MLX4_EN_XDP_TX_NRTXBB  1
1140#define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \
1141				 / 16) & 0x3f)
1142
1143void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
1144				    struct mlx4_en_tx_ring *ring)
1145{
1146	int i;
1147
1148	for (i = 0; i < ring->size; i++) {
1149		struct mlx4_en_tx_info *tx_info = &ring->tx_info[i];
1150		struct mlx4_en_tx_desc *tx_desc = ring->buf +
1151			(i << LOG_TXBB_SIZE);
1152
1153		tx_info->map0_byte_count = PAGE_SIZE;
1154		tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB;
1155		tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data);
1156		tx_info->ts_requested = 0;
1157		tx_info->nr_maps = 1;
1158		tx_info->linear = 1;
1159		tx_info->inl = 0;
1160
1161		tx_desc->data.lkey = ring->mr_key;
1162		tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ;
1163		tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
1164	}
1165}
1166
1167netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
1168			       struct mlx4_en_rx_alloc *frame,
1169			       struct mlx4_en_priv *priv, unsigned int length,
1170			       int tx_ind, bool *doorbell_pending)
1171{
1172	struct mlx4_en_tx_desc *tx_desc;
1173	struct mlx4_en_tx_info *tx_info;
1174	struct mlx4_wqe_data_seg *data;
1175	struct mlx4_en_tx_ring *ring;
1176	dma_addr_t dma;
1177	__be32 op_own;
1178	int index;
1179
1180	if (unlikely(!priv->port_up))
1181		goto tx_drop;
1182
1183	ring = priv->tx_ring[TX_XDP][tx_ind];
1184
1185	if (unlikely(mlx4_en_is_tx_ring_full(ring)))
1186		goto tx_drop_count;
1187
1188	index = ring->prod & ring->size_mask;
1189	tx_info = &ring->tx_info[index];
1190
1191	tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
1192	data = &tx_desc->data;
1193
1194	dma = page_pool_get_dma_addr(frame->page);
1195
1196	tx_info->page = frame->page;
1197	frame->page = NULL;
1198	tx_info->map0_dma = dma;
1199	tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN);
1200
1201	dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset,
1202					 length, DMA_TO_DEVICE);
1203
1204	data->addr = cpu_to_be64(dma + frame->page_offset);
1205	dma_wmb();
1206	data->byte_count = cpu_to_be32(length);
1207
1208	/* tx completion can avoid cache line miss for common cases */
1209
1210	op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1211		((ring->prod & ring->size) ?
1212		 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1213
1214	rx_ring->xdp_tx++;
1215
1216	WRITE_ONCE(ring->prod, ring->prod + MLX4_EN_XDP_TX_NRTXBB);
1217
1218	/* Ensure new descriptor hits memory
1219	 * before setting ownership of this descriptor to HW
1220	 */
1221	dma_wmb();
1222	tx_desc->ctrl.owner_opcode = op_own;
1223	ring->xmit_more++;
1224
1225	*doorbell_pending = true;
1226
1227	return NETDEV_TX_OK;
1228
1229tx_drop_count:
1230	rx_ring->xdp_tx_full++;
1231	*doorbell_pending = true;
1232tx_drop:
1233	return NETDEV_TX_BUSY;
1234}