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skge.c
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linux-6.19.14/drivers/net/ethernet/marvell/skge.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit 4 * Ethernet adapters. Based on earlier sk98lin, e100 and 5 * FreeBSD if_sk drivers. 6 * 7 * This driver intentionally does not support all the features 8 * of the original driver such as link fail-over and link management because 9 * those should be done at higher levels. 10 * 11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org> 12 */ 13 14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16#include <linux/in.h> 17#include <linux/kernel.h> 18#include <linux/module.h> 19#include <linux/moduleparam.h> 20#include <linux/netdevice.h> 21#include <linux/etherdevice.h> 22#include <linux/ethtool.h> 23#include <linux/pci.h> 24#include <linux/if_vlan.h> 25#include <linux/ip.h> 26#include <linux/delay.h> 27#include <linux/crc32.h> 28#include <linux/dma-mapping.h> 29#include <linux/debugfs.h> 30#include <linux/sched.h> 31#include <linux/seq_file.h> 32#include <linux/mii.h> 33#include <linux/slab.h> 34#include <linux/dmi.h> 35#include <linux/prefetch.h> 36#include <asm/irq.h> 37 38#include "skge.h" 39 40#define DRV_NAME "skge" 41#define DRV_VERSION "1.14" 42 43#define DEFAULT_TX_RING_SIZE 128 44#define DEFAULT_RX_RING_SIZE 512 45#define MAX_TX_RING_SIZE 1024 46#define TX_LOW_WATER (MAX_SKB_FRAGS + 1) 47#define MAX_RX_RING_SIZE 4096 48#define RX_COPY_THRESHOLD 128 49#define RX_BUF_SIZE 1536 50#define PHY_RETRIES 1000 51#define ETH_JUMBO_MTU 9000 52#define TX_WATCHDOG (5 * HZ) 53#define BLINK_MS 250 54#define LINK_HZ HZ 55 56#define SKGE_EEPROM_MAGIC 0x9933aabb 57 58 59MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); 60MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 61MODULE_LICENSE("GPL"); 62MODULE_VERSION(DRV_VERSION); 63 64static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 65 NETIF_MSG_LINK | NETIF_MSG_IFUP | 66 NETIF_MSG_IFDOWN); 67 68static int debug = -1; /* defaults above */ 69module_param(debug, int, 0); 70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 71 72static const struct pci_device_id skge_id_table[] = { 73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */ 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */ 75#ifdef CONFIG_SKGE_GENESIS 76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */ 77#endif 78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */ 79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */ 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */ 81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */ 82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ 83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */ 84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */ 85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */ 86 { 0 } 87}; 88MODULE_DEVICE_TABLE(pci, skge_id_table); 89 90static int skge_up(struct net_device *dev); 91static int skge_down(struct net_device *dev); 92static void skge_phy_reset(struct skge_port *skge); 93static void skge_tx_clean(struct net_device *dev); 94static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 95static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 96static void genesis_get_stats(struct skge_port *skge, u64 *data); 97static void yukon_get_stats(struct skge_port *skge, u64 *data); 98static void yukon_init(struct skge_hw *hw, int port); 99static void genesis_mac_init(struct skge_hw *hw, int port); 100static void genesis_link_up(struct skge_port *skge); 101static void skge_set_multicast(struct net_device *dev); 102static irqreturn_t skge_intr(int irq, void *dev_id); 103 104/* Avoid conditionals by using array */ 105static const int txqaddr[] = { Q_XA1, Q_XA2 }; 106static const int rxqaddr[] = { Q_R1, Q_R2 }; 107static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 108static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 109static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; 110static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 }; 111 112static inline bool is_genesis(const struct skge_hw *hw) 113{ 114#ifdef CONFIG_SKGE_GENESIS 115 return hw->chip_id == CHIP_ID_GENESIS; 116#else 117 return false; 118#endif 119} 120 121static int skge_get_regs_len(struct net_device *dev) 122{ 123 return 0x4000; 124} 125 126/* 127 * Returns copy of whole control register region 128 * Note: skip RAM address register because accessing it will 129 * cause bus hangs! 130 */ 131static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, 132 void *p) 133{ 134 const struct skge_port *skge = netdev_priv(dev); 135 const void __iomem *io = skge->hw->regs; 136 137 regs->version = 1; 138 memset(p, 0, regs->len); 139 memcpy_fromio(p, io, B3_RAM_ADDR); 140 141 if (regs->len > B3_RI_WTO_R1) { 142 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 143 regs->len - B3_RI_WTO_R1); 144 } 145} 146 147/* Wake on Lan only supported on Yukon chips with rev 1 or above */ 148static u32 wol_supported(const struct skge_hw *hw) 149{ 150 if (is_genesis(hw)) 151 return 0; 152 153 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) 154 return 0; 155 156 return WAKE_MAGIC | WAKE_PHY; 157} 158 159static void skge_wol_init(struct skge_port *skge) 160{ 161 struct skge_hw *hw = skge->hw; 162 int port = skge->port; 163 u16 ctrl; 164 165 skge_write16(hw, B0_CTST, CS_RST_CLR); 166 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 167 168 /* Turn on Vaux */ 169 skge_write8(hw, B0_POWER_CTRL, 170 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 171 172 /* WA code for COMA mode -- clear PHY reset */ 173 if (hw->chip_id == CHIP_ID_YUKON_LITE && 174 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 175 u32 reg = skge_read32(hw, B2_GP_IO); 176 reg |= GP_DIR_9; 177 reg &= ~GP_IO_9; 178 skge_write32(hw, B2_GP_IO, reg); 179 } 180 181 skge_write32(hw, SK_REG(port, GPHY_CTRL), 182 GPC_DIS_SLEEP | 183 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | 184 GPC_ANEG_1 | GPC_RST_SET); 185 186 skge_write32(hw, SK_REG(port, GPHY_CTRL), 187 GPC_DIS_SLEEP | 188 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | 189 GPC_ANEG_1 | GPC_RST_CLR); 190 191 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 192 193 /* Force to 10/100 skge_reset will re-enable on resume */ 194 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 195 (PHY_AN_100FULL | PHY_AN_100HALF | 196 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA)); 197 /* no 1000 HD/FD */ 198 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); 199 gm_phy_write(hw, port, PHY_MARV_CTRL, 200 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE | 201 PHY_CT_RE_CFG | PHY_CT_DUP_MD); 202 203 204 /* Set GMAC to no flow control and auto update for speed/duplex */ 205 gma_write16(hw, port, GM_GP_CTRL, 206 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 207 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 208 209 /* Set WOL address */ 210 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 211 skge->netdev->dev_addr, ETH_ALEN); 212 213 /* Turn on appropriate WOL control bits */ 214 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 215 ctrl = 0; 216 if (skge->wol & WAKE_PHY) 217 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 218 else 219 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 220 221 if (skge->wol & WAKE_MAGIC) 222 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 223 else 224 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 225 226 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 227 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 228 229 /* block receiver */ 230 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 231} 232 233static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 234{ 235 struct skge_port *skge = netdev_priv(dev); 236 237 wol->supported = wol_supported(skge->hw); 238 wol->wolopts = skge->wol; 239} 240 241static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 242{ 243 struct skge_port *skge = netdev_priv(dev); 244 struct skge_hw *hw = skge->hw; 245 246 if ((wol->wolopts & ~wol_supported(hw)) || 247 !device_can_wakeup(&hw->pdev->dev)) 248 return -EOPNOTSUPP; 249 250 skge->wol = wol->wolopts; 251 252 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); 253 254 return 0; 255} 256 257/* Determine supported/advertised modes based on hardware. 258 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx 259 */ 260static u32 skge_supported_modes(const struct skge_hw *hw) 261{ 262 u32 supported; 263 264 if (hw->copper) { 265 supported = (SUPPORTED_10baseT_Half | 266 SUPPORTED_10baseT_Full | 267 SUPPORTED_100baseT_Half | 268 SUPPORTED_100baseT_Full | 269 SUPPORTED_1000baseT_Half | 270 SUPPORTED_1000baseT_Full | 271 SUPPORTED_Autoneg | 272 SUPPORTED_TP); 273 274 if (is_genesis(hw)) 275 supported &= ~(SUPPORTED_10baseT_Half | 276 SUPPORTED_10baseT_Full | 277 SUPPORTED_100baseT_Half | 278 SUPPORTED_100baseT_Full); 279 280 else if (hw->chip_id == CHIP_ID_YUKON) 281 supported &= ~SUPPORTED_1000baseT_Half; 282 } else 283 supported = (SUPPORTED_1000baseT_Full | 284 SUPPORTED_1000baseT_Half | 285 SUPPORTED_FIBRE | 286 SUPPORTED_Autoneg); 287 288 return supported; 289} 290 291static int skge_get_link_ksettings(struct net_device *dev, 292 struct ethtool_link_ksettings *cmd) 293{ 294 struct skge_port *skge = netdev_priv(dev); 295 struct skge_hw *hw = skge->hw; 296 u32 supported, advertising; 297 298 supported = skge_supported_modes(hw); 299 300 if (hw->copper) { 301 cmd->base.port = PORT_TP; 302 cmd->base.phy_address = hw->phy_addr; 303 } else 304 cmd->base.port = PORT_FIBRE; 305 306 advertising = skge->advertising; 307 cmd->base.autoneg = skge->autoneg; 308 cmd->base.speed = skge->speed; 309 cmd->base.duplex = skge->duplex; 310 311 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 312 supported); 313 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 314 advertising); 315 316 return 0; 317} 318 319static int skge_set_link_ksettings(struct net_device *dev, 320 const struct ethtool_link_ksettings *cmd) 321{ 322 struct skge_port *skge = netdev_priv(dev); 323 const struct skge_hw *hw = skge->hw; 324 u32 supported = skge_supported_modes(hw); 325 int err = 0; 326 u32 advertising; 327 328 ethtool_convert_link_mode_to_legacy_u32(&advertising, 329 cmd->link_modes.advertising); 330 331 if (cmd->base.autoneg == AUTONEG_ENABLE) { 332 advertising = supported; 333 skge->duplex = -1; 334 skge->speed = -1; 335 } else { 336 u32 setting; 337 u32 speed = cmd->base.speed; 338 339 switch (speed) { 340 case SPEED_1000: 341 if (cmd->base.duplex == DUPLEX_FULL) 342 setting = SUPPORTED_1000baseT_Full; 343 else if (cmd->base.duplex == DUPLEX_HALF) 344 setting = SUPPORTED_1000baseT_Half; 345 else 346 return -EINVAL; 347 break; 348 case SPEED_100: 349 if (cmd->base.duplex == DUPLEX_FULL) 350 setting = SUPPORTED_100baseT_Full; 351 else if (cmd->base.duplex == DUPLEX_HALF) 352 setting = SUPPORTED_100baseT_Half; 353 else 354 return -EINVAL; 355 break; 356 357 case SPEED_10: 358 if (cmd->base.duplex == DUPLEX_FULL) 359 setting = SUPPORTED_10baseT_Full; 360 else if (cmd->base.duplex == DUPLEX_HALF) 361 setting = SUPPORTED_10baseT_Half; 362 else 363 return -EINVAL; 364 break; 365 default: 366 return -EINVAL; 367 } 368 369 if ((setting & supported) == 0) 370 return -EINVAL; 371 372 skge->speed = speed; 373 skge->duplex = cmd->base.duplex; 374 } 375 376 skge->autoneg = cmd->base.autoneg; 377 skge->advertising = advertising; 378 379 if (netif_running(dev)) { 380 skge_down(dev); 381 err = skge_up(dev); 382 if (err) { 383 dev_close(dev); 384 return err; 385 } 386 } 387 388 return 0; 389} 390 391static void skge_get_drvinfo(struct net_device *dev, 392 struct ethtool_drvinfo *info) 393{ 394 struct skge_port *skge = netdev_priv(dev); 395 396 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 397 strscpy(info->version, DRV_VERSION, sizeof(info->version)); 398 strscpy(info->bus_info, pci_name(skge->hw->pdev), 399 sizeof(info->bus_info)); 400} 401 402static const struct skge_stat { 403 char name[ETH_GSTRING_LEN]; 404 u16 xmac_offset; 405 u16 gma_offset; 406} skge_stats[] = { 407 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, 408 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, 409 410 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, 411 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, 412 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, 413 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, 414 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, 415 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, 416 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, 417 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, 418 419 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, 420 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, 421 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, 422 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, 423 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, 424 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, 425 426 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, 427 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, 428 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, 429 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, 430 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, 431}; 432 433static int skge_get_sset_count(struct net_device *dev, int sset) 434{ 435 switch (sset) { 436 case ETH_SS_STATS: 437 return ARRAY_SIZE(skge_stats); 438 default: 439 return -EOPNOTSUPP; 440 } 441} 442 443static void skge_get_ethtool_stats(struct net_device *dev, 444 struct ethtool_stats *stats, u64 *data) 445{ 446 struct skge_port *skge = netdev_priv(dev); 447 448 if (is_genesis(skge->hw)) 449 genesis_get_stats(skge, data); 450 else 451 yukon_get_stats(skge, data); 452} 453 454/* Use hardware MIB variables for critical path statistics and 455 * transmit feedback not reported at interrupt. 456 * Other errors are accounted for in interrupt handler. 457 */ 458static struct net_device_stats *skge_get_stats(struct net_device *dev) 459{ 460 struct skge_port *skge = netdev_priv(dev); 461 u64 data[ARRAY_SIZE(skge_stats)]; 462 463 if (is_genesis(skge->hw)) 464 genesis_get_stats(skge, data); 465 else 466 yukon_get_stats(skge, data); 467 468 dev->stats.tx_bytes = data[0]; 469 dev->stats.rx_bytes = data[1]; 470 dev->stats.tx_packets = data[2] + data[4] + data[6]; 471 dev->stats.rx_packets = data[3] + data[5] + data[7]; 472 dev->stats.multicast = data[3] + data[5]; 473 dev->stats.collisions = data[10]; 474 dev->stats.tx_aborted_errors = data[12]; 475 476 return &dev->stats; 477} 478 479static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) 480{ 481 int i; 482 483 switch (stringset) { 484 case ETH_SS_STATS: 485 for (i = 0; i < ARRAY_SIZE(skge_stats); i++) 486 ethtool_puts(&data, skge_stats[i].name); 487 break; 488 } 489} 490 491static void skge_get_ring_param(struct net_device *dev, 492 struct ethtool_ringparam *p, 493 struct kernel_ethtool_ringparam *kernel_p, 494 struct netlink_ext_ack *extack) 495{ 496 struct skge_port *skge = netdev_priv(dev); 497 498 p->rx_max_pending = MAX_RX_RING_SIZE; 499 p->tx_max_pending = MAX_TX_RING_SIZE; 500 501 p->rx_pending = skge->rx_ring.count; 502 p->tx_pending = skge->tx_ring.count; 503} 504 505static int skge_set_ring_param(struct net_device *dev, 506 struct ethtool_ringparam *p, 507 struct kernel_ethtool_ringparam *kernel_p, 508 struct netlink_ext_ack *extack) 509{ 510 struct skge_port *skge = netdev_priv(dev); 511 int err = 0; 512 513 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || 514 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE) 515 return -EINVAL; 516 517 skge->rx_ring.count = p->rx_pending; 518 skge->tx_ring.count = p->tx_pending; 519 520 if (netif_running(dev)) { 521 skge_down(dev); 522 err = skge_up(dev); 523 if (err) 524 dev_close(dev); 525 } 526 527 return err; 528} 529 530static u32 skge_get_msglevel(struct net_device *netdev) 531{ 532 struct skge_port *skge = netdev_priv(netdev); 533 return skge->msg_enable; 534} 535 536static void skge_set_msglevel(struct net_device *netdev, u32 value) 537{ 538 struct skge_port *skge = netdev_priv(netdev); 539 skge->msg_enable = value; 540} 541 542static int skge_nway_reset(struct net_device *dev) 543{ 544 struct skge_port *skge = netdev_priv(dev); 545 546 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) 547 return -EINVAL; 548 549 skge_phy_reset(skge); 550 return 0; 551} 552 553static void skge_get_pauseparam(struct net_device *dev, 554 struct ethtool_pauseparam *ecmd) 555{ 556 struct skge_port *skge = netdev_priv(dev); 557 558 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) || 559 (skge->flow_control == FLOW_MODE_SYM_OR_REM)); 560 ecmd->tx_pause = (ecmd->rx_pause || 561 (skge->flow_control == FLOW_MODE_LOC_SEND)); 562 563 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause; 564} 565 566static int skge_set_pauseparam(struct net_device *dev, 567 struct ethtool_pauseparam *ecmd) 568{ 569 struct skge_port *skge = netdev_priv(dev); 570 struct ethtool_pauseparam old; 571 int err = 0; 572 573 skge_get_pauseparam(dev, &old); 574 575 if (ecmd->autoneg != old.autoneg) 576 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC; 577 else { 578 if (ecmd->rx_pause && ecmd->tx_pause) 579 skge->flow_control = FLOW_MODE_SYMMETRIC; 580 else if (ecmd->rx_pause && !ecmd->tx_pause) 581 skge->flow_control = FLOW_MODE_SYM_OR_REM; 582 else if (!ecmd->rx_pause && ecmd->tx_pause) 583 skge->flow_control = FLOW_MODE_LOC_SEND; 584 else 585 skge->flow_control = FLOW_MODE_NONE; 586 } 587 588 if (netif_running(dev)) { 589 skge_down(dev); 590 err = skge_up(dev); 591 if (err) { 592 dev_close(dev); 593 return err; 594 } 595 } 596 597 return 0; 598} 599 600/* Chip internal frequency for clock calculations */ 601static inline u32 hwkhz(const struct skge_hw *hw) 602{ 603 return is_genesis(hw) ? 53125 : 78125; 604} 605 606/* Chip HZ to microseconds */ 607static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) 608{ 609 return (ticks * 1000) / hwkhz(hw); 610} 611 612/* Microseconds to chip HZ */ 613static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) 614{ 615 return hwkhz(hw) * usec / 1000; 616} 617 618static int skge_get_coalesce(struct net_device *dev, 619 struct ethtool_coalesce *ecmd, 620 struct kernel_ethtool_coalesce *kernel_coal, 621 struct netlink_ext_ack *extack) 622{ 623 struct skge_port *skge = netdev_priv(dev); 624 struct skge_hw *hw = skge->hw; 625 int port = skge->port; 626 627 ecmd->rx_coalesce_usecs = 0; 628 ecmd->tx_coalesce_usecs = 0; 629 630 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { 631 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); 632 u32 msk = skge_read32(hw, B2_IRQM_MSK); 633 634 if (msk & rxirqmask[port]) 635 ecmd->rx_coalesce_usecs = delay; 636 if (msk & txirqmask[port]) 637 ecmd->tx_coalesce_usecs = delay; 638 } 639 640 return 0; 641} 642 643/* Note: interrupt timer is per board, but can turn on/off per port */ 644static int skge_set_coalesce(struct net_device *dev, 645 struct ethtool_coalesce *ecmd, 646 struct kernel_ethtool_coalesce *kernel_coal, 647 struct netlink_ext_ack *extack) 648{ 649 struct skge_port *skge = netdev_priv(dev); 650 struct skge_hw *hw = skge->hw; 651 int port = skge->port; 652 u32 msk = skge_read32(hw, B2_IRQM_MSK); 653 u32 delay = 25; 654 655 if (ecmd->rx_coalesce_usecs == 0) 656 msk &= ~rxirqmask[port]; 657 else if (ecmd->rx_coalesce_usecs < 25 || 658 ecmd->rx_coalesce_usecs > 33333) 659 return -EINVAL; 660 else { 661 msk |= rxirqmask[port]; 662 delay = ecmd->rx_coalesce_usecs; 663 } 664 665 if (ecmd->tx_coalesce_usecs == 0) 666 msk &= ~txirqmask[port]; 667 else if (ecmd->tx_coalesce_usecs < 25 || 668 ecmd->tx_coalesce_usecs > 33333) 669 return -EINVAL; 670 else { 671 msk |= txirqmask[port]; 672 delay = min(delay, ecmd->rx_coalesce_usecs); 673 } 674 675 skge_write32(hw, B2_IRQM_MSK, msk); 676 if (msk == 0) 677 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); 678 else { 679 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); 680 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 681 } 682 return 0; 683} 684 685enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST }; 686static void skge_led(struct skge_port *skge, enum led_mode mode) 687{ 688 struct skge_hw *hw = skge->hw; 689 int port = skge->port; 690 691 spin_lock_bh(&hw->phy_lock); 692 if (is_genesis(hw)) { 693 switch (mode) { 694 case LED_MODE_OFF: 695 if (hw->phy_type == SK_PHY_BCOM) 696 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); 697 else { 698 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); 699 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); 700 } 701 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 702 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); 703 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); 704 break; 705 706 case LED_MODE_ON: 707 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); 708 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); 709 710 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 711 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 712 713 break; 714 715 case LED_MODE_TST: 716 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); 717 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); 718 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 719 720 if (hw->phy_type == SK_PHY_BCOM) 721 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); 722 else { 723 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); 724 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); 725 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 726 } 727 728 } 729 } else { 730 switch (mode) { 731 case LED_MODE_OFF: 732 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 733 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 734 PHY_M_LED_MO_DUP(MO_LED_OFF) | 735 PHY_M_LED_MO_10(MO_LED_OFF) | 736 PHY_M_LED_MO_100(MO_LED_OFF) | 737 PHY_M_LED_MO_1000(MO_LED_OFF) | 738 PHY_M_LED_MO_RX(MO_LED_OFF)); 739 break; 740 case LED_MODE_ON: 741 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 742 PHY_M_LED_PULS_DUR(PULS_170MS) | 743 PHY_M_LED_BLINK_RT(BLINK_84MS) | 744 PHY_M_LEDC_TX_CTRL | 745 PHY_M_LEDC_DP_CTRL); 746 747 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 748 PHY_M_LED_MO_RX(MO_LED_OFF) | 749 (skge->speed == SPEED_100 ? 750 PHY_M_LED_MO_100(MO_LED_ON) : 0)); 751 break; 752 case LED_MODE_TST: 753 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 754 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 755 PHY_M_LED_MO_DUP(MO_LED_ON) | 756 PHY_M_LED_MO_10(MO_LED_ON) | 757 PHY_M_LED_MO_100(MO_LED_ON) | 758 PHY_M_LED_MO_1000(MO_LED_ON) | 759 PHY_M_LED_MO_RX(MO_LED_ON)); 760 } 761 } 762 spin_unlock_bh(&hw->phy_lock); 763} 764 765/* blink LED's for finding board */ 766static int skge_set_phys_id(struct net_device *dev, 767 enum ethtool_phys_id_state state) 768{ 769 struct skge_port *skge = netdev_priv(dev); 770 771 switch (state) { 772 case ETHTOOL_ID_ACTIVE: 773 return 2; /* cycle on/off twice per second */ 774 775 case ETHTOOL_ID_ON: 776 skge_led(skge, LED_MODE_TST); 777 break; 778 779 case ETHTOOL_ID_OFF: 780 skge_led(skge, LED_MODE_OFF); 781 break; 782 783 case ETHTOOL_ID_INACTIVE: 784 /* back to regular LED state */ 785 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF); 786 } 787 788 return 0; 789} 790 791static int skge_get_eeprom_len(struct net_device *dev) 792{ 793 struct skge_port *skge = netdev_priv(dev); 794 u32 reg2; 795 796 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); 797 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 798} 799 800static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset) 801{ 802 u32 val; 803 804 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset); 805 806 do { 807 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); 808 } while (!(offset & PCI_VPD_ADDR_F)); 809 810 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); 811 return val; 812} 813 814static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) 815{ 816 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val); 817 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, 818 offset | PCI_VPD_ADDR_F); 819 820 do { 821 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); 822 } while (offset & PCI_VPD_ADDR_F); 823} 824 825static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 826 u8 *data) 827{ 828 struct skge_port *skge = netdev_priv(dev); 829 struct pci_dev *pdev = skge->hw->pdev; 830 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); 831 int length = eeprom->len; 832 u16 offset = eeprom->offset; 833 834 if (!cap) 835 return -EINVAL; 836 837 eeprom->magic = SKGE_EEPROM_MAGIC; 838 839 while (length > 0) { 840 u32 val = skge_vpd_read(pdev, cap, offset); 841 int n = min_t(int, length, sizeof(val)); 842 843 memcpy(data, &val, n); 844 length -= n; 845 data += n; 846 offset += n; 847 } 848 return 0; 849} 850 851static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 852 u8 *data) 853{ 854 struct skge_port *skge = netdev_priv(dev); 855 struct pci_dev *pdev = skge->hw->pdev; 856 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); 857 int length = eeprom->len; 858 u16 offset = eeprom->offset; 859 860 if (!cap) 861 return -EINVAL; 862 863 if (eeprom->magic != SKGE_EEPROM_MAGIC) 864 return -EINVAL; 865 866 while (length > 0) { 867 u32 val; 868 int n = min_t(int, length, sizeof(val)); 869 870 if (n < sizeof(val)) 871 val = skge_vpd_read(pdev, cap, offset); 872 memcpy(&val, data, n); 873 874 skge_vpd_write(pdev, cap, offset, val); 875 876 length -= n; 877 data += n; 878 offset += n; 879 } 880 return 0; 881} 882 883static const struct ethtool_ops skge_ethtool_ops = { 884 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 885 .get_drvinfo = skge_get_drvinfo, 886 .get_regs_len = skge_get_regs_len, 887 .get_regs = skge_get_regs, 888 .get_wol = skge_get_wol, 889 .set_wol = skge_set_wol, 890 .get_msglevel = skge_get_msglevel, 891 .set_msglevel = skge_set_msglevel, 892 .nway_reset = skge_nway_reset, 893 .get_link = ethtool_op_get_link, 894 .get_eeprom_len = skge_get_eeprom_len, 895 .get_eeprom = skge_get_eeprom, 896 .set_eeprom = skge_set_eeprom, 897 .get_ringparam = skge_get_ring_param, 898 .set_ringparam = skge_set_ring_param, 899 .get_pauseparam = skge_get_pauseparam, 900 .set_pauseparam = skge_set_pauseparam, 901 .get_coalesce = skge_get_coalesce, 902 .set_coalesce = skge_set_coalesce, 903 .get_strings = skge_get_strings, 904 .set_phys_id = skge_set_phys_id, 905 .get_sset_count = skge_get_sset_count, 906 .get_ethtool_stats = skge_get_ethtool_stats, 907 .get_link_ksettings = skge_get_link_ksettings, 908 .set_link_ksettings = skge_set_link_ksettings, 909}; 910 911/* 912 * Allocate ring elements and chain them together 913 * One-to-one association of board descriptors with ring elements 914 */ 915static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) 916{ 917 struct skge_tx_desc *d; 918 struct skge_element *e; 919 int i; 920 921 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL); 922 if (!ring->start) 923 return -ENOMEM; 924 925 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { 926 e->desc = d; 927 if (i == ring->count - 1) { 928 e->next = ring->start; 929 d->next_offset = base; 930 } else { 931 e->next = e + 1; 932 d->next_offset = base + (i+1) * sizeof(*d); 933 } 934 } 935 ring->to_use = ring->to_clean = ring->start; 936 937 return 0; 938} 939 940/* Allocate and setup a new buffer for receiving */ 941static int skge_rx_setup(struct skge_port *skge, struct skge_element *e, 942 struct sk_buff *skb, unsigned int bufsize) 943{ 944 struct skge_rx_desc *rd = e->desc; 945 dma_addr_t map; 946 947 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize, 948 DMA_FROM_DEVICE); 949 950 if (dma_mapping_error(&skge->hw->pdev->dev, map)) 951 return -1; 952 953 rd->dma_lo = lower_32_bits(map); 954 rd->dma_hi = upper_32_bits(map); 955 e->skb = skb; 956 rd->csum1_start = ETH_HLEN; 957 rd->csum2_start = ETH_HLEN; 958 rd->csum1 = 0; 959 rd->csum2 = 0; 960 961 wmb(); 962 963 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; 964 dma_unmap_addr_set(e, mapaddr, map); 965 dma_unmap_len_set(e, maplen, bufsize); 966 return 0; 967} 968 969/* Resume receiving using existing skb, 970 * Note: DMA address is not changed by chip. 971 * MTU not changed while receiver active. 972 */ 973static inline void skge_rx_reuse(struct skge_element *e, unsigned int size) 974{ 975 struct skge_rx_desc *rd = e->desc; 976 977 rd->csum2 = 0; 978 rd->csum2_start = ETH_HLEN; 979 980 wmb(); 981 982 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; 983} 984 985 986/* Free all buffers in receive ring, assumes receiver stopped */ 987static void skge_rx_clean(struct skge_port *skge) 988{ 989 struct skge_hw *hw = skge->hw; 990 struct skge_ring *ring = &skge->rx_ring; 991 struct skge_element *e; 992 993 e = ring->start; 994 do { 995 struct skge_rx_desc *rd = e->desc; 996 rd->control = 0; 997 if (e->skb) { 998 dma_unmap_single(&hw->pdev->dev, 999 dma_unmap_addr(e, mapaddr), 1000 dma_unmap_len(e, maplen), 1001 DMA_FROM_DEVICE); 1002 dev_kfree_skb(e->skb); 1003 e->skb = NULL; 1004 } 1005 } while ((e = e->next) != ring->start); 1006} 1007 1008 1009/* Allocate buffers for receive ring 1010 * For receive: to_clean is next received frame. 1011 */ 1012static int skge_rx_fill(struct net_device *dev) 1013{ 1014 struct skge_port *skge = netdev_priv(dev); 1015 struct skge_ring *ring = &skge->rx_ring; 1016 struct skge_element *e; 1017 1018 e = ring->start; 1019 do { 1020 struct sk_buff *skb; 1021 1022 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN, 1023 GFP_KERNEL); 1024 if (!skb) 1025 return -ENOMEM; 1026 1027 skb_reserve(skb, NET_IP_ALIGN); 1028 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) { 1029 dev_kfree_skb(skb); 1030 return -EIO; 1031 } 1032 } while ((e = e->next) != ring->start); 1033 1034 ring->to_clean = ring->start; 1035 return 0; 1036} 1037 1038static const char *skge_pause(enum pause_status status) 1039{ 1040 switch (status) { 1041 case FLOW_STAT_NONE: 1042 return "none"; 1043 case FLOW_STAT_REM_SEND: 1044 return "rx only"; 1045 case FLOW_STAT_LOC_SEND: 1046 return "tx_only"; 1047 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */ 1048 return "both"; 1049 default: 1050 return "indeterminated"; 1051 } 1052} 1053 1054 1055static void skge_link_up(struct skge_port *skge) 1056{ 1057 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), 1058 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON); 1059 1060 netif_carrier_on(skge->netdev); 1061 netif_wake_queue(skge->netdev); 1062 1063 netif_info(skge, link, skge->netdev, 1064 "Link is up at %d Mbps, %s duplex, flow control %s\n", 1065 skge->speed, 1066 skge->duplex == DUPLEX_FULL ? "full" : "half", 1067 skge_pause(skge->flow_status)); 1068} 1069 1070static void skge_link_down(struct skge_port *skge) 1071{ 1072 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); 1073 netif_carrier_off(skge->netdev); 1074 netif_stop_queue(skge->netdev); 1075 1076 netif_info(skge, link, skge->netdev, "Link is down\n"); 1077} 1078 1079static void xm_link_down(struct skge_hw *hw, int port) 1080{ 1081 struct net_device *dev = hw->dev[port]; 1082 struct skge_port *skge = netdev_priv(dev); 1083 1084 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 1085 1086 if (netif_carrier_ok(dev)) 1087 skge_link_down(skge); 1088} 1089 1090static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) 1091{ 1092 int i; 1093 1094 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 1095 *val = xm_read16(hw, port, XM_PHY_DATA); 1096 1097 if (hw->phy_type == SK_PHY_XMAC) 1098 goto ready; 1099 1100 for (i = 0; i < PHY_RETRIES; i++) { 1101 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) 1102 goto ready; 1103 udelay(1); 1104 } 1105 1106 return -ETIMEDOUT; 1107 ready: 1108 *val = xm_read16(hw, port, XM_PHY_DATA); 1109 1110 return 0; 1111} 1112 1113static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) 1114{ 1115 u16 v = 0; 1116 if (__xm_phy_read(hw, port, reg, &v)) 1117 pr_warn("%s: phy read timed out\n", hw->dev[port]->name); 1118 return v; 1119} 1120 1121static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1122{ 1123 int i; 1124 1125 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 1126 for (i = 0; i < PHY_RETRIES; i++) { 1127 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 1128 goto ready; 1129 udelay(1); 1130 } 1131 return -EIO; 1132 1133 ready: 1134 xm_write16(hw, port, XM_PHY_DATA, val); 1135 for (i = 0; i < PHY_RETRIES; i++) { 1136 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 1137 return 0; 1138 udelay(1); 1139 } 1140 return -ETIMEDOUT; 1141} 1142 1143static void genesis_init(struct skge_hw *hw) 1144{ 1145 /* set blink source counter */ 1146 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); 1147 skge_write8(hw, B2_BSC_CTRL, BSC_START); 1148 1149 /* configure mac arbiter */ 1150 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1151 1152 /* configure mac arbiter timeout values */ 1153 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); 1154 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); 1155 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); 1156 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); 1157 1158 skge_write8(hw, B3_MA_RCINI_RX1, 0); 1159 skge_write8(hw, B3_MA_RCINI_RX2, 0); 1160 skge_write8(hw, B3_MA_RCINI_TX1, 0); 1161 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1162 1163 /* configure packet arbiter timeout */ 1164 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); 1165 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); 1166 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); 1167 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); 1168 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); 1169} 1170 1171static void genesis_reset(struct skge_hw *hw, int port) 1172{ 1173 static const u8 zero[8] = { 0 }; 1174 u32 reg; 1175 1176 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 1177 1178 /* reset the statistics module */ 1179 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); 1180 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 1181 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ 1182 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ 1183 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ 1184 1185 /* disable Broadcom PHY IRQ */ 1186 if (hw->phy_type == SK_PHY_BCOM) 1187 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); 1188 1189 xm_outhash(hw, port, XM_HSM, zero); 1190 1191 /* Flush TX and RX fifo */ 1192 reg = xm_read32(hw, port, XM_MODE); 1193 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); 1194 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); 1195} 1196 1197/* Convert mode to MII values */ 1198static const u16 phy_pause_map[] = { 1199 [FLOW_MODE_NONE] = 0, 1200 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM, 1201 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP, 1202 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM, 1203}; 1204 1205/* special defines for FIBER (88E1011S only) */ 1206static const u16 fiber_pause_map[] = { 1207 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE, 1208 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD, 1209 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD, 1210 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD, 1211}; 1212 1213 1214/* Check status of Broadcom phy link */ 1215static void bcom_check_link(struct skge_hw *hw, int port) 1216{ 1217 struct net_device *dev = hw->dev[port]; 1218 struct skge_port *skge = netdev_priv(dev); 1219 u16 status; 1220 1221 /* read twice because of latch */ 1222 xm_phy_read(hw, port, PHY_BCOM_STAT); 1223 status = xm_phy_read(hw, port, PHY_BCOM_STAT); 1224 1225 if ((status & PHY_ST_LSYNC) == 0) { 1226 xm_link_down(hw, port); 1227 return; 1228 } 1229 1230 if (skge->autoneg == AUTONEG_ENABLE) { 1231 u16 lpa, aux; 1232 1233 if (!(status & PHY_ST_AN_OVER)) 1234 return; 1235 1236 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 1237 if (lpa & PHY_B_AN_RF) { 1238 netdev_notice(dev, "remote fault\n"); 1239 return; 1240 } 1241 1242 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); 1243 1244 /* Check Duplex mismatch */ 1245 switch (aux & PHY_B_AS_AN_RES_MSK) { 1246 case PHY_B_RES_1000FD: 1247 skge->duplex = DUPLEX_FULL; 1248 break; 1249 case PHY_B_RES_1000HD: 1250 skge->duplex = DUPLEX_HALF; 1251 break; 1252 default: 1253 netdev_notice(dev, "duplex mismatch\n"); 1254 return; 1255 } 1256 1257 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1258 switch (aux & PHY_B_AS_PAUSE_MSK) { 1259 case PHY_B_AS_PAUSE_MSK: 1260 skge->flow_status = FLOW_STAT_SYMMETRIC; 1261 break; 1262 case PHY_B_AS_PRR: 1263 skge->flow_status = FLOW_STAT_REM_SEND; 1264 break; 1265 case PHY_B_AS_PRT: 1266 skge->flow_status = FLOW_STAT_LOC_SEND; 1267 break; 1268 default: 1269 skge->flow_status = FLOW_STAT_NONE; 1270 } 1271 skge->speed = SPEED_1000; 1272 } 1273 1274 if (!netif_carrier_ok(dev)) 1275 genesis_link_up(skge); 1276} 1277 1278/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional 1279 * Phy on for 100 or 10Mbit operation 1280 */ 1281static void bcom_phy_init(struct skge_port *skge) 1282{ 1283 struct skge_hw *hw = skge->hw; 1284 int port = skge->port; 1285 int i; 1286 u16 id1, r, ext, ctl; 1287 1288 /* magic workaround patterns for Broadcom */ 1289 static const struct { 1290 u16 reg; 1291 u16 val; 1292 } A1hack[] = { 1293 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, 1294 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, 1295 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, 1296 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1297 }, C0hack[] = { 1298 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, 1299 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, 1300 }; 1301 1302 /* read Id from external PHY (all have the same address) */ 1303 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); 1304 1305 /* Optimize MDIO transfer by suppressing preamble. */ 1306 r = xm_read16(hw, port, XM_MMU_CMD); 1307 r |= XM_MMU_NO_PRE; 1308 xm_write16(hw, port, XM_MMU_CMD, r); 1309 1310 switch (id1) { 1311 case PHY_BCOM_ID1_C0: 1312 /* 1313 * Workaround BCOM Errata for the C0 type. 1314 * Write magic patterns to reserved registers. 1315 */ 1316 for (i = 0; i < ARRAY_SIZE(C0hack); i++) 1317 xm_phy_write(hw, port, 1318 C0hack[i].reg, C0hack[i].val); 1319 1320 break; 1321 case PHY_BCOM_ID1_A1: 1322 /* 1323 * Workaround BCOM Errata for the A1 type. 1324 * Write magic patterns to reserved registers. 1325 */ 1326 for (i = 0; i < ARRAY_SIZE(A1hack); i++) 1327 xm_phy_write(hw, port, 1328 A1hack[i].reg, A1hack[i].val); 1329 break; 1330 } 1331 1332 /* 1333 * Workaround BCOM Errata (#10523) for all BCom PHYs. 1334 * Disable Power Management after reset. 1335 */ 1336 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); 1337 r |= PHY_B_AC_DIS_PM; 1338 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); 1339 1340 /* Dummy read */ 1341 xm_read16(hw, port, XM_ISRC); 1342 1343 ext = PHY_B_PEC_EN_LTR; /* enable tx led */ 1344 ctl = PHY_CT_SP1000; /* always 1000mbit */ 1345 1346 if (skge->autoneg == AUTONEG_ENABLE) { 1347 /* 1348 * Workaround BCOM Errata #1 for the C5 type. 1349 * 1000Base-T Link Acquisition Failure in Slave Mode 1350 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register 1351 */ 1352 u16 adv = PHY_B_1000C_RD; 1353 if (skge->advertising & ADVERTISED_1000baseT_Half) 1354 adv |= PHY_B_1000C_AHD; 1355 if (skge->advertising & ADVERTISED_1000baseT_Full) 1356 adv |= PHY_B_1000C_AFD; 1357 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); 1358 1359 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; 1360 } else { 1361 if (skge->duplex == DUPLEX_FULL) 1362 ctl |= PHY_CT_DUP_MD; 1363 /* Force to slave */ 1364 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); 1365 } 1366 1367 /* Set autonegotiation pause parameters */ 1368 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, 1369 phy_pause_map[skge->flow_control] | PHY_AN_CSMA); 1370 1371 /* Handle Jumbo frames */ 1372 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 1373 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1374 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); 1375 1376 ext |= PHY_B_PEC_HIGH_LA; 1377 1378 } 1379 1380 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); 1381 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); 1382 1383 /* Use link status change interrupt */ 1384 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1385} 1386 1387static void xm_phy_init(struct skge_port *skge) 1388{ 1389 struct skge_hw *hw = skge->hw; 1390 int port = skge->port; 1391 u16 ctrl = 0; 1392 1393 if (skge->autoneg == AUTONEG_ENABLE) { 1394 if (skge->advertising & ADVERTISED_1000baseT_Half) 1395 ctrl |= PHY_X_AN_HD; 1396 if (skge->advertising & ADVERTISED_1000baseT_Full) 1397 ctrl |= PHY_X_AN_FD; 1398 1399 ctrl |= fiber_pause_map[skge->flow_control]; 1400 1401 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); 1402 1403 /* Restart Auto-negotiation */ 1404 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; 1405 } else { 1406 /* Set DuplexMode in Config register */ 1407 if (skge->duplex == DUPLEX_FULL) 1408 ctrl |= PHY_CT_DUP_MD; 1409 /* 1410 * Do NOT enable Auto-negotiation here. This would hold 1411 * the link down because no IDLEs are transmitted 1412 */ 1413 } 1414 1415 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); 1416 1417 /* Poll PHY for status changes */ 1418 mod_timer(&skge->link_timer, jiffies + LINK_HZ); 1419} 1420 1421static int xm_check_link(struct net_device *dev) 1422{ 1423 struct skge_port *skge = netdev_priv(dev); 1424 struct skge_hw *hw = skge->hw; 1425 int port = skge->port; 1426 u16 status; 1427 1428 /* read twice because of latch */ 1429 xm_phy_read(hw, port, PHY_XMAC_STAT); 1430 status = xm_phy_read(hw, port, PHY_XMAC_STAT); 1431 1432 if ((status & PHY_ST_LSYNC) == 0) { 1433 xm_link_down(hw, port); 1434 return 0; 1435 } 1436 1437 if (skge->autoneg == AUTONEG_ENABLE) { 1438 u16 lpa, res; 1439 1440 if (!(status & PHY_ST_AN_OVER)) 1441 return 0; 1442 1443 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 1444 if (lpa & PHY_B_AN_RF) { 1445 netdev_notice(dev, "remote fault\n"); 1446 return 0; 1447 } 1448 1449 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); 1450 1451 /* Check Duplex mismatch */ 1452 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) { 1453 case PHY_X_RS_FD: 1454 skge->duplex = DUPLEX_FULL; 1455 break; 1456 case PHY_X_RS_HD: 1457 skge->duplex = DUPLEX_HALF; 1458 break; 1459 default: 1460 netdev_notice(dev, "duplex mismatch\n"); 1461 return 0; 1462 } 1463 1464 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1465 if ((skge->flow_control == FLOW_MODE_SYMMETRIC || 1466 skge->flow_control == FLOW_MODE_SYM_OR_REM) && 1467 (lpa & PHY_X_P_SYM_MD)) 1468 skge->flow_status = FLOW_STAT_SYMMETRIC; 1469 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM && 1470 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) 1471 /* Enable PAUSE receive, disable PAUSE transmit */ 1472 skge->flow_status = FLOW_STAT_REM_SEND; 1473 else if (skge->flow_control == FLOW_MODE_LOC_SEND && 1474 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) 1475 /* Disable PAUSE receive, enable PAUSE transmit */ 1476 skge->flow_status = FLOW_STAT_LOC_SEND; 1477 else 1478 skge->flow_status = FLOW_STAT_NONE; 1479 1480 skge->speed = SPEED_1000; 1481 } 1482 1483 if (!netif_carrier_ok(dev)) 1484 genesis_link_up(skge); 1485 return 1; 1486} 1487 1488/* Poll to check for link coming up. 1489 * 1490 * Since internal PHY is wired to a level triggered pin, can't 1491 * get an interrupt when carrier is detected, need to poll for 1492 * link coming up. 1493 */ 1494static void xm_link_timer(struct timer_list *t) 1495{ 1496 struct skge_port *skge = timer_container_of(skge, t, link_timer); 1497 struct net_device *dev = skge->netdev; 1498 struct skge_hw *hw = skge->hw; 1499 int port = skge->port; 1500 int i; 1501 unsigned long flags; 1502 1503 if (!netif_running(dev)) 1504 return; 1505 1506 spin_lock_irqsave(&hw->phy_lock, flags); 1507 1508 /* 1509 * Verify that the link by checking GPIO register three times. 1510 * This pin has the signal from the link_sync pin connected to it. 1511 */ 1512 for (i = 0; i < 3; i++) { 1513 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) 1514 goto link_down; 1515 } 1516 1517 /* Re-enable interrupt to detect link down */ 1518 if (xm_check_link(dev)) { 1519 u16 msk = xm_read16(hw, port, XM_IMSK); 1520 msk &= ~XM_IS_INP_ASS; 1521 xm_write16(hw, port, XM_IMSK, msk); 1522 xm_read16(hw, port, XM_ISRC); 1523 } else { 1524link_down: 1525 mod_timer(&skge->link_timer, 1526 round_jiffies(jiffies + LINK_HZ)); 1527 } 1528 spin_unlock_irqrestore(&hw->phy_lock, flags); 1529} 1530 1531static void genesis_mac_init(struct skge_hw *hw, int port) 1532{ 1533 struct net_device *dev = hw->dev[port]; 1534 struct skge_port *skge = netdev_priv(dev); 1535 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; 1536 int i; 1537 u32 r; 1538 static const u8 zero[6] = { 0 }; 1539 1540 for (i = 0; i < 10; i++) { 1541 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 1542 MFF_SET_MAC_RST); 1543 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) 1544 goto reset_ok; 1545 udelay(1); 1546 } 1547 1548 netdev_warn(dev, "genesis reset failed\n"); 1549 1550 reset_ok: 1551 /* Unreset the XMAC. */ 1552 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1553 1554 /* 1555 * Perform additional initialization for external PHYs, 1556 * namely for the 1000baseTX cards that use the XMAC's 1557 * GMII mode. 1558 */ 1559 if (hw->phy_type != SK_PHY_XMAC) { 1560 /* Take external Phy out of reset */ 1561 r = skge_read32(hw, B2_GP_IO); 1562 if (port == 0) 1563 r |= GP_DIR_0|GP_IO_0; 1564 else 1565 r |= GP_DIR_2|GP_IO_2; 1566 1567 skge_write32(hw, B2_GP_IO, r); 1568 1569 /* Enable GMII interface */ 1570 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); 1571 } 1572 1573 1574 switch (hw->phy_type) { 1575 case SK_PHY_XMAC: 1576 xm_phy_init(skge); 1577 break; 1578 case SK_PHY_BCOM: 1579 bcom_phy_init(skge); 1580 bcom_check_link(hw, port); 1581 } 1582 1583 /* Set Station Address */ 1584 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 1585 1586 /* We don't use match addresses so clear */ 1587 for (i = 1; i < 16; i++) 1588 xm_outaddr(hw, port, XM_EXM(i), zero); 1589 1590 /* Clear MIB counters */ 1591 xm_write16(hw, port, XM_STAT_CMD, 1592 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1593 /* Clear two times according to Errata #3 */ 1594 xm_write16(hw, port, XM_STAT_CMD, 1595 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1596 1597 /* configure Rx High Water Mark (XM_RX_HI_WM) */ 1598 xm_write16(hw, port, XM_RX_HI_WM, 1450); 1599 1600 /* We don't need the FCS appended to the packet. */ 1601 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; 1602 if (jumbo) 1603 r |= XM_RX_BIG_PK_OK; 1604 1605 if (skge->duplex == DUPLEX_HALF) { 1606 /* 1607 * If in manual half duplex mode the other side might be in 1608 * full duplex mode, so ignore if a carrier extension is not seen 1609 * on frames received 1610 */ 1611 r |= XM_RX_DIS_CEXT; 1612 } 1613 xm_write16(hw, port, XM_RX_CMD, r); 1614 1615 /* We want short frames padded to 60 bytes. */ 1616 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); 1617 1618 /* Increase threshold for jumbo frames on dual port */ 1619 if (hw->ports > 1 && jumbo) 1620 xm_write16(hw, port, XM_TX_THR, 1020); 1621 else 1622 xm_write16(hw, port, XM_TX_THR, 512); 1623 1624 /* 1625 * Enable the reception of all error frames. This is 1626 * a necessary evil due to the design of the XMAC. The 1627 * XMAC's receive FIFO is only 8K in size, however jumbo 1628 * frames can be up to 9000 bytes in length. When bad 1629 * frame filtering is enabled, the XMAC's RX FIFO operates 1630 * in 'store and forward' mode. For this to work, the 1631 * entire frame has to fit into the FIFO, but that means 1632 * that jumbo frames larger than 8192 bytes will be 1633 * truncated. Disabling all bad frame filtering causes 1634 * the RX FIFO to operate in streaming mode, in which 1635 * case the XMAC will start transferring frames out of the 1636 * RX FIFO as soon as the FIFO threshold is reached. 1637 */ 1638 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); 1639 1640 1641 /* 1642 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) 1643 * - Enable all bits excepting 'Octets Rx OK Low CntOv' 1644 * and 'Octets Rx OK Hi Cnt Ov'. 1645 */ 1646 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); 1647 1648 /* 1649 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) 1650 * - Enable all bits excepting 'Octets Tx OK Low CntOv' 1651 * and 'Octets Tx OK Hi Cnt Ov'. 1652 */ 1653 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); 1654 1655 /* Configure MAC arbiter */ 1656 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1657 1658 /* configure timeout values */ 1659 skge_write8(hw, B3_MA_TOINI_RX1, 72); 1660 skge_write8(hw, B3_MA_TOINI_RX2, 72); 1661 skge_write8(hw, B3_MA_TOINI_TX1, 72); 1662 skge_write8(hw, B3_MA_TOINI_TX2, 72); 1663 1664 skge_write8(hw, B3_MA_RCINI_RX1, 0); 1665 skge_write8(hw, B3_MA_RCINI_RX2, 0); 1666 skge_write8(hw, B3_MA_RCINI_TX1, 0); 1667 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1668 1669 /* Configure Rx MAC FIFO */ 1670 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); 1671 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); 1672 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 1673 1674 /* Configure Tx MAC FIFO */ 1675 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); 1676 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 1677 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 1678 1679 if (jumbo) { 1680 /* Enable frame flushing if jumbo frames used */ 1681 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); 1682 } else { 1683 /* enable timeout timers if normal frames */ 1684 skge_write16(hw, B3_PA_CTRL, 1685 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); 1686 } 1687} 1688 1689static void genesis_stop(struct skge_port *skge) 1690{ 1691 struct skge_hw *hw = skge->hw; 1692 int port = skge->port; 1693 unsigned retries = 1000; 1694 u16 cmd; 1695 1696 /* Disable Tx and Rx */ 1697 cmd = xm_read16(hw, port, XM_MMU_CMD); 1698 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1699 xm_write16(hw, port, XM_MMU_CMD, cmd); 1700 1701 genesis_reset(hw, port); 1702 1703 /* Clear Tx packet arbiter timeout IRQ */ 1704 skge_write16(hw, B3_PA_CTRL, 1705 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); 1706 1707 /* Reset the MAC */ 1708 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1709 do { 1710 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); 1711 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) 1712 break; 1713 } while (--retries > 0); 1714 1715 /* For external PHYs there must be special handling */ 1716 if (hw->phy_type != SK_PHY_XMAC) { 1717 u32 reg = skge_read32(hw, B2_GP_IO); 1718 if (port == 0) { 1719 reg |= GP_DIR_0; 1720 reg &= ~GP_IO_0; 1721 } else { 1722 reg |= GP_DIR_2; 1723 reg &= ~GP_IO_2; 1724 } 1725 skge_write32(hw, B2_GP_IO, reg); 1726 skge_read32(hw, B2_GP_IO); 1727 } 1728 1729 xm_write16(hw, port, XM_MMU_CMD, 1730 xm_read16(hw, port, XM_MMU_CMD) 1731 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 1732 1733 xm_read16(hw, port, XM_MMU_CMD); 1734} 1735 1736 1737static void genesis_get_stats(struct skge_port *skge, u64 *data) 1738{ 1739 struct skge_hw *hw = skge->hw; 1740 int port = skge->port; 1741 int i; 1742 unsigned long timeout = jiffies + HZ; 1743 1744 xm_write16(hw, port, 1745 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); 1746 1747 /* wait for update to complete */ 1748 while (xm_read16(hw, port, XM_STAT_CMD) 1749 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { 1750 if (time_after(jiffies, timeout)) 1751 break; 1752 udelay(10); 1753 } 1754 1755 /* special case for 64 bit octet counter */ 1756 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 1757 | xm_read32(hw, port, XM_TXO_OK_LO); 1758 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 1759 | xm_read32(hw, port, XM_RXO_OK_LO); 1760 1761 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 1762 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); 1763} 1764 1765static void genesis_mac_intr(struct skge_hw *hw, int port) 1766{ 1767 struct net_device *dev = hw->dev[port]; 1768 struct skge_port *skge = netdev_priv(dev); 1769 u16 status = xm_read16(hw, port, XM_ISRC); 1770 1771 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 1772 "mac interrupt status 0x%x\n", status); 1773 1774 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { 1775 xm_link_down(hw, port); 1776 mod_timer(&skge->link_timer, jiffies + 1); 1777 } 1778 1779 if (status & XM_IS_TXF_UR) { 1780 xm_write32(hw, port, XM_MODE, XM_MD_FTF); 1781 ++dev->stats.tx_fifo_errors; 1782 } 1783} 1784 1785static void genesis_link_up(struct skge_port *skge) 1786{ 1787 struct skge_hw *hw = skge->hw; 1788 int port = skge->port; 1789 u16 cmd, msk; 1790 u32 mode; 1791 1792 cmd = xm_read16(hw, port, XM_MMU_CMD); 1793 1794 /* 1795 * enabling pause frame reception is required for 1000BT 1796 * because the XMAC is not reset if the link is going down 1797 */ 1798 if (skge->flow_status == FLOW_STAT_NONE || 1799 skge->flow_status == FLOW_STAT_LOC_SEND) 1800 /* Disable Pause Frame Reception */ 1801 cmd |= XM_MMU_IGN_PF; 1802 else 1803 /* Enable Pause Frame Reception */ 1804 cmd &= ~XM_MMU_IGN_PF; 1805 1806 xm_write16(hw, port, XM_MMU_CMD, cmd); 1807 1808 mode = xm_read32(hw, port, XM_MODE); 1809 if (skge->flow_status == FLOW_STAT_SYMMETRIC || 1810 skge->flow_status == FLOW_STAT_LOC_SEND) { 1811 /* 1812 * Configure Pause Frame Generation 1813 * Use internal and external Pause Frame Generation. 1814 * Sending pause frames is edge triggered. 1815 * Send a Pause frame with the maximum pause time if 1816 * internal oder external FIFO full condition occurs. 1817 * Send a zero pause time frame to re-start transmission. 1818 */ 1819 /* XM_PAUSE_DA = '010000C28001' (default) */ 1820 /* XM_MAC_PTIME = 0xffff (maximum) */ 1821 /* remember this value is defined in big endian (!) */ 1822 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); 1823 1824 mode |= XM_PAUSE_MODE; 1825 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); 1826 } else { 1827 /* 1828 * disable pause frame generation is required for 1000BT 1829 * because the XMAC is not reset if the link is going down 1830 */ 1831 /* Disable Pause Mode in Mode Register */ 1832 mode &= ~XM_PAUSE_MODE; 1833 1834 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); 1835 } 1836 1837 xm_write32(hw, port, XM_MODE, mode); 1838 1839 /* Turn on detection of Tx underrun */ 1840 msk = xm_read16(hw, port, XM_IMSK); 1841 msk &= ~XM_IS_TXF_UR; 1842 xm_write16(hw, port, XM_IMSK, msk); 1843 1844 xm_read16(hw, port, XM_ISRC); 1845 1846 /* get MMU Command Reg. */ 1847 cmd = xm_read16(hw, port, XM_MMU_CMD); 1848 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) 1849 cmd |= XM_MMU_GMII_FD; 1850 1851 /* 1852 * Workaround BCOM Errata (#10523) for all BCom Phys 1853 * Enable Power Management after link up 1854 */ 1855 if (hw->phy_type == SK_PHY_BCOM) { 1856 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1857 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) 1858 & ~PHY_B_AC_DIS_PM); 1859 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1860 } 1861 1862 /* enable Rx/Tx */ 1863 xm_write16(hw, port, XM_MMU_CMD, 1864 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1865 skge_link_up(skge); 1866} 1867 1868 1869static inline void bcom_phy_intr(struct skge_port *skge) 1870{ 1871 struct skge_hw *hw = skge->hw; 1872 int port = skge->port; 1873 u16 isrc; 1874 1875 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); 1876 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 1877 "phy interrupt status 0x%x\n", isrc); 1878 1879 if (isrc & PHY_B_IS_PSE) 1880 pr_err("%s: uncorrectable pair swap error\n", 1881 hw->dev[port]->name); 1882 1883 /* Workaround BCom Errata: 1884 * enable and disable loopback mode if "NO HCD" occurs. 1885 */ 1886 if (isrc & PHY_B_IS_NO_HDCL) { 1887 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); 1888 xm_phy_write(hw, port, PHY_BCOM_CTRL, 1889 ctrl | PHY_CT_LOOP); 1890 xm_phy_write(hw, port, PHY_BCOM_CTRL, 1891 ctrl & ~PHY_CT_LOOP); 1892 } 1893 1894 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) 1895 bcom_check_link(hw, port); 1896 1897} 1898 1899static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1900{ 1901 int i; 1902 1903 gma_write16(hw, port, GM_SMI_DATA, val); 1904 gma_write16(hw, port, GM_SMI_CTRL, 1905 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); 1906 for (i = 0; i < PHY_RETRIES; i++) { 1907 udelay(1); 1908 1909 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 1910 return 0; 1911 } 1912 1913 pr_warn("%s: phy write timeout\n", hw->dev[port]->name); 1914 return -EIO; 1915} 1916 1917static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) 1918{ 1919 int i; 1920 1921 gma_write16(hw, port, GM_SMI_CTRL, 1922 GM_SMI_CT_PHY_AD(hw->phy_addr) 1923 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 1924 1925 for (i = 0; i < PHY_RETRIES; i++) { 1926 udelay(1); 1927 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) 1928 goto ready; 1929 } 1930 1931 return -ETIMEDOUT; 1932 ready: 1933 *val = gma_read16(hw, port, GM_SMI_DATA); 1934 return 0; 1935} 1936 1937static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) 1938{ 1939 u16 v = 0; 1940 if (__gm_phy_read(hw, port, reg, &v)) 1941 pr_warn("%s: phy read timeout\n", hw->dev[port]->name); 1942 return v; 1943} 1944 1945/* Marvell Phy Initialization */ 1946static void yukon_init(struct skge_hw *hw, int port) 1947{ 1948 struct skge_port *skge = netdev_priv(hw->dev[port]); 1949 u16 ctrl, ct1000, adv; 1950 1951 if (skge->autoneg == AUTONEG_ENABLE) { 1952 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 1953 1954 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 1955 PHY_M_EC_MAC_S_MSK); 1956 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 1957 1958 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 1959 1960 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 1961 } 1962 1963 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 1964 if (skge->autoneg == AUTONEG_DISABLE) 1965 ctrl &= ~PHY_CT_ANE; 1966 1967 ctrl |= PHY_CT_RESET; 1968 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 1969 1970 ctrl = 0; 1971 ct1000 = 0; 1972 adv = PHY_AN_CSMA; 1973 1974 if (skge->autoneg == AUTONEG_ENABLE) { 1975 if (hw->copper) { 1976 if (skge->advertising & ADVERTISED_1000baseT_Full) 1977 ct1000 |= PHY_M_1000C_AFD; 1978 if (skge->advertising & ADVERTISED_1000baseT_Half) 1979 ct1000 |= PHY_M_1000C_AHD; 1980 if (skge->advertising & ADVERTISED_100baseT_Full) 1981 adv |= PHY_M_AN_100_FD; 1982 if (skge->advertising & ADVERTISED_100baseT_Half) 1983 adv |= PHY_M_AN_100_HD; 1984 if (skge->advertising & ADVERTISED_10baseT_Full) 1985 adv |= PHY_M_AN_10_FD; 1986 if (skge->advertising & ADVERTISED_10baseT_Half) 1987 adv |= PHY_M_AN_10_HD; 1988 1989 /* Set Flow-control capabilities */ 1990 adv |= phy_pause_map[skge->flow_control]; 1991 } else { 1992 if (skge->advertising & ADVERTISED_1000baseT_Full) 1993 adv |= PHY_M_AN_1000X_AFD; 1994 if (skge->advertising & ADVERTISED_1000baseT_Half) 1995 adv |= PHY_M_AN_1000X_AHD; 1996 1997 adv |= fiber_pause_map[skge->flow_control]; 1998 } 1999 2000 /* Restart Auto-negotiation */ 2001 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 2002 } else { 2003 /* forced speed/duplex settings */ 2004 ct1000 = PHY_M_1000C_MSE; 2005 2006 if (skge->duplex == DUPLEX_FULL) 2007 ctrl |= PHY_CT_DUP_MD; 2008 2009 switch (skge->speed) { 2010 case SPEED_1000: 2011 ctrl |= PHY_CT_SP1000; 2012 break; 2013 case SPEED_100: 2014 ctrl |= PHY_CT_SP100; 2015 break; 2016 } 2017 2018 ctrl |= PHY_CT_RESET; 2019 } 2020 2021 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 2022 2023 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 2024 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2025 2026 /* Enable phy interrupt on autonegotiation complete (or link up) */ 2027 if (skge->autoneg == AUTONEG_ENABLE) 2028 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); 2029 else 2030 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 2031} 2032 2033static void yukon_reset(struct skge_hw *hw, int port) 2034{ 2035 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ 2036 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 2037 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 2038 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 2039 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 2040 2041 gma_write16(hw, port, GM_RX_CTRL, 2042 gma_read16(hw, port, GM_RX_CTRL) 2043 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2044} 2045 2046/* Apparently, early versions of Yukon-Lite had wrong chip_id? */ 2047static int is_yukon_lite_a0(struct skge_hw *hw) 2048{ 2049 u32 reg; 2050 int ret; 2051 2052 if (hw->chip_id != CHIP_ID_YUKON) 2053 return 0; 2054 2055 reg = skge_read32(hw, B2_FAR); 2056 skge_write8(hw, B2_FAR + 3, 0xff); 2057 ret = (skge_read8(hw, B2_FAR + 3) != 0); 2058 skge_write32(hw, B2_FAR, reg); 2059 return ret; 2060} 2061 2062static void yukon_mac_init(struct skge_hw *hw, int port) 2063{ 2064 struct skge_port *skge = netdev_priv(hw->dev[port]); 2065 int i; 2066 u32 reg; 2067 const u8 *addr = hw->dev[port]->dev_addr; 2068 2069 /* WA code for COMA mode -- set PHY reset */ 2070 if (hw->chip_id == CHIP_ID_YUKON_LITE && 2071 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 2072 reg = skge_read32(hw, B2_GP_IO); 2073 reg |= GP_DIR_9 | GP_IO_9; 2074 skge_write32(hw, B2_GP_IO, reg); 2075 } 2076 2077 /* hard reset */ 2078 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2079 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2080 2081 /* WA code for COMA mode -- clear PHY reset */ 2082 if (hw->chip_id == CHIP_ID_YUKON_LITE && 2083 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 2084 reg = skge_read32(hw, B2_GP_IO); 2085 reg |= GP_DIR_9; 2086 reg &= ~GP_IO_9; 2087 skge_write32(hw, B2_GP_IO, reg); 2088 } 2089 2090 /* Set hardware config mode */ 2091 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | 2092 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; 2093 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; 2094 2095 /* Clear GMC reset */ 2096 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); 2097 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); 2098 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); 2099 2100 if (skge->autoneg == AUTONEG_DISABLE) { 2101 reg = GM_GPCR_AU_ALL_DIS; 2102 gma_write16(hw, port, GM_GP_CTRL, 2103 gma_read16(hw, port, GM_GP_CTRL) | reg); 2104 2105 switch (skge->speed) { 2106 case SPEED_1000: 2107 reg &= ~GM_GPCR_SPEED_100; 2108 reg |= GM_GPCR_SPEED_1000; 2109 break; 2110 case SPEED_100: 2111 reg &= ~GM_GPCR_SPEED_1000; 2112 reg |= GM_GPCR_SPEED_100; 2113 break; 2114 case SPEED_10: 2115 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); 2116 break; 2117 } 2118 2119 if (skge->duplex == DUPLEX_FULL) 2120 reg |= GM_GPCR_DUP_FULL; 2121 } else 2122 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 2123 2124 switch (skge->flow_control) { 2125 case FLOW_MODE_NONE: 2126 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2127 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 2128 break; 2129 case FLOW_MODE_LOC_SEND: 2130 /* disable Rx flow-control */ 2131 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 2132 break; 2133 case FLOW_MODE_SYMMETRIC: 2134 case FLOW_MODE_SYM_OR_REM: 2135 /* enable Tx & Rx flow-control */ 2136 break; 2137 } 2138 2139 gma_write16(hw, port, GM_GP_CTRL, reg); 2140 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 2141 2142 yukon_init(hw, port); 2143 2144 /* MIB clear */ 2145 reg = gma_read16(hw, port, GM_PHY_ADDR); 2146 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 2147 2148 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 2149 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); 2150 gma_write16(hw, port, GM_PHY_ADDR, reg); 2151 2152 /* transmit control */ 2153 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 2154 2155 /* receive control reg: unicast + multicast + no FCS */ 2156 gma_write16(hw, port, GM_RX_CTRL, 2157 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 2158 2159 /* transmit flow control */ 2160 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 2161 2162 /* transmit parameter */ 2163 gma_write16(hw, port, GM_TX_PARAM, 2164 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 2165 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 2166 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); 2167 2168 /* configure the Serial Mode Register */ 2169 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) 2170 | GM_SMOD_VLAN_ENA 2171 | IPG_DATA_VAL(IPG_DATA_DEF); 2172 2173 if (hw->dev[port]->mtu > ETH_DATA_LEN) 2174 reg |= GM_SMOD_JUMBO_ENA; 2175 2176 gma_write16(hw, port, GM_SERIAL_MODE, reg); 2177 2178 /* physical address: used for pause frames */ 2179 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 2180 /* virtual address for data */ 2181 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 2182 2183 /* enable interrupt mask for counter overflows */ 2184 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 2185 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 2186 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 2187 2188 /* Initialize Mac Fifo */ 2189 2190 /* Configure Rx MAC FIFO */ 2191 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); 2192 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 2193 2194 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2195 if (is_yukon_lite_a0(hw)) 2196 reg &= ~GMF_RX_F_FL_ON; 2197 2198 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 2199 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); 2200 /* 2201 * because Pause Packet Truncation in GMAC is not working 2202 * we have to increase the Flush Threshold to 64 bytes 2203 * in order to flush pause packets in Rx FIFO on Yukon-1 2204 */ 2205 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); 2206 2207 /* Configure Tx MAC FIFO */ 2208 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 2209 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 2210} 2211 2212/* Go into power down mode */ 2213static void yukon_suspend(struct skge_hw *hw, int port) 2214{ 2215 u16 ctrl; 2216 2217 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 2218 ctrl |= PHY_M_PC_POL_R_DIS; 2219 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 2220 2221 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 2222 ctrl |= PHY_CT_RESET; 2223 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2224 2225 /* switch IEEE compatible power down mode on */ 2226 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 2227 ctrl |= PHY_CT_PDOWN; 2228 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2229} 2230 2231static void yukon_stop(struct skge_port *skge) 2232{ 2233 struct skge_hw *hw = skge->hw; 2234 int port = skge->port; 2235 2236 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 2237 yukon_reset(hw, port); 2238 2239 gma_write16(hw, port, GM_GP_CTRL, 2240 gma_read16(hw, port, GM_GP_CTRL) 2241 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); 2242 gma_read16(hw, port, GM_GP_CTRL); 2243 2244 yukon_suspend(hw, port); 2245 2246 /* set GPHY Control reset */ 2247 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2248 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2249} 2250 2251static void yukon_get_stats(struct skge_port *skge, u64 *data) 2252{ 2253 struct skge_hw *hw = skge->hw; 2254 int port = skge->port; 2255 int i; 2256 2257 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 2258 | gma_read32(hw, port, GM_TXO_OK_LO); 2259 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 2260 | gma_read32(hw, port, GM_RXO_OK_LO); 2261 2262 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 2263 data[i] = gma_read32(hw, port, 2264 skge_stats[i].gma_offset); 2265} 2266 2267static void yukon_mac_intr(struct skge_hw *hw, int port) 2268{ 2269 struct net_device *dev = hw->dev[port]; 2270 struct skge_port *skge = netdev_priv(dev); 2271 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2272 2273 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 2274 "mac interrupt status 0x%x\n", status); 2275 2276 if (status & GM_IS_RX_FF_OR) { 2277 ++dev->stats.rx_fifo_errors; 2278 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2279 } 2280 2281 if (status & GM_IS_TX_FF_UR) { 2282 ++dev->stats.tx_fifo_errors; 2283 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2284 } 2285 2286} 2287 2288static u16 yukon_speed(const struct skge_hw *hw, u16 aux) 2289{ 2290 switch (aux & PHY_M_PS_SPEED_MSK) { 2291 case PHY_M_PS_SPEED_1000: 2292 return SPEED_1000; 2293 case PHY_M_PS_SPEED_100: 2294 return SPEED_100; 2295 default: 2296 return SPEED_10; 2297 } 2298} 2299 2300static void yukon_link_up(struct skge_port *skge) 2301{ 2302 struct skge_hw *hw = skge->hw; 2303 int port = skge->port; 2304 u16 reg; 2305 2306 /* Enable Transmit FIFO Underrun */ 2307 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 2308 2309 reg = gma_read16(hw, port, GM_GP_CTRL); 2310 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) 2311 reg |= GM_GPCR_DUP_FULL; 2312 2313 /* enable Rx/Tx */ 2314 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 2315 gma_write16(hw, port, GM_GP_CTRL, reg); 2316 2317 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 2318 skge_link_up(skge); 2319} 2320 2321static void yukon_link_down(struct skge_port *skge) 2322{ 2323 struct skge_hw *hw = skge->hw; 2324 int port = skge->port; 2325 u16 ctrl; 2326 2327 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2328 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2329 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2330 2331 if (skge->flow_status == FLOW_STAT_REM_SEND) { 2332 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2333 ctrl |= PHY_M_AN_ASP; 2334 /* restore Asymmetric Pause bit */ 2335 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); 2336 } 2337 2338 skge_link_down(skge); 2339 2340 yukon_init(hw, port); 2341} 2342 2343static void yukon_phy_intr(struct skge_port *skge) 2344{ 2345 struct skge_hw *hw = skge->hw; 2346 int port = skge->port; 2347 const char *reason = NULL; 2348 u16 istatus, phystat; 2349 2350 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2351 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2352 2353 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 2354 "phy interrupt status 0x%x 0x%x\n", istatus, phystat); 2355 2356 if (istatus & PHY_M_IS_AN_COMPL) { 2357 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) 2358 & PHY_M_AN_RF) { 2359 reason = "remote fault"; 2360 goto failed; 2361 } 2362 2363 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { 2364 reason = "master/slave fault"; 2365 goto failed; 2366 } 2367 2368 if (!(phystat & PHY_M_PS_SPDUP_RES)) { 2369 reason = "speed/duplex"; 2370 goto failed; 2371 } 2372 2373 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) 2374 ? DUPLEX_FULL : DUPLEX_HALF; 2375 skge->speed = yukon_speed(hw, phystat); 2376 2377 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 2378 switch (phystat & PHY_M_PS_PAUSE_MSK) { 2379 case PHY_M_PS_PAUSE_MSK: 2380 skge->flow_status = FLOW_STAT_SYMMETRIC; 2381 break; 2382 case PHY_M_PS_RX_P_EN: 2383 skge->flow_status = FLOW_STAT_REM_SEND; 2384 break; 2385 case PHY_M_PS_TX_P_EN: 2386 skge->flow_status = FLOW_STAT_LOC_SEND; 2387 break; 2388 default: 2389 skge->flow_status = FLOW_STAT_NONE; 2390 } 2391 2392 if (skge->flow_status == FLOW_STAT_NONE || 2393 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) 2394 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2395 else 2396 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2397 yukon_link_up(skge); 2398 return; 2399 } 2400 2401 if (istatus & PHY_M_IS_LSP_CHANGE) 2402 skge->speed = yukon_speed(hw, phystat); 2403 2404 if (istatus & PHY_M_IS_DUP_CHANGE) 2405 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2406 if (istatus & PHY_M_IS_LST_CHANGE) { 2407 if (phystat & PHY_M_PS_LINK_UP) 2408 yukon_link_up(skge); 2409 else 2410 yukon_link_down(skge); 2411 } 2412 return; 2413 failed: 2414 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason); 2415 2416 /* XXX restart autonegotiation? */ 2417} 2418 2419static void skge_phy_reset(struct skge_port *skge) 2420{ 2421 struct skge_hw *hw = skge->hw; 2422 int port = skge->port; 2423 struct net_device *dev = hw->dev[port]; 2424 2425 netif_stop_queue(skge->netdev); 2426 netif_carrier_off(skge->netdev); 2427 2428 spin_lock_bh(&hw->phy_lock); 2429 if (is_genesis(hw)) { 2430 genesis_reset(hw, port); 2431 genesis_mac_init(hw, port); 2432 } else { 2433 yukon_reset(hw, port); 2434 yukon_init(hw, port); 2435 } 2436 spin_unlock_bh(&hw->phy_lock); 2437 2438 skge_set_multicast(dev); 2439} 2440 2441/* Basic MII support */ 2442static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2443{ 2444 struct mii_ioctl_data *data = if_mii(ifr); 2445 struct skge_port *skge = netdev_priv(dev); 2446 struct skge_hw *hw = skge->hw; 2447 int err = -EOPNOTSUPP; 2448 2449 if (!netif_running(dev)) 2450 return -ENODEV; /* Phy still in reset */ 2451 2452 switch (cmd) { 2453 case SIOCGMIIPHY: 2454 data->phy_id = hw->phy_addr; 2455 2456 fallthrough; 2457 case SIOCGMIIREG: { 2458 u16 val = 0; 2459 spin_lock_bh(&hw->phy_lock); 2460 2461 if (is_genesis(hw)) 2462 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2463 else 2464 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2465 spin_unlock_bh(&hw->phy_lock); 2466 data->val_out = val; 2467 break; 2468 } 2469 2470 case SIOCSMIIREG: 2471 spin_lock_bh(&hw->phy_lock); 2472 if (is_genesis(hw)) 2473 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2474 data->val_in); 2475 else 2476 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2477 data->val_in); 2478 spin_unlock_bh(&hw->phy_lock); 2479 break; 2480 } 2481 return err; 2482} 2483 2484static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) 2485{ 2486 u32 end; 2487 2488 start /= 8; 2489 len /= 8; 2490 end = start + len - 1; 2491 2492 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 2493 skge_write32(hw, RB_ADDR(q, RB_START), start); 2494 skge_write32(hw, RB_ADDR(q, RB_WP), start); 2495 skge_write32(hw, RB_ADDR(q, RB_RP), start); 2496 skge_write32(hw, RB_ADDR(q, RB_END), end); 2497 2498 if (q == Q_R1 || q == Q_R2) { 2499 /* Set thresholds on receive queue's */ 2500 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), 2501 start + (2*len)/3); 2502 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), 2503 start + (len/3)); 2504 } else { 2505 /* Enable store & forward on Tx queue's because 2506 * Tx FIFO is only 4K on Genesis and 1K on Yukon 2507 */ 2508 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 2509 } 2510 2511 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 2512} 2513 2514/* Setup Bus Memory Interface */ 2515static void skge_qset(struct skge_port *skge, u16 q, 2516 const struct skge_element *e) 2517{ 2518 struct skge_hw *hw = skge->hw; 2519 u32 watermark = 0x600; 2520 u64 base = skge->dma + (e->desc - skge->mem); 2521 2522 /* optimization to reduce window on 32bit/33mhz */ 2523 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) 2524 watermark /= 2; 2525 2526 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); 2527 skge_write32(hw, Q_ADDR(q, Q_F), watermark); 2528 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); 2529 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); 2530} 2531 2532static int skge_up(struct net_device *dev) 2533{ 2534 struct skge_port *skge = netdev_priv(dev); 2535 struct skge_hw *hw = skge->hw; 2536 int port = skge->port; 2537 u32 chunk, ram_addr; 2538 size_t rx_size, tx_size; 2539 int err; 2540 2541 if (!is_valid_ether_addr(dev->dev_addr)) 2542 return -EINVAL; 2543 2544 netif_info(skge, ifup, skge->netdev, "enabling interface\n"); 2545 2546 if (dev->mtu > RX_BUF_SIZE) 2547 skge->rx_buf_size = dev->mtu + ETH_HLEN; 2548 else 2549 skge->rx_buf_size = RX_BUF_SIZE; 2550 2551 2552 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); 2553 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); 2554 skge->mem_size = tx_size + rx_size; 2555 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size, 2556 &skge->dma, GFP_KERNEL); 2557 if (!skge->mem) 2558 return -ENOMEM; 2559 2560 BUG_ON(skge->dma & 7); 2561 2562 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) { 2563 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n"); 2564 err = -EINVAL; 2565 goto free_pci_mem; 2566 } 2567 2568 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma); 2569 if (err) 2570 goto free_pci_mem; 2571 2572 err = skge_rx_fill(dev); 2573 if (err) 2574 goto free_rx_ring; 2575 2576 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, 2577 skge->dma + rx_size); 2578 if (err) 2579 goto free_rx_ring; 2580 2581 if (hw->ports == 1) { 2582 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED, 2583 dev->name, hw); 2584 if (err) { 2585 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n", 2586 hw->pdev->irq, err); 2587 goto free_tx_ring; 2588 } 2589 } 2590 2591 /* Initialize MAC */ 2592 netif_carrier_off(dev); 2593 spin_lock_bh(&hw->phy_lock); 2594 if (is_genesis(hw)) 2595 genesis_mac_init(hw, port); 2596 else 2597 yukon_mac_init(hw, port); 2598 spin_unlock_bh(&hw->phy_lock); 2599 2600 /* Configure RAMbuffers - equally between ports and tx/rx */ 2601 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); 2602 ram_addr = hw->ram_offset + 2 * chunk * port; 2603 2604 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); 2605 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); 2606 2607 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); 2608 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); 2609 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); 2610 2611 /* Start receiver BMU */ 2612 wmb(); 2613 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); 2614 skge_led(skge, LED_MODE_ON); 2615 2616 spin_lock_irq(&hw->hw_lock); 2617 hw->intr_mask |= portmask[port]; 2618 skge_write32(hw, B0_IMSK, hw->intr_mask); 2619 skge_read32(hw, B0_IMSK); 2620 spin_unlock_irq(&hw->hw_lock); 2621 2622 napi_enable(&skge->napi); 2623 2624 skge_set_multicast(dev); 2625 2626 return 0; 2627 2628 free_tx_ring: 2629 kfree(skge->tx_ring.start); 2630 free_rx_ring: 2631 skge_rx_clean(skge); 2632 kfree(skge->rx_ring.start); 2633 free_pci_mem: 2634 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, 2635 skge->dma); 2636 skge->mem = NULL; 2637 2638 return err; 2639} 2640 2641/* stop receiver */ 2642static void skge_rx_stop(struct skge_hw *hw, int port) 2643{ 2644 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); 2645 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), 2646 RB_RST_SET|RB_DIS_OP_MD); 2647 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); 2648} 2649 2650static int skge_down(struct net_device *dev) 2651{ 2652 struct skge_port *skge = netdev_priv(dev); 2653 struct skge_hw *hw = skge->hw; 2654 int port = skge->port; 2655 2656 if (!skge->mem) 2657 return 0; 2658 2659 netif_info(skge, ifdown, skge->netdev, "disabling interface\n"); 2660 2661 netif_tx_disable(dev); 2662 2663 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC) 2664 timer_delete_sync(&skge->link_timer); 2665 2666 napi_disable(&skge->napi); 2667 netif_carrier_off(dev); 2668 2669 spin_lock_irq(&hw->hw_lock); 2670 hw->intr_mask &= ~portmask[port]; 2671 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); 2672 skge_read32(hw, B0_IMSK); 2673 spin_unlock_irq(&hw->hw_lock); 2674 2675 if (hw->ports == 1) 2676 free_irq(hw->pdev->irq, hw); 2677 2678 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); 2679 if (is_genesis(hw)) 2680 genesis_stop(skge); 2681 else 2682 yukon_stop(skge); 2683 2684 /* Stop transmitter */ 2685 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); 2686 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2687 RB_RST_SET|RB_DIS_OP_MD); 2688 2689 2690 /* Disable Force Sync bit and Enable Alloc bit */ 2691 skge_write8(hw, SK_REG(port, TXA_CTRL), 2692 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2693 2694 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2695 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2696 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2697 2698 /* Reset PCI FIFO */ 2699 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); 2700 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2701 2702 /* Reset the RAM Buffer async Tx queue */ 2703 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); 2704 2705 skge_rx_stop(hw, port); 2706 2707 if (is_genesis(hw)) { 2708 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); 2709 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); 2710 } else { 2711 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2712 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2713 } 2714 2715 skge_led(skge, LED_MODE_OFF); 2716 2717 netif_tx_lock_bh(dev); 2718 skge_tx_clean(dev); 2719 netif_tx_unlock_bh(dev); 2720 2721 skge_rx_clean(skge); 2722 2723 kfree(skge->rx_ring.start); 2724 kfree(skge->tx_ring.start); 2725 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, 2726 skge->dma); 2727 skge->mem = NULL; 2728 return 0; 2729} 2730 2731static inline int skge_avail(const struct skge_ring *ring) 2732{ 2733 smp_mb(); 2734 return ((ring->to_clean > ring->to_use) ? 0 : ring->count) 2735 + (ring->to_clean - ring->to_use) - 1; 2736} 2737 2738static netdev_tx_t skge_xmit_frame(struct sk_buff *skb, 2739 struct net_device *dev) 2740{ 2741 struct skge_port *skge = netdev_priv(dev); 2742 struct skge_hw *hw = skge->hw; 2743 struct skge_element *e; 2744 struct skge_tx_desc *td; 2745 int i; 2746 u32 control, len; 2747 dma_addr_t map; 2748 2749 if (skb_padto(skb, ETH_ZLEN)) 2750 return NETDEV_TX_OK; 2751 2752 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) 2753 return NETDEV_TX_BUSY; 2754 2755 e = skge->tx_ring.to_use; 2756 td = e->desc; 2757 BUG_ON(td->control & BMU_OWN); 2758 e->skb = skb; 2759 len = skb_headlen(skb); 2760 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE); 2761 if (dma_mapping_error(&hw->pdev->dev, map)) 2762 goto mapping_error; 2763 2764 dma_unmap_addr_set(e, mapaddr, map); 2765 dma_unmap_len_set(e, maplen, len); 2766 2767 td->dma_lo = lower_32_bits(map); 2768 td->dma_hi = upper_32_bits(map); 2769 2770 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2771 const int offset = skb_checksum_start_offset(skb); 2772 2773 /* This seems backwards, but it is what the sk98lin 2774 * does. Looks like hardware is wrong? 2775 */ 2776 if (ipip_hdr(skb)->protocol == IPPROTO_UDP && 2777 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) 2778 control = BMU_TCP_CHECK; 2779 else 2780 control = BMU_UDP_CHECK; 2781 2782 td->csum_offs = 0; 2783 td->csum_start = offset; 2784 td->csum_write = offset + skb->csum_offset; 2785 } else 2786 control = BMU_CHECK; 2787 2788 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ 2789 control |= BMU_EOF | BMU_IRQ_EOF; 2790 else { 2791 struct skge_tx_desc *tf = td; 2792 2793 control |= BMU_STFWD; 2794 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2795 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2796 2797 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 2798 skb_frag_size(frag), DMA_TO_DEVICE); 2799 if (dma_mapping_error(&hw->pdev->dev, map)) 2800 goto mapping_unwind; 2801 2802 e = e->next; 2803 e->skb = skb; 2804 tf = e->desc; 2805 BUG_ON(tf->control & BMU_OWN); 2806 2807 tf->dma_lo = lower_32_bits(map); 2808 tf->dma_hi = upper_32_bits(map); 2809 dma_unmap_addr_set(e, mapaddr, map); 2810 dma_unmap_len_set(e, maplen, skb_frag_size(frag)); 2811 2812 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag); 2813 } 2814 tf->control |= BMU_EOF | BMU_IRQ_EOF; 2815 } 2816 /* Make sure all the descriptors written */ 2817 wmb(); 2818 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; 2819 wmb(); 2820 2821 netdev_sent_queue(dev, skb->len); 2822 2823 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); 2824 2825 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev, 2826 "tx queued, slot %td, len %d\n", 2827 e - skge->tx_ring.start, skb->len); 2828 2829 skge->tx_ring.to_use = e->next; 2830 smp_wmb(); 2831 2832 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) { 2833 netdev_dbg(dev, "transmit queue full\n"); 2834 netif_stop_queue(dev); 2835 } 2836 2837 return NETDEV_TX_OK; 2838 2839mapping_unwind: 2840 e = skge->tx_ring.to_use; 2841 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), 2842 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2843 while (i-- > 0) { 2844 e = e->next; 2845 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), 2846 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2847 } 2848 2849mapping_error: 2850 if (net_ratelimit()) 2851 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 2852 dev_kfree_skb_any(skb); 2853 return NETDEV_TX_OK; 2854} 2855 2856 2857/* Free resources associated with this reing element */ 2858static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e, 2859 u32 control) 2860{ 2861 /* skb header vs. fragment */ 2862 if (control & BMU_STF) 2863 dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr), 2864 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2865 else 2866 dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr), 2867 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2868} 2869 2870/* Free all buffers in transmit ring */ 2871static void skge_tx_clean(struct net_device *dev) 2872{ 2873 struct skge_port *skge = netdev_priv(dev); 2874 struct skge_element *e; 2875 2876 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 2877 struct skge_tx_desc *td = e->desc; 2878 2879 skge_tx_unmap(skge->hw->pdev, e, td->control); 2880 2881 if (td->control & BMU_EOF) 2882 dev_kfree_skb(e->skb); 2883 td->control = 0; 2884 } 2885 2886 netdev_reset_queue(dev); 2887 skge->tx_ring.to_clean = e; 2888} 2889 2890static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue) 2891{ 2892 struct skge_port *skge = netdev_priv(dev); 2893 2894 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n"); 2895 2896 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); 2897 skge_tx_clean(dev); 2898 netif_wake_queue(dev); 2899} 2900 2901static int skge_change_mtu(struct net_device *dev, int new_mtu) 2902{ 2903 int err; 2904 2905 if (!netif_running(dev)) { 2906 WRITE_ONCE(dev->mtu, new_mtu); 2907 return 0; 2908 } 2909 2910 skge_down(dev); 2911 2912 WRITE_ONCE(dev->mtu, new_mtu); 2913 2914 err = skge_up(dev); 2915 if (err) 2916 dev_close(dev); 2917 2918 return err; 2919} 2920 2921static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 2922 2923static void genesis_add_filter(u8 filter[8], const u8 *addr) 2924{ 2925 u32 crc, bit; 2926 2927 crc = ether_crc_le(ETH_ALEN, addr); 2928 bit = ~crc & 0x3f; 2929 filter[bit/8] |= 1 << (bit%8); 2930} 2931 2932static void genesis_set_multicast(struct net_device *dev) 2933{ 2934 struct skge_port *skge = netdev_priv(dev); 2935 struct skge_hw *hw = skge->hw; 2936 int port = skge->port; 2937 struct netdev_hw_addr *ha; 2938 u32 mode; 2939 u8 filter[8]; 2940 2941 mode = xm_read32(hw, port, XM_MODE); 2942 mode |= XM_MD_ENA_HASH; 2943 if (dev->flags & IFF_PROMISC) 2944 mode |= XM_MD_ENA_PROM; 2945 else 2946 mode &= ~XM_MD_ENA_PROM; 2947 2948 if (dev->flags & IFF_ALLMULTI) 2949 memset(filter, 0xff, sizeof(filter)); 2950 else { 2951 memset(filter, 0, sizeof(filter)); 2952 2953 if (skge->flow_status == FLOW_STAT_REM_SEND || 2954 skge->flow_status == FLOW_STAT_SYMMETRIC) 2955 genesis_add_filter(filter, pause_mc_addr); 2956 2957 netdev_for_each_mc_addr(ha, dev) 2958 genesis_add_filter(filter, ha->addr); 2959 } 2960 2961 xm_write32(hw, port, XM_MODE, mode); 2962 xm_outhash(hw, port, XM_HSM, filter); 2963} 2964 2965static void yukon_add_filter(u8 filter[8], const u8 *addr) 2966{ 2967 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f; 2968 2969 filter[bit / 8] |= 1 << (bit % 8); 2970} 2971 2972static void yukon_set_multicast(struct net_device *dev) 2973{ 2974 struct skge_port *skge = netdev_priv(dev); 2975 struct skge_hw *hw = skge->hw; 2976 int port = skge->port; 2977 struct netdev_hw_addr *ha; 2978 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND || 2979 skge->flow_status == FLOW_STAT_SYMMETRIC); 2980 u16 reg; 2981 u8 filter[8]; 2982 2983 memset(filter, 0, sizeof(filter)); 2984 2985 reg = gma_read16(hw, port, GM_RX_CTRL); 2986 reg |= GM_RXCR_UCF_ENA; 2987 2988 if (dev->flags & IFF_PROMISC) /* promiscuous */ 2989 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2990 else if (dev->flags & IFF_ALLMULTI) /* all multicast */ 2991 memset(filter, 0xff, sizeof(filter)); 2992 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */ 2993 reg &= ~GM_RXCR_MCF_ENA; 2994 else { 2995 reg |= GM_RXCR_MCF_ENA; 2996 2997 if (rx_pause) 2998 yukon_add_filter(filter, pause_mc_addr); 2999 3000 netdev_for_each_mc_addr(ha, dev) 3001 yukon_add_filter(filter, ha->addr); 3002 } 3003 3004 3005 gma_write16(hw, port, GM_MC_ADDR_H1, 3006 (u16)filter[0] | ((u16)filter[1] << 8)); 3007 gma_write16(hw, port, GM_MC_ADDR_H2, 3008 (u16)filter[2] | ((u16)filter[3] << 8)); 3009 gma_write16(hw, port, GM_MC_ADDR_H3, 3010 (u16)filter[4] | ((u16)filter[5] << 8)); 3011 gma_write16(hw, port, GM_MC_ADDR_H4, 3012 (u16)filter[6] | ((u16)filter[7] << 8)); 3013 3014 gma_write16(hw, port, GM_RX_CTRL, reg); 3015} 3016 3017static inline u16 phy_length(const struct skge_hw *hw, u32 status) 3018{ 3019 if (is_genesis(hw)) 3020 return status >> XMR_FS_LEN_SHIFT; 3021 else 3022 return status >> GMR_FS_LEN_SHIFT; 3023} 3024 3025static inline int bad_phy_status(const struct skge_hw *hw, u32 status) 3026{ 3027 if (is_genesis(hw)) 3028 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; 3029 else 3030 return (status & GMR_FS_ANY_ERR) || 3031 (status & GMR_FS_RX_OK) == 0; 3032} 3033 3034static void skge_set_multicast(struct net_device *dev) 3035{ 3036 struct skge_port *skge = netdev_priv(dev); 3037 3038 if (is_genesis(skge->hw)) 3039 genesis_set_multicast(dev); 3040 else 3041 yukon_set_multicast(dev); 3042 3043} 3044 3045 3046/* Get receive buffer from descriptor. 3047 * Handles copy of small buffers and reallocation failures 3048 */ 3049static struct sk_buff *skge_rx_get(struct net_device *dev, 3050 struct skge_element *e, 3051 u32 control, u32 status, u16 csum) 3052{ 3053 struct skge_port *skge = netdev_priv(dev); 3054 struct sk_buff *skb; 3055 u16 len = control & BMU_BBC; 3056 3057 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev, 3058 "rx slot %td status 0x%x len %d\n", 3059 e - skge->rx_ring.start, status, len); 3060 3061 if (len > skge->rx_buf_size) 3062 goto error; 3063 3064 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)) 3065 goto error; 3066 3067 if (bad_phy_status(skge->hw, status)) 3068 goto error; 3069 3070 if (phy_length(skge->hw, status) != len) 3071 goto error; 3072 3073 if (len < RX_COPY_THRESHOLD) { 3074 skb = netdev_alloc_skb_ip_align(dev, len); 3075 if (!skb) 3076 goto resubmit; 3077 3078 dma_sync_single_for_cpu(&skge->hw->pdev->dev, 3079 dma_unmap_addr(e, mapaddr), 3080 dma_unmap_len(e, maplen), 3081 DMA_FROM_DEVICE); 3082 skb_copy_from_linear_data(e->skb, skb->data, len); 3083 dma_sync_single_for_device(&skge->hw->pdev->dev, 3084 dma_unmap_addr(e, mapaddr), 3085 dma_unmap_len(e, maplen), 3086 DMA_FROM_DEVICE); 3087 skge_rx_reuse(e, skge->rx_buf_size); 3088 } else { 3089 struct skge_element ee; 3090 struct sk_buff *nskb; 3091 3092 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size); 3093 if (!nskb) 3094 goto resubmit; 3095 3096 ee = *e; 3097 3098 skb = ee.skb; 3099 prefetch(skb->data); 3100 3101 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) { 3102 dev_kfree_skb(nskb); 3103 goto resubmit; 3104 } 3105 3106 dma_unmap_single(&skge->hw->pdev->dev, 3107 dma_unmap_addr(&ee, mapaddr), 3108 dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE); 3109 } 3110 3111 skb_put(skb, len); 3112 3113 if (dev->features & NETIF_F_RXCSUM) { 3114 skb->csum = le16_to_cpu(csum); 3115 skb->ip_summed = CHECKSUM_COMPLETE; 3116 } 3117 3118 skb->protocol = eth_type_trans(skb, dev); 3119 3120 return skb; 3121error: 3122 3123 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev, 3124 "rx err, slot %td control 0x%x status 0x%x\n", 3125 e - skge->rx_ring.start, control, status); 3126 3127 if (is_genesis(skge->hw)) { 3128 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) 3129 dev->stats.rx_length_errors++; 3130 if (status & XMR_FS_FRA_ERR) 3131 dev->stats.rx_frame_errors++; 3132 if (status & XMR_FS_FCS_ERR) 3133 dev->stats.rx_crc_errors++; 3134 } else { 3135 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) 3136 dev->stats.rx_length_errors++; 3137 if (status & GMR_FS_FRAGMENT) 3138 dev->stats.rx_frame_errors++; 3139 if (status & GMR_FS_CRC_ERR) 3140 dev->stats.rx_crc_errors++; 3141 } 3142 3143resubmit: 3144 skge_rx_reuse(e, skge->rx_buf_size); 3145 return NULL; 3146} 3147 3148/* Free all buffers in Tx ring which are no longer owned by device */ 3149static void skge_tx_done(struct net_device *dev) 3150{ 3151 struct skge_port *skge = netdev_priv(dev); 3152 struct skge_ring *ring = &skge->tx_ring; 3153 struct skge_element *e; 3154 unsigned int bytes_compl = 0, pkts_compl = 0; 3155 3156 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 3157 3158 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 3159 u32 control = ((const struct skge_tx_desc *) e->desc)->control; 3160 3161 if (control & BMU_OWN) 3162 break; 3163 3164 skge_tx_unmap(skge->hw->pdev, e, control); 3165 3166 if (control & BMU_EOF) { 3167 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev, 3168 "tx done slot %td\n", 3169 e - skge->tx_ring.start); 3170 3171 pkts_compl++; 3172 bytes_compl += e->skb->len; 3173 3174 dev_consume_skb_any(e->skb); 3175 } 3176 } 3177 netdev_completed_queue(dev, pkts_compl, bytes_compl); 3178 skge->tx_ring.to_clean = e; 3179 3180 /* Can run lockless until we need to synchronize to restart queue. */ 3181 smp_mb(); 3182 3183 if (unlikely(netif_queue_stopped(dev) && 3184 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { 3185 netif_tx_lock(dev); 3186 if (unlikely(netif_queue_stopped(dev) && 3187 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { 3188 netif_wake_queue(dev); 3189 3190 } 3191 netif_tx_unlock(dev); 3192 } 3193} 3194 3195static int skge_poll(struct napi_struct *napi, int budget) 3196{ 3197 struct skge_port *skge = container_of(napi, struct skge_port, napi); 3198 struct net_device *dev = skge->netdev; 3199 struct skge_hw *hw = skge->hw; 3200 struct skge_ring *ring = &skge->rx_ring; 3201 struct skge_element *e; 3202 int work_done = 0; 3203 3204 skge_tx_done(dev); 3205 3206 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 3207 3208 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) { 3209 struct skge_rx_desc *rd = e->desc; 3210 struct sk_buff *skb; 3211 u32 control; 3212 3213 rmb(); 3214 control = rd->control; 3215 if (control & BMU_OWN) 3216 break; 3217 3218 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2); 3219 if (likely(skb)) { 3220 napi_gro_receive(napi, skb); 3221 ++work_done; 3222 } 3223 } 3224 ring->to_clean = e; 3225 3226 /* restart receiver */ 3227 wmb(); 3228 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); 3229 3230 if (work_done < budget && napi_complete_done(napi, work_done)) { 3231 unsigned long flags; 3232 3233 spin_lock_irqsave(&hw->hw_lock, flags); 3234 hw->intr_mask |= napimask[skge->port]; 3235 skge_write32(hw, B0_IMSK, hw->intr_mask); 3236 skge_read32(hw, B0_IMSK); 3237 spin_unlock_irqrestore(&hw->hw_lock, flags); 3238 } 3239 3240 return work_done; 3241} 3242 3243/* Parity errors seem to happen when Genesis is connected to a switch 3244 * with no other ports present. Heartbeat error?? 3245 */ 3246static void skge_mac_parity(struct skge_hw *hw, int port) 3247{ 3248 struct net_device *dev = hw->dev[port]; 3249 3250 ++dev->stats.tx_heartbeat_errors; 3251 3252 if (is_genesis(hw)) 3253 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 3254 MFF_CLR_PERR); 3255 else 3256 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ 3257 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), 3258 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) 3259 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); 3260} 3261 3262static void skge_mac_intr(struct skge_hw *hw, int port) 3263{ 3264 if (is_genesis(hw)) 3265 genesis_mac_intr(hw, port); 3266 else 3267 yukon_mac_intr(hw, port); 3268} 3269 3270/* Handle device specific framing and timeout interrupts */ 3271static void skge_error_irq(struct skge_hw *hw) 3272{ 3273 struct pci_dev *pdev = hw->pdev; 3274 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); 3275 3276 if (is_genesis(hw)) { 3277 /* clear xmac errors */ 3278 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) 3279 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); 3280 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) 3281 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); 3282 } else { 3283 /* Timestamp (unused) overflow */ 3284 if (hwstatus & IS_IRQ_TIST_OV) 3285 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3286 } 3287 3288 if (hwstatus & IS_RAM_RD_PAR) { 3289 dev_err(&pdev->dev, "Ram read data parity error\n"); 3290 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); 3291 } 3292 3293 if (hwstatus & IS_RAM_WR_PAR) { 3294 dev_err(&pdev->dev, "Ram write data parity error\n"); 3295 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); 3296 } 3297 3298 if (hwstatus & IS_M1_PAR_ERR) 3299 skge_mac_parity(hw, 0); 3300 3301 if (hwstatus & IS_M2_PAR_ERR) 3302 skge_mac_parity(hw, 1); 3303 3304 if (hwstatus & IS_R1_PAR_ERR) { 3305 dev_err(&pdev->dev, "%s: receive queue parity error\n", 3306 hw->dev[0]->name); 3307 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); 3308 } 3309 3310 if (hwstatus & IS_R2_PAR_ERR) { 3311 dev_err(&pdev->dev, "%s: receive queue parity error\n", 3312 hw->dev[1]->name); 3313 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); 3314 } 3315 3316 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { 3317 u16 pci_status, pci_cmd; 3318 3319 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 3320 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 3321 3322 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n", 3323 pci_cmd, pci_status); 3324 3325 /* Write the error bits back to clear them. */ 3326 pci_status &= PCI_STATUS_ERROR_BITS; 3327 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3328 pci_write_config_word(pdev, PCI_COMMAND, 3329 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 3330 pci_write_config_word(pdev, PCI_STATUS, pci_status); 3331 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3332 3333 /* if error still set then just ignore it */ 3334 hwstatus = skge_read32(hw, B0_HWE_ISRC); 3335 if (hwstatus & IS_IRQ_STAT) { 3336 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); 3337 hw->intr_mask &= ~IS_HW_ERR; 3338 } 3339 } 3340} 3341 3342/* 3343 * Interrupt from PHY are handled in tasklet (softirq) 3344 * because accessing phy registers requires spin wait which might 3345 * cause excess interrupt latency. 3346 */ 3347static void skge_extirq(struct tasklet_struct *t) 3348{ 3349 struct skge_hw *hw = from_tasklet(hw, t, phy_task); 3350 int port; 3351 3352 for (port = 0; port < hw->ports; port++) { 3353 struct net_device *dev = hw->dev[port]; 3354 3355 if (netif_running(dev)) { 3356 struct skge_port *skge = netdev_priv(dev); 3357 3358 spin_lock(&hw->phy_lock); 3359 if (!is_genesis(hw)) 3360 yukon_phy_intr(skge); 3361 else if (hw->phy_type == SK_PHY_BCOM) 3362 bcom_phy_intr(skge); 3363 spin_unlock(&hw->phy_lock); 3364 } 3365 } 3366 3367 spin_lock_irq(&hw->hw_lock); 3368 hw->intr_mask |= IS_EXT_REG; 3369 skge_write32(hw, B0_IMSK, hw->intr_mask); 3370 skge_read32(hw, B0_IMSK); 3371 spin_unlock_irq(&hw->hw_lock); 3372} 3373 3374static irqreturn_t skge_intr(int irq, void *dev_id) 3375{ 3376 struct skge_hw *hw = dev_id; 3377 u32 status; 3378 int handled = 0; 3379 3380 spin_lock(&hw->hw_lock); 3381 /* Reading this register masks IRQ */ 3382 status = skge_read32(hw, B0_SP_ISRC); 3383 if (status == 0 || status == ~0) 3384 goto out; 3385 3386 handled = 1; 3387 status &= hw->intr_mask; 3388 if (status & IS_EXT_REG) { 3389 hw->intr_mask &= ~IS_EXT_REG; 3390 tasklet_schedule(&hw->phy_task); 3391 } 3392 3393 if (status & (IS_XA1_F|IS_R1_F)) { 3394 struct skge_port *skge = netdev_priv(hw->dev[0]); 3395 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); 3396 napi_schedule(&skge->napi); 3397 } 3398 3399 if (status & IS_PA_TO_TX1) 3400 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); 3401 3402 if (status & IS_PA_TO_RX1) { 3403 ++hw->dev[0]->stats.rx_over_errors; 3404 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); 3405 } 3406 3407 3408 if (status & IS_MAC1) 3409 skge_mac_intr(hw, 0); 3410 3411 if (hw->dev[1]) { 3412 struct skge_port *skge = netdev_priv(hw->dev[1]); 3413 3414 if (status & (IS_XA2_F|IS_R2_F)) { 3415 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); 3416 napi_schedule(&skge->napi); 3417 } 3418 3419 if (status & IS_PA_TO_RX2) { 3420 ++hw->dev[1]->stats.rx_over_errors; 3421 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); 3422 } 3423 3424 if (status & IS_PA_TO_TX2) 3425 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); 3426 3427 if (status & IS_MAC2) 3428 skge_mac_intr(hw, 1); 3429 } 3430 3431 if (status & IS_HW_ERR) 3432 skge_error_irq(hw); 3433out: 3434 skge_write32(hw, B0_IMSK, hw->intr_mask); 3435 skge_read32(hw, B0_IMSK); 3436 spin_unlock(&hw->hw_lock); 3437 3438 return IRQ_RETVAL(handled); 3439} 3440 3441#ifdef CONFIG_NET_POLL_CONTROLLER 3442static void skge_netpoll(struct net_device *dev) 3443{ 3444 struct skge_port *skge = netdev_priv(dev); 3445 3446 disable_irq(dev->irq); 3447 skge_intr(dev->irq, skge->hw); 3448 enable_irq(dev->irq); 3449} 3450#endif 3451 3452static int skge_set_mac_address(struct net_device *dev, void *p) 3453{ 3454 struct skge_port *skge = netdev_priv(dev); 3455 struct skge_hw *hw = skge->hw; 3456 unsigned port = skge->port; 3457 const struct sockaddr *addr = p; 3458 u16 ctrl; 3459 3460 if (!is_valid_ether_addr(addr->sa_data)) 3461 return -EADDRNOTAVAIL; 3462 3463 eth_hw_addr_set(dev, addr->sa_data); 3464 3465 if (!netif_running(dev)) { 3466 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3467 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3468 } else { 3469 /* disable Rx */ 3470 spin_lock_bh(&hw->phy_lock); 3471 ctrl = gma_read16(hw, port, GM_GP_CTRL); 3472 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); 3473 3474 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3475 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3476 3477 if (is_genesis(hw)) 3478 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 3479 else { 3480 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3481 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3482 } 3483 3484 gma_write16(hw, port, GM_GP_CTRL, ctrl); 3485 spin_unlock_bh(&hw->phy_lock); 3486 } 3487 3488 return 0; 3489} 3490 3491static const struct { 3492 u8 id; 3493 const char *name; 3494} skge_chips[] = { 3495 { CHIP_ID_GENESIS, "Genesis" }, 3496 { CHIP_ID_YUKON, "Yukon" }, 3497 { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, 3498 { CHIP_ID_YUKON_LP, "Yukon-LP"}, 3499}; 3500 3501static const char *skge_board_name(const struct skge_hw *hw) 3502{ 3503 int i; 3504 static char buf[16]; 3505 3506 for (i = 0; i < ARRAY_SIZE(skge_chips); i++) 3507 if (skge_chips[i].id == hw->chip_id) 3508 return skge_chips[i].name; 3509 3510 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id); 3511 return buf; 3512} 3513 3514 3515/* 3516 * Setup the board data structure, but don't bring up 3517 * the port(s) 3518 */ 3519static int skge_reset(struct skge_hw *hw) 3520{ 3521 u32 reg; 3522 u16 ctst, pci_status; 3523 u8 t8, mac_cfg, pmd_type; 3524 int i; 3525 3526 ctst = skge_read16(hw, B0_CTST); 3527 3528 /* do a SW reset */ 3529 skge_write8(hw, B0_CTST, CS_RST_SET); 3530 skge_write8(hw, B0_CTST, CS_RST_CLR); 3531 3532 /* clear PCI errors, if any */ 3533 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3534 skge_write8(hw, B2_TST_CTRL2, 0); 3535 3536 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); 3537 pci_write_config_word(hw->pdev, PCI_STATUS, 3538 pci_status | PCI_STATUS_ERROR_BITS); 3539 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3540 skge_write8(hw, B0_CTST, CS_MRST_CLR); 3541 3542 /* restore CLK_RUN bits (for Yukon-Lite) */ 3543 skge_write16(hw, B0_CTST, 3544 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); 3545 3546 hw->chip_id = skge_read8(hw, B2_CHIP_ID); 3547 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; 3548 pmd_type = skge_read8(hw, B2_PMD_TYP); 3549 hw->copper = (pmd_type == 'T' || pmd_type == '1'); 3550 3551 switch (hw->chip_id) { 3552 case CHIP_ID_GENESIS: 3553#ifdef CONFIG_SKGE_GENESIS 3554 switch (hw->phy_type) { 3555 case SK_PHY_XMAC: 3556 hw->phy_addr = PHY_ADDR_XMAC; 3557 break; 3558 case SK_PHY_BCOM: 3559 hw->phy_addr = PHY_ADDR_BCOM; 3560 break; 3561 default: 3562 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", 3563 hw->phy_type); 3564 return -EOPNOTSUPP; 3565 } 3566 break; 3567#else 3568 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n"); 3569 return -EOPNOTSUPP; 3570#endif 3571 3572 case CHIP_ID_YUKON: 3573 case CHIP_ID_YUKON_LITE: 3574 case CHIP_ID_YUKON_LP: 3575 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') 3576 hw->copper = 1; 3577 3578 hw->phy_addr = PHY_ADDR_MARV; 3579 break; 3580 3581 default: 3582 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3583 hw->chip_id); 3584 return -EOPNOTSUPP; 3585 } 3586 3587 mac_cfg = skge_read8(hw, B2_MAC_CFG); 3588 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; 3589 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; 3590 3591 /* read the adapters RAM size */ 3592 t8 = skge_read8(hw, B2_E_0); 3593 if (is_genesis(hw)) { 3594 if (t8 == 3) { 3595 /* special case: 4 x 64k x 36, offset = 0x80000 */ 3596 hw->ram_size = 0x100000; 3597 hw->ram_offset = 0x80000; 3598 } else 3599 hw->ram_size = t8 * 512; 3600 } else if (t8 == 0) 3601 hw->ram_size = 0x20000; 3602 else 3603 hw->ram_size = t8 * 4096; 3604 3605 hw->intr_mask = IS_HW_ERR; 3606 3607 /* Use PHY IRQ for all but fiber based Genesis board */ 3608 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)) 3609 hw->intr_mask |= IS_EXT_REG; 3610 3611 if (is_genesis(hw)) 3612 genesis_init(hw); 3613 else { 3614 /* switch power to VCC (WA for VAUX problem) */ 3615 skge_write8(hw, B0_POWER_CTRL, 3616 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 3617 3618 /* avoid boards with stuck Hardware error bits */ 3619 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && 3620 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { 3621 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); 3622 hw->intr_mask &= ~IS_HW_ERR; 3623 } 3624 3625 /* Clear PHY COMA */ 3626 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3627 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); 3628 reg &= ~PCI_PHY_COMA; 3629 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); 3630 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3631 3632 3633 for (i = 0; i < hw->ports; i++) { 3634 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3635 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3636 } 3637 } 3638 3639 /* turn off hardware timer (unused) */ 3640 skge_write8(hw, B2_TI_CTRL, TIM_STOP); 3641 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3642 skge_write8(hw, B0_LED, LED_STAT_ON); 3643 3644 /* enable the Tx Arbiters */ 3645 for (i = 0; i < hw->ports; i++) 3646 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3647 3648 /* Initialize ram interface */ 3649 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); 3650 3651 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); 3652 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); 3653 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); 3654 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); 3655 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); 3656 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); 3657 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); 3658 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); 3659 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); 3660 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); 3661 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); 3662 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); 3663 3664 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); 3665 3666 /* Set interrupt moderation for Transmit only 3667 * Receive interrupts avoided by NAPI 3668 */ 3669 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); 3670 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); 3671 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 3672 3673 /* Leave irq disabled until first port is brought up. */ 3674 skge_write32(hw, B0_IMSK, 0); 3675 3676 for (i = 0; i < hw->ports; i++) { 3677 if (is_genesis(hw)) 3678 genesis_reset(hw, i); 3679 else 3680 yukon_reset(hw, i); 3681 } 3682 3683 return 0; 3684} 3685 3686 3687#ifdef CONFIG_SKGE_DEBUG 3688 3689static struct dentry *skge_debug; 3690 3691static int skge_debug_show(struct seq_file *seq, void *v) 3692{ 3693 struct net_device *dev = seq->private; 3694 const struct skge_port *skge = netdev_priv(dev); 3695 const struct skge_hw *hw = skge->hw; 3696 const struct skge_element *e; 3697 3698 if (!netif_running(dev)) 3699 return -ENETDOWN; 3700 3701 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), 3702 skge_read32(hw, B0_IMSK)); 3703 3704 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring)); 3705 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 3706 const struct skge_tx_desc *t = e->desc; 3707 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n", 3708 t->control, t->dma_hi, t->dma_lo, t->status, 3709 t->csum_offs, t->csum_write, t->csum_start); 3710 } 3711 3712 seq_puts(seq, "\nRx Ring:\n"); 3713 for (e = skge->rx_ring.to_clean; ; e = e->next) { 3714 const struct skge_rx_desc *r = e->desc; 3715 3716 if (r->control & BMU_OWN) 3717 break; 3718 3719 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n", 3720 r->control, r->dma_hi, r->dma_lo, r->status, 3721 r->timestamp, r->csum1, r->csum1_start); 3722 } 3723 3724 return 0; 3725} 3726DEFINE_SHOW_ATTRIBUTE(skge_debug); 3727 3728/* 3729 * Use network device events to create/remove/rename 3730 * debugfs file entries 3731 */ 3732static int skge_device_event(struct notifier_block *unused, 3733 unsigned long event, void *ptr) 3734{ 3735 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3736 struct skge_port *skge; 3737 3738 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug) 3739 goto done; 3740 3741 skge = netdev_priv(dev); 3742 switch (event) { 3743 case NETDEV_CHANGENAME: 3744 debugfs_change_name(skge->debugfs, "%s", dev->name); 3745 break; 3746 3747 case NETDEV_GOING_DOWN: 3748 debugfs_remove(skge->debugfs); 3749 skge->debugfs = NULL; 3750 break; 3751 3752 case NETDEV_UP: 3753 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug, 3754 dev, &skge_debug_fops); 3755 break; 3756 } 3757 3758done: 3759 return NOTIFY_DONE; 3760} 3761 3762static struct notifier_block skge_notifier = { 3763 .notifier_call = skge_device_event, 3764}; 3765 3766 3767static __init void skge_debug_init(void) 3768{ 3769 skge_debug = debugfs_create_dir("skge", NULL); 3770 3771 register_netdevice_notifier(&skge_notifier); 3772} 3773 3774static __exit void skge_debug_cleanup(void) 3775{ 3776 if (skge_debug) { 3777 unregister_netdevice_notifier(&skge_notifier); 3778 debugfs_remove(skge_debug); 3779 skge_debug = NULL; 3780 } 3781} 3782 3783#else 3784#define skge_debug_init() 3785#define skge_debug_cleanup() 3786#endif 3787 3788static const struct net_device_ops skge_netdev_ops = { 3789 .ndo_open = skge_up, 3790 .ndo_stop = skge_down, 3791 .ndo_start_xmit = skge_xmit_frame, 3792 .ndo_eth_ioctl = skge_ioctl, 3793 .ndo_get_stats = skge_get_stats, 3794 .ndo_tx_timeout = skge_tx_timeout, 3795 .ndo_change_mtu = skge_change_mtu, 3796 .ndo_validate_addr = eth_validate_addr, 3797 .ndo_set_rx_mode = skge_set_multicast, 3798 .ndo_set_mac_address = skge_set_mac_address, 3799#ifdef CONFIG_NET_POLL_CONTROLLER 3800 .ndo_poll_controller = skge_netpoll, 3801#endif 3802}; 3803 3804 3805/* Initialize network device */ 3806static struct net_device *skge_devinit(struct skge_hw *hw, int port, 3807 int highmem) 3808{ 3809 struct skge_port *skge; 3810 struct net_device *dev = alloc_etherdev(sizeof(*skge)); 3811 u8 addr[ETH_ALEN]; 3812 3813 if (!dev) 3814 return NULL; 3815 3816 SET_NETDEV_DEV(dev, &hw->pdev->dev); 3817 dev->netdev_ops = &skge_netdev_ops; 3818 dev->ethtool_ops = &skge_ethtool_ops; 3819 dev->watchdog_timeo = TX_WATCHDOG; 3820 dev->irq = hw->pdev->irq; 3821 3822 /* MTU range: 60 - 9000 */ 3823 dev->min_mtu = ETH_ZLEN; 3824 dev->max_mtu = ETH_JUMBO_MTU; 3825 3826 if (highmem) 3827 dev->features |= NETIF_F_HIGHDMA; 3828 3829 skge = netdev_priv(dev); 3830 netif_napi_add(dev, &skge->napi, skge_poll); 3831 skge->netdev = dev; 3832 skge->hw = hw; 3833 skge->msg_enable = netif_msg_init(debug, default_msg); 3834 3835 skge->tx_ring.count = DEFAULT_TX_RING_SIZE; 3836 skge->rx_ring.count = DEFAULT_RX_RING_SIZE; 3837 3838 /* Auto speed and flow control */ 3839 skge->autoneg = AUTONEG_ENABLE; 3840 skge->flow_control = FLOW_MODE_SYM_OR_REM; 3841 skge->duplex = -1; 3842 skge->speed = -1; 3843 skge->advertising = skge_supported_modes(hw); 3844 3845 if (device_can_wakeup(&hw->pdev->dev)) { 3846 skge->wol = wol_supported(hw) & WAKE_MAGIC; 3847 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); 3848 } 3849 3850 hw->dev[port] = dev; 3851 3852 skge->port = port; 3853 3854 /* Only used for Genesis XMAC */ 3855 if (is_genesis(hw)) 3856 timer_setup(&skge->link_timer, xm_link_timer, 0); 3857 else { 3858 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 3859 NETIF_F_RXCSUM; 3860 dev->features |= dev->hw_features; 3861 } 3862 3863 /* read the mac address */ 3864 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); 3865 eth_hw_addr_set(dev, addr); 3866 3867 return dev; 3868} 3869 3870static void skge_show_addr(struct net_device *dev) 3871{ 3872 const struct skge_port *skge = netdev_priv(dev); 3873 3874 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr); 3875} 3876 3877static int only_32bit_dma; 3878 3879static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3880{ 3881 struct net_device *dev, *dev1; 3882 struct skge_hw *hw; 3883 int err, using_dac = 0; 3884 3885 err = pci_enable_device(pdev); 3886 if (err) { 3887 dev_err(&pdev->dev, "cannot enable PCI device\n"); 3888 goto err_out; 3889 } 3890 3891 err = pci_request_regions(pdev, DRV_NAME); 3892 if (err) { 3893 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 3894 goto err_out_disable_pdev; 3895 } 3896 3897 pci_set_master(pdev); 3898 3899 if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 3900 using_dac = 1; 3901 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 3902 } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) { 3903 using_dac = 0; 3904 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 3905 } 3906 3907 if (err) { 3908 dev_err(&pdev->dev, "no usable DMA configuration\n"); 3909 goto err_out_free_regions; 3910 } 3911 3912#ifdef __BIG_ENDIAN 3913 /* byte swap descriptors in hardware */ 3914 { 3915 u32 reg; 3916 3917 pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 3918 reg |= PCI_REV_DESC; 3919 pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 3920 } 3921#endif 3922 3923 err = -ENOMEM; 3924 /* space for skge@pci:0000:04:00.0 */ 3925 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 3926 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 3927 if (!hw) 3928 goto err_out_free_regions; 3929 3930 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 3931 3932 hw->pdev = pdev; 3933 spin_lock_init(&hw->hw_lock); 3934 spin_lock_init(&hw->phy_lock); 3935 tasklet_setup(&hw->phy_task, skge_extirq); 3936 3937 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000); 3938 if (!hw->regs) { 3939 dev_err(&pdev->dev, "cannot map device registers\n"); 3940 goto err_out_free_hw; 3941 } 3942 3943 err = skge_reset(hw); 3944 if (err) 3945 goto err_out_iounmap; 3946 3947 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n", 3948 DRV_VERSION, 3949 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, 3950 skge_board_name(hw), hw->chip_rev); 3951 3952 dev = skge_devinit(hw, 0, using_dac); 3953 if (!dev) { 3954 err = -ENOMEM; 3955 goto err_out_led_off; 3956 } 3957 3958 /* Some motherboards are broken and has zero in ROM. */ 3959 if (!is_valid_ether_addr(dev->dev_addr)) 3960 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n"); 3961 3962 err = register_netdev(dev); 3963 if (err) { 3964 dev_err(&pdev->dev, "cannot register net device\n"); 3965 goto err_out_free_netdev; 3966 } 3967 3968 skge_show_addr(dev); 3969 3970 if (hw->ports > 1) { 3971 dev1 = skge_devinit(hw, 1, using_dac); 3972 if (!dev1) { 3973 err = -ENOMEM; 3974 goto err_out_unregister; 3975 } 3976 3977 err = register_netdev(dev1); 3978 if (err) { 3979 dev_err(&pdev->dev, "cannot register second net device\n"); 3980 goto err_out_free_dev1; 3981 } 3982 3983 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, 3984 hw->irq_name, hw); 3985 if (err) { 3986 dev_err(&pdev->dev, "cannot assign irq %d\n", 3987 pdev->irq); 3988 goto err_out_unregister_dev1; 3989 } 3990 3991 skge_show_addr(dev1); 3992 } 3993 pci_set_drvdata(pdev, hw); 3994 3995 return 0; 3996 3997err_out_unregister_dev1: 3998 unregister_netdev(dev1); 3999err_out_free_dev1: 4000 free_netdev(dev1); 4001err_out_unregister: 4002 unregister_netdev(dev); 4003err_out_free_netdev: 4004 free_netdev(dev); 4005err_out_led_off: 4006 skge_write16(hw, B0_LED, LED_STAT_OFF); 4007err_out_iounmap: 4008 iounmap(hw->regs); 4009err_out_free_hw: 4010 kfree(hw); 4011err_out_free_regions: 4012 pci_release_regions(pdev); 4013err_out_disable_pdev: 4014 pci_disable_device(pdev); 4015err_out: 4016 return err; 4017} 4018 4019static void skge_remove(struct pci_dev *pdev) 4020{ 4021 struct skge_hw *hw = pci_get_drvdata(pdev); 4022 struct net_device *dev0, *dev1; 4023 4024 if (!hw) 4025 return; 4026 4027 dev1 = hw->dev[1]; 4028 if (dev1) 4029 unregister_netdev(dev1); 4030 dev0 = hw->dev[0]; 4031 unregister_netdev(dev0); 4032 4033 tasklet_kill(&hw->phy_task); 4034 4035 spin_lock_irq(&hw->hw_lock); 4036 hw->intr_mask = 0; 4037 4038 if (hw->ports > 1) { 4039 skge_write32(hw, B0_IMSK, 0); 4040 skge_read32(hw, B0_IMSK); 4041 } 4042 spin_unlock_irq(&hw->hw_lock); 4043 4044 skge_write16(hw, B0_LED, LED_STAT_OFF); 4045 skge_write8(hw, B0_CTST, CS_RST_SET); 4046 4047 if (hw->ports > 1) 4048 free_irq(pdev->irq, hw); 4049 pci_release_regions(pdev); 4050 pci_disable_device(pdev); 4051 if (dev1) 4052 free_netdev(dev1); 4053 free_netdev(dev0); 4054 4055 iounmap(hw->regs); 4056 kfree(hw); 4057} 4058 4059#ifdef CONFIG_PM_SLEEP 4060static int skge_suspend(struct device *dev) 4061{ 4062 struct skge_hw *hw = dev_get_drvdata(dev); 4063 int i; 4064 4065 if (!hw) 4066 return 0; 4067 4068 for (i = 0; i < hw->ports; i++) { 4069 struct net_device *dev = hw->dev[i]; 4070 struct skge_port *skge = netdev_priv(dev); 4071 4072 if (netif_running(dev)) 4073 skge_down(dev); 4074 4075 if (skge->wol) 4076 skge_wol_init(skge); 4077 } 4078 4079 skge_write32(hw, B0_IMSK, 0); 4080 4081 return 0; 4082} 4083 4084static int skge_resume(struct device *dev) 4085{ 4086 struct skge_hw *hw = dev_get_drvdata(dev); 4087 int i, err; 4088 4089 if (!hw) 4090 return 0; 4091 4092 err = skge_reset(hw); 4093 if (err) 4094 goto out; 4095 4096 for (i = 0; i < hw->ports; i++) { 4097 struct net_device *dev = hw->dev[i]; 4098 4099 if (netif_running(dev)) { 4100 err = skge_up(dev); 4101 4102 if (err) { 4103 netdev_err(dev, "could not up: %d\n", err); 4104 dev_close(dev); 4105 goto out; 4106 } 4107 } 4108 } 4109out: 4110 return err; 4111} 4112 4113static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume); 4114#define SKGE_PM_OPS (&skge_pm_ops) 4115 4116#else 4117 4118#define SKGE_PM_OPS NULL 4119#endif /* CONFIG_PM_SLEEP */ 4120 4121static void skge_shutdown(struct pci_dev *pdev) 4122{ 4123 struct skge_hw *hw = pci_get_drvdata(pdev); 4124 int i; 4125 4126 if (!hw) 4127 return; 4128 4129 for (i = 0; i < hw->ports; i++) { 4130 struct net_device *dev = hw->dev[i]; 4131 struct skge_port *skge = netdev_priv(dev); 4132 4133 if (skge->wol) 4134 skge_wol_init(skge); 4135 } 4136 4137 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 4138 pci_set_power_state(pdev, PCI_D3hot); 4139} 4140 4141static struct pci_driver skge_driver = { 4142 .name = DRV_NAME, 4143 .id_table = skge_id_table, 4144 .probe = skge_probe, 4145 .remove = skge_remove, 4146 .shutdown = skge_shutdown, 4147 .driver.pm = SKGE_PM_OPS, 4148}; 4149 4150static const struct dmi_system_id skge_32bit_dma_boards[] = { 4151 { 4152 .ident = "Gigabyte nForce boards", 4153 .matches = { 4154 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"), 4155 DMI_MATCH(DMI_BOARD_NAME, "nForce"), 4156 }, 4157 }, 4158 { 4159 .ident = "ASUS P5NSLI", 4160 .matches = { 4161 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 4162 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI") 4163 }, 4164 }, 4165 { 4166 .ident = "FUJITSU SIEMENS A8NE-FM", 4167 .matches = { 4168 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."), 4169 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM") 4170 }, 4171 }, 4172 {} 4173}; 4174 4175static int __init skge_init_module(void) 4176{ 4177 if (dmi_check_system(skge_32bit_dma_boards)) 4178 only_32bit_dma = 1; 4179 skge_debug_init(); 4180 return pci_register_driver(&skge_driver); 4181} 4182 4183static void __exit skge_cleanup_module(void) 4184{ 4185 pci_unregister_driver(&skge_driver); 4186 skge_debug_cleanup(); 4187} 4188 4189module_init(skge_init_module); 4190module_exit(skge_cleanup_module);
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