otx2_reg.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Marvell RVU Ethernet driver
  3 *
  4 * Copyright (C) 2020 Marvell.
  5 *
  6 */
  7
  8#ifndef OTX2_REG_H
  9#define OTX2_REG_H
 10
 11#include <rvu_struct.h>
 12
 13/* RVU PF registers */
 14#define	RVU_PF_VFX_PFVF_MBOX0		    (0x00000)
 15#define	RVU_PF_VFX_PFVF_MBOX1		    (0x00008)
 16#define RVU_PF_VFX_PFVF_MBOXX(a, b)         (0x0 | (a) << 12 | (b) << 3)
 17#define RVU_PF_VF_BAR4_ADDR                 (0x10)
 18#define RVU_PF_BLOCK_ADDRX_DISC(a)          (0x200 | (a) << 3)
 19#define RVU_PF_VFME_STATUSX(a)              (0x800 | (a) << 3)
 20#define RVU_PF_VFTRPENDX(a)                 (0x820 | (a) << 3)
 21#define RVU_PF_VFTRPEND_W1SX(a)             (0x840 | (a) << 3)
 22#define RVU_PF_VFPF_MBOX_INTX(a)            (0x880 | (a) << 3)
 23#define RVU_PF_VFPF_MBOX_INT_W1SX(a)        (0x8A0 | (a) << 3)
 24#define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a)    (0x8C0 | (a) << 3)
 25#define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a)    (0x8E0 | (a) << 3)
 26#define RVU_PF_VFFLR_INTX(a)                (0x900 | (a) << 3)
 27#define RVU_PF_VFFLR_INT_W1SX(a)            (0x920 | (a) << 3)
 28#define RVU_PF_VFFLR_INT_ENA_W1SX(a)        (0x940 | (a) << 3)
 29#define RVU_PF_VFFLR_INT_ENA_W1CX(a)        (0x960 | (a) << 3)
 30#define RVU_PF_VFME_INTX(a)                 (0x980 | (a) << 3)
 31#define RVU_PF_VFME_INT_W1SX(a)             (0x9A0 | (a) << 3)
 32#define RVU_PF_VFME_INT_ENA_W1SX(a)         (0x9C0 | (a) << 3)
 33#define RVU_PF_VFME_INT_ENA_W1CX(a)         (0x9E0 | (a) << 3)
 34#define RVU_PF_PFAF_MBOX0                   (0xC00)
 35#define RVU_PF_PFAF_MBOX1                   (0xC08)
 36#define RVU_PF_PFAF_MBOXX(a)                (0xC00 | (a) << 3)
 37#define RVU_PF_INT                          (0xc20)
 38#define RVU_PF_INT_W1S                      (0xc28)
 39#define RVU_PF_INT_ENA_W1S                  (0xc30)
 40#define RVU_PF_INT_ENA_W1C                  (0xc38)
 41#define RVU_PF_MSIX_VECX_ADDR(a)            (0x000 | (a) << 4)
 42#define RVU_PF_MSIX_VECX_CTL(a)             (0x008 | (a) << 4)
 43#define RVU_PF_MSIX_PBAX(a)                 (0xF0000 | (a) << 3)
 44#define RVU_PF_VF_MBOX_ADDR                 (0xC40)
 45#define RVU_PF_LMTLINE_ADDR                 (0xC48)
 46
 47#define RVU_MBOX_PF_VFX_PFVF_TRIGX(a)		(0x2000 | (a) << 3)
 48#define RVU_MBOX_PF_VFPF_INTX(a)		(0x1000 | (a) << 3)
 49#define RVU_MBOX_PF_VFPF_INT_W1SX(a)		(0x1020 | (a) << 3)
 50#define RVU_MBOX_PF_VFPF_INT_ENA_W1SX(a)	(0x1040 | (a) << 3)
 51#define RVU_MBOX_PF_VFPF_INT_ENA_W1CX(a)	(0x1060 | (a) << 3)
 52
 53#define RVU_MBOX_PF_VFPF1_INTX(a)		(0x1080 | (a) << 3)
 54#define RVU_MBOX_PF_VFPF1_INT_W1SX(a)		(0x10a0 | (a) << 3)
 55#define RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(a)	(0x10c0 | (a) << 3)
 56#define RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(a)	(0x10e0 | (a) << 3)
 57
 58/* RVU VF registers */
 59#define	RVU_VF_VFPF_MBOX0		    (0x00000)
 60#define	RVU_VF_VFPF_MBOX1		    (0x00008)
 61#define	RVU_VF_VFPF_MBOXX(a)		    (0x00 | (a) << 3)
 62#define	RVU_VF_INT			    (0x20)
 63#define	RVU_VF_INT_W1S			    (0x28)
 64#define	RVU_VF_INT_ENA_W1S		    (0x30)
 65#define	RVU_VF_INT_ENA_W1C		    (0x38)
 66#define	RVU_VF_BLOCK_ADDRX_DISC(a)	    (0x200 | (a) << 3)
 67#define	RVU_VF_MSIX_VECX_ADDR(a)	    (0x000 | (a) << 4)
 68#define	RVU_VF_MSIX_VECX_CTL(a)		    (0x008 | (a) << 4)
 69#define	RVU_VF_MSIX_PBAX(a)		    (0xF0000 | (a) << 3)
 70#define RVU_VF_MBOX_REGION                  (0xC0000)
 71
 72/* CN20K RVU_MBOX_E: RVU PF/VF MBOX Address Range Enumeration */
 73#define RVU_MBOX_AF_PFX_ADDR(a)             (0x5000 | (a) << 4)
 74#define RVU_PFX_FUNC_PFAF_MBOX		    (0x80000)
 75#define RVU_PFX_FUNCX_VFAF_MBOX		    (0x40000)
 76
 77#define RVU_FUNC_BLKADDR_SHIFT		20
 78#define RVU_FUNC_BLKADDR_MASK		0x1FULL
 79
 80/* NPA LF registers */
 81#define NPA_LFBASE			(BLKTYPE_NPA << RVU_FUNC_BLKADDR_SHIFT)
 82#define NPA_LF_AURA_OP_ALLOCX(a)	(NPA_LFBASE | 0x10 | (a) << 3)
 83#define NPA_LF_AURA_OP_FREE0            (NPA_LFBASE | 0x20)
 84#define NPA_LF_AURA_OP_FREE1            (NPA_LFBASE | 0x28)
 85#define NPA_LF_AURA_OP_CNT              (NPA_LFBASE | 0x30)
 86#define NPA_LF_AURA_OP_LIMIT            (NPA_LFBASE | 0x50)
 87#define NPA_LF_AURA_OP_INT              (NPA_LFBASE | 0x60)
 88#define NPA_LF_AURA_OP_THRESH           (NPA_LFBASE | 0x70)
 89#define NPA_LF_POOL_OP_PC               (NPA_LFBASE | 0x100)
 90#define NPA_LF_POOL_OP_AVAILABLE        (NPA_LFBASE | 0x110)
 91#define NPA_LF_POOL_OP_PTR_START0       (NPA_LFBASE | 0x120)
 92#define NPA_LF_POOL_OP_PTR_START1       (NPA_LFBASE | 0x128)
 93#define NPA_LF_POOL_OP_PTR_END0         (NPA_LFBASE | 0x130)
 94#define NPA_LF_POOL_OP_PTR_END1         (NPA_LFBASE | 0x138)
 95#define NPA_LF_POOL_OP_INT              (NPA_LFBASE | 0x160)
 96#define NPA_LF_POOL_OP_THRESH           (NPA_LFBASE | 0x170)
 97#define NPA_LF_ERR_INT                  (NPA_LFBASE | 0x200)
 98#define NPA_LF_ERR_INT_W1S              (NPA_LFBASE | 0x208)
 99#define NPA_LF_ERR_INT_ENA_W1C          (NPA_LFBASE | 0x210)
100#define NPA_LF_ERR_INT_ENA_W1S          (NPA_LFBASE | 0x218)
101#define NPA_LF_RAS                      (NPA_LFBASE | 0x220)
102#define NPA_LF_RAS_W1S                  (NPA_LFBASE | 0x228)
103#define NPA_LF_RAS_ENA_W1C              (NPA_LFBASE | 0x230)
104#define NPA_LF_RAS_ENA_W1S              (NPA_LFBASE | 0x238)
105#define NPA_LF_QINTX_CNT(a)             (NPA_LFBASE | 0x300 | (a) << 12)
106#define NPA_LF_QINTX_INT(a)             (NPA_LFBASE | 0x310 | (a) << 12)
107#define NPA_LF_QINTX_INT_W1S(a)         (NPA_LFBASE | 0x318 | (a) << 12)
108#define NPA_LF_QINTX_ENA_W1S(a)         (NPA_LFBASE | 0x320 | (a) << 12)
109#define NPA_LF_QINTX_ENA_W1C(a)         (NPA_LFBASE | 0x330 | (a) << 12)
110#define NPA_LF_AURA_BATCH_FREE0         (NPA_LFBASE | 0x400)
111
112/* NIX LF registers */
113#define	NIX_LFBASE			(BLKTYPE_NIX << RVU_FUNC_BLKADDR_SHIFT)
114#define	NIX_LF_RX_SECRETX(a)		(NIX_LFBASE | 0x0 | (a) << 3)
115#define	NIX_LF_CFG			(NIX_LFBASE | 0x100)
116#define	NIX_LF_GINT			(NIX_LFBASE | 0x200)
117#define	NIX_LF_GINT_W1S			(NIX_LFBASE | 0x208)
118#define	NIX_LF_GINT_ENA_W1C		(NIX_LFBASE | 0x210)
119#define	NIX_LF_GINT_ENA_W1S		(NIX_LFBASE | 0x218)
120#define	NIX_LF_ERR_INT			(NIX_LFBASE | 0x220)
121#define	NIX_LF_ERR_INT_W1S		(NIX_LFBASE | 0x228)
122#define	NIX_LF_ERR_INT_ENA_W1C		(NIX_LFBASE | 0x230)
123#define	NIX_LF_ERR_INT_ENA_W1S		(NIX_LFBASE | 0x238)
124#define	NIX_LF_RAS			(NIX_LFBASE | 0x240)
125#define	NIX_LF_RAS_W1S			(NIX_LFBASE | 0x248)
126#define	NIX_LF_RAS_ENA_W1C		(NIX_LFBASE | 0x250)
127#define	NIX_LF_RAS_ENA_W1S		(NIX_LFBASE | 0x258)
128#define	NIX_LF_SQ_OP_ERR_DBG		(NIX_LFBASE | 0x260)
129#define	NIX_LF_MNQ_ERR_DBG		(NIX_LFBASE | 0x270)
130#define	NIX_LF_SEND_ERR_DBG		(NIX_LFBASE | 0x280)
131#define	NIX_LF_TX_STATX(a)		(NIX_LFBASE | 0x300 | (a) << 3)
132#define	NIX_LF_RX_STATX(a)		(NIX_LFBASE | 0x400 | (a) << 3)
133#define	NIX_LF_OP_SENDX(a)		(NIX_LFBASE | 0x800 | (a) << 3)
134#define	NIX_LF_RQ_OP_INT		(NIX_LFBASE | 0x900)
135#define	NIX_LF_RQ_OP_OCTS		(NIX_LFBASE | 0x910)
136#define	NIX_LF_RQ_OP_PKTS		(NIX_LFBASE | 0x920)
137#define	NIX_LF_OP_IPSEC_DYNO_CN		(NIX_LFBASE | 0x980)
138#define	NIX_LF_SQ_OP_INT		(NIX_LFBASE | 0xa00)
139#define	NIX_LF_SQ_OP_OCTS		(NIX_LFBASE | 0xa10)
140#define	NIX_LF_SQ_OP_PKTS		(NIX_LFBASE | 0xa20)
141#define	NIX_LF_SQ_OP_STATUS		(NIX_LFBASE | 0xa30)
142#define	NIX_LF_CQ_OP_INT		(NIX_LFBASE | 0xb00)
143#define	NIX_LF_CQ_OP_DOOR		(NIX_LFBASE | 0xb30)
144#define	NIX_LF_CQ_OP_STATUS		(NIX_LFBASE | 0xb40)
145#define	NIX_LF_QINTX_CNT(a)		(NIX_LFBASE | 0xC00 | (a) << 12)
146#define	NIX_LF_QINTX_INT(a)		(NIX_LFBASE | 0xC10 | (a) << 12)
147#define	NIX_LF_QINTX_INT_W1S(a)		(NIX_LFBASE | 0xC18 | (a) << 12)
148#define	NIX_LF_QINTX_ENA_W1S(a)		(NIX_LFBASE | 0xC20 | (a) << 12)
149#define	NIX_LF_QINTX_ENA_W1C(a)		(NIX_LFBASE | 0xC30 | (a) << 12)
150#define	NIX_LF_CINTX_CNT(a)		(NIX_LFBASE | 0xD00 | (a) << 12)
151#define	NIX_LF_CINTX_WAIT(a)		(NIX_LFBASE | 0xD10 | (a) << 12)
152#define	NIX_LF_CINTX_INT(a)		(NIX_LFBASE | 0xD20 | (a) << 12)
153#define	NIX_LF_CINTX_INT_W1S(a)		(NIX_LFBASE | 0xD30 | (a) << 12)
154#define	NIX_LF_CINTX_ENA_W1S(a)		(NIX_LFBASE | 0xD40 | (a) << 12)
155#define	NIX_LF_CINTX_ENA_W1C(a)		(NIX_LFBASE | 0xD50 | (a) << 12)
156
157/* LMT LF registers */
158#define LMT_LFBASE			BIT_ULL(RVU_FUNC_BLKADDR_SHIFT)
159#define LMT_LF_LMTLINEX(a)		(LMT_LFBASE | 0x000 | (a) << 12)
160#define LMT_LF_LMTCANCEL		(LMT_LFBASE | 0x400)
161
162/* CN20K registers */
163#define RVU_PF_DISC			(0x0)
164
165#endif /* OTX2_REG_H */