otx2_common.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Marvell RVU Ethernet driver
   3 *
   4 * Copyright (C) 2020 Marvell.
   5 *
   6 */
   7
   8#include <linux/interrupt.h>
   9#include <linux/pci.h>
  10#include <net/page_pool/helpers.h>
  11#include <net/tso.h>
  12#include <linux/bitfield.h>
  13#include <linux/dcbnl.h>
  14#include <net/xfrm.h>
  15
  16#include "otx2_reg.h"
  17#include "otx2_common.h"
  18#include "otx2_struct.h"
  19#include "cn10k.h"
  20#include "otx2_xsk.h"
  21
  22static bool otx2_is_pfc_enabled(struct otx2_nic *pfvf)
  23{
  24	return IS_ENABLED(CONFIG_DCB) && !!pfvf->pfc_en;
  25}
  26
  27static void otx2_nix_rq_op_stats(struct queue_stats *stats,
  28				 struct otx2_nic *pfvf, int qidx)
  29{
  30	u64 incr = (u64)qidx << 32;
  31	void __iomem *ptr;
  32
  33	ptr = otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
  34	stats->bytes = otx2_atomic64_add(incr, ptr);
  35
  36	ptr = otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
  37	stats->pkts = otx2_atomic64_add(incr, ptr);
  38}
  39
  40static void otx2_nix_sq_op_stats(struct queue_stats *stats,
  41				 struct otx2_nic *pfvf, int qidx)
  42{
  43	u64 incr = (u64)qidx << 32;
  44	void __iomem *ptr;
  45
  46	ptr = otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
  47	stats->bytes = otx2_atomic64_add(incr, ptr);
  48
  49	ptr = otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
  50	stats->pkts = otx2_atomic64_add(incr, ptr);
  51}
  52
  53void otx2_update_lmac_stats(struct otx2_nic *pfvf)
  54{
  55	struct msg_req *req;
  56
  57	if (!netif_running(pfvf->netdev))
  58		return;
  59
  60	mutex_lock(&pfvf->mbox.lock);
  61	req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
  62	if (!req) {
  63		mutex_unlock(&pfvf->mbox.lock);
  64		return;
  65	}
  66
  67	otx2_sync_mbox_msg(&pfvf->mbox);
  68	mutex_unlock(&pfvf->mbox.lock);
  69}
  70
  71void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
  72{
  73	struct msg_req *req;
  74
  75	if (!netif_running(pfvf->netdev))
  76		return;
  77	mutex_lock(&pfvf->mbox.lock);
  78	req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
  79	if (req)
  80		otx2_sync_mbox_msg(&pfvf->mbox);
  81	mutex_unlock(&pfvf->mbox.lock);
  82}
  83
  84int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
  85{
  86	struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
  87
  88	if (!pfvf->qset.rq)
  89		return 0;
  90
  91	otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
  92	return 1;
  93}
  94EXPORT_SYMBOL(otx2_update_rq_stats);
  95
  96int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
  97{
  98	struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
  99
 100	if (!pfvf->qset.sq)
 101		return 0;
 102
 103	if (qidx >= pfvf->hw.non_qos_queues) {
 104		if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap))
 105			return 0;
 106	}
 107
 108	otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
 109	return 1;
 110}
 111EXPORT_SYMBOL(otx2_update_sq_stats);
 112
 113void otx2_get_dev_stats(struct otx2_nic *pfvf)
 114{
 115	struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
 116
 117	dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
 118	dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP);
 119	dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST);
 120	dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST);
 121	dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST);
 122	dev_stats->rx_frames = dev_stats->rx_bcast_frames +
 123			       dev_stats->rx_mcast_frames +
 124			       dev_stats->rx_ucast_frames;
 125
 126	dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
 127	dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP) +
 128			       (unsigned long)atomic_long_read(&dev_stats->tx_discards);
 129
 130	dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST);
 131	dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST);
 132	dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST);
 133	dev_stats->tx_frames = dev_stats->tx_bcast_frames +
 134			       dev_stats->tx_mcast_frames +
 135			       dev_stats->tx_ucast_frames;
 136}
 137
 138void otx2_get_stats64(struct net_device *netdev,
 139		      struct rtnl_link_stats64 *stats)
 140{
 141	struct otx2_nic *pfvf = netdev_priv(netdev);
 142	struct otx2_dev_stats *dev_stats;
 143
 144	otx2_get_dev_stats(pfvf);
 145
 146	dev_stats = &pfvf->hw.dev_stats;
 147	stats->rx_bytes = dev_stats->rx_bytes;
 148	stats->rx_packets = dev_stats->rx_frames;
 149	stats->rx_dropped = dev_stats->rx_drops;
 150	stats->multicast = dev_stats->rx_mcast_frames;
 151
 152	stats->tx_bytes = dev_stats->tx_bytes;
 153	stats->tx_packets = dev_stats->tx_frames;
 154	stats->tx_dropped = dev_stats->tx_drops;
 155}
 156EXPORT_SYMBOL(otx2_get_stats64);
 157
 158/* Sync MAC address with RVU AF */
 159static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
 160{
 161	struct nix_set_mac_addr *req;
 162	int err;
 163
 164	mutex_lock(&pfvf->mbox.lock);
 165	req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
 166	if (!req) {
 167		mutex_unlock(&pfvf->mbox.lock);
 168		return -ENOMEM;
 169	}
 170
 171	ether_addr_copy(req->mac_addr, mac);
 172
 173	err = otx2_sync_mbox_msg(&pfvf->mbox);
 174	mutex_unlock(&pfvf->mbox.lock);
 175	return err;
 176}
 177
 178static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
 179				struct net_device *netdev)
 180{
 181	struct nix_get_mac_addr_rsp *rsp;
 182	struct mbox_msghdr *msghdr;
 183	struct msg_req *req;
 184	int err;
 185
 186	mutex_lock(&pfvf->mbox.lock);
 187	req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
 188	if (!req) {
 189		mutex_unlock(&pfvf->mbox.lock);
 190		return -ENOMEM;
 191	}
 192
 193	err = otx2_sync_mbox_msg(&pfvf->mbox);
 194	if (err) {
 195		mutex_unlock(&pfvf->mbox.lock);
 196		return err;
 197	}
 198
 199	msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
 200	if (IS_ERR(msghdr)) {
 201		mutex_unlock(&pfvf->mbox.lock);
 202		return PTR_ERR(msghdr);
 203	}
 204	rsp = (struct nix_get_mac_addr_rsp *)msghdr;
 205	eth_hw_addr_set(netdev, rsp->mac_addr);
 206	mutex_unlock(&pfvf->mbox.lock);
 207
 208	return 0;
 209}
 210
 211int otx2_set_mac_address(struct net_device *netdev, void *p)
 212{
 213	struct otx2_nic *pfvf = netdev_priv(netdev);
 214	struct sockaddr *addr = p;
 215
 216	if (!is_valid_ether_addr(addr->sa_data))
 217		return -EADDRNOTAVAIL;
 218
 219	if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
 220		eth_hw_addr_set(netdev, addr->sa_data);
 221		/* update dmac field in vlan offload rule */
 222		if (netif_running(netdev) &&
 223		    pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
 224			otx2_install_rxvlan_offload_flow(pfvf);
 225		/* update dmac address in ntuple and DMAC filter list */
 226		if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
 227			otx2_dmacflt_update_pfmac_flow(pfvf);
 228	} else {
 229		return -EPERM;
 230	}
 231
 232	return 0;
 233}
 234EXPORT_SYMBOL(otx2_set_mac_address);
 235
 236int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
 237{
 238	struct nix_frs_cfg *req;
 239	u16 maxlen;
 240	int err;
 241
 242	maxlen = pfvf->hw.max_mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
 243
 244	mutex_lock(&pfvf->mbox.lock);
 245	req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
 246	if (!req) {
 247		mutex_unlock(&pfvf->mbox.lock);
 248		return -ENOMEM;
 249	}
 250
 251	req->maxlen = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
 252
 253	/* Use max receive length supported by hardware for loopback devices */
 254	if (is_otx2_lbkvf(pfvf->pdev))
 255		req->maxlen = maxlen;
 256
 257	err = otx2_sync_mbox_msg(&pfvf->mbox);
 258	mutex_unlock(&pfvf->mbox.lock);
 259	return err;
 260}
 261EXPORT_SYMBOL(otx2_hw_set_mtu);
 262
 263int otx2_config_pause_frm(struct otx2_nic *pfvf)
 264{
 265	struct cgx_pause_frm_cfg *req;
 266	int err;
 267
 268	if (is_otx2_lbkvf(pfvf->pdev) || is_otx2_sdp_rep(pfvf->pdev))
 269		return 0;
 270
 271	mutex_lock(&pfvf->mbox.lock);
 272	req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
 273	if (!req) {
 274		err = -ENOMEM;
 275		goto unlock;
 276	}
 277
 278	req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
 279	req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
 280	req->set = 1;
 281
 282	err = otx2_sync_mbox_msg(&pfvf->mbox);
 283unlock:
 284	mutex_unlock(&pfvf->mbox.lock);
 285	return err;
 286}
 287EXPORT_SYMBOL(otx2_config_pause_frm);
 288
 289int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
 290{
 291	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
 292	struct nix_rss_flowkey_cfg_rsp *rsp;
 293	struct nix_rss_flowkey_cfg *req;
 294	int err;
 295
 296	mutex_lock(&pfvf->mbox.lock);
 297	req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
 298	if (!req) {
 299		mutex_unlock(&pfvf->mbox.lock);
 300		return -ENOMEM;
 301	}
 302	req->mcam_index = -1; /* Default or reserved index */
 303	req->flowkey_cfg = rss->flowkey_cfg;
 304	req->group = DEFAULT_RSS_CONTEXT_GROUP;
 305
 306	err = otx2_sync_mbox_msg(&pfvf->mbox);
 307	if (err)
 308		goto fail;
 309
 310	rsp = (struct nix_rss_flowkey_cfg_rsp *)
 311			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
 312	if (IS_ERR(rsp)) {
 313		err = PTR_ERR(rsp);
 314		goto fail;
 315	}
 316
 317	pfvf->hw.flowkey_alg_idx = rsp->alg_idx;
 318fail:
 319	mutex_unlock(&pfvf->mbox.lock);
 320	return err;
 321}
 322
 323int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id, const u32 *ind_tbl)
 324{
 325	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
 326	const int index = rss->rss_size * ctx_id;
 327	struct mbox *mbox = &pfvf->mbox;
 328	struct nix_aq_enq_req *aq;
 329	int idx, err;
 330
 331	mutex_lock(&mbox->lock);
 332	ind_tbl = ind_tbl ?: rss->ind_tbl;
 333	/* Get memory to put this msg */
 334	for (idx = 0; idx < rss->rss_size; idx++) {
 335		/* Ignore the queue if AF_XDP zero copy is enabled */
 336		if (test_bit(ind_tbl[idx], pfvf->af_xdp_zc_qidx))
 337			continue;
 338
 339		aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
 340		if (!aq) {
 341			/* The shared memory buffer can be full.
 342			 * Flush it and retry
 343			 */
 344			err = otx2_sync_mbox_msg(mbox);
 345			if (err) {
 346				mutex_unlock(&mbox->lock);
 347				return err;
 348			}
 349			aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
 350			if (!aq) {
 351				mutex_unlock(&mbox->lock);
 352				return -ENOMEM;
 353			}
 354		}
 355
 356		aq->rss.rq = ind_tbl[idx];
 357
 358		/* Fill AQ info */
 359		aq->qidx = index + idx;
 360		aq->ctype = NIX_AQ_CTYPE_RSS;
 361		aq->op = NIX_AQ_INSTOP_INIT;
 362	}
 363	err = otx2_sync_mbox_msg(mbox);
 364	mutex_unlock(&mbox->lock);
 365	return err;
 366}
 367
 368void otx2_set_rss_key(struct otx2_nic *pfvf)
 369{
 370	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
 371	u64 *key = (u64 *)&rss->key[4];
 372	int idx;
 373
 374	/* 352bit or 44byte key needs to be configured as below
 375	 * NIX_LF_RX_SECRETX0 = key<351:288>
 376	 * NIX_LF_RX_SECRETX1 = key<287:224>
 377	 * NIX_LF_RX_SECRETX2 = key<223:160>
 378	 * NIX_LF_RX_SECRETX3 = key<159:96>
 379	 * NIX_LF_RX_SECRETX4 = key<95:32>
 380	 * NIX_LF_RX_SECRETX5<63:32> = key<31:0>
 381	 */
 382	otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
 383		     (u64)(*((u32 *)&rss->key)) << 32);
 384	idx = sizeof(rss->key) / sizeof(u64);
 385	while (idx > 0) {
 386		idx--;
 387		otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
 388	}
 389}
 390
 391int otx2_rss_init(struct otx2_nic *pfvf)
 392{
 393	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
 394	int idx, ret = 0;
 395
 396	rss->rss_size = sizeof(*rss->ind_tbl);
 397
 398	/* Init RSS key if it is not setup already */
 399	if (!rss->enable)
 400		netdev_rss_key_fill(rss->key, sizeof(rss->key));
 401	otx2_set_rss_key(pfvf);
 402
 403	if (!netif_is_rxfh_configured(pfvf->netdev))
 404		for (idx = 0; idx < rss->rss_size; idx++)
 405			rss->ind_tbl[idx] =
 406				ethtool_rxfh_indir_default(idx,
 407							   pfvf->hw.rx_queues);
 408
 409	ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP, NULL);
 410	if (ret)
 411		return ret;
 412
 413	/* Flowkey or hash config to be used for generating flow tag */
 414	rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg :
 415			   NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 |
 416			   NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP |
 417			   NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN |
 418			   NIX_FLOW_KEY_TYPE_IPV4_PROTO;
 419
 420	ret = otx2_set_flowkey_cfg(pfvf);
 421	if (ret)
 422		return ret;
 423
 424	rss->enable = true;
 425	return 0;
 426}
 427
 428/* Setup UDP segmentation algorithm in HW */
 429static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)
 430{
 431	struct nix_lso_format *field;
 432
 433	field = (struct nix_lso_format *)&lso->fields[0];
 434	lso->field_mask = GENMASK(18, 0);
 435
 436	/* IP's Length field */
 437	field->layer = NIX_TXLAYER_OL3;
 438	/* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
 439	field->offset = v4 ? 2 : 4;
 440	field->sizem1 = 1; /* i.e 2 bytes */
 441	field->alg = NIX_LSOALG_ADD_PAYLEN;
 442	field++;
 443
 444	/* No ID field in IPv6 header */
 445	if (v4) {
 446		/* Increment IPID */
 447		field->layer = NIX_TXLAYER_OL3;
 448		field->offset = 4;
 449		field->sizem1 = 1; /* i.e 2 bytes */
 450		field->alg = NIX_LSOALG_ADD_SEGNUM;
 451		field++;
 452	}
 453
 454	/* Update length in UDP header */
 455	field->layer = NIX_TXLAYER_OL4;
 456	field->offset = 4;
 457	field->sizem1 = 1;
 458	field->alg = NIX_LSOALG_ADD_PAYLEN;
 459}
 460
 461/* Setup segmentation algorithms in HW and retrieve algorithm index */
 462void otx2_setup_segmentation(struct otx2_nic *pfvf)
 463{
 464	struct nix_lso_format_cfg_rsp *rsp;
 465	struct nix_lso_format_cfg *lso;
 466	struct otx2_hw *hw = &pfvf->hw;
 467	int err;
 468
 469	mutex_lock(&pfvf->mbox.lock);
 470
 471	/* UDPv4 segmentation */
 472	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
 473	if (!lso)
 474		goto fail;
 475
 476	/* Setup UDP/IP header fields that HW should update per segment */
 477	otx2_setup_udp_segmentation(lso, true);
 478
 479	err = otx2_sync_mbox_msg(&pfvf->mbox);
 480	if (err)
 481		goto fail;
 482
 483	rsp = (struct nix_lso_format_cfg_rsp *)
 484			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
 485	if (IS_ERR(rsp))
 486		goto fail;
 487
 488	hw->lso_udpv4_idx = rsp->lso_format_idx;
 489
 490	/* UDPv6 segmentation */
 491	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
 492	if (!lso)
 493		goto fail;
 494
 495	/* Setup UDP/IP header fields that HW should update per segment */
 496	otx2_setup_udp_segmentation(lso, false);
 497
 498	err = otx2_sync_mbox_msg(&pfvf->mbox);
 499	if (err)
 500		goto fail;
 501
 502	rsp = (struct nix_lso_format_cfg_rsp *)
 503			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
 504	if (IS_ERR(rsp))
 505		goto fail;
 506
 507	hw->lso_udpv6_idx = rsp->lso_format_idx;
 508	mutex_unlock(&pfvf->mbox.lock);
 509	return;
 510fail:
 511	mutex_unlock(&pfvf->mbox.lock);
 512	netdev_info(pfvf->netdev,
 513		    "Failed to get LSO index for UDP GSO offload, disabling\n");
 514	pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
 515}
 516
 517void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
 518{
 519	/* Configure CQE interrupt coalescing parameters
 520	 *
 521	 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence
 522	 * set 1 less than cq_ecount_wait. And cq_time_wait is in
 523	 * usecs, convert that to 100ns count.
 524	 */
 525	otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
 526		     ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
 527		     ((u64)pfvf->hw.cq_qcount_wait << 32) |
 528		     (pfvf->hw.cq_ecount_wait - 1));
 529}
 530
 531static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool,
 532			       dma_addr_t *dma)
 533{
 534	unsigned int offset = 0;
 535	struct page *page;
 536	size_t sz;
 537
 538	sz = SKB_DATA_ALIGN(pool->rbsize);
 539	sz = ALIGN(sz, OTX2_ALIGN);
 540
 541	page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC);
 542	if (unlikely(!page))
 543		return -ENOMEM;
 544
 545	*dma = page_pool_get_dma_addr(page) + offset;
 546	return 0;
 547}
 548
 549static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
 550			     dma_addr_t *dma, int qidx, int idx)
 551{
 552	u8 *buf;
 553
 554	if (pool->xsk_pool)
 555		return otx2_xsk_pool_alloc_buf(pfvf, pool, dma, idx);
 556
 557	if (pool->page_pool)
 558		return otx2_alloc_pool_buf(pfvf, pool, dma);
 559
 560	buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN);
 561	if (unlikely(!buf))
 562		return -ENOMEM;
 563
 564	*dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
 565				    DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
 566	if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
 567		page_frag_free(buf);
 568		return -ENOMEM;
 569	}
 570
 571	return 0;
 572}
 573
 574int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
 575		    dma_addr_t *dma, int qidx, int idx)
 576{
 577	int ret;
 578
 579	local_bh_disable();
 580	ret = __otx2_alloc_rbuf(pfvf, pool, dma, qidx, idx);
 581	local_bh_enable();
 582	return ret;
 583}
 584
 585int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
 586		      dma_addr_t *dma)
 587{
 588	if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma,
 589				       cq->cq_idx, cq->pool_ptrs - 1)))
 590		return -ENOMEM;
 591	return 0;
 592}
 593
 594void otx2_tx_timeout(struct net_device *netdev, unsigned int txq)
 595{
 596	struct otx2_nic *pfvf = netdev_priv(netdev);
 597
 598	schedule_work(&pfvf->reset_task);
 599}
 600EXPORT_SYMBOL(otx2_tx_timeout);
 601
 602void otx2_get_mac_from_af(struct net_device *netdev)
 603{
 604	struct otx2_nic *pfvf = netdev_priv(netdev);
 605	int err;
 606
 607	err = otx2_hw_get_mac_addr(pfvf, netdev);
 608	if (err)
 609		dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
 610
 611	/* If AF doesn't provide a valid MAC, generate a random one */
 612	if (!is_valid_ether_addr(netdev->dev_addr))
 613		eth_hw_addr_random(netdev);
 614}
 615EXPORT_SYMBOL(otx2_get_mac_from_af);
 616
 617int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc)
 618{
 619	u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC];
 620	struct otx2_hw *hw = &pfvf->hw;
 621	struct nix_txschq_config *req;
 622	u64 schq, parent;
 623	u64 dwrr_val;
 624
 625	dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
 626
 627	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
 628	if (!req)
 629		return -ENOMEM;
 630
 631	req->lvl = lvl;
 632	req->num_regs = 1;
 633
 634	schq_list = hw->txschq_list;
 635#ifdef CONFIG_DCB
 636	if (txschq_for_pfc)
 637		schq_list = pfvf->pfc_schq_list;
 638#endif
 639
 640	schq = schq_list[lvl][prio];
 641	/* Set topology e.t.c configuration */
 642	if (lvl == NIX_TXSCH_LVL_SMQ) {
 643		req->reg[0] = NIX_AF_SMQX_CFG(schq);
 644		req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU;
 645		req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |
 646				  (0x2ULL << 36);
 647		/* Set link type for DWRR MTU selection on CN10K silicons */
 648		if (!is_dev_otx2(pfvf->pdev))
 649			req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57),
 650						(u64)hw->smq_link_type);
 651		req->num_regs++;
 652		/* MDQ config */
 653		parent = schq_list[NIX_TXSCH_LVL_TL4][prio];
 654		req->reg[1] = NIX_AF_MDQX_PARENT(schq);
 655		req->regval[1] = parent << 16;
 656		req->num_regs++;
 657		/* Set DWRR quantum */
 658		req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);
 659		req->regval[2] =  dwrr_val;
 660	} else if (lvl == NIX_TXSCH_LVL_TL4) {
 661		int sdp_chan =  hw->tx_chan_base + prio;
 662
 663		if (is_otx2_sdp_rep(pfvf->pdev))
 664			prio = 0;
 665		parent = schq_list[NIX_TXSCH_LVL_TL3][prio];
 666		req->reg[0] = NIX_AF_TL4X_PARENT(schq);
 667		req->regval[0] = (u64)parent << 16;
 668		req->num_regs++;
 669		req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
 670		req->regval[1] = dwrr_val;
 671		if (is_otx2_sdp_rep(pfvf->pdev)) {
 672			req->num_regs++;
 673			req->reg[2] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
 674			req->regval[2] = BIT_ULL(12) | BIT_ULL(13) |
 675					 (sdp_chan & 0xff);
 676		}
 677	} else if (lvl == NIX_TXSCH_LVL_TL3) {
 678		parent = schq_list[NIX_TXSCH_LVL_TL2][prio];
 679		req->reg[0] = NIX_AF_TL3X_PARENT(schq);
 680		req->regval[0] = (u64)parent << 16;
 681		req->num_regs++;
 682		req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
 683		req->regval[1] = dwrr_val;
 684		if (lvl == hw->txschq_link_cfg_lvl &&
 685		    !is_otx2_sdp_rep(pfvf->pdev)) {
 686			req->num_regs++;
 687			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
 688			/* Enable this queue and backpressure
 689			 * and set relative channel
 690			 */
 691			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
 692		}
 693	} else if (lvl == NIX_TXSCH_LVL_TL2) {
 694		parent = schq_list[NIX_TXSCH_LVL_TL1][prio];
 695		req->reg[0] = NIX_AF_TL2X_PARENT(schq);
 696		req->regval[0] = (u64)parent << 16;
 697
 698		req->num_regs++;
 699		req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
 700		req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val;
 701
 702		if (lvl == hw->txschq_link_cfg_lvl &&
 703		    !is_otx2_sdp_rep(pfvf->pdev)) {
 704			req->num_regs++;
 705			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
 706			/* Enable this queue and backpressure
 707			 * and set relative channel
 708			 */
 709			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
 710		}
 711	} else if (lvl == NIX_TXSCH_LVL_TL1) {
 712		/* Default config for TL1.
 713		 * For VF this is always ignored.
 714		 */
 715
 716		/* On CN10K, if RR_WEIGHT is greater than 16384, HW will
 717		 * clip it to 16384, so configuring a 24bit max value
 718		 * will work on both OTx2 and CN10K.
 719		 */
 720		req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
 721		req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
 722
 723		req->num_regs++;
 724		req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
 725		req->regval[1] = hw->txschq_aggr_lvl_rr_prio << 1;
 726
 727		req->num_regs++;
 728		req->reg[2] = NIX_AF_TL1X_CIR(schq);
 729		req->regval[2] = 0;
 730	}
 731
 732	return otx2_sync_mbox_msg(&pfvf->mbox);
 733}
 734EXPORT_SYMBOL(otx2_txschq_config);
 735
 736int otx2_smq_flush(struct otx2_nic *pfvf, int smq)
 737{
 738	struct nix_txschq_config *req;
 739	int rc;
 740
 741	mutex_lock(&pfvf->mbox.lock);
 742
 743	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
 744	if (!req) {
 745		mutex_unlock(&pfvf->mbox.lock);
 746		return -ENOMEM;
 747	}
 748
 749	req->lvl = NIX_TXSCH_LVL_SMQ;
 750	req->reg[0] = NIX_AF_SMQX_CFG(smq);
 751	req->regval[0] |= BIT_ULL(49);
 752	req->num_regs++;
 753
 754	rc = otx2_sync_mbox_msg(&pfvf->mbox);
 755	mutex_unlock(&pfvf->mbox.lock);
 756	return rc;
 757}
 758EXPORT_SYMBOL(otx2_smq_flush);
 759
 760int otx2_txsch_alloc(struct otx2_nic *pfvf)
 761{
 762	int chan_cnt = pfvf->hw.tx_chan_cnt;
 763	struct nix_txsch_alloc_req *req;
 764	struct nix_txsch_alloc_rsp *rsp;
 765	int lvl, schq, rc;
 766
 767	/* Get memory to put this msg */
 768	req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
 769	if (!req)
 770		return -ENOMEM;
 771
 772	/* Request one schq per level */
 773	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
 774		req->schq[lvl] = 1;
 775
 776	if (is_otx2_sdp_rep(pfvf->pdev) && chan_cnt > 1) {
 777		req->schq[NIX_TXSCH_LVL_SMQ] = chan_cnt;
 778		req->schq[NIX_TXSCH_LVL_TL4] = chan_cnt;
 779	}
 780
 781	rc = otx2_sync_mbox_msg(&pfvf->mbox);
 782	if (rc)
 783		return rc;
 784
 785	rsp = (struct nix_txsch_alloc_rsp *)
 786	      otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
 787	if (IS_ERR(rsp))
 788		return PTR_ERR(rsp);
 789
 790	/* Setup transmit scheduler list */
 791	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
 792		pfvf->hw.txschq_cnt[lvl] = rsp->schq[lvl];
 793		for (schq = 0; schq < rsp->schq[lvl]; schq++)
 794			pfvf->hw.txschq_list[lvl][schq] =
 795				rsp->schq_list[lvl][schq];
 796	}
 797
 798	pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;
 799	pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio;
 800
 801	return 0;
 802}
 803
 804void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq)
 805{
 806	struct nix_txsch_free_req *free_req;
 807	int err;
 808
 809	mutex_lock(&pfvf->mbox.lock);
 810
 811	free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
 812	if (!free_req) {
 813		mutex_unlock(&pfvf->mbox.lock);
 814		netdev_err(pfvf->netdev,
 815			   "Failed alloc txschq free req\n");
 816		return;
 817	}
 818
 819	free_req->schq_lvl = lvl;
 820	free_req->schq = schq;
 821
 822	err = otx2_sync_mbox_msg(&pfvf->mbox);
 823	if (err) {
 824		netdev_err(pfvf->netdev,
 825			   "Failed stop txschq %d at level %d\n", schq, lvl);
 826	}
 827
 828	mutex_unlock(&pfvf->mbox.lock);
 829}
 830EXPORT_SYMBOL(otx2_txschq_free_one);
 831
 832void otx2_txschq_stop(struct otx2_nic *pfvf)
 833{
 834	int lvl, schq, idx;
 835
 836	/* free non QOS TLx nodes */
 837	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
 838		for (idx = 0; idx < pfvf->hw.txschq_cnt[lvl]; idx++) {
 839			otx2_txschq_free_one(pfvf, lvl,
 840					     pfvf->hw.txschq_list[lvl][idx]);
 841		}
 842	}
 843
 844	/* Clear the txschq list */
 845	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
 846		for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++)
 847			pfvf->hw.txschq_list[lvl][schq] = 0;
 848	}
 849
 850}
 851
 852void otx2_sqb_flush(struct otx2_nic *pfvf)
 853{
 854	int qidx, sqe_tail, sqe_head;
 855	struct otx2_snd_queue *sq;
 856	void __iomem *ptr;
 857	u64 incr, val;
 858
 859	ptr = otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
 860	for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
 861		sq = &pfvf->qset.sq[qidx];
 862		if (!sq->sqb_ptrs)
 863			continue;
 864
 865		incr = (u64)qidx << 32;
 866		val = otx2_atomic64_add(incr, ptr);
 867		sqe_head = (val >> 20) & 0x3F;
 868		sqe_tail = (val >> 28) & 0x3F;
 869		if (sqe_head != sqe_tail)
 870			usleep_range(50, 60);
 871	}
 872}
 873
 874/* RED and drop levels of CQ on packet reception.
 875 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty).
 876 */
 877#define RQ_PASS_LVL_CQ(skid, qsize)	((((skid) + 16) * 256) / (qsize))
 878#define RQ_DROP_LVL_CQ(skid, qsize)	(((skid) * 256) / (qsize))
 879
 880/* RED and drop levels of AURA for packet reception.
 881 * For AURA level is measure of fullness (0x0 = empty, 255 = full).
 882 * Eg: For RQ length 1K, for pass/drop level 204/230.
 883 * RED accepts pkts if free pointers > 102 & <= 205.
 884 * Drops pkts if free pointers < 102.
 885 */
 886#define RQ_BP_LVL_AURA   (255 - ((85 * 256) / 100)) /* BP when 85% is full */
 887#define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */
 888#define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */
 889
 890int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
 891{
 892	struct otx2_qset *qset = &pfvf->qset;
 893	struct nix_aq_enq_req *aq;
 894
 895	/* Get memory to put this msg */
 896	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
 897	if (!aq)
 898		return -ENOMEM;
 899
 900	aq->rq.cq = qidx;
 901	aq->rq.ena = 1;
 902	aq->rq.pb_caching = 1;
 903	aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */
 904	aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
 905	aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */
 906	aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */
 907	aq->rq.qint_idx = 0;
 908	aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */
 909	aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */
 910	aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
 911	aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
 912	aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA;
 913	aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA;
 914
 915	/* Fill AQ info */
 916	aq->qidx = qidx;
 917	aq->ctype = NIX_AQ_CTYPE_RQ;
 918	aq->op = NIX_AQ_INSTOP_INIT;
 919
 920	return otx2_sync_mbox_msg(&pfvf->mbox);
 921}
 922
 923int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura)
 924{
 925	struct otx2_nic *pfvf = dev;
 926	struct otx2_snd_queue *sq;
 927	struct nix_aq_enq_req *aq;
 928
 929	sq = &pfvf->qset.sq[qidx];
 930	sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
 931	/* Get memory to put this msg */
 932	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
 933	if (!aq)
 934		return -ENOMEM;
 935
 936	aq->sq.cq = pfvf->hw.rx_queues + qidx;
 937	aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
 938	aq->sq.cq_ena = 1;
 939	aq->sq.ena = 1;
 940	aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);
 941	aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
 942	aq->sq.default_chan = pfvf->hw.tx_chan_base + chan_offset;
 943	aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
 944	aq->sq.sqb_aura = sqb_aura;
 945	aq->sq.sq_int_ena = NIX_SQINT_BITS;
 946	aq->sq.qint_idx = 0;
 947	/* Due pipelining impact minimum 2000 unused SQ CQE's
 948	 * need to maintain to avoid CQ overflow.
 949	 */
 950	aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
 951
 952	/* Fill AQ info */
 953	aq->qidx = qidx;
 954	aq->ctype = NIX_AQ_CTYPE_SQ;
 955	aq->op = NIX_AQ_INSTOP_INIT;
 956
 957	return otx2_sync_mbox_msg(&pfvf->mbox);
 958}
 959
 960int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
 961{
 962	struct otx2_qset *qset = &pfvf->qset;
 963	struct otx2_snd_queue *sq;
 964	struct otx2_pool *pool;
 965	u8 chan_offset;
 966	int err;
 967
 968	pool = &pfvf->qset.pool[sqb_aura];
 969	sq = &qset->sq[qidx];
 970	sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128;
 971	sq->sqe_cnt = qset->sqe_cnt;
 972
 973	err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
 974	if (err)
 975		return err;
 976
 977	/* Allocate memory for NIX SQE (which includes NIX SG) and CPT SG.
 978	 * SG of NIX and CPT are same in size. Allocate memory for CPT SG
 979	 * same as NIX SQE for base address alignment.
 980	 * Layout of a NIX SQE and CPT SG entry:
 981	 *      -----------------------------
 982	 *     |     CPT Scatter Gather      |
 983	 *     |       (SQE SIZE)            |
 984	 *     |                             |
 985	 *      -----------------------------
 986	 *     |       NIX SQE               |
 987	 *     |       (SQE SIZE)            |
 988	 *     |                             |
 989	 *      -----------------------------
 990	 */
 991	err = qmem_alloc(pfvf->dev, &sq->sqe_ring, qset->sqe_cnt,
 992			 sq->sqe_size * 2);
 993	if (err)
 994		return err;
 995
 996	err = qmem_alloc(pfvf->dev, &sq->cpt_resp, qset->sqe_cnt, 64);
 997	if (err)
 998		return err;
 999
1000	if (qidx < pfvf->hw.tx_queues) {
1001		err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
1002				 TSO_HEADER_SIZE);
1003		if (err)
1004			return err;
1005	}
1006
1007	sq->sqe_base = sq->sqe->base;
1008	sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL);
1009	if (!sq->sg)
1010		return -ENOMEM;
1011
1012	if (pfvf->ptp && qidx < pfvf->hw.tx_queues) {
1013		err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
1014				 sizeof(*sq->timestamps));
1015		if (err) {
1016			kfree(sq->sg);
1017			sq->sg = NULL;
1018			return err;
1019		}
1020	}
1021
1022	sq->head = 0;
1023	sq->cons_head = 0;
1024	sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
1025	sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
1026	/* Set SQE threshold to 10% of total SQEs */
1027	sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100;
1028	sq->aura_id = sqb_aura;
1029	sq->aura_fc_addr = pool->fc_addr->base;
1030	sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
1031
1032	sq->stats.bytes = 0;
1033	sq->stats.pkts = 0;
1034	/* Attach XSK_BUFF_POOL to XDP queue */
1035	if (qidx > pfvf->hw.xdp_queues)
1036		otx2_attach_xsk_buff(pfvf, sq, (qidx - pfvf->hw.xdp_queues));
1037
1038
1039	chan_offset = qidx % pfvf->hw.tx_chan_cnt;
1040	err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, chan_offset, sqb_aura);
1041	if (err) {
1042		kfree(sq->sg);
1043		sq->sg = NULL;
1044		return err;
1045	}
1046
1047	return 0;
1048
1049}
1050
1051int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
1052{
1053	struct otx2_qset *qset = &pfvf->qset;
1054	int err, pool_id, non_xdp_queues;
1055	struct nix_aq_enq_req *aq;
1056	struct otx2_cq_queue *cq;
1057	struct otx2_pool *pool;
1058
1059	cq = &qset->cq[qidx];
1060	cq->cq_idx = qidx;
1061	non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues;
1062	if (qidx < pfvf->hw.rx_queues) {
1063		cq->cq_type = CQ_RX;
1064		cq->cint_idx = qidx;
1065		cq->cqe_cnt = qset->rqe_cnt;
1066		if (pfvf->xdp_prog) {
1067			xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0);
1068			pool = &qset->pool[qidx];
1069			if (pool->xsk_pool) {
1070				xdp_rxq_info_reg_mem_model(&cq->xdp_rxq,
1071							   MEM_TYPE_XSK_BUFF_POOL,
1072							   NULL);
1073				xsk_pool_set_rxq_info(pool->xsk_pool, &cq->xdp_rxq);
1074			} else if (pool->page_pool) {
1075				xdp_rxq_info_reg_mem_model(&cq->xdp_rxq,
1076							   MEM_TYPE_PAGE_POOL,
1077							   pool->page_pool);
1078			}
1079		}
1080	} else if (qidx < non_xdp_queues) {
1081		cq->cq_type = CQ_TX;
1082		cq->cint_idx = qidx - pfvf->hw.rx_queues;
1083		cq->cqe_cnt = qset->sqe_cnt;
1084	} else {
1085		if (pfvf->hw.xdp_queues &&
1086		    qidx < non_xdp_queues + pfvf->hw.xdp_queues) {
1087			cq->cq_type = CQ_XDP;
1088			cq->cint_idx = qidx - non_xdp_queues;
1089			cq->cqe_cnt = qset->sqe_cnt;
1090		} else {
1091			cq->cq_type = CQ_QOS;
1092			cq->cint_idx = qidx - non_xdp_queues -
1093				       pfvf->hw.xdp_queues;
1094			cq->cqe_cnt = qset->sqe_cnt;
1095		}
1096	}
1097	cq->cqe_size = pfvf->qset.xqe_size;
1098
1099	/* Allocate memory for CQEs */
1100	err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
1101	if (err)
1102		return err;
1103
1104	/* Save CQE CPU base for faster reference */
1105	cq->cqe_base = cq->cqe->base;
1106	/* In case where all RQs auras point to single pool,
1107	 * all CQs receive buffer pool also point to same pool.
1108	 */
1109	pool_id = ((cq->cq_type == CQ_RX) &&
1110		   (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
1111	cq->rbpool = &qset->pool[pool_id];
1112	cq->refill_task_sched = false;
1113
1114	/* Get memory to put this msg */
1115	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
1116	if (!aq)
1117		return -ENOMEM;
1118
1119	aq->cq.ena = 1;
1120	aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
1121	aq->cq.caching = 1;
1122	aq->cq.base = cq->cqe->iova;
1123	aq->cq.cint_idx = cq->cint_idx;
1124	aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS;
1125	aq->cq.qint_idx = 0;
1126	aq->cq.avg_level = 255;
1127
1128	if (qidx < pfvf->hw.rx_queues) {
1129		aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
1130		aq->cq.drop_ena = 1;
1131
1132		if (!is_otx2_lbkvf(pfvf->pdev)) {
1133			/* Enable receive CQ backpressure */
1134			aq->cq.bp_ena = 1;
1135#ifdef CONFIG_DCB
1136			aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]];
1137#else
1138			aq->cq.bpid = pfvf->bpid[0];
1139#endif
1140
1141			/* Set backpressure level is same as cq pass level */
1142			aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
1143		}
1144	}
1145
1146	/* Fill AQ info */
1147	aq->qidx = qidx;
1148	aq->ctype = NIX_AQ_CTYPE_CQ;
1149	aq->op = NIX_AQ_INSTOP_INIT;
1150
1151	return otx2_sync_mbox_msg(&pfvf->mbox);
1152}
1153
1154static void otx2_pool_refill_task(struct work_struct *work)
1155{
1156	struct otx2_cq_queue *cq;
1157	struct refill_work *wrk;
1158	struct otx2_nic *pfvf;
1159	int qidx;
1160
1161	wrk = container_of(work, struct refill_work, pool_refill_work.work);
1162	pfvf = wrk->pf;
1163	qidx = wrk - pfvf->refill_wrk;
1164	cq = &pfvf->qset.cq[qidx];
1165
1166	cq->refill_task_sched = false;
1167
1168	local_bh_disable();
1169	napi_schedule(wrk->napi);
1170	local_bh_enable();
1171}
1172
1173int otx2_config_nix_queues(struct otx2_nic *pfvf)
1174{
1175	int qidx, err;
1176
1177	/* Initialize RX queues */
1178	for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
1179		u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1180
1181		err = otx2_rq_init(pfvf, qidx, lpb_aura);
1182		if (err)
1183			return err;
1184	}
1185
1186	/* Initialize TX queues */
1187	for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) {
1188		u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1189
1190		err = otx2_sq_init(pfvf, qidx, sqb_aura);
1191		if (err)
1192			return err;
1193	}
1194
1195	/* Initialize completion queues */
1196	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1197		err = otx2_cq_init(pfvf, qidx);
1198		if (err)
1199			return err;
1200	}
1201
1202	pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf,
1203							   NIX_LF_CQ_OP_STATUS);
1204
1205	/* Initialize work queue for receive buffer refill */
1206	pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1207					sizeof(struct refill_work), GFP_KERNEL);
1208	if (!pfvf->refill_wrk)
1209		return -ENOMEM;
1210
1211	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1212		pfvf->refill_wrk[qidx].pf = pfvf;
1213		INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1214				  otx2_pool_refill_task);
1215	}
1216	return 0;
1217}
1218
1219int otx2_config_nix(struct otx2_nic *pfvf)
1220{
1221	struct nix_lf_alloc_req  *nixlf;
1222	struct nix_lf_alloc_rsp *rsp;
1223	int err;
1224
1225	pfvf->qset.xqe_size = pfvf->hw.xqe_size;
1226
1227	/* Get memory to put this msg */
1228	nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1229	if (!nixlf)
1230		return -ENOMEM;
1231
1232	/* Set RQ/SQ/CQ counts */
1233	nixlf->rq_cnt = pfvf->hw.rx_queues;
1234	nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf);
1235	nixlf->cq_cnt = pfvf->qset.cq_cnt;
1236	nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE;
1237	nixlf->rss_grps = MAX_RSS_GROUPS;
1238	nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64;
1239	/* We don't know absolute NPA LF idx attached.
1240	 * AF will replace 'RVU_DEFAULT_PF_FUNC' with
1241	 * NPA LF attached to this RVU PF/VF.
1242	 */
1243	nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
1244	/* Disable alignment pad, enable L2 length check,
1245	 * enable L4 TCP/UDP checksum verification.
1246	 */
1247	nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
1248
1249	err = otx2_sync_mbox_msg(&pfvf->mbox);
1250	if (err)
1251		return err;
1252
1253	rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1254							   &nixlf->hdr);
1255	if (IS_ERR(rsp))
1256		return PTR_ERR(rsp);
1257
1258	if (rsp->qints < 1)
1259		return -ENXIO;
1260
1261	return rsp->hdr.rc;
1262}
1263
1264void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1265{
1266	struct otx2_qset *qset = &pfvf->qset;
1267	struct otx2_hw *hw = &pfvf->hw;
1268	struct otx2_snd_queue *sq;
1269	int sqb, qidx;
1270	u64 iova, pa;
1271
1272	for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
1273		sq = &qset->sq[qidx];
1274		if (!sq->sqb_ptrs)
1275			continue;
1276		for (sqb = 0; sqb < sq->sqb_count; sqb++) {
1277			if (!sq->sqb_ptrs[sqb])
1278				continue;
1279			iova = sq->sqb_ptrs[sqb];
1280			pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1281			dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1282					     DMA_FROM_DEVICE,
1283					     DMA_ATTR_SKIP_CPU_SYNC);
1284			put_page(virt_to_page(phys_to_virt(pa)));
1285		}
1286		sq->sqb_count = 0;
1287	}
1288}
1289
1290void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool,
1291		    u64 iova, int size)
1292{
1293	struct page *page;
1294	u64 pa;
1295
1296	pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1297	page = virt_to_head_page(phys_to_virt(pa));
1298	if (pool->page_pool) {
1299		page_pool_put_full_page(pool->page_pool, page, true);
1300	} else if (pool->xsk_pool) {
1301		/* Note: No way of identifying xdp_buff */
1302	} else {
1303		dma_unmap_page_attrs(pfvf->dev, iova, size,
1304				     DMA_FROM_DEVICE,
1305				     DMA_ATTR_SKIP_CPU_SYNC);
1306
1307		put_page(page);
1308	}
1309}
1310
1311void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1312{
1313	int pool_id, pool_start = 0, pool_end = 0, size = 0;
1314	struct otx2_pool *pool;
1315	u64 iova;
1316	int idx;
1317
1318	if (type == AURA_NIX_SQ) {
1319		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1320		pool_end =  pool_start + pfvf->hw.sqpool_cnt;
1321		size = pfvf->hw.sqb_size;
1322	}
1323	if (type == AURA_NIX_RQ) {
1324		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1325		pool_end = pfvf->hw.rqpool_cnt;
1326		size = pfvf->rbsize;
1327	}
1328
1329	/* Free SQB and RQB pointers from the aura pool */
1330	for (pool_id = pool_start; pool_id < pool_end; pool_id++) {
1331		pool = &pfvf->qset.pool[pool_id];
1332		iova = otx2_aura_allocptr(pfvf, pool_id);
1333		while (iova) {
1334			if (type == AURA_NIX_RQ)
1335				iova -= OTX2_HEAD_ROOM;
1336			otx2_free_bufs(pfvf, pool, iova, size);
1337			iova = otx2_aura_allocptr(pfvf, pool_id);
1338		}
1339
1340		for (idx = 0 ; idx < pool->xdp_cnt; idx++) {
1341			if (!pool->xdp[idx])
1342				continue;
1343
1344			xsk_buff_free(pool->xdp[idx]);
1345		}
1346	}
1347}
1348
1349void otx2_aura_pool_free(struct otx2_nic *pfvf)
1350{
1351	struct otx2_pool *pool;
1352	int pool_id;
1353
1354	if (!pfvf->qset.pool)
1355		return;
1356
1357	for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1358		pool = &pfvf->qset.pool[pool_id];
1359		qmem_free(pfvf->dev, pool->stack);
1360		qmem_free(pfvf->dev, pool->fc_addr);
1361		page_pool_destroy(pool->page_pool);
1362		devm_kfree(pfvf->dev, pool->xdp);
1363		pool->xsk_pool = NULL;
1364	}
1365	devm_kfree(pfvf->dev, pfvf->qset.pool);
1366	pfvf->qset.pool = NULL;
1367}
1368
1369int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1370		   int pool_id, int numptrs)
1371{
1372	return pfvf->hw_ops->aura_aq_init(pfvf, aura_id, pool_id,
1373					  numptrs);
1374}
1375
1376int otx2_aura_aq_init(struct otx2_nic *pfvf, int aura_id,
1377		      int pool_id, int numptrs)
1378{
1379	struct npa_aq_enq_req *aq;
1380	struct otx2_pool *pool;
1381	int err;
1382
1383	pool = &pfvf->qset.pool[pool_id];
1384
1385	/* Allocate memory for HW to update Aura count.
1386	 * Alloc one cache line, so that it fits all FC_STYPE modes.
1387	 */
1388	if (!pool->fc_addr) {
1389		err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1390		if (err)
1391			return err;
1392	}
1393
1394	/* Initialize this aura's context via AF */
1395	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1396	if (!aq) {
1397		/* Shared mbox memory buffer is full, flush it and retry */
1398		err = otx2_sync_mbox_msg(&pfvf->mbox);
1399		if (err)
1400			return err;
1401		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1402		if (!aq)
1403			return -ENOMEM;
1404	}
1405
1406	aq->aura_id = aura_id;
1407	/* Will be filled by AF with correct pool context address */
1408	aq->aura.pool_addr = pool_id;
1409	aq->aura.pool_caching = 1;
1410	aq->aura.shift = ilog2(numptrs) - 8;
1411	aq->aura.count = numptrs;
1412	aq->aura.limit = numptrs;
1413	aq->aura.avg_level = 255;
1414	aq->aura.ena = 1;
1415	aq->aura.fc_ena = 1;
1416	aq->aura.fc_addr = pool->fc_addr->iova;
1417	aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
1418
1419	/* Enable backpressure for RQ aura */
1420	if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
1421		aq->aura.bp_ena = 0;
1422		/* If NIX1 LF is attached then specify NIX1_RX.
1423		 *
1424		 * Below NPA_AURA_S[BP_ENA] is set according to the
1425		 * NPA_BPINTF_E enumeration given as:
1426		 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
1427		 * NIX0_RX is 0x0 + 0*0x1 = 0
1428		 * NIX1_RX is 0x0 + 1*0x1 = 1
1429		 * But in HRM it is given that
1430		 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
1431		 * NIX-RX based on [BP] level. One bit per NIX-RX; index
1432		 * enumerated by NPA_BPINTF_E."
1433		 */
1434		if (pfvf->nix_blkaddr == BLKADDR_NIX1)
1435			aq->aura.bp_ena = 1;
1436#ifdef CONFIG_DCB
1437		aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]];
1438#else
1439		aq->aura.nix0_bpid = pfvf->bpid[0];
1440#endif
1441
1442		/* Set backpressure level for RQ's Aura */
1443		aq->aura.bp = RQ_BP_LVL_AURA;
1444	}
1445
1446	/* Fill AQ info */
1447	aq->ctype = NPA_AQ_CTYPE_AURA;
1448	aq->op = NPA_AQ_INSTOP_INIT;
1449
1450	return 0;
1451}
1452
1453int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1454		   int stack_pages, int numptrs, int buf_size, int type)
1455{
1456	return pfvf->hw_ops->pool_aq_init(pfvf, pool_id, stack_pages, numptrs,
1457					  buf_size, type);
1458}
1459
1460int otx2_pool_aq_init(struct otx2_nic *pfvf, u16 pool_id,
1461		      int stack_pages, int numptrs, int buf_size, int type)
1462{
1463	struct page_pool_params pp_params = { 0 };
1464	struct xsk_buff_pool *xsk_pool;
1465	struct npa_aq_enq_req *aq;
1466	struct otx2_pool *pool;
1467	int err;
1468
1469	pool = &pfvf->qset.pool[pool_id];
1470	/* Alloc memory for stack which is used to store buffer pointers */
1471	err = qmem_alloc(pfvf->dev, &pool->stack,
1472			 stack_pages, pfvf->hw.stack_pg_bytes);
1473	if (err)
1474		return err;
1475
1476	pool->rbsize = buf_size;
1477
1478	/* Initialize this pool's context via AF */
1479	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1480	if (!aq) {
1481		/* Shared mbox memory buffer is full, flush it and retry */
1482		err = otx2_sync_mbox_msg(&pfvf->mbox);
1483		if (err) {
1484			qmem_free(pfvf->dev, pool->stack);
1485			return err;
1486		}
1487		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1488		if (!aq) {
1489			qmem_free(pfvf->dev, pool->stack);
1490			return -ENOMEM;
1491		}
1492	}
1493
1494	aq->aura_id = pool_id;
1495	aq->pool.stack_base = pool->stack->iova;
1496	aq->pool.stack_caching = 1;
1497	aq->pool.ena = 1;
1498	aq->pool.buf_size = buf_size / 128;
1499	aq->pool.stack_max_pages = stack_pages;
1500	aq->pool.shift = ilog2(numptrs) - 8;
1501	aq->pool.ptr_start = 0;
1502	aq->pool.ptr_end = ~0ULL;
1503
1504	/* Fill AQ info */
1505	aq->ctype = NPA_AQ_CTYPE_POOL;
1506	aq->op = NPA_AQ_INSTOP_INIT;
1507
1508	if (type != AURA_NIX_RQ)
1509		return 0;
1510
1511	if (!test_bit(pool_id, pfvf->af_xdp_zc_qidx)) {
1512		pp_params.order = get_order(buf_size);
1513		pp_params.flags = PP_FLAG_DMA_MAP;
1514		pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs);
1515		pp_params.nid = NUMA_NO_NODE;
1516		pp_params.dev = pfvf->dev;
1517		pp_params.dma_dir = DMA_FROM_DEVICE;
1518		pool->page_pool = page_pool_create(&pp_params);
1519		if (IS_ERR(pool->page_pool)) {
1520			netdev_err(pfvf->netdev, "Creation of page pool failed\n");
1521			return PTR_ERR(pool->page_pool);
1522		}
1523		return 0;
1524	}
1525
1526	/* Set XSK pool to support AF_XDP zero-copy */
1527	xsk_pool = xsk_get_pool_from_qid(pfvf->netdev, pool_id);
1528	if (xsk_pool) {
1529		pool->xsk_pool = xsk_pool;
1530		pool->xdp_cnt = numptrs;
1531		pool->xdp = devm_kcalloc(pfvf->dev,
1532					 numptrs, sizeof(struct xdp_buff *), GFP_KERNEL);
1533		if (!pool->xdp)
1534			return -ENOMEM;
1535	}
1536
1537	return 0;
1538}
1539
1540int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1541{
1542	int qidx, pool_id, stack_pages, num_sqbs;
1543	struct otx2_qset *qset = &pfvf->qset;
1544	struct otx2_hw *hw = &pfvf->hw;
1545	struct otx2_snd_queue *sq;
1546	struct otx2_pool *pool;
1547	dma_addr_t bufptr;
1548	int err, ptr;
1549
1550	/* Calculate number of SQBs needed.
1551	 *
1552	 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB.
1553	 * Last SQE is used for pointing to next SQB.
1554	 */
1555	num_sqbs = (hw->sqb_size / 128) - 1;
1556	num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs;
1557
1558	/* Get no of stack pages needed */
1559	stack_pages =
1560		(num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1561
1562	for (qidx = 0; qidx < hw->non_qos_queues; qidx++) {
1563		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1564		/* Initialize aura context */
1565		err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1566		if (err)
1567			goto fail;
1568
1569		/* Initialize pool context */
1570		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1571				     num_sqbs, hw->sqb_size, AURA_NIX_SQ);
1572		if (err)
1573			goto fail;
1574	}
1575
1576	/* Flush accumulated messages */
1577	err = otx2_sync_mbox_msg(&pfvf->mbox);
1578	if (err)
1579		goto fail;
1580
1581	/* Allocate pointers and free them to aura/pool */
1582	for (qidx = 0; qidx < hw->non_qos_queues; qidx++) {
1583		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1584		pool = &pfvf->qset.pool[pool_id];
1585
1586		sq = &qset->sq[qidx];
1587		sq->sqb_count = 0;
1588		sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
1589		if (!sq->sqb_ptrs) {
1590			err = -ENOMEM;
1591			goto err_mem;
1592		}
1593
1594		for (ptr = 0; ptr < num_sqbs; ptr++) {
1595			err = otx2_alloc_rbuf(pfvf, pool, &bufptr, pool_id, ptr);
1596			if (err) {
1597				if (pool->xsk_pool) {
1598					ptr--;
1599					while (ptr >= 0) {
1600						xsk_buff_free(pool->xdp[ptr]);
1601						ptr--;
1602					}
1603				}
1604				goto err_mem;
1605			}
1606
1607			pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1608			sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
1609		}
1610	}
1611
1612err_mem:
1613	return err ? -ENOMEM : 0;
1614
1615fail:
1616	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1617	otx2_aura_pool_free(pfvf);
1618	return err;
1619}
1620
1621int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1622{
1623	struct otx2_hw *hw = &pfvf->hw;
1624	int stack_pages, pool_id, rq;
1625	struct otx2_pool *pool;
1626	int err, ptr, num_ptrs;
1627	dma_addr_t bufptr;
1628
1629	num_ptrs = pfvf->qset.rqe_cnt;
1630
1631	stack_pages =
1632		(num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1633
1634	for (rq = 0; rq < hw->rx_queues; rq++) {
1635		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1636		/* Initialize aura context */
1637		err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1638		if (err)
1639			goto fail;
1640	}
1641	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1642		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1643				     num_ptrs, pfvf->rbsize, AURA_NIX_RQ);
1644		if (err)
1645			goto fail;
1646	}
1647
1648	/* Flush accumulated messages */
1649	err = otx2_sync_mbox_msg(&pfvf->mbox);
1650	if (err)
1651		goto fail;
1652
1653	/* Allocate pointers and free them to aura/pool */
1654	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1655		pool = &pfvf->qset.pool[pool_id];
1656
1657		for (ptr = 0; ptr < num_ptrs; ptr++) {
1658			err = otx2_alloc_rbuf(pfvf, pool, &bufptr, pool_id, ptr);
1659			if (err) {
1660				if (pool->xsk_pool) {
1661					while (ptr)
1662						xsk_buff_free(pool->xdp[--ptr]);
1663				}
1664				return -ENOMEM;
1665			}
1666
1667			pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1668						   pool->xsk_pool ? bufptr :
1669						   bufptr + OTX2_HEAD_ROOM);
1670		}
1671	}
1672	return 0;
1673fail:
1674	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1675	otx2_aura_pool_free(pfvf);
1676	return err;
1677}
1678
1679int otx2_config_npa(struct otx2_nic *pfvf)
1680{
1681	struct otx2_qset *qset = &pfvf->qset;
1682	struct npa_lf_alloc_req  *npalf;
1683	struct otx2_hw *hw = &pfvf->hw;
1684	int aura_cnt;
1685
1686	/* Pool - Stack of free buffer pointers
1687	 * Aura - Alloc/frees pointers from/to pool for NIX DMA.
1688	 */
1689
1690	if (!hw->pool_cnt)
1691		return -EINVAL;
1692
1693	qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1694				  sizeof(struct otx2_pool), GFP_KERNEL);
1695	if (!qset->pool)
1696		return -ENOMEM;
1697
1698	/* Get memory to put this msg */
1699	npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1700	if (!npalf)
1701		return -ENOMEM;
1702
1703	/* Set aura and pool counts */
1704	npalf->nr_pools = hw->pool_cnt;
1705	aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
1706	npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
1707
1708	return otx2_sync_mbox_msg(&pfvf->mbox);
1709}
1710
1711int otx2_detach_resources(struct mbox *mbox)
1712{
1713	struct rsrc_detach *detach;
1714
1715	mutex_lock(&mbox->lock);
1716	detach = otx2_mbox_alloc_msg_detach_resources(mbox);
1717	if (!detach) {
1718		mutex_unlock(&mbox->lock);
1719		return -ENOMEM;
1720	}
1721
1722	/* detach all */
1723	detach->partial = false;
1724
1725	/* Send detach request to AF */
1726	otx2_sync_mbox_msg(mbox);
1727	mutex_unlock(&mbox->lock);
1728	return 0;
1729}
1730EXPORT_SYMBOL(otx2_detach_resources);
1731
1732int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1733{
1734	struct rsrc_attach *attach;
1735	struct msg_req *msix;
1736	int err;
1737
1738	mutex_lock(&pfvf->mbox.lock);
1739	/* Get memory to put this msg */
1740	attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1741	if (!attach) {
1742		mutex_unlock(&pfvf->mbox.lock);
1743		return -ENOMEM;
1744	}
1745
1746	attach->npalf = true;
1747	attach->nixlf = true;
1748
1749	/* Send attach request to AF */
1750	err = otx2_sync_mbox_msg(&pfvf->mbox);
1751	if (err) {
1752		mutex_unlock(&pfvf->mbox.lock);
1753		return err;
1754	}
1755
1756	pfvf->nix_blkaddr = BLKADDR_NIX0;
1757
1758	/* If the platform has two NIX blocks then LF may be
1759	 * allocated from NIX1.
1760	 */
1761	if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1762		pfvf->nix_blkaddr = BLKADDR_NIX1;
1763
1764	/* Get NPA and NIX MSIX vector offsets */
1765	msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1766	if (!msix) {
1767		mutex_unlock(&pfvf->mbox.lock);
1768		return -ENOMEM;
1769	}
1770
1771	err = otx2_sync_mbox_msg(&pfvf->mbox);
1772	if (err) {
1773		mutex_unlock(&pfvf->mbox.lock);
1774		return err;
1775	}
1776	mutex_unlock(&pfvf->mbox.lock);
1777
1778	if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1779	    pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1780		dev_err(pfvf->dev,
1781			"RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
1782		return -EINVAL;
1783	}
1784
1785	return 0;
1786}
1787EXPORT_SYMBOL(otx2_attach_npa_nix);
1788
1789void otx2_ctx_disable(struct mbox *mbox, int type, bool npa)
1790{
1791	struct hwctx_disable_req *req;
1792
1793	mutex_lock(&mbox->lock);
1794	/* Request AQ to disable this context */
1795	if (npa)
1796		req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox);
1797	else
1798		req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox);
1799
1800	if (!req) {
1801		mutex_unlock(&mbox->lock);
1802		return;
1803	}
1804
1805	req->ctype = type;
1806
1807	if (otx2_sync_mbox_msg(mbox))
1808		dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1809			__func__);
1810
1811	mutex_unlock(&mbox->lock);
1812}
1813
1814int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1815{
1816	struct nix_bp_cfg_req *req;
1817
1818	if (enable)
1819		req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1820	else
1821		req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1822
1823	if (!req)
1824		return -ENOMEM;
1825
1826	req->chan_base = 0;
1827	if (otx2_is_pfc_enabled(pfvf)) {
1828		req->chan_cnt = IEEE_8021QAZ_MAX_TCS;
1829		req->bpid_per_chan = 1;
1830	} else {
1831		req->chan_cnt = pfvf->hw.rx_chan_cnt;
1832		req->bpid_per_chan = 0;
1833	}
1834
1835	return otx2_sync_mbox_msg(&pfvf->mbox);
1836}
1837EXPORT_SYMBOL(otx2_nix_config_bp);
1838
1839int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable)
1840{
1841	struct nix_bp_cfg_req *req;
1842
1843	if (enable)
1844		req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf->mbox);
1845	else
1846		req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf->mbox);
1847
1848	if (!req)
1849		return -ENOMEM;
1850
1851	req->chan_base = 0;
1852	if (otx2_is_pfc_enabled(pfvf)) {
1853		req->chan_cnt = IEEE_8021QAZ_MAX_TCS;
1854		req->bpid_per_chan = 1;
1855	} else {
1856		req->chan_cnt = pfvf->hw.rx_chan_cnt;
1857		req->bpid_per_chan = 0;
1858	}
1859
1860	return otx2_sync_mbox_msg(&pfvf->mbox);
1861}
1862EXPORT_SYMBOL(otx2_nix_cpt_config_bp);
1863
1864/* Mbox message handlers */
1865void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1866			    struct cgx_stats_rsp *rsp)
1867{
1868	int id;
1869
1870	for (id = 0; id < CGX_RX_STATS_COUNT; id++)
1871		pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1872	for (id = 0; id < CGX_TX_STATS_COUNT; id++)
1873		pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1874}
1875
1876void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1877				struct cgx_fec_stats_rsp *rsp)
1878{
1879	pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1880	pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1881}
1882
1883void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1884			       struct npa_lf_alloc_rsp *rsp)
1885{
1886	pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1887	pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1888}
1889EXPORT_SYMBOL(mbox_handler_npa_lf_alloc);
1890
1891void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1892			       struct nix_lf_alloc_rsp *rsp)
1893{
1894	pfvf->hw.sqb_size = rsp->sqb_size;
1895	pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1896	pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1897	pfvf->hw.rx_chan_cnt = rsp->rx_chan_cnt;
1898	pfvf->hw.tx_chan_cnt = rsp->tx_chan_cnt;
1899	pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1900	pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1901	pfvf->hw.cgx_links = rsp->cgx_links;
1902	pfvf->hw.lbk_links = rsp->lbk_links;
1903	pfvf->hw.tx_link = rsp->tx_link;
1904}
1905EXPORT_SYMBOL(mbox_handler_nix_lf_alloc);
1906
1907void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1908			      struct msix_offset_rsp *rsp)
1909{
1910	pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1911	pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1912}
1913EXPORT_SYMBOL(mbox_handler_msix_offset);
1914
1915void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1916				struct nix_bp_cfg_rsp *rsp)
1917{
1918	int chan, chan_id;
1919
1920	for (chan = 0; chan < rsp->chan_cnt; chan++) {
1921		chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F);
1922		pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1923	}
1924}
1925EXPORT_SYMBOL(mbox_handler_nix_bp_enable);
1926
1927void otx2_free_cints(struct otx2_nic *pfvf, int n)
1928{
1929	struct otx2_qset *qset = &pfvf->qset;
1930	struct otx2_hw *hw = &pfvf->hw;
1931	int irq, qidx;
1932
1933	for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1934	     qidx < n;
1935	     qidx++, irq++) {
1936		int vector = pci_irq_vector(pfvf->pdev, irq);
1937
1938		irq_set_affinity_hint(vector, NULL);
1939		free_cpumask_var(hw->affinity_mask[irq]);
1940		free_irq(vector, &qset->napi[qidx]);
1941	}
1942}
1943EXPORT_SYMBOL(otx2_free_cints);
1944
1945void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1946{
1947	struct otx2_hw *hw = &pfvf->hw;
1948	int vec, cpu, irq, cint;
1949
1950	vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1951	cpu = cpumask_first(cpu_online_mask);
1952
1953	/* CQ interrupts */
1954	for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1955		if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL))
1956			return;
1957
1958		cpumask_set_cpu(cpu, hw->affinity_mask[vec]);
1959
1960		irq = pci_irq_vector(pfvf->pdev, vec);
1961		irq_set_affinity_hint(irq, hw->affinity_mask[vec]);
1962
1963		cpu = cpumask_next(cpu, cpu_online_mask);
1964		if (unlikely(cpu >= nr_cpu_ids))
1965			cpu = 0;
1966	}
1967}
1968
1969static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw)
1970{
1971	if (is_otx2_lbkvf(pfvf->pdev)) {
1972		pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK;
1973		return hw->lbk_dwrr_mtu;
1974	}
1975
1976	pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM;
1977	return hw->rpm_dwrr_mtu;
1978}
1979
1980u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1981{
1982	struct nix_hw_info *rsp;
1983	struct msg_req *req;
1984	u16 max_mtu;
1985	int rc;
1986
1987	mutex_lock(&pfvf->mbox.lock);
1988
1989	req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1990	if (!req) {
1991		rc =  -ENOMEM;
1992		goto out;
1993	}
1994
1995	rc = otx2_sync_mbox_msg(&pfvf->mbox);
1996	if (!rc) {
1997		rsp = (struct nix_hw_info *)
1998		       otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1999		if (IS_ERR(rsp)) {
2000			rc = PTR_ERR(rsp);
2001			goto out;
2002		}
2003
2004		/* HW counts VLAN insertion bytes (8 for double tag)
2005		 * irrespective of whether SQE is requesting to insert VLAN
2006		 * in the packet or not. Hence these 8 bytes have to be
2007		 * discounted from max packet size otherwise HW will throw
2008		 * SMQ errors
2009		 */
2010		max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN;
2011
2012		/* Also save DWRR MTU, needed for DWRR weight calculation */
2013		pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp);
2014		if (!pfvf->hw.dwrr_mtu)
2015			pfvf->hw.dwrr_mtu = 1;
2016	}
2017
2018out:
2019	mutex_unlock(&pfvf->mbox.lock);
2020	if (rc) {
2021		dev_warn(pfvf->dev,
2022			 "Failed to get MTU from hardware setting default value(1500)\n");
2023		max_mtu = 1500;
2024	}
2025	return max_mtu;
2026}
2027EXPORT_SYMBOL(otx2_get_max_mtu);
2028
2029int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features)
2030{
2031	netdev_features_t changed = features ^ netdev->features;
2032	struct otx2_nic *pfvf = netdev_priv(netdev);
2033	bool ntuple = !!(features & NETIF_F_NTUPLE);
2034	bool tc = !!(features & NETIF_F_HW_TC);
2035
2036	if ((changed & NETIF_F_NTUPLE) && !ntuple)
2037		otx2_destroy_ntuple_flows(pfvf);
2038
2039	if ((changed & NETIF_F_NTUPLE) && ntuple) {
2040		if (!pfvf->flow_cfg->max_flows) {
2041			netdev_err(netdev,
2042				   "Can't enable NTUPLE, MCAM entries not allocated\n");
2043			return -EINVAL;
2044		}
2045	}
2046
2047	if ((changed & NETIF_F_HW_TC) && !tc &&
2048	    otx2_tc_flower_rule_cnt(pfvf)) {
2049		netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n");
2050		return -EBUSY;
2051	}
2052
2053	if ((changed & NETIF_F_NTUPLE) && ntuple &&
2054	    otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) {
2055		netdev_err(netdev,
2056			   "Can't enable NTUPLE when TC flower offload is active, disable TC rules and retry\n");
2057		return -EINVAL;
2058	}
2059
2060	return 0;
2061}
2062EXPORT_SYMBOL(otx2_handle_ntuple_tc_features);
2063
2064int otx2_set_hw_capabilities(struct otx2_nic *pfvf)
2065{
2066	struct mbox *mbox = &pfvf->mbox;
2067	struct otx2_hw *hw = &pfvf->hw;
2068	struct get_hw_cap_rsp *rsp;
2069	struct msg_req *req;
2070	int ret = -ENOMEM;
2071
2072	mutex_lock(&mbox->lock);
2073
2074	req = otx2_mbox_alloc_msg_get_hw_cap(mbox);
2075	if (!req)
2076		goto fail;
2077
2078	ret = otx2_sync_mbox_msg(mbox);
2079	if (ret)
2080		goto fail;
2081
2082	rsp = (struct get_hw_cap_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox,
2083							 0, &req->hdr);
2084	if (IS_ERR(rsp)) {
2085		ret = -EINVAL;
2086		goto fail;
2087	}
2088
2089	if (rsp->hw_caps & HW_CAP_MACSEC)
2090		__set_bit(CN10K_HW_MACSEC, &hw->cap_flag);
2091
2092	mutex_unlock(&mbox->lock);
2093
2094	return 0;
2095fail:
2096	dev_err(pfvf->dev, "Cannot get MACSEC capability from AF\n");
2097	mutex_unlock(&mbox->lock);
2098	return ret;
2099}
2100
2101#define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
2102int __weak								\
2103otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf,		\
2104				struct _req_type *req,			\
2105				struct _rsp_type *rsp)			\
2106{									\
2107	/* Nothing to do here */					\
2108	return 0;							\
2109}									\
2110EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name);
2111MBOX_UP_CGX_MESSAGES
2112MBOX_UP_MCS_MESSAGES
2113#undef M
2114
2115dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf,
2116				 struct sk_buff *skb, int seg, int *len)
2117{
2118	enum dma_data_direction dir = DMA_TO_DEVICE;
2119	const skb_frag_t *frag;
2120	struct page *page;
2121	int offset;
2122
2123	/* Crypto hardware need write permission for ipsec crypto offload */
2124	if (unlikely(xfrm_offload(skb))) {
2125		dir = DMA_BIDIRECTIONAL;
2126		skb = skb_unshare(skb, GFP_ATOMIC);
2127	}
2128
2129	/* First segment is always skb->data */
2130	if (!seg) {
2131		page = virt_to_page(skb->data);
2132		offset = offset_in_page(skb->data);
2133		*len = skb_headlen(skb);
2134	} else {
2135		frag = &skb_shinfo(skb)->frags[seg - 1];
2136		page = skb_frag_page(frag);
2137		offset = skb_frag_off(frag);
2138		*len = skb_frag_size(frag);
2139	}
2140	return otx2_dma_map_page(pfvf, page, offset, *len, dir);
2141}
2142
2143void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg)
2144{
2145	enum dma_data_direction dir = DMA_TO_DEVICE;
2146	struct sk_buff *skb = NULL;
2147	int seg;
2148
2149	skb = (struct sk_buff *)sg->skb;
2150	if (unlikely(xfrm_offload(skb)))
2151		dir = DMA_BIDIRECTIONAL;
2152
2153	for (seg = 0; seg < sg->num_segs; seg++) {
2154		otx2_dma_unmap_page(pfvf, sg->dma_addr[seg],
2155				    sg->size[seg], dir);
2156	}
2157	sg->num_segs = 0;
2158}