FILE
rvu_struct.h
File preview with syntax highlighting.
linux-6.19.14/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef RVU_STRUCT_H 9#define RVU_STRUCT_H 10 11/* RVU Block revision IDs */ 12#define RVU_BLK_RVUM_REVID 0x01 13 14#define RVU_MULTI_BLK_VER 0x7ULL 15 16#define NIX_MAX_CTX_SIZE 128 17 18/* RVU Block Address Enumeration */ 19enum rvu_block_addr_e { 20 BLKADDR_RVUM = 0x0ULL, 21 BLKADDR_LMT = 0x1ULL, 22 BLKADDR_MSIX = 0x2ULL, 23 BLKADDR_NPA = 0x3ULL, 24 BLKADDR_NIX0 = 0x4ULL, 25 BLKADDR_NIX1 = 0x5ULL, 26 BLKADDR_NPC = 0x6ULL, 27 BLKADDR_SSO = 0x7ULL, 28 BLKADDR_SSOW = 0x8ULL, 29 BLKADDR_TIM = 0x9ULL, 30 BLKADDR_CPT0 = 0xaULL, 31 BLKADDR_CPT1 = 0xbULL, 32 BLKADDR_NDC_NIX0_RX = 0xcULL, 33 BLKADDR_NDC_NIX0_TX = 0xdULL, 34 BLKADDR_NDC_NPA0 = 0xeULL, 35 BLKADDR_NDC_NIX1_RX = 0x10ULL, 36 BLKADDR_NDC_NIX1_TX = 0x11ULL, 37 BLKADDR_APR = 0x16ULL, 38 BLKADDR_MBOX = 0x1bULL, 39 BLK_COUNT = 0x1cULL, 40}; 41 42/* RVU Block Type Enumeration */ 43enum rvu_block_type_e { 44 BLKTYPE_RVUM = 0x0, 45 BLKTYPE_MSIX = 0x1, 46 BLKTYPE_LMT = 0x2, 47 BLKTYPE_NIX = 0x3, 48 BLKTYPE_NPA = 0x4, 49 BLKTYPE_NPC = 0x5, 50 BLKTYPE_SSO = 0x6, 51 BLKTYPE_SSOW = 0x7, 52 BLKTYPE_TIM = 0x8, 53 BLKTYPE_CPT = 0x9, 54 BLKTYPE_NDC = 0xa, 55 BLKTYPE_MBOX = 0x13, 56 BLKTYPE_MAX = 0x13, 57}; 58 59/* RVU Admin function Interrupt Vector Enumeration */ 60enum rvu_af_int_vec_e { 61 RVU_AF_INT_VEC_POISON = 0x0, 62 RVU_AF_INT_VEC_PFFLR = 0x1, 63 RVU_AF_INT_VEC_PFME = 0x2, 64 RVU_AF_INT_VEC_GEN = 0x3, 65 RVU_AF_INT_VEC_MBOX = 0x4, 66 RVU_AF_INT_VEC_CNT = 0x5, 67}; 68 69/* CPT Admin function Interrupt Vector Enumeration */ 70enum cpt_af_int_vec_e { 71 CPT_AF_INT_VEC_FLT0 = 0x0, 72 CPT_AF_INT_VEC_FLT1 = 0x1, 73 CPT_AF_INT_VEC_RVU = 0x2, 74 CPT_AF_INT_VEC_RAS = 0x3, 75 CPT_AF_INT_VEC_CNT = 0x4, 76}; 77 78enum cpt_cn10k_flt_int_vec_e { 79 CPT_10K_AF_INT_VEC_FLT0 = 0x0, 80 CPT_10K_AF_INT_VEC_FLT1 = 0x1, 81 CPT_10K_AF_INT_VEC_FLT2 = 0x2, 82 CPT_10K_AF_INT_VEC_FLT_MAX = 0x3, 83}; 84 85/* NPA Admin function Interrupt Vector Enumeration */ 86enum npa_af_int_vec_e { 87 NPA_AF_INT_VEC_RVU = 0x0, 88 NPA_AF_INT_VEC_GEN = 0x1, 89 NPA_AF_INT_VEC_AQ_DONE = 0x2, 90 NPA_AF_INT_VEC_AF_ERR = 0x3, 91 NPA_AF_INT_VEC_POISON = 0x4, 92 NPA_AF_INT_VEC_CNT = 0x5, 93}; 94 95/* NIX Admin function Interrupt Vector Enumeration */ 96enum nix_af_int_vec_e { 97 NIX_AF_INT_VEC_RVU = 0x0, 98 NIX_AF_INT_VEC_GEN = 0x1, 99 NIX_AF_INT_VEC_AQ_DONE = 0x2, 100 NIX_AF_INT_VEC_AF_ERR = 0x3, 101 NIX_AF_INT_VEC_POISON = 0x4, 102 NIX_AF_INT_VEC_CNT = 0x5, 103}; 104 105/** 106 * RVU PF Interrupt Vector Enumeration 107 */ 108enum rvu_pf_int_vec_e { 109 RVU_PF_INT_VEC_VFFLR0 = 0x0, 110 RVU_PF_INT_VEC_VFFLR1 = 0x1, 111 RVU_PF_INT_VEC_VFME0 = 0x2, 112 RVU_PF_INT_VEC_VFME1 = 0x3, 113 RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4, 114 RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5, 115 RVU_PF_INT_VEC_AFPF_MBOX = 0x6, 116 RVU_PF_INT_VEC_CNT = 0x7, 117}; 118 119/* NPA admin queue completion enumeration */ 120enum npa_aq_comp { 121 NPA_AQ_COMP_NOTDONE = 0x0, 122 NPA_AQ_COMP_GOOD = 0x1, 123 NPA_AQ_COMP_SWERR = 0x2, 124 NPA_AQ_COMP_CTX_POISON = 0x3, 125 NPA_AQ_COMP_CTX_FAULT = 0x4, 126 NPA_AQ_COMP_LOCKERR = 0x5, 127}; 128 129/* NPA admin queue context types */ 130enum npa_aq_ctype { 131 NPA_AQ_CTYPE_AURA = 0x0, 132 NPA_AQ_CTYPE_POOL = 0x1, 133}; 134 135/* NPA admin queue instruction opcodes */ 136enum npa_aq_instop { 137 NPA_AQ_INSTOP_NOP = 0x0, 138 NPA_AQ_INSTOP_INIT = 0x1, 139 NPA_AQ_INSTOP_WRITE = 0x2, 140 NPA_AQ_INSTOP_READ = 0x3, 141 NPA_AQ_INSTOP_LOCK = 0x4, 142 NPA_AQ_INSTOP_UNLOCK = 0x5, 143}; 144 145/* ALLOC/FREE input queues Enumeration from coprocessors */ 146enum npa_inpq { 147 NPA_INPQ_NIX0_RX = 0x0, 148 NPA_INPQ_NIX0_TX = 0x1, 149 NPA_INPQ_NIX1_RX = 0x2, 150 NPA_INPQ_NIX1_TX = 0x3, 151 NPA_INPQ_SSO = 0x4, 152 NPA_INPQ_TIM = 0x5, 153 NPA_INPQ_DPI = 0x6, 154 NPA_INPQ_AURA_OP = 0xe, 155 NPA_INPQ_INTERNAL_RSV = 0xf, 156}; 157 158/* NPA admin queue instruction structure */ 159struct npa_aq_inst_s { 160 u64 op : 4; /* W0 */ 161 u64 ctype : 4; 162 u64 lf : 9; 163 u64 reserved_17_23 : 7; 164 u64 cindex : 20; 165 u64 reserved_44_62 : 19; 166 u64 doneint : 1; 167 u64 res_addr; /* W1 */ 168}; 169 170/* NPA admin queue result structure */ 171struct npa_aq_res_s { 172 u64 op : 4; /* W0 */ 173 u64 ctype : 4; 174 u64 compcode : 8; 175 u64 doneint : 1; 176 u64 reserved_17_63 : 47; 177 u64 reserved_64_127; /* W1 */ 178}; 179 180struct npa_aura_s { 181 u64 pool_addr; /* W0 */ 182 u64 ena : 1; /* W1 */ 183 u64 reserved_65 : 2; 184 u64 pool_caching : 1; 185 u64 pool_way_mask : 16; 186 u64 avg_con : 9; 187 u64 reserved_93 : 1; 188 u64 pool_drop_ena : 1; 189 u64 aura_drop_ena : 1; 190 u64 bp_ena : 2; 191 u64 reserved_98_103 : 6; 192 u64 aura_drop : 8; 193 u64 shift : 6; 194 u64 reserved_118_119 : 2; 195 u64 avg_level : 8; 196 u64 count : 36; /* W2 */ 197 u64 reserved_164_167 : 4; 198 u64 nix0_bpid : 9; 199 u64 reserved_177_179 : 3; 200 u64 nix1_bpid : 9; 201 u64 reserved_189_191 : 3; 202 u64 limit : 36; /* W3 */ 203 u64 reserved_228_231 : 4; 204 u64 bp : 8; 205 u64 reserved_241_243 : 3; 206 u64 fc_be : 1; 207 u64 fc_ena : 1; 208 u64 fc_up_crossing : 1; 209 u64 fc_stype : 2; 210 u64 fc_hyst_bits : 4; 211 u64 reserved_252_255 : 4; 212 u64 fc_addr; /* W4 */ 213 u64 pool_drop : 8; /* W5 */ 214 u64 update_time : 16; 215 u64 err_int : 8; 216 u64 err_int_ena : 8; 217 u64 thresh_int : 1; 218 u64 thresh_int_ena : 1; 219 u64 thresh_up : 1; 220 u64 reserved_363 : 1; 221 u64 thresh_qint_idx : 7; 222 u64 reserved_371 : 1; 223 u64 err_qint_idx : 7; 224 u64 reserved_379_383 : 5; 225 u64 thresh : 36; /* W6*/ 226 u64 rsvd_423_420 : 4; 227 u64 fc_msh_dst : 11; 228 u64 reserved_435_447 : 13; 229 u64 reserved_448_511; /* W7 */ 230}; 231 232struct npa_pool_s { 233 u64 stack_base; /* W0 */ 234 u64 ena : 1; 235 u64 nat_align : 1; 236 u64 reserved_66_67 : 2; 237 u64 stack_caching : 1; 238 u64 reserved_70_71 : 3; 239 u64 stack_way_mask : 16; 240 u64 buf_offset : 12; 241 u64 reserved_100_103 : 4; 242 u64 buf_size : 11; 243 u64 reserved_115_127 : 13; 244 u64 stack_max_pages : 32; 245 u64 stack_pages : 32; 246 u64 op_pc : 48; 247 u64 reserved_240_255 : 16; 248 u64 stack_offset : 4; 249 u64 reserved_260_263 : 4; 250 u64 shift : 6; 251 u64 reserved_270_271 : 2; 252 u64 avg_level : 8; 253 u64 avg_con : 9; 254 u64 fc_ena : 1; 255 u64 fc_stype : 2; 256 u64 fc_hyst_bits : 4; 257 u64 fc_up_crossing : 1; 258 u64 fc_be : 1; 259 u64 reserved_298_299 : 2; 260 u64 update_time : 16; 261 u64 reserved_316_319 : 4; 262 u64 fc_addr; /* W5 */ 263 u64 ptr_start; /* W6 */ 264 u64 ptr_end; /* W7 */ 265 u64 reserved_512_535 : 24; 266 u64 err_int : 8; 267 u64 err_int_ena : 8; 268 u64 thresh_int : 1; 269 u64 thresh_int_ena : 1; 270 u64 thresh_up : 1; 271 u64 reserved_555 : 1; 272 u64 thresh_qint_idx : 7; 273 u64 reserved_563 : 1; 274 u64 err_qint_idx : 7; 275 u64 reserved_571_575 : 5; 276 u64 thresh : 36; 277 u64 rsvd_615_612 : 4; 278 u64 fc_msh_dst : 11; 279 u64 reserved_627_639 : 13; 280 u64 reserved_640_703; /* W10 */ 281 u64 reserved_704_767; /* W11 */ 282 u64 reserved_768_831; /* W12 */ 283 u64 reserved_832_895; /* W13 */ 284 u64 reserved_896_959; /* W14 */ 285 u64 reserved_960_1023; /* W15 */ 286}; 287 288/* NIX admin queue completion status */ 289enum nix_aq_comp { 290 NIX_AQ_COMP_NOTDONE = 0x0, 291 NIX_AQ_COMP_GOOD = 0x1, 292 NIX_AQ_COMP_SWERR = 0x2, 293 NIX_AQ_COMP_CTX_POISON = 0x3, 294 NIX_AQ_COMP_CTX_FAULT = 0x4, 295 NIX_AQ_COMP_LOCKERR = 0x5, 296 NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6, 297}; 298 299/* NIX admin queue context types */ 300enum nix_aq_ctype { 301 NIX_AQ_CTYPE_RQ = 0x0, 302 NIX_AQ_CTYPE_SQ = 0x1, 303 NIX_AQ_CTYPE_CQ = 0x2, 304 NIX_AQ_CTYPE_MCE = 0x3, 305 NIX_AQ_CTYPE_RSS = 0x4, 306 NIX_AQ_CTYPE_DYNO = 0x5, 307 NIX_AQ_CTYPE_BANDPROF = 0x6, 308}; 309 310/* NIX admin queue instruction opcodes */ 311enum nix_aq_instop { 312 NIX_AQ_INSTOP_NOP = 0x0, 313 NIX_AQ_INSTOP_INIT = 0x1, 314 NIX_AQ_INSTOP_WRITE = 0x2, 315 NIX_AQ_INSTOP_READ = 0x3, 316 NIX_AQ_INSTOP_LOCK = 0x4, 317 NIX_AQ_INSTOP_UNLOCK = 0x5, 318}; 319 320/* NIX admin queue instruction structure */ 321struct nix_aq_inst_s { 322 u64 op : 4; 323 u64 ctype : 4; 324 u64 lf : 9; 325 u64 reserved_17_23 : 7; 326 u64 cindex : 20; 327 u64 reserved_44_62 : 19; 328 u64 doneint : 1; 329 u64 res_addr; /* W1 */ 330}; 331 332/* NIX admin queue result structure */ 333struct nix_aq_res_s { 334 u64 op : 4; 335 u64 ctype : 4; 336 u64 compcode : 8; 337 u64 doneint : 1; 338 u64 reserved_17_63 : 47; 339 u64 reserved_64_127; /* W1 */ 340}; 341 342/* NIX Completion queue context structure */ 343struct nix_cq_ctx_s { 344 u64 base; 345 u64 lbp_ena : 1; 346 u64 lbpid_low : 3; 347 u64 bp_ena : 1; 348 u64 lbpid_med : 3; 349 u64 bpid : 9; 350 u64 lbpid_high : 3; 351 u64 qint_idx : 7; 352 u64 cq_err : 1; 353 u64 cint_idx : 7; 354 u64 avg_con : 9; 355 u64 wrptr : 20; 356 u64 tail : 20; 357 u64 head : 20; 358 u64 avg_level : 8; 359 u64 update_time : 16; 360 u64 bp : 8; 361 u64 drop : 8; 362 u64 drop_ena : 1; 363 u64 ena : 1; 364 u64 cpt_drop_err_en : 1; 365 u64 rsvd_211 : 1; 366 u64 substream : 12; 367 u64 stash_thresh : 4; 368 u64 lbp_frac : 4; 369 u64 caching : 1; 370 u64 stashing : 1; 371 u64 rsvd_234_235 : 2; 372 u64 qsize : 4; 373 u64 cq_err_int : 8; 374 u64 cq_err_int_ena : 8; 375 /* Ensure all context sizes are 128 bytes */ 376 u64 padding[12]; 377}; 378 379static_assert(sizeof(struct nix_cq_ctx_s) == NIX_MAX_CTX_SIZE); 380 381/* CN10K NIX Receive queue context structure */ 382struct nix_cn10k_rq_ctx_s { 383 u64 ena : 1; 384 u64 sso_ena : 1; 385 u64 ipsech_ena : 1; 386 u64 ena_wqwd : 1; 387 u64 cq : 20; 388 u64 rsvd_36_24 : 13; 389 u64 lenerr_dis : 1; 390 u64 csum_il4_dis : 1; 391 u64 csum_ol4_dis : 1; 392 u64 len_il4_dis : 1; 393 u64 len_il3_dis : 1; 394 u64 len_ol4_dis : 1; 395 u64 len_ol3_dis : 1; 396 u64 wqe_aura : 20; 397 u64 spb_aura : 20; 398 u64 lpb_aura : 20; 399 u64 sso_grp : 10; 400 u64 sso_tt : 2; 401 u64 pb_caching : 2; 402 u64 wqe_caching : 1; 403 u64 xqe_drop_ena : 1; 404 u64 spb_drop_ena : 1; 405 u64 lpb_drop_ena : 1; 406 u64 pb_stashing : 1; 407 u64 ipsecd_drop_ena : 1; 408 u64 chi_ena : 1; 409 u64 rsvd_127_125 : 3; 410 u64 band_prof_id : 10; /* W2 */ 411 u64 rsvd_138 : 1; 412 u64 policer_ena : 1; 413 u64 spb_sizem1 : 6; 414 u64 wqe_skip : 2; 415 u64 rsvd_150_148 : 3; 416 u64 spb_ena : 1; 417 u64 lpb_sizem1 : 12; 418 u64 first_skip : 7; 419 u64 rsvd_171 : 1; 420 u64 later_skip : 6; 421 u64 xqe_imm_size : 6; 422 u64 band_prof_id_h : 4; 423 u64 rsvd_189_188 : 2; 424 u64 xqe_imm_copy : 1; 425 u64 xqe_hdr_split : 1; 426 u64 xqe_drop : 8; /* W3 */ 427 u64 xqe_pass : 8; 428 u64 wqe_pool_drop : 8; 429 u64 wqe_pool_pass : 8; 430 u64 spb_aura_drop : 8; 431 u64 spb_aura_pass : 8; 432 u64 spb_pool_drop : 8; 433 u64 spb_pool_pass : 8; 434 u64 lpb_aura_drop : 8; /* W4 */ 435 u64 lpb_aura_pass : 8; 436 u64 lpb_pool_drop : 8; 437 u64 lpb_pool_pass : 8; 438 u64 rsvd_291_288 : 4; 439 u64 rq_int : 8; 440 u64 rq_int_ena : 8; 441 u64 qint_idx : 7; 442 u64 rsvd_319_315 : 5; 443 u64 ltag : 24; /* W5 */ 444 u64 good_utag : 8; 445 u64 bad_utag : 8; 446 u64 flow_tagw : 6; 447 u64 ipsec_vwqe : 1; 448 u64 vwqe_ena : 1; 449 u64 vwqe_wait : 8; 450 u64 max_vsize_exp : 4; 451 u64 vwqe_skip : 2; 452 u64 rsvd_383_382 : 2; 453 u64 octs : 48; /* W6 */ 454 u64 rsvd_447_432 : 16; 455 u64 pkts : 48; /* W7 */ 456 u64 rsvd_511_496 : 16; 457 u64 drop_octs : 48; /* W8 */ 458 u64 rsvd_575_560 : 16; 459 u64 drop_pkts : 48; /* W9 */ 460 u64 rsvd_639_624 : 16; 461 u64 re_pkts : 48; /* W10 */ 462 u64 rsvd_703_688 : 16; 463 u64 rsvd_767_704; /* W11 */ 464 u64 rsvd_831_768; /* W12 */ 465 u64 rsvd_895_832; /* W13 */ 466 u64 rsvd_959_896; /* W14 */ 467 u64 rsvd_1023_960; /* W15 */ 468}; 469 470static_assert(sizeof(struct nix_cn10k_rq_ctx_s) == NIX_MAX_CTX_SIZE); 471 472/* CN10K NIX Send queue context structure */ 473struct nix_cn10k_sq_ctx_s { 474 u64 ena : 1; 475 u64 qint_idx : 6; 476 u64 substream : 20; 477 u64 sdp_mcast : 1; 478 u64 cq : 20; 479 u64 sqe_way_mask : 16; 480 u64 smq : 10; /* W1 */ 481 u64 cq_ena : 1; 482 u64 xoff : 1; 483 u64 sso_ena : 1; 484 u64 smq_rr_weight : 14; 485 u64 default_chan : 12; 486 u64 sqb_count : 16; 487 u64 rsvd_120_119 : 2; 488 u64 smq_rr_count_lb : 7; 489 u64 smq_rr_count_ub : 25; /* W2 */ 490 u64 sqb_aura : 20; 491 u64 sq_int : 8; 492 u64 sq_int_ena : 8; 493 u64 sqe_stype : 2; 494 u64 rsvd_191 : 1; 495 u64 max_sqe_size : 2; /* W3 */ 496 u64 cq_limit : 8; 497 u64 lmt_dis : 1; 498 u64 mnq_dis : 1; 499 u64 smq_next_sq : 20; 500 u64 smq_lso_segnum : 8; 501 u64 tail_offset : 6; 502 u64 smenq_offset : 6; 503 u64 head_offset : 6; 504 u64 smenq_next_sqb_vld : 1; 505 u64 smq_pend : 1; 506 u64 smq_next_sq_vld : 1; 507 u64 rsvd_255_253 : 3; 508 u64 next_sqb : 64; /* W4 */ 509 u64 tail_sqb : 64; /* W5 */ 510 u64 smenq_sqb : 64; /* W6 */ 511 u64 smenq_next_sqb : 64; /* W7 */ 512 u64 head_sqb : 64; /* W8 */ 513 u64 rsvd_583_576 : 8; /* W9 */ 514 u64 vfi_lso_total : 18; 515 u64 vfi_lso_sizem1 : 3; 516 u64 vfi_lso_sb : 8; 517 u64 vfi_lso_mps : 14; 518 u64 vfi_lso_vlan0_ins_ena : 1; 519 u64 vfi_lso_vlan1_ins_ena : 1; 520 u64 vfi_lso_vld : 1; 521 u64 rsvd_639_630 : 10; 522 u64 scm_lso_rem : 18; /* W10 */ 523 u64 rsvd_703_658 : 46; 524 u64 octs : 48; /* W11 */ 525 u64 rsvd_767_752 : 16; 526 u64 pkts : 48; /* W12 */ 527 u64 rsvd_831_816 : 16; 528 u64 rsvd_895_832 : 64; /* W13 */ 529 u64 dropped_octs : 48; 530 u64 rsvd_959_944 : 16; 531 u64 dropped_pkts : 48; 532 u64 rsvd_1023_1008 : 16; 533}; 534 535static_assert(sizeof(struct nix_cn10k_sq_ctx_s) == NIX_MAX_CTX_SIZE); 536 537/* NIX Receive queue context structure */ 538struct nix_rq_ctx_s { 539 u64 ena : 1; 540 u64 sso_ena : 1; 541 u64 ipsech_ena : 1; 542 u64 ena_wqwd : 1; 543 u64 cq : 20; 544 u64 substream : 20; 545 u64 wqe_aura : 20; 546 u64 spb_aura : 20; 547 u64 lpb_aura : 20; 548 u64 sso_grp : 10; 549 u64 sso_tt : 2; 550 u64 pb_caching : 2; 551 u64 wqe_caching : 1; 552 u64 xqe_drop_ena : 1; 553 u64 spb_drop_ena : 1; 554 u64 lpb_drop_ena : 1; 555 u64 rsvd_127_122 : 6; 556 u64 rsvd_139_128 : 12; /* W2 */ 557 u64 spb_sizem1 : 6; 558 u64 wqe_skip : 2; 559 u64 rsvd_150_148 : 3; 560 u64 spb_ena : 1; 561 u64 lpb_sizem1 : 12; 562 u64 first_skip : 7; 563 u64 rsvd_171 : 1; 564 u64 later_skip : 6; 565 u64 xqe_imm_size : 6; 566 u64 rsvd_189_184 : 6; 567 u64 xqe_imm_copy : 1; 568 u64 xqe_hdr_split : 1; 569 u64 xqe_drop : 8; /* W3*/ 570 u64 xqe_pass : 8; 571 u64 wqe_pool_drop : 8; 572 u64 wqe_pool_pass : 8; 573 u64 spb_aura_drop : 8; 574 u64 spb_aura_pass : 8; 575 u64 spb_pool_drop : 8; 576 u64 spb_pool_pass : 8; 577 u64 lpb_aura_drop : 8; /* W4 */ 578 u64 lpb_aura_pass : 8; 579 u64 lpb_pool_drop : 8; 580 u64 lpb_pool_pass : 8; 581 u64 rsvd_291_288 : 4; 582 u64 rq_int : 8; 583 u64 rq_int_ena : 8; 584 u64 qint_idx : 7; 585 u64 rsvd_319_315 : 5; 586 u64 ltag : 24; /* W5 */ 587 u64 good_utag : 8; 588 u64 bad_utag : 8; 589 u64 flow_tagw : 6; 590 u64 rsvd_383_366 : 18; 591 u64 octs : 48; /* W6 */ 592 u64 rsvd_447_432 : 16; 593 u64 pkts : 48; /* W7 */ 594 u64 rsvd_511_496 : 16; 595 u64 drop_octs : 48; /* W8 */ 596 u64 rsvd_575_560 : 16; 597 u64 drop_pkts : 48; /* W9 */ 598 u64 rsvd_639_624 : 16; 599 u64 re_pkts : 48; /* W10 */ 600 u64 rsvd_703_688 : 16; 601 u64 rsvd_767_704; /* W11 */ 602 u64 rsvd_831_768; /* W12 */ 603 u64 rsvd_895_832; /* W13 */ 604 u64 rsvd_959_896; /* W14 */ 605 u64 rsvd_1023_960; /* W15 */ 606}; 607 608static_assert(sizeof(struct nix_rq_ctx_s) == NIX_MAX_CTX_SIZE); 609 610/* NIX sqe sizes */ 611enum nix_maxsqesz { 612 NIX_MAXSQESZ_W16 = 0x0, 613 NIX_MAXSQESZ_W8 = 0x1, 614}; 615 616/* NIX SQB caching type */ 617enum nix_stype { 618 NIX_STYPE_STF = 0x0, 619 NIX_STYPE_STT = 0x1, 620 NIX_STYPE_STP = 0x2, 621}; 622 623/* NIX Send queue context structure */ 624struct nix_sq_ctx_s { 625 u64 ena : 1; 626 u64 qint_idx : 6; 627 u64 substream : 20; 628 u64 sdp_mcast : 1; 629 u64 cq : 20; 630 u64 sqe_way_mask : 16; 631 u64 smq : 9; 632 u64 cq_ena : 1; 633 u64 xoff : 1; 634 u64 sso_ena : 1; 635 u64 smq_rr_quantum : 24; 636 u64 default_chan : 12; 637 u64 sqb_count : 16; 638 u64 smq_rr_count : 25; 639 u64 sqb_aura : 20; 640 u64 sq_int : 8; 641 u64 sq_int_ena : 8; 642 u64 sqe_stype : 2; 643 u64 rsvd_191 : 1; 644 u64 max_sqe_size : 2; 645 u64 cq_limit : 8; 646 u64 lmt_dis : 1; 647 u64 mnq_dis : 1; 648 u64 smq_next_sq : 20; 649 u64 smq_lso_segnum : 8; 650 u64 tail_offset : 6; 651 u64 smenq_offset : 6; 652 u64 head_offset : 6; 653 u64 smenq_next_sqb_vld : 1; 654 u64 smq_pend : 1; 655 u64 smq_next_sq_vld : 1; 656 u64 rsvd_255_253 : 3; 657 u64 next_sqb : 64;/* W4 */ 658 u64 tail_sqb : 64;/* W5 */ 659 u64 smenq_sqb : 64;/* W6 */ 660 u64 smenq_next_sqb : 64;/* W7 */ 661 u64 head_sqb : 64;/* W8 */ 662 u64 rsvd_583_576 : 8; 663 u64 vfi_lso_total : 18; 664 u64 vfi_lso_sizem1 : 3; 665 u64 vfi_lso_sb : 8; 666 u64 vfi_lso_mps : 14; 667 u64 vfi_lso_vlan0_ins_ena : 1; 668 u64 vfi_lso_vlan1_ins_ena : 1; 669 u64 vfi_lso_vld : 1; 670 u64 rsvd_639_630 : 10; 671 u64 scm_lso_rem : 18; 672 u64 rsvd_703_658 : 46; 673 u64 octs : 48; 674 u64 rsvd_767_752 : 16; 675 u64 pkts : 48; 676 u64 rsvd_831_816 : 16; 677 u64 rsvd_895_832 : 64;/* W13 */ 678 u64 dropped_octs : 48; 679 u64 rsvd_959_944 : 16; 680 u64 dropped_pkts : 48; 681 u64 rsvd_1023_1008 : 16; 682}; 683 684static_assert(sizeof(struct nix_sq_ctx_s) == NIX_MAX_CTX_SIZE); 685 686/* NIX Receive side scaling entry structure*/ 687struct nix_rsse_s { 688 uint32_t rq : 20; 689 uint32_t reserved_20_31 : 12; 690 /* Ensure all context sizes are minimum 128 bytes */ 691 u64 padding[15]; 692}; 693 694static_assert(sizeof(struct nix_rsse_s) == NIX_MAX_CTX_SIZE); 695 696/* NIX receive multicast/mirror entry structure */ 697struct nix_rx_mce_s { 698 uint64_t op : 2; 699 uint64_t rsvd_2 : 1; 700 uint64_t eol : 1; 701 uint64_t index : 20; 702 uint64_t rsvd_31_24 : 8; 703 uint64_t pf_func : 16; 704 uint64_t next : 16; 705 /* Ensure all context sizes are minimum 128 bytes */ 706 u64 padding[15]; 707}; 708 709static_assert(sizeof(struct nix_rx_mce_s) == NIX_MAX_CTX_SIZE); 710 711enum nix_band_prof_layers { 712 BAND_PROF_LEAF_LAYER = 0, 713 BAND_PROF_INVAL_LAYER = 1, 714 BAND_PROF_MID_LAYER = 2, 715 BAND_PROF_TOP_LAYER = 3, 716 BAND_PROF_NUM_LAYERS = 4, 717}; 718 719enum NIX_RX_BAND_PROF_ACTIONRESULT_E { 720 NIX_RX_BAND_PROF_ACTIONRESULT_PASS = 0x0, 721 NIX_RX_BAND_PROF_ACTIONRESULT_DROP = 0x1, 722 NIX_RX_BAND_PROF_ACTIONRESULT_RED = 0x2, 723}; 724 725enum nix_band_prof_pc_mode { 726 NIX_RX_PC_MODE_VLAN = 0, 727 NIX_RX_PC_MODE_DSCP = 1, 728 NIX_RX_PC_MODE_GEN = 2, 729 NIX_RX_PC_MODE_RSVD = 3, 730}; 731 732/* NIX ingress policer bandwidth profile structure */ 733struct nix_bandprof_s { 734 uint64_t pc_mode : 2; /* W0 */ 735 uint64_t icolor : 2; 736 uint64_t tnl_ena : 1; 737 uint64_t reserved_5_7 : 3; 738 uint64_t peir_exponent : 5; 739 uint64_t reserved_13_15 : 3; 740 uint64_t pebs_exponent : 5; 741 uint64_t reserved_21_23 : 3; 742 uint64_t cir_exponent : 5; 743 uint64_t reserved_29_31 : 3; 744 uint64_t cbs_exponent : 5; 745 uint64_t reserved_37_39 : 3; 746 uint64_t peir_mantissa : 8; 747 uint64_t pebs_mantissa : 8; 748 uint64_t cir_mantissa : 8; 749 uint64_t cbs_mantissa : 8; /* W1 */ 750 uint64_t lmode : 1; 751 uint64_t l_sellect : 3; 752 uint64_t rdiv : 4; 753 uint64_t adjust_exponent : 5; 754 uint64_t reserved_85_86 : 2; 755 uint64_t adjust_mantissa : 9; 756 uint64_t gc_action : 2; 757 uint64_t yc_action : 2; 758 uint64_t rc_action : 2; 759 uint64_t meter_algo : 2; 760 uint64_t band_prof_id : 7; 761 uint64_t band_prof_id_h : 4; 762 uint64_t reserved_115_118 : 4; 763 uint64_t hl_en : 1; 764 uint64_t reserved_120_127 : 8; 765 uint64_t ts : 48; /* W2 */ 766 uint64_t reserved_176_191 : 16; 767 uint64_t pe_accum : 32; /* W3 */ 768 uint64_t c_accum : 32; 769 uint64_t green_pkt_pass : 48; /* W4 */ 770 uint64_t reserved_304_319 : 16; 771 uint64_t yellow_pkt_pass : 48; /* W5 */ 772 uint64_t reserved_368_383 : 16; 773 uint64_t red_pkt_pass : 48; /* W6 */ 774 uint64_t reserved_432_447 : 16; 775 uint64_t green_octs_pass : 48; /* W7 */ 776 uint64_t reserved_496_511 : 16; 777 uint64_t yellow_octs_pass : 48; /* W8 */ 778 uint64_t reserved_560_575 : 16; 779 uint64_t red_octs_pass : 48; /* W9 */ 780 uint64_t reserved_624_639 : 16; 781 uint64_t green_pkt_drop : 48; /* W10 */ 782 uint64_t reserved_688_703 : 16; 783 uint64_t yellow_pkt_drop : 48; /* W11 */ 784 uint64_t reserved_752_767 : 16; 785 uint64_t red_pkt_drop : 48; /* W12 */ 786 uint64_t reserved_816_831 : 16; 787 uint64_t green_octs_drop : 48; /* W13 */ 788 uint64_t reserved_880_895 : 16; 789 uint64_t yellow_octs_drop : 48; /* W14 */ 790 uint64_t reserved_944_959 : 16; 791 uint64_t red_octs_drop : 48; /* W15 */ 792 uint64_t reserved_1008_1023 : 16; 793}; 794 795static_assert(sizeof(struct nix_bandprof_s) == NIX_MAX_CTX_SIZE); 796 797enum nix_lsoalg { 798 NIX_LSOALG_NOP, 799 NIX_LSOALG_ADD_SEGNUM, 800 NIX_LSOALG_ADD_PAYLEN, 801 NIX_LSOALG_ADD_OFFSET, 802 NIX_LSOALG_TCP_FLAGS, 803}; 804 805enum nix_txlayer { 806 NIX_TXLAYER_OL3, 807 NIX_TXLAYER_OL4, 808 NIX_TXLAYER_IL3, 809 NIX_TXLAYER_IL4, 810}; 811 812struct nix_lso_format { 813 u64 offset : 8; 814 u64 layer : 2; 815 u64 rsvd_10_11 : 2; 816 u64 sizem1 : 2; 817 u64 rsvd_14_15 : 2; 818 u64 alg : 3; 819 u64 rsvd_19_63 : 45; 820}; 821 822struct nix_rx_flowkey_alg { 823 u64 key_offset :6; 824 u64 ln_mask :1; 825 u64 fn_mask :1; 826 u64 hdr_offset :8; 827 u64 bytesm1 :5; 828 u64 lid :3; 829 u64 reserved_24_24 :1; 830 u64 ena :1; 831 u64 sel_chan :1; 832 u64 ltype_mask :4; 833 u64 ltype_match :4; 834 u64 reserved_35_63 :29; 835}; 836 837/* NIX VTAG size */ 838enum nix_vtag_size { 839 VTAGSIZE_T4 = 0x0, 840 VTAGSIZE_T8 = 0x1, 841}; 842 843enum nix_tx_vtag_op { 844 NOP = 0x0, 845 VTAG_INSERT = 0x1, 846 VTAG_REPLACE = 0x2, 847}; 848 849/* NIX RX VTAG actions */ 850#define VTAG_STRIP BIT_ULL(4) 851#define VTAG_CAPTURE BIT_ULL(5) 852 853/* NIX TX stats */ 854enum nix_stat_lf_tx { 855 TX_UCAST = 0x0, 856 TX_BCAST = 0x1, 857 TX_MCAST = 0x2, 858 TX_DROP = 0x3, 859 TX_OCTS = 0x4, 860 TX_STATS_ENUM_LAST, 861}; 862 863/* NIX RX stats */ 864enum nix_stat_lf_rx { 865 RX_OCTS = 0x0, 866 RX_UCAST = 0x1, 867 RX_BCAST = 0x2, 868 RX_MCAST = 0x3, 869 RX_DROP = 0x4, 870 RX_DROP_OCTS = 0x5, 871 RX_FCS = 0x6, 872 RX_ERR = 0x7, 873 RX_DRP_BCAST = 0x8, 874 RX_DRP_MCAST = 0x9, 875 RX_DRP_L3BCAST = 0xa, 876 RX_DRP_L3MCAST = 0xb, 877 RX_STATS_ENUM_LAST, 878}; 879#endif /* RVU_STRUCT_H */
~/
Read-only file preview.