FILE
rvu_reg.h
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linux-6.19.14/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef RVU_REG_H 9#define RVU_REG_H 10 11/* Admin function registers */ 12#define RVU_AF_MSIXTR_BASE (0x10) 13#define RVU_AF_ECO (0x20) 14#define RVU_AF_BLK_RST (0x30) 15#define RVU_AF_PF_BAR4_ADDR (0x40) 16#define RVU_AF_RAS (0x100) 17#define RVU_AF_RAS_W1S (0x108) 18#define RVU_AF_RAS_ENA_W1S (0x110) 19#define RVU_AF_RAS_ENA_W1C (0x118) 20#define RVU_AF_GEN_INT (0x120) 21#define RVU_AF_GEN_INT_W1S (0x128) 22#define RVU_AF_GEN_INT_ENA_W1S (0x130) 23#define RVU_AF_GEN_INT_ENA_W1C (0x138) 24#define RVU_AF_AFPF_MBOX0 (0x02000) 25#define RVU_AF_AFPF_MBOX1 (0x02008) 26#define RVU_AF_AFPFX_MBOXX(a, b) (0x2000 | (a) << 4 | (b) << 3) 27#define RVU_AF_PFME_STATUS (0x2800) 28#define RVU_AF_PFTRPEND (0x2810) 29#define RVU_AF_PFTRPEND_W1S (0x2820) 30#define RVU_AF_PF_RST (0x2840) 31#define RVU_AF_HWVF_RST (0x2850) 32#define RVU_AF_PFAF_MBOX_INT (0x2880) 33#define RVU_AF_PFAF_MBOX_INT_W1S (0x2888) 34#define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890) 35#define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898) 36#define RVU_AF_PFFLR_INT (0x28a0) 37#define RVU_AF_PFFLR_INT_W1S (0x28a8) 38#define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0) 39#define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8) 40#define RVU_AF_PFME_INT (0x28c0) 41#define RVU_AF_PFME_INT_W1S (0x28c8) 42#define RVU_AF_PFME_INT_ENA_W1S (0x28d0) 43#define RVU_AF_PFME_INT_ENA_W1C (0x28d8) 44#define RVU_AF_PFX_BAR4_ADDR(a) (0x5000 | (a) << 4) 45#define RVU_AF_PFX_BAR4_CFG (0x5200 | (a) << 4) 46#define RVU_AF_PFX_VF_BAR4_ADDR (0x5400 | (a) << 4) 47#define RVU_AF_PFX_VF_BAR4_CFG (0x5600 | (a) << 4) 48#define RVU_AF_PFX_LMTLINE_ADDR (0x5800 | (a) << 4) 49#define RVU_AF_SMMU_ADDR_REQ (0x6000) 50#define RVU_AF_SMMU_TXN_REQ (0x6008) 51#define RVU_AF_SMMU_ADDR_RSP_STS (0x6010) 52#define RVU_AF_SMMU_ADDR_TLN (0x6018) 53#define RVU_AF_SMMU_TLN_FLIT0 (0x6020) 54 55/* Admin function's privileged PF/VF registers */ 56#define RVU_PRIV_CONST (0x8000000) 57#define RVU_PRIV_GEN_CFG (0x8000010) 58#define RVU_PRIV_CLK_CFG (0x8000020) 59#define RVU_PRIV_ACTIVE_PC (0x8000030) 60#define RVU_PRIV_PFX_CFG(a) (0x8000100 | (a) << 16) 61#define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16) 62#define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16) 63#define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16) 64#define RVU_PRIV_PFX_NIXX_CFG(a) (0x8000300 | (a) << 3) 65#define RVU_PRIV_PFX_NPA_CFG (0x8000310) 66#define RVU_PRIV_PFX_SSO_CFG (0x8000320) 67#define RVU_PRIV_PFX_SSOW_CFG (0x8000330) 68#define RVU_PRIV_PFX_TIM_CFG (0x8000340) 69#define RVU_PRIV_PFX_CPTX_CFG(a) (0x8000350 | (a) << 3) 70#define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3) 71#define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16) 72#define RVU_PRIV_HWVFX_NIXX_CFG(a) (0x8001300 | (a) << 3) 73#define RVU_PRIV_HWVFX_NPA_CFG (0x8001310) 74#define RVU_PRIV_HWVFX_SSO_CFG (0x8001320) 75#define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330) 76#define RVU_PRIV_HWVFX_TIM_CFG (0x8001340) 77#define RVU_PRIV_HWVFX_CPTX_CFG(a) (0x8001350 | (a) << 3) 78 79/* RVU PF registers */ 80#define RVU_PF_VFX_PFVF_MBOX0 (0x00000) 81#define RVU_PF_VFX_PFVF_MBOX1 (0x00008) 82#define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) 83#define RVU_PF_VF_BAR4_ADDR (0x10) 84#define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) 85#define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) 86#define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) 87#define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) 88#define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) 89#define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) 90#define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3) 91#define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3) 92#define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) 93#define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3) 94#define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) 95#define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3) 96#define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3) 97#define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3) 98#define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) 99#define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3) 100#define RVU_PF_PFAF_MBOX0 (0xC00) 101#define RVU_PF_PFAF_MBOX1 (0xC08) 102#define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3) 103#define RVU_PF_INT (0xc20) 104#define RVU_PF_INT_W1S (0xc28) 105#define RVU_PF_INT_ENA_W1S (0xc30) 106#define RVU_PF_INT_ENA_W1C (0xc38) 107#define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) 108#define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) 109#define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3) 110#define RVU_PF_VF_MBOX_ADDR (0xC40) 111#define RVU_PF_LMTLINE_ADDR (0xC48) 112 113/* RVU VF registers */ 114#define RVU_VF_VFPF_MBOX0 (0x00000) 115#define RVU_VF_VFPF_MBOX1 (0x00008) 116 117/* NPA block's admin function registers */ 118#define NPA_AF_BLK_RST (0x0000) 119#define NPA_AF_CONST (0x0010) 120#define NPA_AF_CONST1 (0x0018) 121#define NPA_AF_LF_RST (0x0020) 122#define NPA_AF_GEN_CFG (0x0030) 123#define NPA_AF_NDC_CFG (0x0040) 124#define NPA_AF_NDC_SYNC (0x0050) 125#define NPA_AF_INP_CTL (0x00D0) 126#define NPA_AF_ACTIVE_CYCLES_PC (0x00F0) 127#define NPA_AF_AVG_DELAY (0x0100) 128#define NPA_AF_GEN_INT (0x0140) 129#define NPA_AF_GEN_INT_W1S (0x0148) 130#define NPA_AF_GEN_INT_ENA_W1S (0x0150) 131#define NPA_AF_GEN_INT_ENA_W1C (0x0158) 132#define NPA_AF_RVU_INT (0x0160) 133#define NPA_AF_RVU_INT_W1S (0x0168) 134#define NPA_AF_RVU_INT_ENA_W1S (0x0170) 135#define NPA_AF_RVU_INT_ENA_W1C (0x0178) 136#define NPA_AF_ERR_INT (0x0180) 137#define NPA_AF_ERR_INT_W1S (0x0188) 138#define NPA_AF_ERR_INT_ENA_W1S (0x0190) 139#define NPA_AF_ERR_INT_ENA_W1C (0x0198) 140#define NPA_AF_RAS (0x01A0) 141#define NPA_AF_RAS_W1S (0x01A8) 142#define NPA_AF_RAS_ENA_W1S (0x01B0) 143#define NPA_AF_RAS_ENA_W1C (0x01B8) 144#define NPA_AF_BP_TEST (0x0200) 145#define NPA_AF_ECO (0x0300) 146#define NPA_AF_AQ_CFG (0x0600) 147#define NPA_AF_AQ_BASE (0x0610) 148#define NPA_AF_AQ_STATUS (0x0620) 149#define NPA_AF_AQ_DOOR (0x0630) 150#define NPA_AF_AQ_DONE_WAIT (0x0640) 151#define NPA_AF_AQ_DONE (0x0650) 152#define NPA_AF_AQ_DONE_ACK (0x0660) 153#define NPA_AF_AQ_DONE_INT (0x0680) 154#define NPA_AF_AQ_DONE_INT_W1S (0x0688) 155#define NPA_AF_AQ_DONE_ENA_W1S (0x0690) 156#define NPA_AF_AQ_DONE_ENA_W1C (0x0698) 157#define NPA_AF_BATCH_CTL (0x06a0) 158#define NPA_AF_LFX_AURAS_CFG(a) (0x4000 | (a) << 18) 159#define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010 | (a) << 18) 160#define NPA_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 18) 161#define NPA_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 18) 162#define NPA_PRIV_AF_INT_CFG (0x10000) 163#define NPA_PRIV_LFX_CFG (0x10010) 164#define NPA_PRIV_LFX_INT_CFG (0x10020) 165#define NPA_AF_RVU_LF_CFG_DEBUG (0x10030) 166 167/* NIX block's admin function registers */ 168#define NIX_AF_CFG (0x0000) 169#define NIX_AF_STATUS (0x0010) 170#define NIX_AF_NDC_CFG (0x0018) 171#define NIX_AF_CONST (0x0020) 172#define NIX_AF_CONST1 (0x0028) 173#define NIX_AF_CONST2 (0x0030) 174#define NIX_AF_CONST3 (0x0038) 175#define NIX_AF_SQ_CONST (0x0040) 176#define NIX_AF_CQ_CONST (0x0048) 177#define NIX_AF_RQ_CONST (0x0050) 178#define NIX_AF_PL_CONST (0x0058) 179#define NIX_AF_PSE_CONST (0x0060) 180#define NIX_AF_TL1_CONST (0x0070) 181#define NIX_AF_TL2_CONST (0x0078) 182#define NIX_AF_TL3_CONST (0x0080) 183#define NIX_AF_TL4_CONST (0x0088) 184#define NIX_AF_MDQ_CONST (0x0090) 185#define NIX_AF_MC_MIRROR_CONST (0x0098) 186#define NIX_AF_LSO_CFG (0x00A8) 187#define NIX_AF_BLK_RST (0x00B0) 188#define NIX_AF_TX_TSTMP_CFG (0x00C0) 189#define NIX_AF_PL_TS (0x00C8) 190#define NIX_AF_RX_CFG (0x00D0) 191#define NIX_AF_AVG_DELAY (0x00E0) 192#define NIX_AF_CINT_DELAY (0x00F0) 193#define NIX_AF_VWQE_TIMER (0x00F8) 194#define NIX_AF_RX_MCAST_BASE (0x0100) 195#define NIX_AF_RX_MCAST_CFG (0x0110) 196#define NIX_AF_RX_MCAST_BUF_BASE (0x0120) 197#define NIX_AF_RX_MCAST_BUF_CFG (0x0130) 198#define NIX_AF_RX_MIRROR_BUF_BASE (0x0140) 199#define NIX_AF_RX_MIRROR_BUF_CFG (0x0148) 200#define NIX_AF_LF_RST (0x0150) 201#define NIX_AF_GEN_INT (0x0160) 202#define NIX_AF_GEN_INT_W1S (0x0168) 203#define NIX_AF_GEN_INT_ENA_W1S (0x0170) 204#define NIX_AF_GEN_INT_ENA_W1C (0x0178) 205#define NIX_AF_ERR_INT (0x0180) 206#define NIX_AF_ERR_INT_W1S (0x0188) 207#define NIX_AF_ERR_INT_ENA_W1S (0x0190) 208#define NIX_AF_ERR_INT_ENA_W1C (0x0198) 209#define NIX_AF_RAS (0x01A0) 210#define NIX_AF_RAS_W1S (0x01A8) 211#define NIX_AF_RAS_ENA_W1S (0x01B0) 212#define NIX_AF_RAS_ENA_W1C (0x01B8) 213#define NIX_AF_RVU_INT (0x01C0) 214#define NIX_AF_RVU_INT_W1S (0x01C8) 215#define NIX_AF_RVU_INT_ENA_W1S (0x01D0) 216#define NIX_AF_RVU_INT_ENA_W1C (0x01D8) 217#define NIX_AF_TCP_TIMER (0x01E0) 218#define NIX_AF_RX_DEF_ET(a) (0x01F0ull | (uint64_t)(a) << 3) 219#define NIX_AF_RX_DEF_OL2 (0x0200) 220#define NIX_AF_RX_DEF_OIP4 (0x0210) 221#define NIX_AF_RX_DEF_IIP4 (0x0220) 222#define NIX_AF_RX_DEF_VLAN0_PCP_DEI (0x0228) 223#define NIX_AF_RX_DEF_OIP6 (0x0230) 224#define NIX_AF_RX_DEF_VLAN1_PCP_DEI (0x0238) 225#define NIX_AF_RX_DEF_IIP6 (0x0240) 226#define NIX_AF_RX_DEF_OTCP (0x0250) 227#define NIX_AF_RX_DEF_ITCP (0x0260) 228#define NIX_AF_RX_DEF_OUDP (0x0270) 229#define NIX_AF_RX_DEF_IUDP (0x0280) 230#define NIX_AF_RX_DEF_OSCTP (0x0290) 231#define NIX_AF_RX_DEF_CST_APAD0 (0x0298) 232#define NIX_AF_RX_DEF_ISCTP (0x02A0) 233#define NIX_AF_RX_DEF_IPSECX (0x02B0) 234#define NIX_AF_RX_DEF_CST_APAD1 (0x02A8) 235#define NIX_AF_RX_DEF_IIP4_DSCP (0x02E0) 236#define NIX_AF_RX_DEF_OIP4_DSCP (0x02E8) 237#define NIX_AF_RX_DEF_IIP6_DSCP (0x02F0) 238#define NIX_AF_RX_DEF_OIP6_DSCP (0x02F8) 239#define NIX_AF_RX_IPSEC_GEN_CFG (0x0300) 240#define NIX_AF_RX_CPTX_INST_ADDR (0x0310) 241#define NIX_AF_RX_CPTX_INST_QSEL(a) (0x0320ull | (uint64_t)(a) << 3) 242#define NIX_AF_RX_CPTX_CREDIT(a) (0x0360ull | (uint64_t)(a) << 3) 243#define NIX_AF_NDC_RX_SYNC (0x03E0) 244#define NIX_AF_NDC_TX_SYNC (0x03F0) 245#define NIX_AF_AQ_CFG (0x0400) 246#define NIX_AF_AQ_BASE (0x0410) 247#define NIX_AF_AQ_STATUS (0x0420) 248#define NIX_AF_AQ_DOOR (0x0430) 249#define NIX_AF_AQ_DONE_WAIT (0x0440) 250#define NIX_AF_AQ_DONE (0x0450) 251#define NIX_AF_AQ_DONE_ACK (0x0460) 252#define NIX_AF_AQ_DONE_TIMER (0x0470) 253#define NIX_AF_AQ_DONE_INT (0x0480) 254#define NIX_AF_AQ_DONE_INT_W1S (0x0488) 255#define NIX_AF_AQ_DONE_ENA_W1S (0x0490) 256#define NIX_AF_AQ_DONE_ENA_W1C (0x0498) 257#define NIX_AF_RX_LINKX_SLX_SPKT_CNT (0x0500) 258#define NIX_AF_RX_LINKX_SLX_SXQE_CNT (0x0510) 259#define NIX_AF_RX_MCAST_JOBSX_SW_CNT (0x0520) 260#define NIX_AF_RX_MIRROR_JOBSX_SW_CNT (0x0530) 261#define NIX_AF_RX_LINKX_CFG(a) (0x0540 | (a) << 16) 262#define NIX_AF_RX_SW_SYNC (0x0550) 263#define NIX_AF_RX_SW_SYNC_DONE (0x0560) 264#define NIX_AF_SEB_ECO (0x0600) 265#define NIX_AF_SEB_TEST_BP (0x0610) 266#define NIX_AF_NORM_TX_FIFO_STATUS (0x0620) 267#define NIX_AF_EXPR_TX_FIFO_STATUS (0x0630) 268#define NIX_AF_SDP_TX_FIFO_STATUS (0x0640) 269#define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x0660) 270#define NIX_AF_TX_NPC_CAPTURE_INFO (0x0670) 271#define NIX_AF_SEB_CFG (0x05F0) 272#define NIX_PTP_1STEP_EN BIT_ULL(2) 273 274#define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3) 275#define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16) 276#define NIX_AF_SQM_DBG_CTL_STATUS (0x750) 277#define NIX_AF_DWRR_SDP_MTU (0x790) /* All CN10K except CN10KB */ 278#define NIX_AF_DWRR_MTUX(a) (0x790 | (a) << 16) /* Only for CN10KB */ 279#define NIX_AF_DWRR_RPM_MTU (0x7A0) 280#define NIX_AF_PSE_CHANNEL_LEVEL (0x800) 281#define NIX_AF_PSE_SHAPER_CFG (0x810) 282#define NIX_AF_TX_EXPR_CREDIT (0x830) 283#define NIX_AF_MARK_FORMATX_CTL(a) (0x900 | (a) << 18) 284#define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xA00 | (a) << 16) 285#define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xA10 | (a) << 16) 286#define NIX_AF_TX_LINKX_SW_XOFF(a) (0xA20 | (a) << 16) 287#define NIX_AF_TX_LINKX_HW_XOFF(a) (0xA30 | (a) << 16) 288#define NIX_AF_SDP_LINK_CREDIT (0xa40) 289#define NIX_AF_SDP_SW_XOFFX(a) (0xA60 | (a) << 3) 290#define NIX_AF_SDP_HW_XOFFX(a) (0xAC0 | (a) << 3) 291#define NIX_AF_TL4X_BP_STATUS(a) (0xB00 | (a) << 16) 292#define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xB10 | (a) << 16) 293#define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16) 294#define NIX_AF_TL1X_SHAPE(a) (0xC10 | (a) << 16) 295#define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16) 296#define NIX_AF_TL1X_SHAPE_STATE(a) (0xC50 | (a) << 16) 297#define NIX_AF_TL1X_SW_XOFF(a) (0xC70 | (a) << 16) 298#define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16) 299#define NIX_AF_TL1X_GREEN(a) (0xC90 | (a) << 16) 300#define NIX_AF_TL1X_YELLOW(a) (0xCA0 | (a) << 16) 301#define NIX_AF_TL1X_RED(a) (0xCB0 | (a) << 16) 302#define NIX_AF_TL1X_MD_DEBUG0(a) (0xCC0 | (a) << 16) 303#define NIX_AF_TL1X_MD_DEBUG1(a) (0xCC8 | (a) << 16) 304#define NIX_AF_TL1X_MD_DEBUG2(a) (0xCD0 | (a) << 16) 305#define NIX_AF_TL1X_MD_DEBUG3(a) (0xCD8 | (a) << 16) 306#define NIX_AF_TL1A_DEBUG (0xce0) 307#define NIX_AF_TL1B_DEBUG (0xcf0) 308#define NIX_AF_TL1_DEBUG_GREEN (0xd00) 309#define NIX_AF_TL1_DEBUG_NODE (0xd10) 310#define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xD20 | (a) << 16) 311#define NIX_AF_TL1X_DROPPED_BYTES(a) (0xD30 | (a) << 16) 312#define NIX_AF_TL1X_RED_PACKETS(a) (0xD40 | (a) << 16) 313#define NIX_AF_TL1X_RED_BYTES(a) (0xD50 | (a) << 16) 314#define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xD60 | (a) << 16) 315#define NIX_AF_TL1X_YELLOW_BYTES(a) (0xD70 | (a) << 16) 316#define NIX_AF_TL1X_GREEN_PACKETS(a) (0xD80 | (a) << 16) 317#define NIX_AF_TL1X_GREEN_BYTES(a) (0xD90 | (a) << 16) 318#define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16) 319#define NIX_AF_TL2X_SHAPE(a) (0xE10 | (a) << 16) 320#define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16) 321#define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16) 322#define NIX_AF_TL2X_SCHED_STATE(a) (0xE40 | (a) << 16) 323#define NIX_AF_TL2X_SHAPE_STATE(a) (0xE50 | (a) << 16) 324#define NIX_AF_TL2X_POINTERS(a) (0xE60 | (a) << 16) 325#define NIX_AF_TL2X_SW_XOFF(a) (0xE70 | (a) << 16) 326#define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16) 327#define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16) 328#define NIX_AF_TL2X_GREEN(a) (0xE90 | (a) << 16) 329#define NIX_AF_TL2X_YELLOW(a) (0xEA0 | (a) << 16) 330#define NIX_AF_TL2X_RED(a) (0xEB0 | (a) << 16) 331#define NIX_AF_TL2X_MD_DEBUG0(a) (0xEC0 | (a) << 16) 332#define NIX_AF_TL2X_MD_DEBUG1(a) (0xEC8 | (a) << 16) 333#define NIX_AF_TL2X_MD_DEBUG2(a) (0xED0 | (a) << 16) 334#define NIX_AF_TL2X_MD_DEBUG3(a) (0xED8 | (a) << 16) 335#define NIX_AF_TL2A_DEBUG (0xee0) 336#define NIX_AF_TL2B_DEBUG (0xef0) 337#define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16) 338#define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16) 339#define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16) 340#define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16) 341#define NIX_AF_TL3X_SCHED_STATE(a) (0x1040 | (a) << 16) 342#define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050 | (a) << 16) 343#define NIX_AF_TL3X_POINTERS(a) (0x1060 | (a) << 16) 344#define NIX_AF_TL3X_SW_XOFF(a) (0x1070 | (a) << 16) 345#define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16) 346#define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16) 347#define NIX_AF_TL3X_GREEN(a) (0x1090 | (a) << 16) 348#define NIX_AF_TL3X_YELLOW(a) (0x10A0 | (a) << 16) 349#define NIX_AF_TL3X_RED(a) (0x10B0 | (a) << 16) 350#define NIX_AF_TL3X_MD_DEBUG0(a) (0x10C0 | (a) << 16) 351#define NIX_AF_TL3X_MD_DEBUG1(a) (0x10C8 | (a) << 16) 352#define NIX_AF_TL3X_MD_DEBUG2(a) (0x10D0 | (a) << 16) 353#define NIX_AF_TL3X_MD_DEBUG3(a) (0x10D8 | (a) << 16) 354#define NIX_AF_TL3A_DEBUG (0x10e0) 355#define NIX_AF_TL3B_DEBUG (0x10f0) 356#define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16) 357#define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16) 358#define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16) 359#define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16) 360#define NIX_AF_TL4X_SCHED_STATE(a) (0x1240 | (a) << 16) 361#define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250 | (a) << 16) 362#define NIX_AF_TL4X_POINTERS(a) (0x1260 | (a) << 16) 363#define NIX_AF_TL4X_SW_XOFF(a) (0x1270 | (a) << 16) 364#define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16) 365#define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16) 366#define NIX_AF_TL4X_GREEN(a) (0x1290 | (a) << 16) 367#define NIX_AF_TL4X_YELLOW(a) (0x12A0 | (a) << 16) 368#define NIX_AF_TL4X_RED(a) (0x12B0 | (a) << 16) 369#define NIX_AF_TL4X_MD_DEBUG0(a) (0x12C0 | (a) << 16) 370#define NIX_AF_TL4X_MD_DEBUG1(a) (0x12C8 | (a) << 16) 371#define NIX_AF_TL4X_MD_DEBUG2(a) (0x12D0 | (a) << 16) 372#define NIX_AF_TL4X_MD_DEBUG3(a) (0x12D8 | (a) << 16) 373#define NIX_AF_TL4A_DEBUG (0x12e0) 374#define NIX_AF_TL4B_DEBUG (0x12f0) 375#define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16) 376#define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16) 377#define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16) 378#define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16) 379#define NIX_AF_MDQX_SCHED_STATE(a) (0x1440 | (a) << 16) 380#define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450 | (a) << 16) 381#define NIX_AF_MDQX_POINTERS(a) (0x1460 | (a) << 16) 382#define NIX_AF_MDQX_SW_XOFF(a) (0x1470 | (a) << 16) 383#define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16) 384#define NIX_AF_MDQX_MD_DEBUG(a) (0x14C0 | (a) << 16) 385#define NIX_AF_MDQX_PTR_FIFO(a) (0x14D0 | (a) << 16) 386#define NIX_AF_MDQA_DEBUG (0x14e0) 387#define NIX_AF_MDQB_DEBUG (0x14f0) 388#define NIX_AF_TL3_TL2X_CFG(a) (0x1600 | (a) << 18) 389#define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610 | (a) << 16) 390#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3) 391#define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) (0x1800 | (a) << 18 | (b) << 3) 392#define NIX_AF_TX_MCASTX(a) (0x1900 | (a) << 15) 393#define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1A00 | (a) << 16) 394#define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1A10 | (a) << 16) 395#define NIX_AF_RX_BPIDX_STATUS(a) (0x1A20 | (a) << 17) 396#define NIX_AF_RX_CHANX_CFG(a) (0x1A30 | (a) << 15) 397#define NIX_AF_CINT_TIMERX(a) (0x1A40 | (a) << 18) 398#define NIX_AF_LSO_FORMATX_FIELDX(a, b) (0x1B00 | (a) << 16 | (b) << 3) 399#define NIX_AF_LFX_CFG(a) (0x4000 | (a) << 17) 400#define NIX_AF_LFX_SQS_CFG(a) (0x4020 | (a) << 17) 401#define NIX_AF_LFX_TX_CFG2(a) (0x4028 | (a) << 17) 402#define NIX_AF_LFX_SQS_BASE(a) (0x4030 | (a) << 17) 403#define NIX_AF_LFX_RQS_CFG(a) (0x4040 | (a) << 17) 404#define NIX_AF_LFX_RQS_BASE(a) (0x4050 | (a) << 17) 405#define NIX_AF_LFX_CQS_CFG(a) (0x4060 | (a) << 17) 406#define NIX_AF_LFX_CQS_BASE(a) (0x4070 | (a) << 17) 407#define NIX_AF_LFX_TX_CFG(a) (0x4080 | (a) << 17) 408#define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090 | (a) << 17) 409#define NIX_AF_LFX_RX_CFG(a) (0x40A0 | (a) << 17) 410#define NIX_AF_LFX_RSS_CFG(a) (0x40C0 | (a) << 17) 411#define NIX_AF_LFX_RSS_BASE(a) (0x40D0 | (a) << 17) 412#define NIX_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 17) 413#define NIX_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 17) 414#define NIX_AF_LFX_CINTS_CFG(a) (0x4120 | (a) << 17) 415#define NIX_AF_LFX_CINTS_BASE(a) (0x4130 | (a) << 17) 416#define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140 | (a) << 17) 417#define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148 | (a) << 17) 418#define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150 | (a) << 17) 419#define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158 | (a) << 17) 420#define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170 | (a) << 17) 421#define NIX_AF_LFX_TX_STATUS(a) (0x4180 | (a) << 17) 422#define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) (0x4200 | (a) << 17 | (b) << 3) 423#define NIX_AF_LFX_LOCKX(a, b) (0x4300 | (a) << 17 | (b) << 3) 424#define NIX_AF_LFX_TX_STATX(a, b) (0x4400 | (a) << 17 | (b) << 3) 425#define NIX_AF_LFX_RX_STATX(a, b) (0x4500 | (a) << 17 | (b) << 3) 426#define NIX_AF_LFX_RSS_GRPX(a, b) (0x4600 | (a) << 17 | (b) << 3) 427#define NIX_AF_RX_NPC_MC_RCV (0x4700) 428#define NIX_AF_RX_NPC_MC_DROP (0x4710) 429#define NIX_AF_RX_NPC_MIRROR_RCV (0x4720) 430#define NIX_AF_RX_NPC_MIRROR_DROP (0x4730) 431#define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16) 432#define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17) 433#define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0 | (a) << 16) 434#define NIX_AF_SMQX_STATUS(a) (0x730 | (a) << 16) 435#define NIX_AF_MDQX_OUT_MD_COUNT(a) (0xdb0 | (a) << 16) 436 437#define NIX_PRIV_AF_INT_CFG (0x8000000) 438#define NIX_PRIV_LFX_CFG (0x8000010) 439#define NIX_PRIV_LFX_INT_CFG (0x8000020) 440#define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030) 441 442#define NIX_AF_LINKX_BASE_MASK GENMASK_ULL(11, 0) 443#define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16) 444#define NIX_AF_LINKX_MCS_CNT_MASK GENMASK_ULL(33, 32) 445 446#define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12) 447#define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0) 448#define NIX_VLAN_ETYPE_MASK GENMASK_ULL(63, 48) 449 450#define NIX_AF_MDQ_PARENT_MASK GENMASK_ULL(24, 16) 451#define NIX_AF_TL4_PARENT_MASK GENMASK_ULL(23, 16) 452#define NIX_AF_TL3_PARENT_MASK GENMASK_ULL(23, 16) 453#define NIX_AF_TL2_PARENT_MASK GENMASK_ULL(20, 16) 454 455/* SSO */ 456#define SSO_AF_CONST (0x1000) 457#define SSO_AF_CONST1 (0x1008) 458#define SSO_AF_BLK_RST (0x10f8) 459#define SSO_AF_LF_HWGRP_RST (0x10e0) 460#define SSO_AF_RVU_LF_CFG_DEBUG (0x3800) 461#define SSO_PRIV_LFX_HWGRP_CFG (0x10000) 462#define SSO_PRIV_LFX_HWGRP_INT_CFG (0x20000) 463 464/* SSOW */ 465#define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x0010) 466#define SSOW_AF_LF_HWS_RST (0x0030) 467#define SSOW_PRIV_LFX_HWS_CFG (0x1000) 468#define SSOW_PRIV_LFX_HWS_INT_CFG (0x2000) 469 470/* TIM */ 471#define TIM_AF_CONST (0x90) 472#define TIM_PRIV_LFX_CFG (0x20000) 473#define TIM_PRIV_LFX_INT_CFG (0x24000) 474#define TIM_AF_RVU_LF_CFG_DEBUG (0x30000) 475#define TIM_AF_BLK_RST (0x10) 476#define TIM_AF_LF_RST (0x20) 477 478/* CPT */ 479#define CPT_AF_CONSTANTS0 (0x0000) 480#define CPT_AF_CONSTANTS1 (0x1000) 481#define CPT_AF_DIAG (0x3000) 482#define CPT_AF_ECO (0x4000) 483#define CPT_AF_FLTX_INT(a) (0xa000ull | (u64)(a) << 3) 484#define CPT_AF_FLTX_INT_W1S(a) (0xb000ull | (u64)(a) << 3) 485#define CPT_AF_FLTX_INT_ENA_W1C(a) (0xc000ull | (u64)(a) << 3) 486#define CPT_AF_FLTX_INT_ENA_W1S(a) (0xd000ull | (u64)(a) << 3) 487#define CPT_AF_PSNX_EXE(a) (0xe000ull | (u64)(a) << 3) 488#define CPT_AF_PSNX_EXE_W1S(a) (0xf000ull | (u64)(a) << 3) 489#define CPT_AF_PSNX_LF(a) (0x10000ull | (u64)(a) << 3) 490#define CPT_AF_PSNX_LF_W1S(a) (0x11000ull | (u64)(a) << 3) 491#define CPT_AF_EXEX_CTL2(a) (0x12000ull | (u64)(a) << 3) 492#define CPT_AF_EXEX_STS(a) (0x13000ull | (u64)(a) << 3) 493#define CPT_AF_EXE_ERR_INFO (0x14000) 494#define CPT_AF_EXEX_ACTIVE(a) (0x16000ull | (u64)(a) << 3) 495#define CPT_AF_INST_REQ_PC (0x17000) 496#define CPT_AF_INST_LATENCY_PC (0x18000) 497#define CPT_AF_RD_REQ_PC (0x19000) 498#define CPT_AF_RD_LATENCY_PC (0x1a000) 499#define CPT_AF_RD_UC_PC (0x1b000) 500#define CPT_AF_ACTIVE_CYCLES_PC (0x1c000) 501#define CPT_AF_EXE_DBG_CTL (0x1d000) 502#define CPT_AF_EXE_DBG_DATA (0x1e000) 503#define CPT_AF_EXE_REQ_TIMER (0x1f000) 504#define CPT_AF_EXEX_CTL(a) (0x20000ull | (u64)(a) << 3) 505#define CPT_AF_EXE_PERF_CTL (0x21000) 506#define CPT_AF_EXE_DBG_CNTX(a) (0x22000ull | (u64)(a) << 3) 507#define CPT_AF_EXE_PERF_EVENT_CNT (0x23000) 508#define CPT_AF_EXE_EPCI_INBX_CNT(a) (0x24000ull | (u64)(a) << 3) 509#define CPT_AF_EXE_EPCI_OUTBX_CNT(a) (0x25000ull | (u64)(a) << 3) 510#define CPT_AF_EXEX_UCODE_BASE(a) (0x26000ull | (u64)(a) << 3) 511#define CPT_AF_LFX_CTL(a) (0x27000ull | (u64)(a) << 3) 512#define CPT_AF_LFX_CTL2(a) (0x29000ull | (u64)(a) << 3) 513#define CPT_AF_CPTCLK_CNT (0x2a000) 514#define CPT_AF_PF_FUNC (0x2b000) 515#define CPT_AF_LFX_PTR_CTL(a) (0x2c000ull | (u64)(a) << 3) 516#define CPT_AF_GRPX_THR(a) (0x2d000ull | (u64)(a) << 3) 517#define CPT_AF_CTL (0x2e000ull) 518#define CPT_AF_XEX_THR(a) (0x2f000ull | (u64)(a) << 3) 519#define CPT_PRIV_LFX_CFG (0x41000) 520#define CPT_PRIV_AF_INT_CFG (0x42000) 521#define CPT_PRIV_LFX_INT_CFG (0x43000) 522#define CPT_AF_LF_RST (0x44000) 523#define CPT_AF_RVU_LF_CFG_DEBUG (0x45000) 524#define CPT_AF_BLK_RST (0x46000) 525#define CPT_AF_RVU_INT (0x47000) 526#define CPT_AF_RVU_INT_W1S (0x47008) 527#define CPT_AF_RVU_INT_ENA_W1S (0x47010) 528#define CPT_AF_RVU_INT_ENA_W1C (0x47018) 529#define CPT_AF_RAS_INT (0x47020) 530#define CPT_AF_RAS_INT_W1S (0x47028) 531#define CPT_AF_RAS_INT_ENA_W1S (0x47030) 532#define CPT_AF_RAS_INT_ENA_W1C (0x47038) 533#define CPT_AF_CTX_FLUSH_TIMER (0x48000ull) 534#define CPT_AF_CTX_ERR (0x48008ull) 535#define CPT_AF_CTX_ENC_ID (0x48010ull) 536#define CPT_AF_CTX_MIS_PC (0x49400ull) 537#define CPT_AF_CTX_HIT_PC (0x49408ull) 538#define CPT_AF_CTX_AOP_PC (0x49410ull) 539#define CPT_AF_CTX_AOP_LATENCY_PC (0x49418ull) 540#define CPT_AF_CTX_IFETCH_PC (0x49420ull) 541#define CPT_AF_CTX_IFETCH_LATENCY_PC (0x49428ull) 542#define CPT_AF_CTX_FFETCH_PC (0x49430ull) 543#define CPT_AF_CTX_FFETCH_LATENCY_PC (0x49438ull) 544#define CPT_AF_CTX_WBACK_PC (0x49440ull) 545#define CPT_AF_CTX_WBACK_LATENCY_PC (0x49448ull) 546#define CPT_AF_CTX_PSH_PC (0x49450ull) 547#define CPT_AF_CTX_PSH_LATENCY_PC (0x49458ull) 548#define CPT_AF_CTX_CAM_DATA(a) (0x49800ull | (u64)(a) << 3) 549#define CPT_AF_RXC_CFG1 (0x50000ull) 550#define CPT_AF_RXC_TIME (0x50010ull) 551#define CPT_AF_RXC_TIME_CFG (0x50018ull) 552#define CPT_AF_RXC_DFRG (0x50020ull) 553#define CPT_AF_RXC_ACTIVE_STS (0x50028ull) 554#define CPT_AF_RXC_ZOMBIE_STS (0x50030ull) 555#define CPT_AF_X2PX_LINK_CFG(a) (0x51000ull | (u64)(a) << 3) 556 557#define AF_BAR2_ALIASX(a, b) (0x9100000ull | (a) << 12 | (b)) 558#define CPT_AF_BAR2_SEL 0x9000000 559#define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 560 561#define CPT_AF_LF_CTL2_SHIFT 3 562#define CPT_AF_LF_SSO_PF_FUNC_SHIFT 32 563 564#define CPT_LF_CTL 0x10 565#define CPT_LF_INPROG 0x40 566#define CPT_LF_Q_SIZE 0x100 567#define CPT_LF_Q_INST_PTR 0x110 568#define CPT_LF_Q_GRP_PTR 0x120 569#define CPT_LF_CTX_FLUSH 0x510 570 571#define NPC_AF_BLK_RST (0x00040) 572 573/* NPC */ 574#define NPC_AF_CFG (0x00000) 575#define NPC_AF_ACTIVE_PC (0x00010) 576#define NPC_AF_CONST (0x00020) 577#define NPC_AF_CONST1 (0x00030) 578#define NPC_AF_BLK_RST (0x00040) 579#define NPC_AF_MCAM_SCRUB_CTL (0x000a0) 580#define NPC_AF_KCAM_SCRUB_CTL (0x000b0) 581#define NPC_AF_CONST2 (0x00100) 582#define NPC_AF_CONST3 (0x00110) 583#define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3) 584#define NPC_AF_PCK_CFG (0x00600) 585#define NPC_AF_PCK_DEF_OL2 (0x00610) 586#define NPC_AF_PCK_DEF_OIP4 (0x00620) 587#define NPC_AF_PCK_DEF_OIP6 (0x00630) 588#define NPC_AF_PCK_DEF_IIP4 (0x00640) 589#define NPC_AF_INTFX_HASHX_RESULT_CTRL(a, b) (0x006c0 | (a) << 4 | (b) << 3) 590#define NPC_AF_INTFX_HASHX_MASKX(a, b, c) (0x00700 | (a) << 5 | (b) << 4 | (c) << 3) 591#define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3) 592#define NPC_AF_INTFX_HASHX_CFG(a, b) (0x00b00 | (a) << 6 | (b) << 4) 593#define NPC_AF_INTFX_SECRET_KEY0(a) (0x00e00 | (a) << 3) 594#define NPC_AF_INTFX_SECRET_KEY1(a) (0x00e20 | (a) << 3) 595#define NPC_AF_INTFX_SECRET_KEY2(a) (0x00e40 | (a) << 3) 596#define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8) 597#define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6) 598#define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6) 599#define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3) 600#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \ 601 (0x100000 | (a) << 14 | (b) << 6 | (c) << 3) 602#define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \ 603 (0x100020 | (a) << 14 | (b) << 6) 604#define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \ 605 (0x100028 | (a) << 14 | (b) << 6) 606#define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3) 607#define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3) 608#define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \ 609 (0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3) 610#define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \ 611 (0x980000 | (a) << 16 | (b) << 12 | (c) << 3) 612#define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8) 613#define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4) 614#define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4) 615#define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4) 616#define NPC_AF_LKUP_CTL (0x2000000) 617#define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4) 618#define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4) 619#define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4) 620#define NPC_AF_DBG_CTL (0x3000000) 621#define NPC_AF_DBG_STATUS (0x3000010) 622#define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8) 623#define NPC_AF_IKPU_ERR_CTL (0x3000080) 624#define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8) 625#define NPC_AF_MCAM_DBG (0x3001000) 626#define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4) 627#define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4) 628 629#define NPC_AF_EXACT_MEM_ENTRY(a, b) (0x300000 | (a) << 15 | (b) << 3) 630#define NPC_AF_EXACT_CAM_ENTRY(a) (0xC00 | (a) << 3) 631#define NPC_AF_INTFX_EXACT_MASK(a) (0x660 | (a) << 3) 632#define NPC_AF_INTFX_EXACT_RESULT_CTL(a)(0x680 | (a) << 3) 633#define NPC_AF_INTFX_EXACT_CFG(a) (0xA00 | (a) << 3) 634#define NPC_AF_INTFX_EXACT_SECRET0(a) (0xE00 | (a) << 3) 635#define NPC_AF_INTFX_EXACT_SECRET1(a) (0xE20 | (a) << 3) 636#define NPC_AF_INTFX_EXACT_SECRET2(a) (0xE40 | (a) << 3) 637 638#define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) ({ \ 639 u64 offset; \ 640 \ 641 offset = (0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3); \ 642 if (rvu->hw->npc_ext_set) \ 643 offset = (0x8000000ull | (a) << 8 | (b) << 22 | (c) << 3); \ 644 offset; }) 645 646#define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) ({ \ 647 u64 offset; \ 648 \ 649 offset = (0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3); \ 650 if (rvu->hw->npc_ext_set) \ 651 offset = (0x8000010ull | (a) << 8 | (b) << 22 | (c) << 3); \ 652 offset; }) 653 654#define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) ({ \ 655 u64 offset; \ 656 \ 657 offset = (0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3); \ 658 if (rvu->hw->npc_ext_set) \ 659 offset = (0x8000020ull | (a) << 8 | (b) << 22 | (c) << 3); \ 660 offset; }) 661 662#define NPC_AF_MCAMEX_BANKX_CFG(a, b) ({ \ 663 u64 offset; \ 664 \ 665 offset = (0x1800000ull | (a) << 8 | (b) << 4); \ 666 if (rvu->hw->npc_ext_set) \ 667 offset = (0x8000038ull | (a) << 8 | (b) << 22); \ 668 offset; }) 669 670#define NPC_AF_MCAMEX_BANKX_ACTION(a, b) ({ \ 671 u64 offset; \ 672 \ 673 offset = (0x1900000ull | (a) << 8 | (b) << 4); \ 674 if (rvu->hw->npc_ext_set) \ 675 offset = (0x8000040ull | (a) << 8 | (b) << 22); \ 676 offset; }) \ 677 678#define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) ({ \ 679 u64 offset; \ 680 \ 681 offset = (0x1900008ull | (a) << 8 | (b) << 4); \ 682 if (rvu->hw->npc_ext_set) \ 683 offset = (0x8000048ull | (a) << 8 | (b) << 22); \ 684 offset; }) \ 685 686#define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) ({ \ 687 u64 offset; \ 688 \ 689 offset = (0x1880000ull | (a) << 8 | (b) << 4); \ 690 if (rvu->hw->npc_ext_set) \ 691 offset = (0x8000050ull | (a) << 8 | (b) << 22); \ 692 offset; }) \ 693 694#define NPC_AF_MATCH_STATX(a) ({ \ 695 u64 offset; \ 696 \ 697 offset = (0x1880008ull | (a) << 8); \ 698 if (rvu->hw->npc_ext_set) \ 699 offset = (0x8000078ull | (a) << 8); \ 700 offset; }) \ 701 702/* NDC */ 703#define NDC_AF_CONST (0x00000) 704#define NDC_AF_CLK_EN (0x00020) 705#define NDC_AF_CTL (0x00030) 706#define NDC_AF_BANK_CTL (0x00040) 707#define NDC_AF_BANK_CTL_DONE (0x00048) 708#define NDC_AF_INTR (0x00058) 709#define NDC_AF_INTR_W1S (0x00060) 710#define NDC_AF_INTR_ENA_W1S (0x00068) 711#define NDC_AF_INTR_ENA_W1C (0x00070) 712#define NDC_AF_ACTIVE_PC (0x00078) 713#define NDC_AF_CAMS_RD_INTERVAL (0x00080) 714#define NDC_AF_BP_TEST_ENABLE (0x001F8) 715#define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3) 716#define NDC_AF_BLK_RST (0x002F0) 717#define NDC_PRIV_AF_INT_CFG (0x002F8) 718#define NDC_AF_HASHX(a) (0x00300 | (a) << 3) 719#define NDC_AF_PORTX_RTX_RWX_REQ_PC(a, b, c) \ 720 (0x00C00 | (a) << 5 | (b) << 4 | (c) << 3) 721#define NDC_AF_PORTX_RTX_RWX_OSTDN_PC(a, b, c) \ 722 (0x00D00 | (a) << 5 | (b) << 4 | (c) << 3) 723#define NDC_AF_PORTX_RTX_RWX_LAT_PC(a, b, c) \ 724 (0x00E00 | (a) << 5 | (b) << 4 | (c) << 3) 725#define NDC_AF_PORTX_RTX_CANT_ALLOC_PC(a, b) \ 726 (0x00F00 | (a) << 5 | (b) << 4) 727#define NDC_AF_BANKX_HIT_PC(a) (0x01000 | (a) << 3) 728#define NDC_AF_BANKX_MISS_PC(a) (0x01100 | (a) << 3) 729#define NDC_AF_BANKX_LINEX_METADATA(a, b) \ 730 (0x10000 | (a) << 12 | (b) << 3) 731 732/* LBK */ 733#define LBK_CONST (0x10ull) 734#define LBK_LINK_CFG_P2X (0x400ull) 735#define LBK_LINK_CFG_X2P (0x408ull) 736#define LBK_CONST_CHANS GENMASK_ULL(47, 32) 737#define LBK_CONST_DST GENMASK_ULL(31, 28) 738#define LBK_CONST_SRC GENMASK_ULL(27, 24) 739#define LBK_CONST_BUF_SIZE GENMASK_ULL(23, 0) 740#define LBK_LINK_CFG_RANGE_MASK GENMASK_ULL(19, 16) 741#define LBK_LINK_CFG_ID_MASK GENMASK_ULL(11, 6) 742#define LBK_LINK_CFG_BASE_MASK GENMASK_ULL(5, 0) 743 744/* APR */ 745#define APR_AF_LMT_CFG (0x000ull) 746#define APR_AF_LMT_MAP_BASE (0x008ull) 747#define APR_AF_LMT_CTL (0x010ull) 748#define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT 23 749#define APR_LMT_MAP_ENT_SCH_ENA_SHIFT 22 750#define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT 21 751#define LMTST_THROTTLE_MASK GENMASK_ULL(38, 35) 752#define LMTST_WR_PEND_MAX 15 753 754#endif /* RVU_REG_H */
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