rvu_npc.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Marvell RVU Admin Function driver
   3 *
   4 * Copyright (C) 2018 Marvell.
   5 *
   6 */
   7
   8#include <linux/bitfield.h>
   9#include <linux/module.h>
  10#include <linux/pci.h>
  11
  12#include "rvu_struct.h"
  13#include "rvu_reg.h"
  14#include "rvu.h"
  15#include "npc.h"
  16#include "cgx.h"
  17#include "npc_profile.h"
  18#include "rvu_npc_hash.h"
  19
  20#define RSVD_MCAM_ENTRIES_PER_PF	3 /* Broadcast, Promisc and AllMulticast */
  21#define RSVD_MCAM_ENTRIES_PER_NIXLF	1 /* Ucast for LFs */
  22
  23#define NPC_PARSE_RESULT_DMAC_OFFSET	8
  24#define NPC_HW_TSTAMP_OFFSET		8ULL
  25#define NPC_KEX_CHAN_MASK		0xFFFULL
  26#define NPC_KEX_PF_FUNC_MASK		0xFFFFULL
  27
  28#define ALIGN_8B_CEIL(__a)	(((__a) + 7) & (-8))
  29
  30static const char def_pfl_name[] = "default";
  31
  32static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
  33				      int blkaddr, u16 pcifunc);
  34static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
  35				       u16 pcifunc);
  36
  37bool is_npc_intf_tx(u8 intf)
  38{
  39	return !!(intf & 0x1);
  40}
  41
  42bool is_npc_intf_rx(u8 intf)
  43{
  44	return !(intf & 0x1);
  45}
  46
  47bool is_npc_interface_valid(struct rvu *rvu, u8 intf)
  48{
  49	struct rvu_hwinfo *hw = rvu->hw;
  50
  51	return intf < hw->npc_intfs;
  52}
  53
  54int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena)
  55{
  56	/* Due to a HW issue in these silicon versions, parse nibble enable
  57	 * configuration has to be identical for both Rx and Tx interfaces.
  58	 */
  59	if (is_rvu_96xx_B0(rvu))
  60		return nibble_ena;
  61	return 0;
  62}
  63
  64void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
  65{
  66	int blkaddr;
  67	u64 val = 0;
  68
  69	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
  70	if (blkaddr < 0)
  71		return;
  72
  73	/* Config CPI base for the PKIND */
  74	val = pkind | 1ULL << 62;
  75	rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
  76}
  77
  78int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
  79{
  80	struct npc_pkind *pkind = &rvu->hw->pkind;
  81	u32 map;
  82	int i;
  83
  84	for (i = 0; i < pkind->rsrc.max; i++) {
  85		map = pkind->pfchan_map[i];
  86		if (((map >> 16) & 0x3F) == pf)
  87			return i;
  88	}
  89	return -1;
  90}
  91
  92#define NPC_AF_ACTION0_PTR_ADVANCE	GENMASK_ULL(27, 20)
  93
  94int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable)
  95{
  96	int pkind, blkaddr;
  97	u64 val;
  98
  99	pkind = rvu_npc_get_pkind(rvu, pf);
 100	if (pkind < 0) {
 101		dev_err(rvu->dev, "%s: pkind not mapped\n", __func__);
 102		return -EINVAL;
 103	}
 104
 105	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
 106	if (blkaddr < 0) {
 107		dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
 108		return -EINVAL;
 109	}
 110
 111	val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
 112	val &= ~NPC_AF_ACTION0_PTR_ADVANCE;
 113	/* If timestamp is enabled then configure NPC to shift 8 bytes */
 114	if (enable)
 115		val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE,
 116				  NPC_HW_TSTAMP_OFFSET);
 117	rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
 118
 119	return 0;
 120}
 121
 122static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc,
 123				    int nixlf)
 124{
 125	struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam);
 126	struct rvu *rvu = hw->rvu;
 127	int blkaddr = 0, max = 0;
 128	struct rvu_block *block;
 129	struct rvu_pfvf *pfvf;
 130
 131	pfvf = rvu_get_pfvf(rvu, pcifunc);
 132	/* Given a PF/VF and NIX LF number calculate the unicast mcam
 133	 * entry index based on the NIX block assigned to the PF/VF.
 134	 */
 135	blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
 136	while (blkaddr) {
 137		if (pfvf->nix_blkaddr == blkaddr)
 138			break;
 139		block = &rvu->hw->block[blkaddr];
 140		max += block->lf.max;
 141		blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
 142	}
 143
 144	return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF;
 145}
 146
 147int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
 148			     u16 pcifunc, int nixlf, int type)
 149{
 150	struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam);
 151	struct rvu *rvu = hw->rvu;
 152	int pf = rvu_get_pf(rvu->pdev, pcifunc);
 153	int index;
 154
 155	/* Check if this is for a PF */
 156	if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
 157		/* Reserved entries exclude PF0 */
 158		pf--;
 159		index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
 160		/* Broadcast address matching entry should be first so
 161		 * that the packet can be replicated to all VFs.
 162		 */
 163		if (type == NIXLF_BCAST_ENTRY)
 164			return index;
 165		else if (type == NIXLF_ALLMULTI_ENTRY)
 166			return index + 1;
 167		else if (type == NIXLF_PROMISC_ENTRY)
 168			return index + 2;
 169	}
 170
 171	return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf);
 172}
 173
 174int npc_get_bank(struct npc_mcam *mcam, int index)
 175{
 176	int bank = index / mcam->banksize;
 177
 178	/* 0,1 & 2,3 banks are combined for this keysize */
 179	if (mcam->keysize == NPC_MCAM_KEY_X2)
 180		return bank ? 2 : 0;
 181
 182	return bank;
 183}
 184
 185bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
 186			   int blkaddr, int index)
 187{
 188	int bank = npc_get_bank(mcam, index);
 189	u64 cfg;
 190
 191	index &= (mcam->banksize - 1);
 192	cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
 193	return (cfg & 1);
 194}
 195
 196void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 197			   int blkaddr, int index, bool enable)
 198{
 199	int bank = npc_get_bank(mcam, index);
 200	int actbank = bank;
 201
 202	index &= (mcam->banksize - 1);
 203	for (; bank < (actbank + mcam->banks_per_entry); bank++) {
 204		rvu_write64(rvu, blkaddr,
 205			    NPC_AF_MCAMEX_BANKX_CFG(index, bank),
 206			    enable ? 1 : 0);
 207	}
 208}
 209
 210static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 211				 int blkaddr, int index)
 212{
 213	int bank = npc_get_bank(mcam, index);
 214	int actbank = bank;
 215
 216	index &= (mcam->banksize - 1);
 217	for (; bank < (actbank + mcam->banks_per_entry); bank++) {
 218		rvu_write64(rvu, blkaddr,
 219			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
 220		rvu_write64(rvu, blkaddr,
 221			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
 222
 223		rvu_write64(rvu, blkaddr,
 224			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
 225		rvu_write64(rvu, blkaddr,
 226			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
 227
 228		rvu_write64(rvu, blkaddr,
 229			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
 230		rvu_write64(rvu, blkaddr,
 231			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
 232	}
 233}
 234
 235static void npc_get_keyword(struct mcam_entry *entry, int idx,
 236			    u64 *cam0, u64 *cam1)
 237{
 238	u64 kw_mask = 0x00;
 239
 240#define CAM_MASK(n)	(BIT_ULL(n) - 1)
 241
 242	/* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
 243	 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
 244	 *
 245	 * Also, only 48 bits of BANKX_CAMX_W1 are valid.
 246	 */
 247	switch (idx) {
 248	case 0:
 249		/* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
 250		*cam1 = entry->kw[0];
 251		kw_mask = entry->kw_mask[0];
 252		break;
 253	case 1:
 254		/* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
 255		*cam1 = entry->kw[1] & CAM_MASK(48);
 256		kw_mask = entry->kw_mask[1] & CAM_MASK(48);
 257		break;
 258	case 2:
 259		/* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
 260		 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
 261		 */
 262		*cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
 263		*cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
 264		kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
 265		kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
 266		break;
 267	case 3:
 268		/* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
 269		 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
 270		 */
 271		*cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
 272		*cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
 273		kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
 274		kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
 275		break;
 276	case 4:
 277		/* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
 278		 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
 279		 */
 280		*cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
 281		*cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
 282		kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
 283		kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
 284		break;
 285	case 5:
 286		/* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
 287		 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
 288		 */
 289		*cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
 290		*cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
 291		kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
 292		kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
 293		break;
 294	case 6:
 295		/* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
 296		 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
 297		 */
 298		*cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
 299		*cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
 300		kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
 301		kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
 302		break;
 303	case 7:
 304		/* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
 305		*cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
 306		kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
 307		break;
 308	}
 309
 310	*cam1 &= kw_mask;
 311	*cam0 = ~*cam1 & kw_mask;
 312}
 313
 314static void npc_fill_entryword(struct mcam_entry *entry, int idx,
 315			       u64 cam0, u64 cam1)
 316{
 317	/* Similar to npc_get_keyword, but fills mcam_entry structure from
 318	 * CAM registers.
 319	 */
 320	switch (idx) {
 321	case 0:
 322		entry->kw[0] = cam1;
 323		entry->kw_mask[0] = cam1 ^ cam0;
 324		break;
 325	case 1:
 326		entry->kw[1] = cam1;
 327		entry->kw_mask[1] = cam1 ^ cam0;
 328		break;
 329	case 2:
 330		entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48;
 331		entry->kw[2] = (cam1 >> 16) & CAM_MASK(48);
 332		entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
 333		entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48);
 334		break;
 335	case 3:
 336		entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48;
 337		entry->kw[3] = (cam1 >> 16) & CAM_MASK(32);
 338		entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
 339		entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32);
 340		break;
 341	case 4:
 342		entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32;
 343		entry->kw[4] = (cam1 >> 32) & CAM_MASK(32);
 344		entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
 345		entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32);
 346		break;
 347	case 5:
 348		entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32;
 349		entry->kw[5] = (cam1 >> 32) & CAM_MASK(16);
 350		entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
 351		entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16);
 352		break;
 353	case 6:
 354		entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16;
 355		entry->kw[6] = (cam1 >> 48) & CAM_MASK(16);
 356		entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
 357		entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16);
 358		break;
 359	case 7:
 360		entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16;
 361		entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
 362		break;
 363	}
 364}
 365
 366static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam,
 367					int blkaddr, u16 pf_func)
 368{
 369	int bank, nixlf, index;
 370
 371	/* get ucast entry rule entry index */
 372	if (nix_get_nixlf(rvu, pf_func, &nixlf, NULL)) {
 373		dev_err(rvu->dev, "%s: nixlf not attached to pcifunc:0x%x\n",
 374			__func__, pf_func);
 375		/* Action 0 is drop */
 376		return 0;
 377	}
 378
 379	index = npc_get_nixlf_mcam_index(mcam, pf_func, nixlf,
 380					 NIXLF_UCAST_ENTRY);
 381	bank = npc_get_bank(mcam, index);
 382	index &= (mcam->banksize - 1);
 383
 384	return rvu_read64(rvu, blkaddr,
 385			  NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
 386}
 387
 388static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam,
 389			      int blkaddr, int index, struct mcam_entry *entry,
 390			      bool *enable)
 391{
 392	struct rvu_npc_mcam_rule *rule;
 393	u16 owner, target_func;
 394	struct rvu_pfvf *pfvf;
 395	u64 rx_action;
 396
 397	owner = mcam->entry2pfvf_map[index];
 398	target_func = (entry->action >> 4) & 0xffff;
 399	/* do nothing when target is LBK/PF or owner is not PF */
 400	if (is_pffunc_af(owner) || is_lbk_vf(rvu, target_func) ||
 401	    (owner & RVU_PFVF_FUNC_MASK) ||
 402	    !(target_func & RVU_PFVF_FUNC_MASK))
 403		return;
 404
 405	/* save entry2target_pffunc */
 406	pfvf = rvu_get_pfvf(rvu, target_func);
 407	mcam->entry2target_pffunc[index] = target_func;
 408
 409	/* don't enable rule when nixlf not attached or initialized */
 410	if (!(is_nixlf_attached(rvu, target_func) &&
 411	      test_bit(NIXLF_INITIALIZED, &pfvf->flags)))
 412		*enable = false;
 413
 414	/* fix up not needed for the rules added by user(ntuple filters) */
 415	list_for_each_entry(rule, &mcam->mcam_rules, list) {
 416		if (rule->entry == index)
 417			return;
 418	}
 419
 420	/* AF modifies given action iff PF/VF has requested for it */
 421	if ((entry->action & 0xFULL) != NIX_RX_ACTION_DEFAULT)
 422		return;
 423
 424	/* copy VF default entry action to the VF mcam entry */
 425	rx_action = npc_get_default_entry_action(rvu, mcam, blkaddr,
 426						 target_func);
 427	if (rx_action)
 428		entry->action = rx_action;
 429}
 430
 431static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 432				  int blkaddr, int index, u8 intf,
 433				  struct mcam_entry *entry, bool enable)
 434{
 435	int bank = npc_get_bank(mcam, index);
 436	int kw = 0, actbank, actindex;
 437	u8 tx_intf_mask = ~intf & 0x3;
 438	u8 tx_intf = intf;
 439	u64 cam0, cam1;
 440
 441	actbank = bank; /* Save bank id, to set action later on */
 442	actindex = index;
 443	index &= (mcam->banksize - 1);
 444
 445	/* Disable before mcam entry update */
 446	npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
 447
 448	/* Clear mcam entry to avoid writes being suppressed by NPC */
 449	npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
 450
 451	/* CAM1 takes the comparison value and
 452	 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
 453	 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
 454	 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
 455	 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
 456	 */
 457	for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
 458		/* Interface should be set in all banks */
 459		if (is_npc_intf_tx(intf)) {
 460			/* Last bit must be set and rest don't care
 461			 * for TX interfaces
 462			 */
 463			tx_intf_mask = 0x1;
 464			tx_intf = intf & tx_intf_mask;
 465			tx_intf_mask = ~tx_intf & tx_intf_mask;
 466		}
 467
 468		rvu_write64(rvu, blkaddr,
 469			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
 470			    tx_intf);
 471		rvu_write64(rvu, blkaddr,
 472			    NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
 473			    tx_intf_mask);
 474
 475		/* Set the match key */
 476		npc_get_keyword(entry, kw, &cam0, &cam1);
 477		rvu_write64(rvu, blkaddr,
 478			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
 479		rvu_write64(rvu, blkaddr,
 480			    NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
 481
 482		npc_get_keyword(entry, kw + 1, &cam0, &cam1);
 483		rvu_write64(rvu, blkaddr,
 484			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
 485		rvu_write64(rvu, blkaddr,
 486			    NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
 487	}
 488
 489	/* PF installing VF rule */
 490	if (is_npc_intf_rx(intf) && actindex < mcam->bmap_entries)
 491		npc_fixup_vf_rule(rvu, mcam, blkaddr, actindex, entry, &enable);
 492
 493	/* Set 'action' */
 494	rvu_write64(rvu, blkaddr,
 495		    NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
 496
 497	/* Set TAG 'action' */
 498	rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
 499		    entry->vtag_action);
 500
 501	/* Enable the entry */
 502	if (enable)
 503		npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
 504}
 505
 506void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 507			 int blkaddr, u16 src,
 508			 struct mcam_entry *entry, u8 *intf, u8 *ena)
 509{
 510	int sbank = npc_get_bank(mcam, src);
 511	int bank, kw = 0;
 512	u64 cam0, cam1;
 513
 514	src &= (mcam->banksize - 1);
 515	bank = sbank;
 516
 517	for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
 518		cam1 = rvu_read64(rvu, blkaddr,
 519				  NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1));
 520		cam0 = rvu_read64(rvu, blkaddr,
 521				  NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0));
 522		npc_fill_entryword(entry, kw, cam0, cam1);
 523
 524		cam1 = rvu_read64(rvu, blkaddr,
 525				  NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1));
 526		cam0 = rvu_read64(rvu, blkaddr,
 527				  NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0));
 528		npc_fill_entryword(entry, kw + 1, cam0, cam1);
 529	}
 530
 531	entry->action = rvu_read64(rvu, blkaddr,
 532				   NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
 533	entry->vtag_action =
 534		rvu_read64(rvu, blkaddr,
 535			   NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
 536	*intf = rvu_read64(rvu, blkaddr,
 537			   NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3;
 538	*ena = rvu_read64(rvu, blkaddr,
 539			  NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1;
 540}
 541
 542static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
 543				int blkaddr, u16 src, u16 dest)
 544{
 545	int dbank = npc_get_bank(mcam, dest);
 546	int sbank = npc_get_bank(mcam, src);
 547	u64 cfg, sreg, dreg;
 548	int bank, i;
 549
 550	src &= (mcam->banksize - 1);
 551	dest &= (mcam->banksize - 1);
 552
 553	/* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */
 554	for (bank = 0; bank < mcam->banks_per_entry; bank++) {
 555		sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);
 556		dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);
 557		for (i = 0; i < 6; i++) {
 558			cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8));
 559			rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg);
 560		}
 561	}
 562
 563	/* Copy action */
 564	cfg = rvu_read64(rvu, blkaddr,
 565			 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
 566	rvu_write64(rvu, blkaddr,
 567		    NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg);
 568
 569	/* Copy TAG action */
 570	cfg = rvu_read64(rvu, blkaddr,
 571			 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
 572	rvu_write64(rvu, blkaddr,
 573		    NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg);
 574
 575	/* Enable or disable */
 576	cfg = rvu_read64(rvu, blkaddr,
 577			 NPC_AF_MCAMEX_BANKX_CFG(src, sbank));
 578	rvu_write64(rvu, blkaddr,
 579		    NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);
 580}
 581
 582u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
 583			int blkaddr, int index)
 584{
 585	int bank = npc_get_bank(mcam, index);
 586
 587	index &= (mcam->banksize - 1);
 588	return rvu_read64(rvu, blkaddr,
 589			  NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
 590}
 591
 592void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
 593			 int blkaddr, int index, u64 cfg)
 594{
 595	int bank = npc_get_bank(mcam, index);
 596
 597	index &= (mcam->banksize - 1);
 598	return rvu_write64(rvu, blkaddr,
 599			   NPC_AF_MCAMEX_BANKX_ACTION(index, bank), cfg);
 600}
 601
 602void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
 603				 int nixlf, u64 chan, u8 *mac_addr)
 604{
 605	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
 606	struct npc_install_flow_req req = { 0 };
 607	struct npc_install_flow_rsp rsp = { 0 };
 608	struct npc_mcam *mcam = &rvu->hw->mcam;
 609	struct nix_rx_action action = { 0 };
 610	int blkaddr, index;
 611
 612	/* AF's and SDP VFs work in promiscuous mode */
 613	if (is_lbk_vf(rvu, pcifunc) || is_sdp_vf(rvu, pcifunc))
 614		return;
 615
 616	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 617	if (blkaddr < 0)
 618		return;
 619
 620	/* Ucast rule should not be installed if DMAC
 621	 * extraction is not supported by the profile.
 622	 */
 623	if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf))
 624		return;
 625
 626	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 627					 nixlf, NIXLF_UCAST_ENTRY);
 628
 629	/* Don't change the action if entry is already enabled
 630	 * Otherwise RSS action may get overwritten.
 631	 */
 632	if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
 633		*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
 634						      blkaddr, index);
 635	} else {
 636		action.op = NIX_RX_ACTIONOP_UCAST;
 637		action.pf_func = pcifunc;
 638	}
 639
 640	req.default_rule = 1;
 641	ether_addr_copy(req.packet.dmac, mac_addr);
 642	eth_broadcast_addr((u8 *)&req.mask.dmac);
 643	req.features = BIT_ULL(NPC_DMAC);
 644	req.channel = chan;
 645	req.chan_mask = 0xFFFU;
 646	req.intf = pfvf->nix_rx_intf;
 647	req.op = action.op;
 648	req.hdr.pcifunc = 0; /* AF is requester */
 649	req.vf = action.pf_func;
 650	req.index = action.index;
 651	req.match_id = action.match_id;
 652	req.flow_key_alg = action.flow_key_alg;
 653
 654	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
 655}
 656
 657void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
 658				   int nixlf, u64 chan, u8 chan_cnt)
 659{
 660	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
 661	struct npc_install_flow_req req = { 0 };
 662	struct npc_install_flow_rsp rsp = { 0 };
 663	struct npc_mcam *mcam = &rvu->hw->mcam;
 664	struct rvu_hwinfo *hw = rvu->hw;
 665	int blkaddr, ucast_idx, index;
 666	struct nix_rx_action action = { 0 };
 667	u64 relaxed_mask;
 668	u8 flow_key_alg;
 669
 670	if (!hw->cap.nix_rx_multicast && is_cgx_vf(rvu, pcifunc))
 671		return;
 672
 673	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 674	if (blkaddr < 0)
 675		return;
 676
 677	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 678					 nixlf, NIXLF_PROMISC_ENTRY);
 679
 680	if (is_cgx_vf(rvu, pcifunc))
 681		index = npc_get_nixlf_mcam_index(mcam,
 682						 pcifunc & ~RVU_PFVF_FUNC_MASK,
 683						 nixlf, NIXLF_PROMISC_ENTRY);
 684
 685	/* If the corresponding PF's ucast action is RSS,
 686	 * use the same action for promisc also
 687	 */
 688	ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
 689					     nixlf, NIXLF_UCAST_ENTRY);
 690	if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
 691		*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
 692						      blkaddr, ucast_idx);
 693
 694	if (action.op != NIX_RX_ACTIONOP_RSS) {
 695		*(u64 *)&action = 0;
 696		action.op = NIX_RX_ACTIONOP_UCAST;
 697	}
 698
 699	flow_key_alg = action.flow_key_alg;
 700
 701	/* RX_ACTION set to MCAST for CGX PF's */
 702	if (hw->cap.nix_rx_multicast && pfvf->use_mce_list &&
 703	    is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))) {
 704		*(u64 *)&action = 0;
 705		action.op = NIX_RX_ACTIONOP_MCAST;
 706		pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
 707		action.index = pfvf->promisc_mce_idx;
 708	}
 709
 710	/* For cn10k the upper two bits of the channel number are
 711	 * cpt channel number. with masking out these bits in the
 712	 * mcam entry, same entry used for NIX will allow packets
 713	 * received from cpt for parsing.
 714	 */
 715	if (!is_rvu_otx2(rvu)) {
 716		req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
 717	} else {
 718		req.chan_mask = 0xFFFU;
 719	}
 720
 721	if (chan_cnt > 1) {
 722		if (!is_power_of_2(chan_cnt)) {
 723			dev_err(rvu->dev,
 724				"%s: channel count more than 1, must be power of 2\n", __func__);
 725			return;
 726		}
 727		relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1,
 728					   ilog2(chan_cnt));
 729		req.chan_mask &= relaxed_mask;
 730	}
 731
 732	req.channel = chan;
 733	req.intf = pfvf->nix_rx_intf;
 734	req.entry = index;
 735	req.op = action.op;
 736	req.hdr.pcifunc = 0; /* AF is requester */
 737	req.vf = pcifunc;
 738	req.index = action.index;
 739	req.match_id = action.match_id;
 740	req.flow_key_alg = flow_key_alg;
 741
 742	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
 743}
 744
 745void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc,
 746				  int nixlf, bool enable)
 747{
 748	struct npc_mcam *mcam = &rvu->hw->mcam;
 749	int blkaddr, index;
 750
 751	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 752	if (blkaddr < 0)
 753		return;
 754
 755	/* Get 'pcifunc' of PF device */
 756	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 757
 758	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 759					 nixlf, NIXLF_PROMISC_ENTRY);
 760	npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
 761}
 762
 763void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
 764				       int nixlf, u64 chan)
 765{
 766	struct rvu_pfvf *pfvf;
 767	struct npc_install_flow_req req = { 0 };
 768	struct npc_install_flow_rsp rsp = { 0 };
 769	struct npc_mcam *mcam = &rvu->hw->mcam;
 770	struct rvu_hwinfo *hw = rvu->hw;
 771	int blkaddr, index;
 772
 773	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 774	if (blkaddr < 0)
 775		return;
 776
 777	/* Skip LBK VFs */
 778	if (is_lbk_vf(rvu, pcifunc))
 779		return;
 780
 781	/* If pkt replication is not supported,
 782	 * then only PF is allowed to add a bcast match entry.
 783	 */
 784	if (!hw->cap.nix_rx_multicast && is_vf(pcifunc))
 785		return;
 786
 787	/* Get 'pcifunc' of PF device */
 788	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 789	pfvf = rvu_get_pfvf(rvu, pcifunc);
 790
 791	/* Bcast rule should not be installed if both DMAC
 792	 * and LXMB extraction is not supported by the profile.
 793	 */
 794	if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) &&
 795	    !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf))
 796		return;
 797
 798	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 799					 nixlf, NIXLF_BCAST_ENTRY);
 800
 801	if (!hw->cap.nix_rx_multicast) {
 802		/* Early silicon doesn't support pkt replication,
 803		 * so install entry with UCAST action, so that PF
 804		 * receives all broadcast packets.
 805		 */
 806		req.op = NIX_RX_ACTIONOP_UCAST;
 807	} else {
 808		req.op = NIX_RX_ACTIONOP_MCAST;
 809		req.index = pfvf->bcast_mce_idx;
 810	}
 811
 812	eth_broadcast_addr((u8 *)&req.packet.dmac);
 813	eth_broadcast_addr((u8 *)&req.mask.dmac);
 814	req.features = BIT_ULL(NPC_DMAC);
 815	req.channel = chan;
 816	req.chan_mask = 0xFFFU;
 817	req.intf = pfvf->nix_rx_intf;
 818	req.entry = index;
 819	req.hdr.pcifunc = 0; /* AF is requester */
 820	req.vf = pcifunc;
 821
 822	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
 823}
 824
 825void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
 826				    u64 chan)
 827{
 828	struct npc_install_flow_req req = { 0 };
 829	struct npc_install_flow_rsp rsp = { 0 };
 830	struct npc_mcam *mcam = &rvu->hw->mcam;
 831	struct rvu_hwinfo *hw = rvu->hw;
 832	int blkaddr, ucast_idx, index;
 833	u8 mac_addr[ETH_ALEN] = { 0 };
 834	struct nix_rx_action action = { 0 };
 835	struct rvu_pfvf *pfvf;
 836	u8 flow_key_alg;
 837	u16 vf_func;
 838
 839	/* Only CGX PF/VF can add allmulticast entry */
 840	if (is_lbk_vf(rvu, pcifunc) && is_sdp_vf(rvu, pcifunc))
 841		return;
 842
 843	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 844	if (blkaddr < 0)
 845		return;
 846
 847	/* Get 'pcifunc' of PF device */
 848	vf_func = pcifunc & RVU_PFVF_FUNC_MASK;
 849	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 850	pfvf = rvu_get_pfvf(rvu, pcifunc);
 851
 852	/* Mcast rule should not be installed if both DMAC
 853	 * and LXMB extraction is not supported by the profile.
 854	 */
 855	if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) &&
 856	    !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf))
 857		return;
 858
 859	index = npc_get_nixlf_mcam_index(mcam, pcifunc,
 860					 nixlf, NIXLF_ALLMULTI_ENTRY);
 861
 862	/* If the corresponding PF's ucast action is RSS,
 863	 * use the same action for multicast entry also
 864	 */
 865	ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
 866					     nixlf, NIXLF_UCAST_ENTRY);
 867	if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
 868		*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
 869							blkaddr, ucast_idx);
 870
 871	flow_key_alg = action.flow_key_alg;
 872	if (action.op != NIX_RX_ACTIONOP_RSS) {
 873		*(u64 *)&action = 0;
 874		action.op = NIX_RX_ACTIONOP_UCAST;
 875		action.pf_func = pcifunc;
 876	}
 877
 878	/* RX_ACTION set to MCAST for CGX PF's */
 879	if (hw->cap.nix_rx_multicast && pfvf->use_mce_list) {
 880		*(u64 *)&action = 0;
 881		action.op = NIX_RX_ACTIONOP_MCAST;
 882		action.index = pfvf->mcast_mce_idx;
 883	}
 884
 885	mac_addr[0] = 0x01;	/* LSB bit of 1st byte in DMAC */
 886	ether_addr_copy(req.packet.dmac, mac_addr);
 887	ether_addr_copy(req.mask.dmac, mac_addr);
 888	req.features = BIT_ULL(NPC_DMAC);
 889
 890	/* For cn10k the upper two bits of the channel number are
 891	 * cpt channel number. with masking out these bits in the
 892	 * mcam entry, same entry used for NIX will allow packets
 893	 * received from cpt for parsing.
 894	 */
 895	if (!is_rvu_otx2(rvu))
 896		req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
 897	else
 898		req.chan_mask = 0xFFFU;
 899
 900	req.channel = chan;
 901	req.intf = pfvf->nix_rx_intf;
 902	req.entry = index;
 903	req.op = action.op;
 904	req.hdr.pcifunc = 0; /* AF is requester */
 905	req.vf = pcifunc | vf_func;
 906	req.index = action.index;
 907	req.match_id = action.match_id;
 908	req.flow_key_alg = flow_key_alg;
 909
 910	rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
 911}
 912
 913void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
 914				   bool enable)
 915{
 916	struct npc_mcam *mcam = &rvu->hw->mcam;
 917	int blkaddr, index;
 918
 919	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
 920	if (blkaddr < 0)
 921		return;
 922
 923	/* Get 'pcifunc' of PF device */
 924	pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
 925
 926	index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
 927					 NIXLF_ALLMULTI_ENTRY);
 928	npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
 929}
 930
 931static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam,
 932				     int blkaddr, u16 pcifunc, u64 rx_action)
 933{
 934	int actindex, index, bank, entry;
 935	struct rvu_npc_mcam_rule *rule;
 936	bool enable, update;
 937
 938	if (!(pcifunc & RVU_PFVF_FUNC_MASK))
 939		return;
 940
 941	mutex_lock(&mcam->lock);
 942	for (index = 0; index < mcam->bmap_entries; index++) {
 943		if (mcam->entry2target_pffunc[index] == pcifunc) {
 944			update = true;
 945			/* update not needed for the rules added via ntuple filters */
 946			list_for_each_entry(rule, &mcam->mcam_rules, list) {
 947				if (rule->entry == index)
 948					update = false;
 949			}
 950			if (!update)
 951				continue;
 952			bank = npc_get_bank(mcam, index);
 953			actindex = index;
 954			entry = index & (mcam->banksize - 1);
 955
 956			/* read vf flow entry enable status */
 957			enable = is_mcam_entry_enabled(rvu, mcam, blkaddr,
 958						       actindex);
 959			/* disable before mcam entry update */
 960			npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex,
 961					      false);
 962			/* update 'action' */
 963			rvu_write64(rvu, blkaddr,
 964				    NPC_AF_MCAMEX_BANKX_ACTION(entry, bank),
 965				    rx_action);
 966			if (enable)
 967				npc_enable_mcam_entry(rvu, mcam, blkaddr,
 968						      actindex, true);
 969		}
 970	}
 971	mutex_unlock(&mcam->lock);
 972}
 973
 974static void npc_update_rx_action_with_alg_idx(struct rvu *rvu, struct nix_rx_action action,
 975					      struct rvu_pfvf *pfvf, int mcam_index, int blkaddr,
 976					      int alg_idx)
 977
 978{
 979	struct npc_mcam *mcam = &rvu->hw->mcam;
 980	struct rvu_hwinfo *hw = rvu->hw;
 981	int bank, op_rss;
 982
 983	if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_index))
 984		return;
 985
 986	op_rss = (!hw->cap.nix_rx_multicast || !pfvf->use_mce_list);
 987
 988	bank = npc_get_bank(mcam, mcam_index);
 989	mcam_index &= (mcam->banksize - 1);
 990
 991	/* If Rx action is MCAST update only RSS algorithm index */
 992	if (!op_rss) {
 993		*(u64 *)&action = rvu_read64(rvu, blkaddr,
 994				NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank));
 995
 996		action.flow_key_alg = alg_idx;
 997	}
 998	rvu_write64(rvu, blkaddr,
 999		    NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank), *(u64 *)&action);
1000}
1001
1002void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
1003				    int group, int alg_idx, int mcam_index)
1004{
1005	struct npc_mcam *mcam = &rvu->hw->mcam;
1006	struct nix_rx_action action;
1007	int blkaddr, index, bank;
1008	struct rvu_pfvf *pfvf;
1009
1010	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1011	if (blkaddr < 0)
1012		return;
1013
1014	/* Check if this is for reserved default entry */
1015	if (mcam_index < 0) {
1016		if (group != DEFAULT_RSS_CONTEXT_GROUP)
1017			return;
1018		index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1019						 nixlf, NIXLF_UCAST_ENTRY);
1020	} else {
1021		/* TODO: validate this mcam index */
1022		index = mcam_index;
1023	}
1024
1025	if (index >= mcam->total_entries)
1026		return;
1027
1028	bank = npc_get_bank(mcam, index);
1029	index &= (mcam->banksize - 1);
1030
1031	*(u64 *)&action = rvu_read64(rvu, blkaddr,
1032				     NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
1033	/* Ignore if no action was set earlier */
1034	if (!*(u64 *)&action)
1035		return;
1036
1037	action.op = NIX_RX_ACTIONOP_RSS;
1038	action.pf_func = pcifunc;
1039	action.index = group;
1040	action.flow_key_alg = alg_idx;
1041
1042	rvu_write64(rvu, blkaddr,
1043		    NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
1044
1045	/* update the action change in default rule */
1046	pfvf = rvu_get_pfvf(rvu, pcifunc);
1047	if (pfvf->def_ucast_rule)
1048		pfvf->def_ucast_rule->rx_action = action;
1049
1050	if (mcam_index < 0) {
1051		/* update the VF flow rule action with the VF default
1052		 * entry action
1053		 */
1054		npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc,
1055					 *(u64 *)&action);
1056
1057		index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1058						 nixlf, NIXLF_PROMISC_ENTRY);
1059
1060		/* If PF's promiscuous  entry is enabled,
1061		 * Set RSS action for that entry as well
1062		 */
1063		npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index,
1064						  blkaddr, alg_idx);
1065
1066		index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1067						 nixlf, NIXLF_ALLMULTI_ENTRY);
1068		/* If PF's allmulti  entry is enabled,
1069		 * Set RSS action for that entry as well
1070		 */
1071		npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index,
1072						  blkaddr, alg_idx);
1073	}
1074}
1075
1076void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
1077				  int nixlf, int type, bool enable)
1078{
1079	struct npc_mcam *mcam = &rvu->hw->mcam;
1080	struct rvu_hwinfo *hw = rvu->hw;
1081	struct nix_mce_list *mce_list;
1082	int index, blkaddr, mce_idx;
1083	struct rvu_pfvf *pfvf;
1084
1085	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1086	if (blkaddr < 0)
1087		return;
1088
1089	index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK,
1090					 nixlf, type);
1091
1092	/* disable MCAM entry when packet replication is not supported by hw */
1093	if (!hw->cap.nix_rx_multicast && !is_vf(pcifunc)) {
1094		npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1095		return;
1096	}
1097
1098	/* return incase mce list is not enabled */
1099	pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1100	if (hw->cap.nix_rx_multicast && is_vf(pcifunc) &&
1101	    type != NIXLF_BCAST_ENTRY && !pfvf->use_mce_list)
1102		return;
1103
1104	nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx);
1105
1106	nix_update_mce_list(rvu, pcifunc, mce_list,
1107			    mce_idx, index, enable);
1108	if (enable)
1109		npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1110}
1111
1112static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,
1113				       int nixlf, bool enable)
1114{
1115	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1116	struct npc_mcam *mcam = &rvu->hw->mcam;
1117	int index, blkaddr;
1118
1119	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1120	if (blkaddr < 0)
1121		return;
1122
1123	/* Ucast MCAM match entry of this PF/VF */
1124	if (npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC),
1125				     pfvf->nix_rx_intf)) {
1126		index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1127						 nixlf, NIXLF_UCAST_ENTRY);
1128		npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1129	}
1130
1131	/* Nothing to do for VFs, on platforms where pkt replication
1132	 * is not supported
1133	 */
1134	if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast)
1135		return;
1136
1137	/* add/delete pf_func to broadcast MCE list */
1138	npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1139				     NIXLF_BCAST_ENTRY, enable);
1140}
1141
1142void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1143{
1144	if (nixlf < 0)
1145		return;
1146
1147	npc_enadis_default_entries(rvu, pcifunc, nixlf, false);
1148
1149	/* Delete multicast and promisc MCAM entries */
1150	npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1151				     NIXLF_ALLMULTI_ENTRY, false);
1152	npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1153				     NIXLF_PROMISC_ENTRY, false);
1154}
1155
1156bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable)
1157{
1158	int blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1159	struct npc_mcam *mcam = &rvu->hw->mcam;
1160	struct rvu_npc_mcam_rule *rule, *tmp;
1161
1162	mutex_lock(&mcam->lock);
1163
1164	list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1165		if (rule->intf != intf)
1166			continue;
1167
1168		if (rule->entry != entry)
1169			continue;
1170
1171		rule->enable = enable;
1172		mutex_unlock(&mcam->lock);
1173
1174		npc_enable_mcam_entry(rvu, mcam, blkaddr,
1175				      entry, enable);
1176
1177		return true;
1178	}
1179
1180	mutex_unlock(&mcam->lock);
1181	return false;
1182}
1183
1184void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1185{
1186	if (nixlf < 0)
1187		return;
1188
1189	/* Enables only broadcast match entry. Promisc/Allmulti are enabled
1190	 * in set_rx_mode mbox handler.
1191	 */
1192	npc_enadis_default_entries(rvu, pcifunc, nixlf, true);
1193}
1194
1195void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1196{
1197	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1198	struct npc_mcam *mcam = &rvu->hw->mcam;
1199	struct rvu_npc_mcam_rule *rule, *tmp;
1200	int blkaddr;
1201
1202	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1203	if (blkaddr < 0)
1204		return;
1205
1206	mutex_lock(&mcam->lock);
1207
1208	/* Disable MCAM entries directing traffic to this 'pcifunc' */
1209	list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1210		if (is_npc_intf_rx(rule->intf) &&
1211		    rule->rx_action.pf_func == pcifunc &&
1212		    rule->rx_action.op != NIX_RX_ACTIONOP_MCAST) {
1213			npc_enable_mcam_entry(rvu, mcam, blkaddr,
1214					      rule->entry, false);
1215			rule->enable = false;
1216			/* Indicate that default rule is disabled */
1217			if (rule->default_rule) {
1218				pfvf->def_ucast_rule = NULL;
1219				list_del(&rule->list);
1220				kfree(rule);
1221			}
1222		}
1223	}
1224
1225	mutex_unlock(&mcam->lock);
1226
1227	npc_mcam_disable_flows(rvu, pcifunc);
1228
1229	rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1230}
1231
1232void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1233{
1234	struct npc_mcam *mcam = &rvu->hw->mcam;
1235	struct rvu_npc_mcam_rule *rule, *tmp;
1236	int blkaddr;
1237
1238	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1239	if (blkaddr < 0)
1240		return;
1241
1242	mutex_lock(&mcam->lock);
1243
1244	/* Free all MCAM entries owned by this 'pcifunc' */
1245	npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
1246
1247	/* Free all MCAM counters owned by this 'pcifunc' */
1248	npc_mcam_free_all_counters(rvu, mcam, pcifunc);
1249
1250	/* Delete MCAM entries owned by this 'pcifunc' */
1251	list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1252		if (rule->owner == pcifunc && !rule->default_rule) {
1253			list_del(&rule->list);
1254			kfree(rule);
1255		}
1256	}
1257
1258	mutex_unlock(&mcam->lock);
1259
1260	rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1261}
1262
1263static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr,
1264				struct npc_mcam_kex *mkex, u8 intf)
1265{
1266	int lid, lt, ld, fl;
1267
1268	if (is_npc_intf_tx(intf))
1269		return;
1270
1271	rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1272		    mkex->keyx_cfg[NIX_INTF_RX]);
1273
1274	/* Program LDATA */
1275	for (lid = 0; lid < NPC_MAX_LID; lid++) {
1276		for (lt = 0; lt < NPC_MAX_LT; lt++) {
1277			for (ld = 0; ld < NPC_MAX_LD; ld++)
1278				SET_KEX_LD(intf, lid, lt, ld,
1279					   mkex->intf_lid_lt_ld[NIX_INTF_RX]
1280					   [lid][lt][ld]);
1281		}
1282	}
1283	/* Program LFLAGS */
1284	for (ld = 0; ld < NPC_MAX_LD; ld++) {
1285		for (fl = 0; fl < NPC_MAX_LFL; fl++)
1286			SET_KEX_LDFLAGS(intf, ld, fl,
1287					mkex->intf_ld_flags[NIX_INTF_RX]
1288					[ld][fl]);
1289	}
1290}
1291
1292static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr,
1293				struct npc_mcam_kex *mkex, u8 intf)
1294{
1295	int lid, lt, ld, fl;
1296
1297	if (is_npc_intf_rx(intf))
1298		return;
1299
1300	rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1301		    mkex->keyx_cfg[NIX_INTF_TX]);
1302
1303	/* Program LDATA */
1304	for (lid = 0; lid < NPC_MAX_LID; lid++) {
1305		for (lt = 0; lt < NPC_MAX_LT; lt++) {
1306			for (ld = 0; ld < NPC_MAX_LD; ld++)
1307				SET_KEX_LD(intf, lid, lt, ld,
1308					   mkex->intf_lid_lt_ld[NIX_INTF_TX]
1309					   [lid][lt][ld]);
1310		}
1311	}
1312	/* Program LFLAGS */
1313	for (ld = 0; ld < NPC_MAX_LD; ld++) {
1314		for (fl = 0; fl < NPC_MAX_LFL; fl++)
1315			SET_KEX_LDFLAGS(intf, ld, fl,
1316					mkex->intf_ld_flags[NIX_INTF_TX]
1317					[ld][fl]);
1318	}
1319}
1320
1321static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr,
1322				     struct npc_mcam_kex *mkex)
1323{
1324	struct rvu_hwinfo *hw = rvu->hw;
1325	u8 intf;
1326	int ld;
1327
1328	for (ld = 0; ld < NPC_MAX_LD; ld++)
1329		rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld),
1330			    mkex->kex_ld_flags[ld]);
1331
1332	for (intf = 0; intf < hw->npc_intfs; intf++) {
1333		npc_program_mkex_rx(rvu, blkaddr, mkex, intf);
1334		npc_program_mkex_tx(rvu, blkaddr, mkex, intf);
1335	}
1336
1337	/* Programme mkex hash profile */
1338	npc_program_mkex_hash(rvu, blkaddr);
1339}
1340
1341static int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr,
1342				 u64 *size)
1343{
1344	u64 prfl_addr, prfl_sz;
1345
1346	if (!rvu->fwdata)
1347		return -EINVAL;
1348
1349	prfl_addr = rvu->fwdata->mcam_addr;
1350	prfl_sz = rvu->fwdata->mcam_sz;
1351
1352	if (!prfl_addr || !prfl_sz)
1353		return -EINVAL;
1354
1355	*prfl_img_addr = ioremap_wc(prfl_addr, prfl_sz);
1356	if (!(*prfl_img_addr))
1357		return -ENOMEM;
1358
1359	*size = prfl_sz;
1360
1361	return 0;
1362}
1363
1364/* strtoull of "mkexprof" with base:36 */
1365#define MKEX_END_SIGN  0xdeadbeef
1366
1367static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr,
1368				  const char *mkex_profile)
1369{
1370	struct device *dev = &rvu->pdev->dev;
1371	struct npc_mcam_kex *mcam_kex;
1372	void __iomem *mkex_prfl_addr = NULL;
1373	u64 prfl_sz;
1374	int ret;
1375
1376	/* If user not selected mkex profile */
1377	if (rvu->kpu_fwdata_sz ||
1378	    !strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN))
1379		goto program_mkex;
1380
1381	/* Setting up the mapping for mkex profile image */
1382	ret = npc_fwdb_prfl_img_map(rvu, &mkex_prfl_addr, &prfl_sz);
1383	if (ret < 0)
1384		goto program_mkex;
1385
1386	mcam_kex = (struct npc_mcam_kex __force *)mkex_prfl_addr;
1387
1388	while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) {
1389		/* Compare with mkex mod_param name string */
1390		if (mcam_kex->mkex_sign == MKEX_SIGN &&
1391		    !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) {
1392			/* Due to an errata (35786) in A0/B0 pass silicon,
1393			 * parse nibble enable configuration has to be
1394			 * identical for both Rx and Tx interfaces.
1395			 */
1396			if (!is_rvu_96xx_B0(rvu) ||
1397			    mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX])
1398				rvu->kpu.mkex = mcam_kex;
1399			goto program_mkex;
1400		}
1401
1402		mcam_kex++;
1403		prfl_sz -= sizeof(struct npc_mcam_kex);
1404	}
1405	dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile);
1406
1407program_mkex:
1408	dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name);
1409	/* Program selected mkex profile */
1410	npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex);
1411	if (mkex_prfl_addr)
1412		iounmap(mkex_prfl_addr);
1413}
1414
1415static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
1416				 const struct npc_kpu_profile_action *kpuaction,
1417				 int kpu, int entry, bool pkind)
1418{
1419	struct npc_kpu_action0 action0 = {0};
1420	struct npc_kpu_action1 action1 = {0};
1421	u64 reg;
1422
1423	action1.errlev = kpuaction->errlev;
1424	action1.errcode = kpuaction->errcode;
1425	action1.dp0_offset = kpuaction->dp0_offset;
1426	action1.dp1_offset = kpuaction->dp1_offset;
1427	action1.dp2_offset = kpuaction->dp2_offset;
1428
1429	if (pkind)
1430		reg = NPC_AF_PKINDX_ACTION1(entry);
1431	else
1432		reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
1433
1434	rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
1435
1436	action0.byp_count = kpuaction->bypass_count;
1437	action0.capture_ena = kpuaction->cap_ena;
1438	action0.parse_done = kpuaction->parse_done;
1439	action0.next_state = kpuaction->next_state;
1440	action0.capture_lid = kpuaction->lid;
1441	action0.capture_ltype = kpuaction->ltype;
1442	action0.capture_flags = kpuaction->flags;
1443	action0.ptr_advance = kpuaction->ptr_advance;
1444	action0.var_len_offset = kpuaction->offset;
1445	action0.var_len_mask = kpuaction->mask;
1446	action0.var_len_right = kpuaction->right;
1447	action0.var_len_shift = kpuaction->shift;
1448
1449	if (pkind)
1450		reg = NPC_AF_PKINDX_ACTION0(entry);
1451	else
1452		reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
1453
1454	rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
1455}
1456
1457static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
1458			      const struct npc_kpu_profile_cam *kpucam,
1459			      int kpu, int entry)
1460{
1461	struct npc_kpu_cam cam0 = {0};
1462	struct npc_kpu_cam cam1 = {0};
1463
1464	cam1.state = kpucam->state & kpucam->state_mask;
1465	cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
1466	cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
1467	cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
1468
1469	cam0.state = ~kpucam->state & kpucam->state_mask;
1470	cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
1471	cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
1472	cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
1473
1474	rvu_write64(rvu, blkaddr,
1475		    NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
1476	rvu_write64(rvu, blkaddr,
1477		    NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
1478}
1479
1480static inline u64 enable_mask(int count)
1481{
1482	return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
1483}
1484
1485static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
1486				    const struct npc_kpu_profile *profile)
1487{
1488	int entry, num_entries, max_entries;
1489	u64 entry_mask;
1490
1491	if (profile->cam_entries != profile->action_entries) {
1492		dev_err(rvu->dev,
1493			"KPU%d: CAM and action entries [%d != %d] not equal\n",
1494			kpu, profile->cam_entries, profile->action_entries);
1495	}
1496
1497	max_entries = rvu->hw->npc_kpu_entries;
1498
1499	/* Program CAM match entries for previous KPU extracted data */
1500	num_entries = min_t(int, profile->cam_entries, max_entries);
1501	for (entry = 0; entry < num_entries; entry++)
1502		npc_config_kpucam(rvu, blkaddr,
1503				  &profile->cam[entry], kpu, entry);
1504
1505	/* Program this KPU's actions */
1506	num_entries = min_t(int, profile->action_entries, max_entries);
1507	for (entry = 0; entry < num_entries; entry++)
1508		npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
1509				     kpu, entry, false);
1510
1511	/* Enable all programmed entries */
1512	num_entries = min_t(int, profile->action_entries, profile->cam_entries);
1513	entry_mask = enable_mask(num_entries);
1514	/* Disable first KPU_MAX_CST_ENT entries for built-in profile */
1515	if (!rvu->kpu.custom)
1516		entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0);
1517	rvu_write64(rvu, blkaddr,
1518		    NPC_AF_KPUX_ENTRY_DISX(kpu, 0), entry_mask);
1519	if (num_entries > 64) {
1520		rvu_write64(rvu, blkaddr,
1521			    NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
1522			    enable_mask(num_entries - 64));
1523	}
1524
1525	/* Enable this KPU */
1526	rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
1527}
1528
1529static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile)
1530{
1531	profile->custom = 0;
1532	profile->name = def_pfl_name;
1533	profile->version = NPC_KPU_PROFILE_VER;
1534	profile->ikpu = ikpu_action_entries;
1535	profile->pkinds = ARRAY_SIZE(ikpu_action_entries);
1536	profile->kpu = npc_kpu_profiles;
1537	profile->kpus = ARRAY_SIZE(npc_kpu_profiles);
1538	profile->lt_def = &npc_lt_defaults;
1539	profile->mkex = &npc_mkex_default;
1540	profile->mkex_hash = &npc_mkex_hash_default;
1541
1542	return 0;
1543}
1544
1545static int npc_apply_custom_kpu(struct rvu *rvu,
1546				struct npc_kpu_profile_adapter *profile)
1547{
1548	size_t hdr_sz = sizeof(struct npc_kpu_profile_fwdata), offset = 0;
1549	struct npc_kpu_profile_fwdata *fw = rvu->kpu_fwdata;
1550	struct npc_kpu_profile_action *action;
1551	struct npc_kpu_profile_cam *cam;
1552	struct npc_kpu_fwdata *fw_kpu;
1553	int entries;
1554	u16 kpu, entry;
1555
1556	if (rvu->kpu_fwdata_sz < hdr_sz) {
1557		dev_warn(rvu->dev, "Invalid KPU profile size\n");
1558		return -EINVAL;
1559	}
1560	if (le64_to_cpu(fw->signature) != KPU_SIGN) {
1561		dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n",
1562			 fw->signature);
1563		return -EINVAL;
1564	}
1565	/* Verify if the using known profile structure */
1566	if (NPC_KPU_VER_MAJ(profile->version) >
1567	    NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)) {
1568		dev_warn(rvu->dev, "Not supported Major version: %d > %d\n",
1569			 NPC_KPU_VER_MAJ(profile->version),
1570			 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER));
1571		return -EINVAL;
1572	}
1573	/* Verify if profile is aligned with the required kernel changes */
1574	if (NPC_KPU_VER_MIN(profile->version) <
1575	    NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER)) {
1576		dev_warn(rvu->dev,
1577			 "Invalid KPU profile version: %d.%d.%d expected version <= %d.%d.%d\n",
1578			 NPC_KPU_VER_MAJ(profile->version),
1579			 NPC_KPU_VER_MIN(profile->version),
1580			 NPC_KPU_VER_PATCH(profile->version),
1581			 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER),
1582			 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER),
1583			 NPC_KPU_VER_PATCH(NPC_KPU_PROFILE_VER));
1584		return -EINVAL;
1585	}
1586	/* Verify if profile fits the HW */
1587	if (fw->kpus > profile->kpus) {
1588		dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus,
1589			 profile->kpus);
1590		return -EINVAL;
1591	}
1592
1593	profile->custom = 1;
1594	profile->name = fw->name;
1595	profile->version = le64_to_cpu(fw->version);
1596	profile->mkex = &fw->mkex;
1597	profile->lt_def = &fw->lt_def;
1598
1599	for (kpu = 0; kpu < fw->kpus; kpu++) {
1600		fw_kpu = (struct npc_kpu_fwdata *)(fw->data + offset);
1601		if (fw_kpu->entries > KPU_MAX_CST_ENT)
1602			dev_warn(rvu->dev,
1603				 "Too many custom entries on KPU%d: %d > %d\n",
1604				 kpu, fw_kpu->entries, KPU_MAX_CST_ENT);
1605		entries = min(fw_kpu->entries, KPU_MAX_CST_ENT);
1606		cam = (struct npc_kpu_profile_cam *)fw_kpu->data;
1607		offset += sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam);
1608		action = (struct npc_kpu_profile_action *)(fw->data + offset);
1609		offset += fw_kpu->entries * sizeof(*action);
1610		if (rvu->kpu_fwdata_sz < hdr_sz + offset) {
1611			dev_warn(rvu->dev,
1612				 "Profile size mismatch on KPU%i parsing.\n",
1613				 kpu + 1);
1614			return -EINVAL;
1615		}
1616		for (entry = 0; entry < entries; entry++) {
1617			profile->kpu[kpu].cam[entry] = cam[entry];
1618			profile->kpu[kpu].action[entry] = action[entry];
1619		}
1620	}
1621
1622	return 0;
1623}
1624
1625static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr,
1626				 u64 prfl_sz, const char *kpu_profile)
1627{
1628	struct npc_kpu_profile_fwdata *kpu_data = NULL;
1629	int rc = -EINVAL;
1630
1631	kpu_data = (struct npc_kpu_profile_fwdata __force *)prfl_addr;
1632	if (le64_to_cpu(kpu_data->signature) == KPU_SIGN &&
1633	    !strncmp(kpu_data->name, kpu_profile, KPU_NAME_LEN)) {
1634		dev_info(rvu->dev, "Loading KPU profile from firmware db: %s\n",
1635			 kpu_profile);
1636		rvu->kpu_fwdata = kpu_data;
1637		rvu->kpu_fwdata_sz = prfl_sz;
1638		rvu->kpu_prfl_addr = prfl_addr;
1639		rc = 0;
1640	}
1641
1642	return rc;
1643}
1644
1645static int npc_fwdb_detect_load_prfl_img(struct rvu *rvu, uint64_t prfl_sz,
1646					 const char *kpu_profile)
1647{
1648	struct npc_coalesced_kpu_prfl *img_data = NULL;
1649	int i = 0, rc = -EINVAL;
1650	void __iomem *kpu_prfl_addr;
1651	u32 offset;
1652
1653	img_data = (struct npc_coalesced_kpu_prfl __force *)rvu->kpu_prfl_addr;
1654	if (le64_to_cpu(img_data->signature) == KPU_SIGN &&
1655	    !strncmp(img_data->name, kpu_profile, KPU_NAME_LEN)) {
1656		/* Loaded profile is a single KPU profile. */
1657		rc = npc_load_kpu_prfl_img(rvu, rvu->kpu_prfl_addr,
1658					   prfl_sz, kpu_profile);
1659		goto done;
1660	}
1661
1662	/* Loaded profile is coalesced image, offset of first KPU profile.*/
1663	offset = offsetof(struct npc_coalesced_kpu_prfl, prfl_sz) +
1664		(img_data->num_prfl * sizeof(uint16_t));
1665	/* Check if mapped image is coalesced image. */
1666	while (i < img_data->num_prfl) {
1667		/* Profile image offsets are rounded up to next 8 multiple.*/
1668		offset = ALIGN_8B_CEIL(offset);
1669		kpu_prfl_addr = (void __iomem *)((uintptr_t)rvu->kpu_prfl_addr +
1670					 offset);
1671		rc = npc_load_kpu_prfl_img(rvu, kpu_prfl_addr,
1672					   img_data->prfl_sz[i], kpu_profile);
1673		if (!rc)
1674			break;
1675		/* Calculating offset of profile image based on profile size.*/
1676		offset += img_data->prfl_sz[i];
1677		i++;
1678	}
1679done:
1680	return rc;
1681}
1682
1683static int npc_load_kpu_profile_fwdb(struct rvu *rvu, const char *kpu_profile)
1684{
1685	int ret = -EINVAL;
1686	u64 prfl_sz;
1687
1688	/* Setting up the mapping for NPC profile image */
1689	ret = npc_fwdb_prfl_img_map(rvu, &rvu->kpu_prfl_addr, &prfl_sz);
1690	if (ret < 0)
1691		goto done;
1692
1693	/* Detect if profile is coalesced or single KPU profile and load */
1694	ret = npc_fwdb_detect_load_prfl_img(rvu, prfl_sz, kpu_profile);
1695	if (ret == 0)
1696		goto done;
1697
1698	/* Cleaning up if KPU profile image from fwdata is not valid. */
1699	if (rvu->kpu_prfl_addr) {
1700		iounmap(rvu->kpu_prfl_addr);
1701		rvu->kpu_prfl_addr = NULL;
1702		rvu->kpu_fwdata_sz = 0;
1703		rvu->kpu_fwdata = NULL;
1704	}
1705
1706done:
1707	return ret;
1708}
1709
1710static void npc_load_kpu_profile(struct rvu *rvu)
1711{
1712	struct npc_kpu_profile_adapter *profile = &rvu->kpu;
1713	const char *kpu_profile = rvu->kpu_pfl_name;
1714	const struct firmware *fw = NULL;
1715	bool retry_fwdb = false;
1716
1717	/* If user not specified profile customization */
1718	if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN))
1719		goto revert_to_default;
1720	/* First prepare default KPU, then we'll customize top entries. */
1721	npc_prepare_default_kpu(profile);
1722
1723	/* Order of preceedence for load loading NPC profile (high to low)
1724	 * Firmware binary in filesystem.
1725	 * Firmware database method.
1726	 * Default KPU profile.
1727	 */
1728	if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) {
1729		dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n",
1730			 kpu_profile);
1731		rvu->kpu_fwdata = kzalloc(fw->size, GFP_KERNEL);
1732		if (rvu->kpu_fwdata) {
1733			memcpy(rvu->kpu_fwdata, fw->data, fw->size);
1734			rvu->kpu_fwdata_sz = fw->size;
1735		}
1736		release_firmware(fw);
1737		retry_fwdb = true;
1738		goto program_kpu;
1739	}
1740
1741load_image_fwdb:
1742	/* Loading the KPU profile using firmware database */
1743	if (npc_load_kpu_profile_fwdb(rvu, kpu_profile))
1744		goto revert_to_default;
1745
1746program_kpu:
1747	/* Apply profile customization if firmware was loaded. */
1748	if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) {
1749		/* If image from firmware filesystem fails to load or invalid
1750		 * retry with firmware database method.
1751		 */
1752		if (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) {
1753			/* Loading image from firmware database failed. */
1754			if (rvu->kpu_prfl_addr) {
1755				iounmap(rvu->kpu_prfl_addr);
1756				rvu->kpu_prfl_addr = NULL;
1757			} else {
1758				kfree(rvu->kpu_fwdata);
1759			}
1760			rvu->kpu_fwdata = NULL;
1761			rvu->kpu_fwdata_sz = 0;
1762			if (retry_fwdb) {
1763				retry_fwdb = false;
1764				goto load_image_fwdb;
1765			}
1766		}
1767
1768		dev_warn(rvu->dev,
1769			 "Can't load KPU profile %s. Using default.\n",
1770			 kpu_profile);
1771		kfree(rvu->kpu_fwdata);
1772		rvu->kpu_fwdata = NULL;
1773		goto revert_to_default;
1774	}
1775
1776	dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n",
1777		 profile->name, NPC_KPU_VER_MAJ(profile->version),
1778		 NPC_KPU_VER_MIN(profile->version),
1779		 NPC_KPU_VER_PATCH(profile->version));
1780
1781	return;
1782
1783revert_to_default:
1784	npc_prepare_default_kpu(profile);
1785}
1786
1787static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
1788{
1789	struct rvu_hwinfo *hw = rvu->hw;
1790	int num_pkinds, num_kpus, idx;
1791
1792	/* Disable all KPUs and their entries */
1793	for (idx = 0; idx < hw->npc_kpus; idx++) {
1794		rvu_write64(rvu, blkaddr,
1795			    NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
1796		rvu_write64(rvu, blkaddr,
1797			    NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
1798		rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
1799	}
1800
1801	/* Load and customize KPU profile. */
1802	npc_load_kpu_profile(rvu);
1803
1804	/* First program IKPU profile i.e PKIND configs.
1805	 * Check HW max count to avoid configuring junk or
1806	 * writing to unsupported CSR addresses.
1807	 */
1808	num_pkinds = rvu->kpu.pkinds;
1809	num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds);
1810
1811	for (idx = 0; idx < num_pkinds; idx++)
1812		npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true);
1813
1814	/* Program KPU CAM and Action profiles */
1815	num_kpus = rvu->kpu.kpus;
1816	num_kpus = min_t(int, hw->npc_kpus, num_kpus);
1817
1818	for (idx = 0; idx < num_kpus; idx++)
1819		npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]);
1820}
1821
1822void npc_mcam_rsrcs_deinit(struct rvu *rvu)
1823{
1824	struct npc_mcam *mcam = &rvu->hw->mcam;
1825
1826	bitmap_free(mcam->bmap);
1827	bitmap_free(mcam->bmap_reverse);
1828	kfree(mcam->entry2pfvf_map);
1829	kfree(mcam->cntr2pfvf_map);
1830	kfree(mcam->entry2cntr_map);
1831	kfree(mcam->cntr_refcnt);
1832	kfree(mcam->entry2target_pffunc);
1833	kfree(mcam->counters.bmap);
1834}
1835
1836int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
1837{
1838	int nixlf_count = rvu_get_nixlf_count(rvu);
1839	struct npc_mcam *mcam = &rvu->hw->mcam;
1840	int rsvd, err;
1841	u16 index;
1842	int cntr;
1843	u64 cfg;
1844
1845	/* Actual number of MCAM entries vary by entry size */
1846	cfg = (rvu_read64(rvu, blkaddr,
1847			  NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
1848	mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
1849	mcam->keysize = cfg;
1850
1851	/* Number of banks combined per MCAM entry */
1852	if (cfg == NPC_MCAM_KEY_X4)
1853		mcam->banks_per_entry = 4;
1854	else if (cfg == NPC_MCAM_KEY_X2)
1855		mcam->banks_per_entry = 2;
1856	else
1857		mcam->banks_per_entry = 1;
1858
1859	/* Reserve one MCAM entry for each of the NIX LF to
1860	 * guarantee space to install default matching DMAC rule.
1861	 * Also reserve 2 MCAM entries for each PF for default
1862	 * channel based matching or 'bcast & promisc' matching to
1863	 * support BCAST and PROMISC modes of operation for PFs.
1864	 * PF0 is excluded.
1865	 */
1866	rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
1867		((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
1868	if (mcam->total_entries <= rsvd) {
1869		dev_warn(rvu->dev,
1870			 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
1871			 mcam->total_entries);
1872		return -ENOMEM;
1873	}
1874
1875	mcam->bmap_entries = mcam->total_entries - rsvd;
1876	mcam->nixlf_offset = mcam->bmap_entries;
1877	mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
1878
1879	/* Allocate bitmaps for managing MCAM entries */
1880	mcam->bmap = bitmap_zalloc(mcam->bmap_entries, GFP_KERNEL);
1881	if (!mcam->bmap)
1882		return -ENOMEM;
1883
1884	mcam->bmap_reverse = bitmap_zalloc(mcam->bmap_entries, GFP_KERNEL);
1885	if (!mcam->bmap_reverse)
1886		goto free_bmap;
1887
1888	mcam->bmap_fcnt = mcam->bmap_entries;
1889
1890	/* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
1891	mcam->entry2pfvf_map = kcalloc(mcam->bmap_entries, sizeof(u16),
1892				       GFP_KERNEL);
1893
1894	if (!mcam->entry2pfvf_map)
1895		goto free_bmap_reverse;
1896
1897	/* Reserve 1/8th of MCAM entries at the bottom for low priority
1898	 * allocations and another 1/8th at the top for high priority
1899	 * allocations.
1900	 */
1901	mcam->lprio_count = mcam->bmap_entries / 8;
1902	if (mcam->lprio_count > BITS_PER_LONG)
1903		mcam->lprio_count = round_down(mcam->lprio_count,
1904					       BITS_PER_LONG);
1905	mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;
1906	mcam->hprio_count = mcam->lprio_count;
1907	mcam->hprio_end = mcam->hprio_count;
1908
1909	/* Allocate bitmap for managing MCAM counters and memory
1910	 * for saving counter to RVU PFFUNC allocation mapping.
1911	 */
1912	err = rvu_alloc_bitmap(&mcam->counters);
1913	if (err)
1914		goto free_entry_map;
1915
1916	mcam->cntr2pfvf_map = kcalloc(mcam->counters.max, sizeof(u16),
1917				      GFP_KERNEL);
1918	if (!mcam->cntr2pfvf_map)
1919		goto free_cntr_bmap;
1920
1921	/* Alloc memory for MCAM entry to counter mapping and for tracking
1922	 * counter's reference count.
1923	 */
1924	mcam->entry2cntr_map = kcalloc(mcam->bmap_entries, sizeof(u16),
1925				       GFP_KERNEL);
1926	if (!mcam->entry2cntr_map)
1927		goto free_cntr_map;
1928
1929	mcam->cntr_refcnt = kcalloc(mcam->counters.max, sizeof(u16),
1930				    GFP_KERNEL);
1931	if (!mcam->cntr_refcnt)
1932		goto free_entry_cntr_map;
1933
1934	/* Alloc memory for saving target device of mcam rule */
1935	mcam->entry2target_pffunc = kmalloc_array(mcam->total_entries,
1936						  sizeof(u16), GFP_KERNEL);
1937	if (!mcam->entry2target_pffunc)
1938		goto free_cntr_refcnt;
1939
1940	for (index = 0; index < mcam->bmap_entries; index++) {
1941		mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
1942		mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
1943	}
1944
1945	for (cntr = 0; cntr < mcam->counters.max; cntr++)
1946		mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
1947
1948	mutex_init(&mcam->lock);
1949
1950	return 0;
1951
1952free_cntr_refcnt:
1953	kfree(mcam->cntr_refcnt);
1954free_entry_cntr_map:
1955	kfree(mcam->entry2cntr_map);
1956free_cntr_map:
1957	kfree(mcam->cntr2pfvf_map);
1958free_cntr_bmap:
1959	kfree(mcam->counters.bmap);
1960free_entry_map:
1961	kfree(mcam->entry2pfvf_map);
1962free_bmap_reverse:
1963	bitmap_free(mcam->bmap_reverse);
1964free_bmap:
1965	bitmap_free(mcam->bmap);
1966
1967	return -ENOMEM;
1968}
1969
1970static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr)
1971{
1972	struct npc_pkind *pkind = &rvu->hw->pkind;
1973	struct npc_mcam *mcam = &rvu->hw->mcam;
1974	struct rvu_hwinfo *hw = rvu->hw;
1975	u64 npc_const, npc_const1;
1976	u64 npc_const2 = 0;
1977
1978	npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1979	npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1);
1980	if (npc_const1 & BIT_ULL(63))
1981		npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2);
1982
1983	pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT;
1984	hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL;
1985	hw->npc_kpu_entries = npc_const1 & 0xFFFULL;
1986	hw->npc_kpus = (npc_const >> 8) & 0x1FULL;
1987	hw->npc_intfs = npc_const & 0xFULL;
1988	hw->npc_counters = (npc_const >> 48) & 0xFFFFULL;
1989
1990	mcam->banks = (npc_const >> 44) & 0xFULL;
1991	mcam->banksize = (npc_const >> 28) & 0xFFFFULL;
1992	hw->npc_stat_ena = BIT_ULL(9);
1993	/* Extended set */
1994	if (npc_const2) {
1995		hw->npc_ext_set = true;
1996		/* 96xx supports only match_stats and npc_counters
1997		 * reflected in NPC_AF_CONST reg.
1998		 * STAT_SEL and ENA are at [0:8] and 9 bit positions.
1999		 * 98xx has both match_stat and ext and npc_counter
2000		 * reflected in NPC_AF_CONST2
2001		 * STAT_SEL_EXT added at [12:14] bit position.
2002		 * cn10k supports only ext and hence npc_counters in
2003		 * NPC_AF_CONST is 0 and npc_counters reflected in NPC_AF_CONST2.
2004		 * STAT_SEL bitpos incremented from [0:8] to [0:11] and ENA bit moved to 63
2005		 */
2006		if (!hw->npc_counters)
2007			hw->npc_stat_ena = BIT_ULL(63);
2008		hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL;
2009		mcam->banksize = npc_const2 & 0xFFFFULL;
2010	}
2011
2012	mcam->counters.max = hw->npc_counters;
2013}
2014
2015static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr)
2016{
2017	struct npc_mcam_kex *mkex = rvu->kpu.mkex;
2018	struct npc_mcam *mcam = &rvu->hw->mcam;
2019	struct rvu_hwinfo *hw = rvu->hw;
2020	u64 nibble_ena, rx_kex, tx_kex;
2021	u8 intf;
2022
2023	/* Reserve last counter for MCAM RX miss action which is set to
2024	 * drop packet. This way we will know how many pkts didn't match
2025	 * any MCAM entry.
2026	 */
2027	mcam->counters.max--;
2028	mcam->rx_miss_act_cntr = mcam->counters.max;
2029
2030	rx_kex = mkex->keyx_cfg[NIX_INTF_RX];
2031	tx_kex = mkex->keyx_cfg[NIX_INTF_TX];
2032	nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex);
2033
2034	nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena);
2035	if (nibble_ena) {
2036		tx_kex &= ~NPC_PARSE_NIBBLE;
2037		tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena);
2038		mkex->keyx_cfg[NIX_INTF_TX] = tx_kex;
2039	}
2040
2041	/* Configure RX interfaces */
2042	for (intf = 0; intf < hw->npc_intfs; intf++) {
2043		if (is_npc_intf_tx(intf))
2044			continue;
2045
2046		/* Set RX MCAM search key size. LA..LE (ltype only) + Channel */
2047		rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
2048			    rx_kex);
2049
2050		/* If MCAM lookup doesn't result in a match, drop the received
2051		 * packet. And map this action to a counter to count dropped
2052		 * packets.
2053		 */
2054		rvu_write64(rvu, blkaddr,
2055			    NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP);
2056
2057		/* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9]
2058		 * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0]
2059		 */
2060		rvu_write64(rvu, blkaddr,
2061			    NPC_AF_INTFX_MISS_STAT_ACT(intf),
2062			    ((mcam->rx_miss_act_cntr >> 9) << 12) |
2063			    hw->npc_stat_ena | mcam->rx_miss_act_cntr);
2064	}
2065
2066	/* Configure TX interfaces */
2067	for (intf = 0; intf < hw->npc_intfs; intf++) {
2068		if (is_npc_intf_rx(intf))
2069			continue;
2070
2071		/* Extract Ltypes LID_LA to LID_LE */
2072		rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
2073			    tx_kex);
2074
2075		/* Set TX miss action to UCAST_DEFAULT i.e
2076		 * transmit the packet on NIX LF SQ's default channel.
2077		 */
2078		rvu_write64(rvu, blkaddr,
2079			    NPC_AF_INTFX_MISS_ACT(intf),
2080			    NIX_TX_ACTIONOP_UCAST_DEFAULT);
2081	}
2082}
2083
2084int rvu_npc_init(struct rvu *rvu)
2085{
2086	struct npc_kpu_profile_adapter *kpu = &rvu->kpu;
2087	struct npc_pkind *pkind = &rvu->hw->pkind;
2088	struct npc_mcam *mcam = &rvu->hw->mcam;
2089	int blkaddr, entry, bank, err;
2090
2091	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2092	if (blkaddr < 0) {
2093		dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
2094		return -ENODEV;
2095	}
2096
2097	rvu_npc_hw_init(rvu, blkaddr);
2098
2099	/* First disable all MCAM entries, to stop traffic towards NIXLFs */
2100	for (bank = 0; bank < mcam->banks; bank++) {
2101		for (entry = 0; entry < mcam->banksize; entry++)
2102			rvu_write64(rvu, blkaddr,
2103				    NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);
2104	}
2105
2106	err = rvu_alloc_bitmap(&pkind->rsrc);
2107	if (err)
2108		return err;
2109	/* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0',
2110	 * no need to configure PKIND for all LBKs separately.
2111	 */
2112	rvu_alloc_rsrc(&pkind->rsrc);
2113
2114	/* Allocate mem for pkind to PF and channel mapping info */
2115	pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
2116					 sizeof(u32), GFP_KERNEL);
2117	if (!pkind->pfchan_map)
2118		return -ENOMEM;
2119
2120	/* Configure KPU profile */
2121	npc_parser_profile_init(rvu, blkaddr);
2122
2123	/* Config Outer L2, IPv4's NPC layer info */
2124	rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
2125		    (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) |
2126		    kpu->lt_def->pck_ol2.ltype_mask);
2127	rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
2128		    (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) |
2129		    kpu->lt_def->pck_oip4.ltype_mask);
2130
2131	/* Config Inner IPV4 NPC layer info */
2132	rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4,
2133		    (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) |
2134		    kpu->lt_def->pck_iip4.ltype_mask);
2135
2136	/* Enable below for Rx pkts.
2137	 * - Outer IPv4 header checksum validation.
2138	 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B].
2139	 * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M].
2140	 * - Inner IPv4 header checksum validation.
2141	 * - Set non zero checksum error code value
2142	 */
2143	rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
2144		    rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
2145		    ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) |
2146		    BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1));
2147
2148	rvu_npc_setup_interfaces(rvu, blkaddr);
2149
2150	npc_config_secret_key(rvu, blkaddr);
2151	/* Configure MKEX profile */
2152	npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name);
2153
2154	err = npc_mcam_rsrcs_init(rvu, blkaddr);
2155	if (err)
2156		return err;
2157
2158	err = npc_flow_steering_init(rvu, blkaddr);
2159	if (err) {
2160		dev_err(rvu->dev,
2161			"Incorrect mkex profile loaded using default mkex\n");
2162		npc_load_mkex_profile(rvu, blkaddr, def_pfl_name);
2163	}
2164
2165	return 0;
2166}
2167
2168void rvu_npc_freemem(struct rvu *rvu)
2169{
2170	struct npc_pkind *pkind = &rvu->hw->pkind;
2171	struct npc_mcam *mcam = &rvu->hw->mcam;
2172
2173	kfree(pkind->rsrc.bmap);
2174	npc_mcam_rsrcs_deinit(rvu);
2175	if (rvu->kpu_prfl_addr)
2176		iounmap(rvu->kpu_prfl_addr);
2177	else
2178		kfree(rvu->kpu_fwdata);
2179	mutex_destroy(&mcam->lock);
2180}
2181
2182void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
2183				       int blkaddr, int *alloc_cnt,
2184				       int *enable_cnt)
2185{
2186	struct npc_mcam *mcam = &rvu->hw->mcam;
2187	int entry;
2188
2189	*alloc_cnt = 0;
2190	*enable_cnt = 0;
2191
2192	for (entry = 0; entry < mcam->bmap_entries; entry++) {
2193		if (mcam->entry2pfvf_map[entry] == pcifunc) {
2194			(*alloc_cnt)++;
2195			if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry))
2196				(*enable_cnt)++;
2197		}
2198	}
2199}
2200
2201void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
2202					 int blkaddr, int *alloc_cnt,
2203					 int *enable_cnt)
2204{
2205	struct npc_mcam *mcam = &rvu->hw->mcam;
2206	int cntr;
2207
2208	*alloc_cnt = 0;
2209	*enable_cnt = 0;
2210
2211	for (cntr = 0; cntr < mcam->counters.max; cntr++) {
2212		if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
2213			(*alloc_cnt)++;
2214			if (mcam->cntr_refcnt[cntr])
2215				(*enable_cnt)++;
2216		}
2217	}
2218}
2219
2220static int npc_mcam_verify_entry(struct npc_mcam *mcam,
2221				 u16 pcifunc, int entry)
2222{
2223	/* verify AF installed entries */
2224	if (is_pffunc_af(pcifunc))
2225		return 0;
2226	/* Verify if entry is valid and if it is indeed
2227	 * allocated to the requesting PFFUNC.
2228	 */
2229	if (entry >= mcam->bmap_entries)
2230		return NPC_MCAM_INVALID_REQ;
2231
2232	if (pcifunc != mcam->entry2pfvf_map[entry])
2233		return NPC_MCAM_PERM_DENIED;
2234
2235	return 0;
2236}
2237
2238static int npc_mcam_verify_counter(struct npc_mcam *mcam,
2239				   u16 pcifunc, int cntr)
2240{
2241	/* Verify if counter is valid and if it is indeed
2242	 * allocated to the requesting PFFUNC.
2243	 */
2244	if (cntr >= mcam->counters.max)
2245		return NPC_MCAM_INVALID_REQ;
2246
2247	if (pcifunc != mcam->cntr2pfvf_map[cntr])
2248		return NPC_MCAM_PERM_DENIED;
2249
2250	return 0;
2251}
2252
2253static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam,
2254					int blkaddr, u16 entry, u16 cntr)
2255{
2256	u16 index = entry & (mcam->banksize - 1);
2257	u32 bank = npc_get_bank(mcam, entry);
2258	struct rvu_hwinfo *hw = rvu->hw;
2259
2260	/* Set mapping and increment counter's refcnt */
2261	mcam->entry2cntr_map[entry] = cntr;
2262	mcam->cntr_refcnt[cntr]++;
2263	/* Enable stats */
2264	rvu_write64(rvu, blkaddr,
2265		    NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),
2266		    ((cntr >> 9) << 12) | hw->npc_stat_ena | cntr);
2267}
2268
2269static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu,
2270					  struct npc_mcam *mcam,
2271					  int blkaddr, u16 entry, u16 cntr)
2272{
2273	u16 index = entry & (mcam->banksize - 1);
2274	u32 bank = npc_get_bank(mcam, entry);
2275
2276	/* Remove mapping and reduce counter's refcnt */
2277	mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP;
2278	mcam->cntr_refcnt[cntr]--;
2279	/* Disable stats */
2280	rvu_write64(rvu, blkaddr,
2281		    NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);
2282}
2283
2284/* Sets MCAM entry in bitmap as used. Update
2285 * reverse bitmap too. Should be called with
2286 * 'mcam->lock' held.
2287 */
2288static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index)
2289{
2290	u16 entry, rentry;
2291
2292	entry = index;
2293	rentry = mcam->bmap_entries - index - 1;
2294
2295	__set_bit(entry, mcam->bmap);
2296	__set_bit(rentry, mcam->bmap_reverse);
2297	mcam->bmap_fcnt--;
2298}
2299
2300/* Sets MCAM entry in bitmap as free. Update
2301 * reverse bitmap too. Should be called with
2302 * 'mcam->lock' held.
2303 */
2304static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index)
2305{
2306	u16 entry, rentry;
2307
2308	entry = index;
2309	rentry = mcam->bmap_entries - index - 1;
2310
2311	__clear_bit(entry, mcam->bmap);
2312	__clear_bit(rentry, mcam->bmap_reverse);
2313	mcam->bmap_fcnt++;
2314}
2315
2316static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
2317				      int blkaddr, u16 pcifunc)
2318{
2319	u16 index, cntr;
2320
2321	/* Scan all MCAM entries and free the ones mapped to 'pcifunc' */
2322	for (index = 0; index < mcam->bmap_entries; index++) {
2323		if (mcam->entry2pfvf_map[index] == pcifunc) {
2324			mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
2325			/* Free the entry in bitmap */
2326			npc_mcam_clear_bit(mcam, index);
2327			/* Disable the entry */
2328			npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
2329
2330			/* Update entry2counter mapping */
2331			cntr = mcam->entry2cntr_map[index];
2332			if (cntr != NPC_MCAM_INVALID_MAP)
2333				npc_unmap_mcam_entry_and_cntr(rvu, mcam,
2334							      blkaddr, index,
2335							      cntr);
2336			mcam->entry2target_pffunc[index] = 0x0;
2337		}
2338	}
2339}
2340
2341static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
2342				       u16 pcifunc)
2343{
2344	u16 cntr;
2345
2346	/* Scan all MCAM counters and free the ones mapped to 'pcifunc' */
2347	for (cntr = 0; cntr < mcam->counters.max; cntr++) {
2348		if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
2349			mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
2350			mcam->cntr_refcnt[cntr] = 0;
2351			rvu_free_rsrc(&mcam->counters, cntr);
2352			/* This API is expected to be called after freeing
2353			 * MCAM entries, which inturn will remove
2354			 * 'entry to counter' mapping.
2355			 * No need to do it again.
2356			 */
2357		}
2358	}
2359}
2360
2361/* Find area of contiguous free entries of size 'nr'.
2362 * If not found return max contiguous free entries available.
2363 */
2364static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start,
2365				   u16 nr, u16 *max_area)
2366{
2367	u16 max_area_start = 0;
2368	u16 index, next, end;
2369
2370	*max_area = 0;
2371
2372again:
2373	index = find_next_zero_bit(map, size, start);
2374	if (index >= size)
2375		return max_area_start;
2376
2377	end = ((index + nr) >= size) ? size : index + nr;
2378	next = find_next_bit(map, end, index);
2379	if (*max_area < (next - index)) {
2380		*max_area = next - index;
2381		max_area_start = index;
2382	}
2383
2384	if (next < end) {
2385		start = next + 1;
2386		goto again;
2387	}
2388
2389	return max_area_start;
2390}
2391
2392/* Find number of free MCAM entries available
2393 * within range i.e in between 'start' and 'end'.
2394 */
2395static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end)
2396{
2397	u16 index, next;
2398	u16 fcnt = 0;
2399
2400again:
2401	if (start >= end)
2402		return fcnt;
2403
2404	index = find_next_zero_bit(map, end, start);
2405	if (index >= end)
2406		return fcnt;
2407
2408	next = find_next_bit(map, end, index);
2409	if (next <= end) {
2410		fcnt += next - index;
2411		start = next + 1;
2412		goto again;
2413	}
2414
2415	fcnt += end - index;
2416	return fcnt;
2417}
2418
2419static void
2420npc_get_mcam_search_range_priority(struct npc_mcam *mcam,
2421				   struct npc_mcam_alloc_entry_req *req,
2422				   u16 *start, u16 *end, bool *reverse)
2423{
2424	u16 fcnt;
2425
2426	if (req->priority == NPC_MCAM_HIGHER_PRIO)
2427		goto hprio;
2428
2429	/* For a low priority entry allocation
2430	 * - If reference entry is not in hprio zone then
2431	 *      search range: ref_entry to end.
2432	 * - If reference entry is in hprio zone and if
2433	 *   request can be accomodated in non-hprio zone then
2434	 *      search range: 'start of middle zone' to 'end'
2435	 * - else search in reverse, so that less number of hprio
2436	 *   zone entries are allocated.
2437	 */
2438
2439	*reverse = false;
2440	*start = req->ref_entry + 1;
2441	*end = mcam->bmap_entries;
2442
2443	if (req->ref_entry >= mcam->hprio_end)
2444		return;
2445
2446	fcnt = npc_mcam_get_free_count(mcam->bmap,
2447				       mcam->hprio_end, mcam->bmap_entries);
2448	if (fcnt > req->count)
2449		*start = mcam->hprio_end;
2450	else
2451		*reverse = true;
2452	return;
2453
2454hprio:
2455	/* For a high priority entry allocation, search is always
2456	 * in reverse to preserve hprio zone entries.
2457	 * - If reference entry is not in lprio zone then
2458	 *      search range: 0 to ref_entry.
2459	 * - If reference entry is in lprio zone and if
2460	 *   request can be accomodated in middle zone then
2461	 *      search range: 'hprio_end' to 'lprio_start'
2462	 */
2463
2464	*reverse = true;
2465	*start = 0;
2466	*end = req->ref_entry;
2467
2468	if (req->ref_entry <= mcam->lprio_start)
2469		return;
2470
2471	fcnt = npc_mcam_get_free_count(mcam->bmap,
2472				       mcam->hprio_end, mcam->lprio_start);
2473	if (fcnt < req->count)
2474		return;
2475	*start = mcam->hprio_end;
2476	*end = mcam->lprio_start;
2477}
2478
2479static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc,
2480				  struct npc_mcam_alloc_entry_req *req,
2481				  struct npc_mcam_alloc_entry_rsp *rsp)
2482{
2483	u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
2484	u16 fcnt, hp_fcnt, lp_fcnt;
2485	u16 start, end, index;
2486	int entry, next_start;
2487	bool reverse = false;
2488	unsigned long *bmap;
2489	u16 max_contig;
2490
2491	mutex_lock(&mcam->lock);
2492
2493	/* Check if there are any free entries */
2494	if (!mcam->bmap_fcnt) {
2495		mutex_unlock(&mcam->lock);
2496		return NPC_MCAM_ALLOC_FAILED;
2497	}
2498
2499	/* MCAM entries are divided into high priority, middle and
2500	 * low priority zones. Idea is to not allocate top and lower
2501	 * most entries as much as possible, this is to increase
2502	 * probability of honouring priority allocation requests.
2503	 *
2504	 * Two bitmaps are used for mcam entry management,
2505	 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'.
2506	 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'.
2507	 *
2508	 * Reverse bitmap is used to allocate entries
2509	 * - when a higher priority entry is requested
2510	 * - when available free entries are less.
2511	 * Lower priority ones out of avaialble free entries are always
2512	 * chosen when 'high vs low' question arises.
2513	 *
2514	 * For a VF base MCAM match rule is set by its PF. And all the
2515	 * further MCAM rules installed by VF on its own are
2516	 * concatenated with the base rule set by its PF. Hence PF entries
2517	 * should be at lower priority compared to VF entries. Otherwise
2518	 * base rule is hit always and rules installed by VF will be of
2519	 * no use. Hence if the request is from PF then allocate low
2520	 * priority entries.
2521	 */
2522	if (!(pcifunc & RVU_PFVF_FUNC_MASK))
2523		goto lprio_alloc;
2524
2525	/* Get the search range for priority allocation request */
2526	if (req->priority) {
2527		npc_get_mcam_search_range_priority(mcam, req,
2528						   &start, &end, &reverse);
2529		goto alloc;
2530	}
2531
2532	/* Find out the search range for non-priority allocation request
2533	 *
2534	 * Get MCAM free entry count in middle zone.
2535	 */
2536	lp_fcnt = npc_mcam_get_free_count(mcam->bmap,
2537					  mcam->lprio_start,
2538					  mcam->bmap_entries);
2539	hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end);
2540	fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt;
2541
2542	/* Check if request can be accomodated in the middle zone */
2543	if (fcnt > req->count) {
2544		start = mcam->hprio_end;
2545		end = mcam->lprio_start;
2546	} else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) {
2547		/* Expand search zone from half of hprio zone to
2548		 * half of lprio zone.
2549		 */
2550		start = mcam->hprio_end / 2;
2551		end = mcam->bmap_entries - (mcam->lprio_count / 2);
2552		reverse = true;
2553	} else {
2554		/* Not enough free entries, search all entries in reverse,
2555		 * so that low priority ones will get used up.
2556		 */
2557lprio_alloc:
2558		reverse = true;
2559		start = 0;
2560		end = mcam->bmap_entries;
2561		/* Ensure PF requests are always at bottom and if PF requests
2562		 * for higher/lower priority entry wrt reference entry then
2563		 * honour that criteria and start search for entries from bottom
2564		 * and not in mid zone.
2565		 */
2566		if (!(pcifunc & RVU_PFVF_FUNC_MASK) &&
2567		    req->priority == NPC_MCAM_HIGHER_PRIO)
2568			end = req->ref_entry;
2569
2570		if (!(pcifunc & RVU_PFVF_FUNC_MASK) &&
2571		    req->priority == NPC_MCAM_LOWER_PRIO)
2572			start = req->ref_entry;
2573	}
2574
2575alloc:
2576	if (reverse) {
2577		bmap = mcam->bmap_reverse;
2578		start = mcam->bmap_entries - start;
2579		end = mcam->bmap_entries - end;
2580		swap(start, end);
2581	} else {
2582		bmap = mcam->bmap;
2583	}
2584
2585	if (req->contig) {
2586		/* Allocate requested number of contiguous entries, if
2587		 * unsuccessful find max contiguous entries available.
2588		 */
2589		index = npc_mcam_find_zero_area(bmap, end, start,
2590						req->count, &max_contig);
2591		rsp->count = max_contig;
2592		if (reverse)
2593			rsp->entry = mcam->bmap_entries - index - max_contig;
2594		else
2595			rsp->entry = index;
2596	} else {
2597		/* Allocate requested number of non-contiguous entries,
2598		 * if unsuccessful allocate as many as possible.
2599		 */
2600		rsp->count = 0;
2601		next_start = start;
2602		for (entry = 0; entry < req->count; entry++) {
2603			index = find_next_zero_bit(bmap, end, next_start);
2604			if (index >= end)
2605				break;
2606
2607			next_start = start + (index - start) + 1;
2608
2609			/* Save the entry's index */
2610			if (reverse)
2611				index = mcam->bmap_entries - index - 1;
2612			entry_list[entry] = index;
2613			rsp->count++;
2614		}
2615	}
2616
2617	/* If allocating requested no of entries is unsucessful,
2618	 * expand the search range to full bitmap length and retry.
2619	 */
2620	if (!req->priority && (rsp->count < req->count) &&
2621	    ((end - start) != mcam->bmap_entries)) {
2622		reverse = true;
2623		start = 0;
2624		end = mcam->bmap_entries;
2625		goto alloc;
2626	}
2627
2628	/* For priority entry allocation requests, if allocation is
2629	 * failed then expand search to max possible range and retry.
2630	 */
2631	if (req->priority && rsp->count < req->count) {
2632		if (req->priority == NPC_MCAM_LOWER_PRIO &&
2633		    (start != (req->ref_entry + 1))) {
2634			start = req->ref_entry + 1;
2635			end = mcam->bmap_entries;
2636			reverse = false;
2637			goto alloc;
2638		} else if ((req->priority == NPC_MCAM_HIGHER_PRIO) &&
2639			   ((end - start) != req->ref_entry)) {
2640			start = 0;
2641			end = req->ref_entry;
2642			reverse = true;
2643			goto alloc;
2644		}
2645	}
2646
2647	/* Copy MCAM entry indices into mbox response entry_list.
2648	 * Requester always expects indices in ascending order, so
2649	 * reverse the list if reverse bitmap is used for allocation.
2650	 */
2651	if (!req->contig && rsp->count) {
2652		index = 0;
2653		for (entry = rsp->count - 1; entry >= 0; entry--) {
2654			if (reverse)
2655				rsp->entry_list[index++] = entry_list[entry];
2656			else
2657				rsp->entry_list[entry] = entry_list[entry];
2658		}
2659	}
2660
2661	/* Mark the allocated entries as used and set nixlf mapping */
2662	for (entry = 0; entry < rsp->count; entry++) {
2663		index = req->contig ?
2664			(rsp->entry + entry) : rsp->entry_list[entry];
2665		npc_mcam_set_bit(mcam, index);
2666		mcam->entry2pfvf_map[index] = pcifunc;
2667		mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
2668	}
2669
2670	/* Update available free count in mbox response */
2671	rsp->free_count = mcam->bmap_fcnt;
2672
2673	mutex_unlock(&mcam->lock);
2674	return 0;
2675}
2676
2677/* Marks bitmaps to reserved the mcam slot */
2678void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx)
2679{
2680	struct npc_mcam *mcam = &rvu->hw->mcam;
2681
2682	npc_mcam_set_bit(mcam, entry_idx);
2683}
2684
2685int npc_config_cntr_default_entries(struct rvu *rvu, bool enable)
2686{
2687	struct npc_mcam *mcam = &rvu->hw->mcam;
2688	struct npc_install_flow_rsp rsp;
2689	struct rvu_npc_mcam_rule *rule;
2690	int blkaddr;
2691
2692	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2693	if (blkaddr < 0)
2694		return -EINVAL;
2695
2696	mutex_lock(&mcam->lock);
2697	list_for_each_entry(rule, &mcam->mcam_rules, list) {
2698		if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, rule->entry))
2699			continue;
2700		if (!rule->default_rule)
2701			continue;
2702		if (enable && !rule->has_cntr) { /* Alloc and map new counter */
2703			__rvu_mcam_add_counter_to_rule(rvu, rule->owner,
2704						       rule, &rsp);
2705			if (rsp.counter < 0) {
2706				dev_err(rvu->dev,
2707					"%s: Failed to allocate cntr for default rule (err=%d)\n",
2708					__func__, rsp.counter);
2709				break;
2710			}
2711			npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2712						    rule->entry, rsp.counter);
2713			/* Reset counter before use */
2714			rvu_write64(rvu, blkaddr,
2715				    NPC_AF_MATCH_STATX(rule->cntr), 0x0);
2716		}
2717
2718		/* Free and unmap counter */
2719		if (!enable && rule->has_cntr)
2720			__rvu_mcam_remove_counter_from_rule(rvu, rule->owner,
2721							    rule);
2722	}
2723	mutex_unlock(&mcam->lock);
2724
2725	return 0;
2726}
2727
2728int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
2729					  struct npc_mcam_alloc_entry_req *req,
2730					  struct npc_mcam_alloc_entry_rsp *rsp)
2731{
2732	struct npc_mcam *mcam = &rvu->hw->mcam;
2733	u16 pcifunc = req->hdr.pcifunc;
2734	int blkaddr;
2735
2736	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2737	if (blkaddr < 0)
2738		return NPC_MCAM_INVALID_REQ;
2739
2740	rsp->entry = NPC_MCAM_ENTRY_INVALID;
2741	rsp->free_count = 0;
2742
2743	/* Check if ref_entry is greater that the range
2744	 * then set it to max value.
2745	 */
2746	if (req->ref_entry > mcam->bmap_entries)
2747		req->ref_entry = mcam->bmap_entries;
2748
2749	/* ref_entry can't be '0' if requested priority is high.
2750	 * Can't be last entry if requested priority is low.
2751	 */
2752	if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) ||
2753	    ((req->ref_entry == mcam->bmap_entries) &&
2754	     req->priority == NPC_MCAM_LOWER_PRIO))
2755		return NPC_MCAM_INVALID_REQ;
2756
2757	/* Since list of allocated indices needs to be sent to requester,
2758	 * max number of non-contiguous entries per mbox msg is limited.
2759	 */
2760	if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) {
2761		dev_err(rvu->dev,
2762			"%s: %d Non-contiguous MCAM entries requested is more than max (%d) allowed\n",
2763			__func__, req->count, NPC_MAX_NONCONTIG_ENTRIES);
2764		return NPC_MCAM_INVALID_REQ;
2765	}
2766
2767	/* Alloc request from PFFUNC with no NIXLF attached should be denied */
2768	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2769		return NPC_MCAM_ALLOC_DENIED;
2770
2771	return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
2772}
2773
2774int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
2775					 struct npc_mcam_free_entry_req *req,
2776					 struct msg_rsp *rsp)
2777{
2778	struct npc_mcam *mcam = &rvu->hw->mcam;
2779	u16 pcifunc = req->hdr.pcifunc;
2780	int blkaddr, rc = 0;
2781	u16 cntr;
2782
2783	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2784	if (blkaddr < 0)
2785		return NPC_MCAM_INVALID_REQ;
2786
2787	/* Free request from PFFUNC with no NIXLF attached, ignore */
2788	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2789		return NPC_MCAM_INVALID_REQ;
2790
2791	mutex_lock(&mcam->lock);
2792
2793	if (req->all)
2794		goto free_all;
2795
2796	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2797	if (rc)
2798		goto exit;
2799
2800	mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP;
2801	mcam->entry2target_pffunc[req->entry] = 0x0;
2802	npc_mcam_clear_bit(mcam, req->entry);
2803	npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2804
2805	/* Update entry2counter mapping */
2806	cntr = mcam->entry2cntr_map[req->entry];
2807	if (cntr != NPC_MCAM_INVALID_MAP)
2808		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2809					      req->entry, cntr);
2810
2811	goto exit;
2812
2813free_all:
2814	/* Free up all entries allocated to requesting PFFUNC */
2815	npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
2816exit:
2817	mutex_unlock(&mcam->lock);
2818	return rc;
2819}
2820
2821int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu,
2822					 struct npc_mcam_read_entry_req *req,
2823					 struct npc_mcam_read_entry_rsp *rsp)
2824{
2825	struct npc_mcam *mcam = &rvu->hw->mcam;
2826	u16 pcifunc = req->hdr.pcifunc;
2827	int blkaddr, rc;
2828
2829	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2830	if (blkaddr < 0)
2831		return NPC_MCAM_INVALID_REQ;
2832
2833	mutex_lock(&mcam->lock);
2834	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2835	if (!rc) {
2836		npc_read_mcam_entry(rvu, mcam, blkaddr, req->entry,
2837				    &rsp->entry_data,
2838				    &rsp->intf, &rsp->enable);
2839	}
2840
2841	mutex_unlock(&mcam->lock);
2842	return rc;
2843}
2844
2845int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
2846					  struct npc_mcam_write_entry_req *req,
2847					  struct msg_rsp *rsp)
2848{
2849	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
2850	struct npc_mcam *mcam = &rvu->hw->mcam;
2851	u16 pcifunc = req->hdr.pcifunc;
2852	int blkaddr, rc;
2853	u8 nix_intf;
2854
2855	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2856	if (blkaddr < 0)
2857		return NPC_MCAM_INVALID_REQ;
2858
2859	mutex_lock(&mcam->lock);
2860	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2861	if (rc)
2862		goto exit;
2863
2864	if (req->set_cntr &&
2865	    npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) {
2866		rc = NPC_MCAM_INVALID_REQ;
2867		goto exit;
2868	}
2869
2870	if (!is_npc_interface_valid(rvu, req->intf)) {
2871		rc = NPC_MCAM_INVALID_REQ;
2872		goto exit;
2873	}
2874
2875	if (is_npc_intf_tx(req->intf))
2876		nix_intf = pfvf->nix_tx_intf;
2877	else
2878		nix_intf = pfvf->nix_rx_intf;
2879
2880	/* For AF installed rules, the nix_intf should be set to target NIX */
2881	if (is_pffunc_af(req->hdr.pcifunc))
2882		nix_intf = req->intf;
2883
2884	npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf,
2885			      &req->entry_data, req->enable_entry);
2886
2887	if (req->set_cntr)
2888		npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2889					    req->entry, req->cntr);
2890
2891	rc = 0;
2892exit:
2893	mutex_unlock(&mcam->lock);
2894	return rc;
2895}
2896
2897int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
2898					struct npc_mcam_ena_dis_entry_req *req,
2899					struct msg_rsp *rsp)
2900{
2901	struct npc_mcam *mcam = &rvu->hw->mcam;
2902	u16 pcifunc = req->hdr.pcifunc;
2903	int blkaddr, rc;
2904
2905	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2906	if (blkaddr < 0)
2907		return NPC_MCAM_INVALID_REQ;
2908
2909	mutex_lock(&mcam->lock);
2910	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2911	mutex_unlock(&mcam->lock);
2912	if (rc)
2913		return rc;
2914
2915	npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true);
2916
2917	return 0;
2918}
2919
2920int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
2921					struct npc_mcam_ena_dis_entry_req *req,
2922					struct msg_rsp *rsp)
2923{
2924	struct npc_mcam *mcam = &rvu->hw->mcam;
2925	u16 pcifunc = req->hdr.pcifunc;
2926	int blkaddr, rc;
2927
2928	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2929	if (blkaddr < 0)
2930		return NPC_MCAM_INVALID_REQ;
2931
2932	mutex_lock(&mcam->lock);
2933	rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2934	mutex_unlock(&mcam->lock);
2935	if (rc)
2936		return rc;
2937
2938	npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2939
2940	return 0;
2941}
2942
2943int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
2944					  struct npc_mcam_shift_entry_req *req,
2945					  struct npc_mcam_shift_entry_rsp *rsp)
2946{
2947	struct npc_mcam *mcam = &rvu->hw->mcam;
2948	u16 pcifunc = req->hdr.pcifunc;
2949	u16 old_entry, new_entry;
2950	int blkaddr, rc = 0;
2951	u16 index, cntr;
2952
2953	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2954	if (blkaddr < 0)
2955		return NPC_MCAM_INVALID_REQ;
2956
2957	if (req->shift_count > NPC_MCAM_MAX_SHIFTS)
2958		return NPC_MCAM_INVALID_REQ;
2959
2960	mutex_lock(&mcam->lock);
2961	for (index = 0; index < req->shift_count; index++) {
2962		old_entry = req->curr_entry[index];
2963		new_entry = req->new_entry[index];
2964
2965		/* Check if both old and new entries are valid and
2966		 * does belong to this PFFUNC or not.
2967		 */
2968		rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry);
2969		if (rc)
2970			break;
2971
2972		rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry);
2973		if (rc)
2974			break;
2975
2976		/* new_entry should not have a counter mapped */
2977		if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) {
2978			rc = NPC_MCAM_PERM_DENIED;
2979			break;
2980		}
2981
2982		/* Disable the new_entry */
2983		npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false);
2984
2985		/* Copy rule from old entry to new entry */
2986		npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry);
2987
2988		/* Copy counter mapping, if any */
2989		cntr = mcam->entry2cntr_map[old_entry];
2990		if (cntr != NPC_MCAM_INVALID_MAP) {
2991			npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2992						      old_entry, cntr);
2993			npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2994						    new_entry, cntr);
2995		}
2996
2997		/* Enable new_entry and disable old_entry */
2998		npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true);
2999		npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false);
3000	}
3001
3002	/* If shift has failed then report the failed index */
3003	if (index != req->shift_count) {
3004		rc = NPC_MCAM_PERM_DENIED;
3005		rsp->failed_entry_idx = index;
3006	}
3007
3008	mutex_unlock(&mcam->lock);
3009	return rc;
3010}
3011
3012static int __npc_mcam_alloc_counter(struct rvu *rvu,
3013				    struct npc_mcam_alloc_counter_req *req,
3014				    struct npc_mcam_alloc_counter_rsp *rsp)
3015{
3016	struct npc_mcam *mcam = &rvu->hw->mcam;
3017	u16 pcifunc = req->hdr.pcifunc;
3018	u16 max_contig, cntr;
3019	int blkaddr, index;
3020
3021	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3022	if (blkaddr < 0)
3023		return NPC_MCAM_INVALID_REQ;
3024
3025	/* If the request is from a PFFUNC with no NIXLF attached, ignore */
3026	if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
3027		return NPC_MCAM_INVALID_REQ;
3028
3029	/* Since list of allocated counter IDs needs to be sent to requester,
3030	 * max number of non-contiguous counters per mbox msg is limited.
3031	 */
3032	if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS)
3033		return NPC_MCAM_INVALID_REQ;
3034
3035
3036	/* Check if unused counters are available or not */
3037	if (!rvu_rsrc_free_count(&mcam->counters)) {
3038		return NPC_MCAM_ALLOC_FAILED;
3039	}
3040
3041	rsp->count = 0;
3042
3043	if (req->contig) {
3044		/* Allocate requested number of contiguous counters, if
3045		 * unsuccessful find max contiguous entries available.
3046		 */
3047		index = npc_mcam_find_zero_area(mcam->counters.bmap,
3048						mcam->counters.max, 0,
3049						req->count, &max_contig);
3050		rsp->count = max_contig;
3051		rsp->cntr = index;
3052		for (cntr = index; cntr < (index + max_contig); cntr++) {
3053			__set_bit(cntr, mcam->counters.bmap);
3054			mcam->cntr2pfvf_map[cntr] = pcifunc;
3055		}
3056	} else {
3057		/* Allocate requested number of non-contiguous counters,
3058		 * if unsuccessful allocate as many as possible.
3059		 */
3060		for (cntr = 0; cntr < req->count; cntr++) {
3061			index = rvu_alloc_rsrc(&mcam->counters);
3062			if (index < 0)
3063				break;
3064			rsp->cntr_list[cntr] = index;
3065			rsp->count++;
3066			mcam->cntr2pfvf_map[index] = pcifunc;
3067		}
3068	}
3069
3070	return 0;
3071}
3072
3073int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
3074			struct npc_mcam_alloc_counter_req *req,
3075			struct npc_mcam_alloc_counter_rsp *rsp)
3076{
3077	struct npc_mcam *mcam = &rvu->hw->mcam;
3078	int err;
3079
3080	mutex_lock(&mcam->lock);
3081
3082	err = __npc_mcam_alloc_counter(rvu, req, rsp);
3083
3084	mutex_unlock(&mcam->lock);
3085	return err;
3086}
3087
3088static int __npc_mcam_free_counter(struct rvu *rvu,
3089				   struct npc_mcam_oper_counter_req *req,
3090				   struct msg_rsp *rsp)
3091{
3092	struct npc_mcam *mcam = &rvu->hw->mcam;
3093	u16 index, entry = 0;
3094	int blkaddr, err;
3095
3096	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3097	if (blkaddr < 0)
3098		return NPC_MCAM_INVALID_REQ;
3099
3100	err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3101	if (err) {
3102		return err;
3103	}
3104
3105	/* Mark counter as free/unused */
3106	mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP;
3107	rvu_free_rsrc(&mcam->counters, req->cntr);
3108
3109	/* Disable all MCAM entry's stats which are using this counter */
3110	while (entry < mcam->bmap_entries) {
3111		if (!mcam->cntr_refcnt[req->cntr])
3112			break;
3113
3114		index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
3115		if (index >= mcam->bmap_entries)
3116			break;
3117		entry = index + 1;
3118		if (mcam->entry2cntr_map[index] != req->cntr)
3119			continue;
3120
3121		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
3122					      index, req->cntr);
3123	}
3124
3125	return 0;
3126}
3127
3128int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
3129		struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
3130{
3131	struct npc_mcam *mcam = &rvu->hw->mcam;
3132	int err;
3133
3134	mutex_lock(&mcam->lock);
3135
3136	err = __npc_mcam_free_counter(rvu, req, rsp);
3137
3138	mutex_unlock(&mcam->lock);
3139
3140	return err;
3141}
3142
3143void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc,
3144					 struct rvu_npc_mcam_rule *rule)
3145{
3146	struct npc_mcam_oper_counter_req free_req = { 0 };
3147	struct msg_rsp free_rsp;
3148
3149	if (!rule->has_cntr)
3150		return;
3151
3152	free_req.hdr.pcifunc = pcifunc;
3153	free_req.cntr = rule->cntr;
3154
3155	__npc_mcam_free_counter(rvu, &free_req, &free_rsp);
3156	rule->has_cntr = false;
3157}
3158
3159void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc,
3160				    struct rvu_npc_mcam_rule *rule,
3161				    struct npc_install_flow_rsp *rsp)
3162{
3163	struct npc_mcam_alloc_counter_req cntr_req = { 0 };
3164	struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 };
3165	int err;
3166
3167	cntr_req.hdr.pcifunc = pcifunc;
3168	cntr_req.contig = true;
3169	cntr_req.count = 1;
3170
3171	/* we try to allocate a counter to track the stats of this
3172	 * rule. If counter could not be allocated then proceed
3173	 * without counter because counters are limited than entries.
3174	 */
3175	err = __npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
3176	if (!err && cntr_rsp.count) {
3177		rule->cntr = cntr_rsp.cntr;
3178		rule->has_cntr = true;
3179		rsp->counter = rule->cntr;
3180	} else {
3181		rsp->counter = err;
3182	}
3183}
3184
3185int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
3186		struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp)
3187{
3188	struct npc_mcam *mcam = &rvu->hw->mcam;
3189	u16 index, entry = 0;
3190	int blkaddr, rc;
3191
3192	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3193	if (blkaddr < 0)
3194		return NPC_MCAM_INVALID_REQ;
3195
3196	mutex_lock(&mcam->lock);
3197	rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3198	if (rc)
3199		goto exit;
3200
3201	/* Unmap the MCAM entry and counter */
3202	if (!req->all) {
3203		rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry);
3204		if (rc)
3205			goto exit;
3206		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
3207					      req->entry, req->cntr);
3208		goto exit;
3209	}
3210
3211	/* Disable all MCAM entry's stats which are using this counter */
3212	while (entry < mcam->bmap_entries) {
3213		if (!mcam->cntr_refcnt[req->cntr])
3214			break;
3215
3216		index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
3217		if (index >= mcam->bmap_entries)
3218			break;
3219		entry = index + 1;
3220
3221		if (mcam->entry2cntr_map[index] != req->cntr)
3222			continue;
3223
3224		npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
3225					      index, req->cntr);
3226	}
3227exit:
3228	mutex_unlock(&mcam->lock);
3229	return rc;
3230}
3231
3232int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
3233		struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
3234{
3235	struct npc_mcam *mcam = &rvu->hw->mcam;
3236	int blkaddr, err;
3237
3238	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3239	if (blkaddr < 0)
3240		return NPC_MCAM_INVALID_REQ;
3241
3242	mutex_lock(&mcam->lock);
3243	err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3244	mutex_unlock(&mcam->lock);
3245	if (err)
3246		return err;
3247
3248	rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00);
3249
3250	return 0;
3251}
3252
3253int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
3254			struct npc_mcam_oper_counter_req *req,
3255			struct npc_mcam_oper_counter_rsp *rsp)
3256{
3257	struct npc_mcam *mcam = &rvu->hw->mcam;
3258	int blkaddr, err;
3259
3260	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3261	if (blkaddr < 0)
3262		return NPC_MCAM_INVALID_REQ;
3263
3264	mutex_lock(&mcam->lock);
3265	err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3266	mutex_unlock(&mcam->lock);
3267	if (err)
3268		return err;
3269
3270	rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr));
3271	rsp->stat &= BIT_ULL(48) - 1;
3272
3273	return 0;
3274}
3275
3276int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
3277			  struct npc_mcam_alloc_and_write_entry_req *req,
3278			  struct npc_mcam_alloc_and_write_entry_rsp *rsp)
3279{
3280	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
3281	struct npc_mcam_alloc_counter_req cntr_req;
3282	struct npc_mcam_alloc_counter_rsp cntr_rsp;
3283	struct npc_mcam_alloc_entry_req entry_req;
3284	struct npc_mcam_alloc_entry_rsp entry_rsp;
3285	struct npc_mcam *mcam = &rvu->hw->mcam;
3286	u16 entry = NPC_MCAM_ENTRY_INVALID;
3287	u16 cntr = NPC_MCAM_ENTRY_INVALID;
3288	int blkaddr, rc;
3289	u8 nix_intf;
3290
3291	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3292	if (blkaddr < 0)
3293		return NPC_MCAM_INVALID_REQ;
3294
3295	if (!is_npc_interface_valid(rvu, req->intf))
3296		return NPC_MCAM_INVALID_REQ;
3297
3298	/* Try to allocate a MCAM entry */
3299	entry_req.hdr.pcifunc = req->hdr.pcifunc;
3300	entry_req.contig = true;
3301	entry_req.priority = req->priority;
3302	entry_req.ref_entry = req->ref_entry;
3303	entry_req.count = 1;
3304
3305	rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu,
3306						   &entry_req, &entry_rsp);
3307	if (rc)
3308		return rc;
3309
3310	if (!entry_rsp.count)
3311		return NPC_MCAM_ALLOC_FAILED;
3312
3313	entry = entry_rsp.entry;
3314
3315	if (!req->alloc_cntr)
3316		goto write_entry;
3317
3318	/* Now allocate counter */
3319	cntr_req.hdr.pcifunc = req->hdr.pcifunc;
3320	cntr_req.contig = true;
3321	cntr_req.count = 1;
3322
3323	rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
3324	if (rc) {
3325		/* Free allocated MCAM entry */
3326		mutex_lock(&mcam->lock);
3327		mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP;
3328		npc_mcam_clear_bit(mcam, entry);
3329		mutex_unlock(&mcam->lock);
3330		return rc;
3331	}
3332
3333	cntr = cntr_rsp.cntr;
3334
3335write_entry:
3336	mutex_lock(&mcam->lock);
3337
3338	if (is_npc_intf_tx(req->intf))
3339		nix_intf = pfvf->nix_tx_intf;
3340	else
3341		nix_intf = pfvf->nix_rx_intf;
3342
3343	npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf,
3344			      &req->entry_data, req->enable_entry);
3345
3346	if (req->alloc_cntr)
3347		npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr);
3348	mutex_unlock(&mcam->lock);
3349
3350	rsp->entry = entry;
3351	rsp->cntr = cntr;
3352
3353	return 0;
3354}
3355
3356#define GET_KEX_CFG(intf) \
3357	rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
3358
3359#define GET_KEX_FLAGS(ld) \
3360	rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld))
3361
3362#define GET_KEX_LD(intf, lid, lt, ld)	\
3363	rvu_read64(rvu, BLKADDR_NPC,	\
3364		NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld))
3365
3366#define GET_KEX_LDFLAGS(intf, ld, fl)	\
3367	rvu_read64(rvu, BLKADDR_NPC,	\
3368		NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl))
3369
3370int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
3371				     struct npc_get_kex_cfg_rsp *rsp)
3372{
3373	int lid, lt, ld, fl;
3374
3375	rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX);
3376	rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX);
3377	for (lid = 0; lid < NPC_MAX_LID; lid++) {
3378		for (lt = 0; lt < NPC_MAX_LT; lt++) {
3379			for (ld = 0; ld < NPC_MAX_LD; ld++) {
3380				rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] =
3381					GET_KEX_LD(NIX_INTF_RX, lid, lt, ld);
3382				rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] =
3383					GET_KEX_LD(NIX_INTF_TX, lid, lt, ld);
3384			}
3385		}
3386	}
3387	for (ld = 0; ld < NPC_MAX_LD; ld++)
3388		rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld);
3389
3390	for (ld = 0; ld < NPC_MAX_LD; ld++) {
3391		for (fl = 0; fl < NPC_MAX_LFL; fl++) {
3392			rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] =
3393					GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl);
3394			rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] =
3395					GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl);
3396		}
3397	}
3398	memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN);
3399	return 0;
3400}
3401
3402static int
3403npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind,
3404			     u8 var_len_off, u8 var_len_off_mask, u8 shift_dir)
3405{
3406	struct npc_kpu_action0 *act0;
3407	u8 shift_count = 0;
3408	int blkaddr;
3409	u64 val;
3410
3411	if (!var_len_off_mask)
3412		return -EINVAL;
3413
3414	if (var_len_off_mask != 0xff) {
3415		if (shift_dir)
3416			shift_count = __ffs(var_len_off_mask);
3417		else
3418			shift_count = (8 - __fls(var_len_off_mask));
3419	}
3420	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
3421	if (blkaddr < 0) {
3422		dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
3423		return -EINVAL;
3424	}
3425	val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
3426	act0 = (struct npc_kpu_action0 *)&val;
3427	act0->var_len_shift = shift_count;
3428	act0->var_len_right = shift_dir;
3429	act0->var_len_mask = var_len_off_mask;
3430	act0->var_len_offset = var_len_off;
3431	rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
3432	return 0;
3433}
3434
3435int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
3436			   u64 pkind, u8 var_len_off, u8 var_len_off_mask,
3437			   u8 shift_dir)
3438
3439{
3440	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
3441	int blkaddr, nixlf, rc, intf_mode;
3442	int pf = rvu_get_pf(rvu->pdev, pcifunc);
3443	u64 rxpkind, txpkind;
3444	u8 cgx_id, lmac_id;
3445
3446	/* use default pkind to disable edsa/higig */
3447	rxpkind = rvu_npc_get_pkind(rvu, pf);
3448	txpkind = NPC_TX_DEF_PKIND;
3449	intf_mode = NPC_INTF_MODE_DEF;
3450
3451	if (mode & OTX2_PRIV_FLAGS_CUSTOM) {
3452		if (pkind == NPC_RX_CUSTOM_PRE_L2_PKIND) {
3453			rc = npc_set_var_len_offset_pkind(rvu, pcifunc, pkind,
3454							  var_len_off,
3455							  var_len_off_mask,
3456							  shift_dir);
3457			if (rc)
3458				return rc;
3459		}
3460		rxpkind = pkind;
3461		txpkind = pkind;
3462	}
3463
3464	if (dir & PKIND_RX) {
3465		/* rx pkind set req valid only for cgx mapped PFs */
3466		if (!is_cgx_config_permitted(rvu, pcifunc))
3467			return 0;
3468		rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
3469
3470		rc = cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
3471				   rxpkind);
3472		if (rc)
3473			return rc;
3474	}
3475
3476	if (dir & PKIND_TX) {
3477		/* Tx pkind set request valid if PCIFUNC has NIXLF attached */
3478		rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
3479		if (rc)
3480			return rc;
3481
3482		rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf),
3483			    txpkind);
3484	}
3485
3486	pfvf->intf_mode = intf_mode;
3487	return 0;
3488}
3489
3490int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req,
3491				   struct msg_rsp *rsp)
3492{
3493	return rvu_npc_set_parse_mode(rvu, req->hdr.pcifunc, req->mode,
3494				      req->dir, req->pkind, req->var_len_off,
3495				      req->var_len_off_mask, req->shift_dir);
3496}
3497
3498int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu,
3499					      struct msg_req *req,
3500					      struct npc_mcam_read_base_rule_rsp *rsp)
3501{
3502	struct npc_mcam *mcam = &rvu->hw->mcam;
3503	int index, blkaddr, nixlf, rc = 0;
3504	u16 pcifunc = req->hdr.pcifunc;
3505	struct rvu_pfvf *pfvf;
3506	u8 intf, enable;
3507
3508	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3509	if (blkaddr < 0)
3510		return NPC_MCAM_INVALID_REQ;
3511
3512	/* Return the channel number in case of PF */
3513	if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
3514		pfvf = rvu_get_pfvf(rvu, pcifunc);
3515		rsp->entry.kw[0] = pfvf->rx_chan_base;
3516		rsp->entry.kw_mask[0] = 0xFFFULL;
3517		goto out;
3518	}
3519
3520	/* Find the pkt steering rule installed by PF to this VF */
3521	mutex_lock(&mcam->lock);
3522	for (index = 0; index < mcam->bmap_entries; index++) {
3523		if (mcam->entry2target_pffunc[index] == pcifunc)
3524			goto read_entry;
3525	}
3526
3527	rc = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
3528	if (rc < 0) {
3529		mutex_unlock(&mcam->lock);
3530		goto out;
3531	}
3532	/* Read the default ucast entry if there is no pkt steering rule */
3533	index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
3534					 NIXLF_UCAST_ENTRY);
3535read_entry:
3536	/* Read the mcam entry */
3537	npc_read_mcam_entry(rvu, mcam, blkaddr, index, &rsp->entry, &intf,
3538			    &enable);
3539	mutex_unlock(&mcam->lock);
3540out:
3541	return rc;
3542}
3543
3544int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu,
3545					  struct npc_mcam_get_stats_req *req,
3546					  struct npc_mcam_get_stats_rsp *rsp)
3547{
3548	struct npc_mcam *mcam = &rvu->hw->mcam;
3549	u16 index, cntr;
3550	int blkaddr;
3551	u64 regval;
3552	u32 bank;
3553
3554	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3555	if (blkaddr < 0)
3556		return NPC_MCAM_INVALID_REQ;
3557
3558	mutex_lock(&mcam->lock);
3559
3560	index = req->entry & (mcam->banksize - 1);
3561	bank = npc_get_bank(mcam, req->entry);
3562
3563	/* read MCAM entry STAT_ACT register */
3564	regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank));
3565
3566	if (!(regval & rvu->hw->npc_stat_ena)) {
3567		rsp->stat_ena = 0;
3568		mutex_unlock(&mcam->lock);
3569		return 0;
3570	}
3571
3572	cntr = regval & 0x1FF;
3573
3574	rsp->stat_ena = 1;
3575	rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr));
3576	rsp->stat &= BIT_ULL(48) - 1;
3577
3578	mutex_unlock(&mcam->lock);
3579
3580	return 0;
3581}
3582
3583void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf)
3584{
3585	struct npc_mcam *mcam = &rvu->hw->mcam;
3586	struct rvu_npc_mcam_rule *rule;
3587	int ucast_idx, blkaddr;
3588
3589	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3590	if (blkaddr < 0)
3591		return;
3592
3593	ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
3594					     nixlf, NIXLF_UCAST_ENTRY);
3595
3596	npc_enable_mcam_entry(rvu, mcam, blkaddr, ucast_idx, false);
3597
3598	npc_set_mcam_action(rvu, mcam, blkaddr, ucast_idx, 0);
3599
3600	npc_clear_mcam_entry(rvu, mcam, blkaddr, ucast_idx);
3601
3602	mutex_lock(&mcam->lock);
3603	list_for_each_entry(rule, &mcam->mcam_rules, list) {
3604		if (rule->entry == ucast_idx) {
3605			list_del(&rule->list);
3606			kfree(rule);
3607			break;
3608		}
3609	}
3610	mutex_unlock(&mcam->lock);
3611}