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rvu.h
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linux-6.19.14/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef RVU_H 9#define RVU_H 10 11#include <linux/pci.h> 12#include <net/devlink.h> 13#include <linux/soc/marvell/silicons.h> 14 15#include "rvu_struct.h" 16#include "rvu_devlink.h" 17#include "common.h" 18#include "mbox.h" 19#include "npc.h" 20#include "rvu_reg.h" 21#include "ptp.h" 22 23/* PCI device IDs */ 24#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 25#define PCI_DEVID_OCTEONTX2_LBK 0xA061 26 27/* Subsystem Device ID */ 28#define PCI_SUBSYS_DEVID_98XX 0xB100 29#define PCI_SUBSYS_DEVID_96XX 0xB200 30#define PCI_SUBSYS_DEVID_CN10K_A 0xB900 31#define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00 32#define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 33#define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 34#define PCI_SUBSYS_DEVID_CN20KA 0xC220 35#define PCI_SUBSYS_DEVID_CNF20KA 0xC320 36 37/* PCI BAR nos */ 38#define PCI_AF_REG_BAR_NUM 0 39#define PCI_PF_REG_BAR_NUM 2 40#define PCI_MBOX_BAR_NUM 4 41 42#define NAME_SIZE 32 43#define MAX_NIX_BLKS 2 44#define MAX_CPT_BLKS 2 45 46/* PF_FUNC */ 47#define RVU_OTX2_PFVF_PF_SHIFT 10 48#define RVU_OTX2_PFVF_PF_MASK 0x3F 49#define RVU_PFVF_FUNC_SHIFT 0 50#define RVU_PFVF_FUNC_MASK 0x3FF 51#define RVU_CN20K_PFVF_PF_SHIFT 9 52#define RVU_CN20K_PFVF_PF_MASK 0x7F 53 54static inline u16 rvu_make_pcifunc(struct pci_dev *pdev, int pf, int func) 55{ 56 if (is_cn20k(pdev)) 57 return ((pf & RVU_CN20K_PFVF_PF_MASK) << 58 RVU_CN20K_PFVF_PF_SHIFT) | 59 ((func & RVU_PFVF_FUNC_MASK) << 60 RVU_PFVF_FUNC_SHIFT); 61 else 62 return ((pf & RVU_OTX2_PFVF_PF_MASK) << 63 RVU_OTX2_PFVF_PF_SHIFT) | 64 ((func & RVU_PFVF_FUNC_MASK) << 65 RVU_PFVF_FUNC_SHIFT); 66} 67 68static inline int rvu_pcifunc_pf_mask(struct pci_dev *pdev) 69{ 70 if (is_cn20k(pdev)) 71 return ~(RVU_CN20K_PFVF_PF_MASK << RVU_CN20K_PFVF_PF_SHIFT); 72 else 73 return ~(RVU_OTX2_PFVF_PF_MASK << RVU_OTX2_PFVF_PF_SHIFT); 74} 75 76#define RVU_AFPF 25 77 78#ifdef CONFIG_DEBUG_FS 79 80struct dump_ctx { 81 int lf; 82 int id; 83 bool all; 84}; 85 86struct cpt_ctx { 87 int blkaddr; 88 struct rvu *rvu; 89}; 90 91struct rvu_debugfs { 92 struct dentry *root; 93 struct dentry *cgx_root; 94 struct dentry *cgx; 95 struct dentry *lmac; 96 struct dentry *npa; 97 struct dentry *nix; 98 struct dentry *npc; 99 struct dentry *cpt; 100 struct dentry *mcs_root; 101 struct dentry *mcs; 102 struct dentry *mcs_rx; 103 struct dentry *mcs_tx; 104 struct dump_ctx npa_aura_ctx; 105 struct dump_ctx npa_pool_ctx; 106 struct dump_ctx nix_cq_ctx; 107 struct dump_ctx nix_rq_ctx; 108 struct dump_ctx nix_sq_ctx; 109 struct dump_ctx nix_tm_ctx; 110 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 111 int npa_qsize_id; 112 int nix_qsize_id; 113}; 114#endif 115 116struct rvu_work { 117 struct work_struct work; 118 struct rvu *rvu; 119 int num_msgs; 120 int up_num_msgs; 121}; 122 123struct rsrc_bmap { 124 unsigned long *bmap; /* Pointer to resource bitmap */ 125 u16 max; /* Max resource id or count */ 126}; 127 128struct rvu_block { 129 struct rsrc_bmap lf; 130 struct admin_queue *aq; /* NIX/NPA AQ */ 131 u16 *fn_map; /* LF to pcifunc mapping */ 132 bool multislot; 133 bool implemented; 134 u8 addr; /* RVU_BLOCK_ADDR_E */ 135 u8 type; /* RVU_BLOCK_TYPE_E */ 136 u8 lfshift; 137 u64 lookup_reg; 138 u64 pf_lfcnt_reg; 139 u64 vf_lfcnt_reg; 140 u64 lfcfg_reg; 141 u64 msixcfg_reg; 142 u64 lfreset_reg; 143 unsigned char name[NAME_SIZE]; 144 struct rvu *rvu; 145 u64 cpt_flt_eng_map[3]; 146 u64 cpt_rcvrd_eng_map[3]; 147}; 148 149struct nix_mcast { 150 struct qmem *mce_ctx; 151 struct qmem *mcast_buf; 152 int replay_pkind; 153 struct rsrc_bmap mce_counter[2]; 154 /* Counters for both ingress and egress mcast lists */ 155 struct mutex mce_lock; /* Serialize MCE updates */ 156}; 157 158struct nix_mce_list { 159 struct hlist_head head; 160 int count; 161 int max; 162}; 163 164struct nix_mcast_grp_elem { 165 struct nix_mce_list mcast_mce_list; 166 u32 mcast_grp_idx; 167 u32 pcifunc; 168 int mcam_index; 169 int mce_start_index; 170 struct list_head list; 171 u8 dir; 172}; 173 174struct nix_mcast_grp { 175 struct list_head mcast_grp_head; 176 int count; 177 int next_grp_index; 178 struct mutex mcast_grp_lock; /* Serialize MCE updates */ 179}; 180 181/* layer metadata to uniquely identify a packet header field */ 182struct npc_layer_mdata { 183 u8 lid; 184 u8 ltype; 185 u8 hdr; 186 u8 key; 187 u8 len; 188}; 189 190/* Structure to represent a field present in the 191 * generated key. A key field may present anywhere and can 192 * be of any size in the generated key. Once this structure 193 * is populated for fields of interest then field's presence 194 * and location (if present) can be known. 195 */ 196struct npc_key_field { 197 /* Masks where all set bits indicate position 198 * of a field in the key 199 */ 200 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 201 /* Number of words in the key a field spans. If a field is 202 * of 16 bytes and key offset is 4 then the field will use 203 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 204 * nr_kws will be 3(KW0, KW1 and KW2). 205 */ 206 int nr_kws; 207 /* used by packet header fields */ 208 struct npc_layer_mdata layer_mdata; 209}; 210 211struct npc_mcam { 212 struct rsrc_bmap counters; 213 struct mutex lock; /* MCAM entries and counters update lock */ 214 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 215 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 216 u16 bmap_entries; /* Number of unreserved MCAM entries */ 217 u16 bmap_fcnt; /* MCAM entries free count */ 218 u16 *entry2pfvf_map; 219 u16 *entry2cntr_map; 220 u16 *cntr2pfvf_map; 221 u16 *cntr_refcnt; 222 u16 *entry2target_pffunc; 223 u8 keysize; /* MCAM keysize 112/224/448 bits */ 224 u8 banks; /* Number of MCAM banks */ 225 u8 banks_per_entry;/* Number of keywords in key */ 226 u16 banksize; /* Number of MCAM entries in each bank */ 227 u16 total_entries; /* Total number of MCAM entries */ 228 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 229 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 230 u16 lprio_count; 231 u16 lprio_start; 232 u16 hprio_count; 233 u16 hprio_end; 234 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 235 /* fields present in the generated key */ 236 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 237 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 238 u64 tx_features; 239 u64 rx_features; 240 struct list_head mcam_rules; 241}; 242 243/* Structure for per RVU func info ie PF/VF */ 244struct rvu_pfvf { 245 bool npalf; /* Only one NPALF per RVU_FUNC */ 246 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 247 u16 sso; 248 u16 ssow; 249 u16 cptlfs; 250 u16 timlfs; 251 u16 cpt1_lfs; 252 u8 cgx_lmac; 253 254 /* Block LF's MSIX vector info */ 255 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 256#define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 257 u16 *msix_lfmap; /* Vector to block LF mapping */ 258 259 /* NPA contexts */ 260 struct qmem *aura_ctx; 261 struct qmem *pool_ctx; 262 struct qmem *npa_qints_ctx; 263 unsigned long *aura_bmap; 264 unsigned long *pool_bmap; 265 266 /* NIX contexts */ 267 struct qmem *rq_ctx; 268 struct qmem *sq_ctx; 269 struct qmem *cq_ctx; 270 struct qmem *rss_ctx; 271 struct qmem *cq_ints_ctx; 272 struct qmem *nix_qints_ctx; 273 unsigned long *sq_bmap; 274 unsigned long *rq_bmap; 275 unsigned long *cq_bmap; 276 277 u16 rx_chan_base; 278 u16 tx_chan_base; 279 u8 rx_chan_cnt; /* total number of RX channels */ 280 u8 tx_chan_cnt; /* total number of TX channels */ 281 u16 maxlen; 282 u16 minlen; 283 284 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 285 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 286 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 287 288 /* Broadcast/Multicast/Promisc pkt replication info */ 289 u16 bcast_mce_idx; 290 u16 mcast_mce_idx; 291 u16 promisc_mce_idx; 292 struct nix_mce_list bcast_mce_list; 293 struct nix_mce_list mcast_mce_list; 294 struct nix_mce_list promisc_mce_list; 295 bool use_mce_list; 296 297 struct rvu_npc_mcam_rule *def_ucast_rule; 298 299 bool cgx_in_use; /* this PF/VF using CGX? */ 300 int cgx_users; /* number of cgx users - used only by PFs */ 301 302 int intf_mode; 303 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 304 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 305 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 306 u8 lbkid; /* NIX0/1 lbk link ID */ 307 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 308 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 309 unsigned long flags; 310 struct sdp_node_info *sdp_info; 311}; 312 313enum rvu_pfvf_flags { 314 NIXLF_INITIALIZED = 0, 315 PF_SET_VF_MAC, 316 PF_SET_VF_CFG, 317 PF_SET_VF_TRUSTED, 318}; 319 320#define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 321 322struct nix_bp { 323 struct rsrc_bmap bpids; /* free bpids bitmap */ 324 u16 cgx_bpid_cnt; 325 u16 sdp_bpid_cnt; 326 u16 free_pool_base; 327 u16 *fn_map; /* pcifunc mapping */ 328 u8 *intf_map; /* interface type map */ 329 u8 *ref_cnt; 330}; 331 332struct nix_txsch { 333 struct rsrc_bmap schq; 334 u8 lvl; 335#define NIX_TXSCHQ_FREE BIT_ULL(1) 336#define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 337#define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 338#define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 339#define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 340#define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 341 u32 *pfvf_map; 342}; 343 344struct nix_mark_format { 345 u8 total; 346 u8 in_use; 347 u32 *cfg; 348}; 349 350/* smq(flush) to tl1 cir/pir info */ 351struct nix_smq_tree_ctx { 352 u16 schq; 353 u64 cir_off; 354 u64 cir_val; 355 u64 pir_off; 356 u64 pir_val; 357}; 358 359/* smq flush context */ 360struct nix_smq_flush_ctx { 361 int smq; 362 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 363}; 364 365struct npc_pkind { 366 struct rsrc_bmap rsrc; 367 u32 *pfchan_map; 368}; 369 370struct nix_flowkey { 371#define NIX_FLOW_KEY_ALG_MAX 32 372 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 373 int in_use; 374}; 375 376struct nix_lso { 377 u8 total; 378 u8 in_use; 379}; 380 381struct nix_txvlan { 382#define NIX_TX_VTAG_DEF_MAX 0x400 383 struct rsrc_bmap rsrc; 384 u16 *entry2pfvf_map; 385 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 386}; 387 388struct nix_ipolicer { 389 struct rsrc_bmap band_prof; 390 u16 *pfvf_map; 391 u16 *match_id; 392 u16 *ref_count; 393}; 394 395struct nix_hw { 396 int blkaddr; 397 struct rvu *rvu; 398 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 399 struct nix_mcast mcast; 400 struct nix_mcast_grp mcast_grp; 401 struct nix_flowkey flowkey; 402 struct nix_mark_format mark_format; 403 struct nix_lso lso; 404 struct nix_txvlan txvlan; 405 struct nix_ipolicer *ipolicer; 406 struct nix_bp bp; 407 u64 *tx_credits; 408 u8 cc_mcs_cnt; 409}; 410 411/* RVU block's capabilities or functionality, 412 * which vary by silicon version/skew. 413 */ 414struct hw_cap { 415 /* Transmit side supported functionality */ 416 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 417 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 418 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 419 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 420 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 421 bool nix_shaping; /* Is shaping and coloring supported */ 422 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 423 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 424 bool nix_rx_multicast; /* Rx packet replication support */ 425 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 426 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 427 bool programmable_chans; /* Channels programmable ? */ 428 bool ipolicer; 429 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 430 bool npc_hash_extract; /* Hash extract enabled ? */ 431 bool npc_exact_match_enabled; /* Exact match supported ? */ 432 bool cpt_rxc; /* Is CPT-RXC supported */ 433}; 434 435struct rvu_hwinfo { 436 u8 total_pfs; /* MAX RVU PFs HW supports */ 437 u16 total_vfs; /* Max RVU VFs HW supports */ 438 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 439 u8 cgx; 440 u8 lmac_per_cgx; 441 u16 cgx_chan_base; /* CGX base channel number */ 442 u16 lbk_chan_base; /* LBK base channel number */ 443 u16 sdp_chan_base; /* SDP base channel number */ 444 u16 cpt_chan_base; /* CPT base channel number */ 445 u8 cgx_links; 446 u8 lbk_links; 447 u8 sdp_links; 448 u8 cpt_links; /* Number of CPT links */ 449 u8 npc_kpus; /* No of parser units */ 450 u8 npc_pkinds; /* No of port kinds */ 451 u8 npc_intfs; /* No of interfaces */ 452 u8 npc_kpu_entries; /* No of KPU entries */ 453 u16 npc_counters; /* No of match stats counters */ 454 u32 lbk_bufsize; /* FIFO size supported by LBK */ 455 bool npc_ext_set; /* Extended register set */ 456 u64 npc_stat_ena; /* Match stats enable bit */ 457 458 struct hw_cap cap; 459 struct rvu_block block[BLK_COUNT]; /* Block info */ 460 struct nix_hw *nix; 461 struct rvu *rvu; 462 struct npc_pkind pkind; 463 struct npc_mcam mcam; 464 struct npc_exact_table *table; 465}; 466 467struct mbox_wq_info { 468 struct otx2_mbox mbox; 469 struct rvu_work *mbox_wrk; 470 471 struct otx2_mbox mbox_up; 472 struct rvu_work *mbox_wrk_up; 473 474 struct workqueue_struct *mbox_wq; 475}; 476 477struct rvu_irq_data { 478 u64 intr_status; 479 void (*rvu_queue_work_hdlr)(struct mbox_wq_info *mw, int first, 480 int mdevs, u64 intr); 481 void (*afvf_queue_work_hdlr)(struct mbox_wq_info *mw, int first, 482 int mdevs, u64 intr); 483 struct rvu *rvu; 484 int vec_num; 485 int start; 486 int mdevs; 487}; 488 489struct mbox_ops { 490 irqreturn_t (*pf_intr_handler)(int irq, void *rvu_irq); 491 irqreturn_t (*afvf_intr_handler)(int irq, void *rvu_irq); 492}; 493 494struct channel_fwdata { 495 struct sdp_node_info info; 496 u8 valid; 497#define RVU_CHANL_INFO_RESERVED 379 498 u8 reserved[RVU_CHANL_INFO_RESERVED]; 499}; 500 501struct altaf_intr_notify { 502 unsigned long flr_pf_bmap[2]; 503 unsigned long flr_vf_bmap[2]; 504 unsigned long gint_paddr; 505 unsigned long gint_iova_addr; 506 unsigned long reserved[6]; 507}; 508 509struct rvu_fwdata { 510#define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 511#define RVU_FWDATA_VERSION 0x0001 512 u32 header_magic; 513 u32 version; /* version id */ 514 515 /* MAC address */ 516#define PF_MACNUM_MAX 32 517#define VF_MACNUM_MAX 256 518 u64 pf_macs[PF_MACNUM_MAX]; 519 u64 vf_macs[VF_MACNUM_MAX]; 520 u64 sclk; 521 u64 rclk; 522 u64 mcam_addr; 523 u64 mcam_sz; 524 u64 msixtr_base; 525 u32 ptp_ext_clk_rate; 526 u32 ptp_ext_tstamp; 527 struct channel_fwdata channel_data; 528 struct altaf_intr_notify altaf_intr_info; 529#define FWDATA_RESERVED_MEM 946 530 u64 reserved[FWDATA_RESERVED_MEM]; 531#define CGX_MAX 9 532#define CGX_LMACS_MAX 4 533#define CGX_LMACS_USX 8 534#define FWDATA_CGX_LMAC_OFFSET 10536 535 union { 536 struct cgx_lmac_fwdata_s 537 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 538 struct cgx_lmac_fwdata_s 539 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 540 }; 541 /* Do not add new fields below this line */ 542}; 543 544struct ptp; 545 546/* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 547 * source where it came from. 548 */ 549struct npc_kpu_profile_adapter { 550 const char *name; 551 u64 version; 552 const struct npc_lt_def_cfg *lt_def; 553 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 554 const struct npc_kpu_profile *kpu; /* array[kpus] */ 555 struct npc_mcam_kex *mkex; 556 struct npc_mcam_kex_hash *mkex_hash; 557 bool custom; 558 size_t pkinds; 559 size_t kpus; 560}; 561 562#define RVU_SWITCH_LBK_CHAN 63 563 564struct rvu_switch { 565 struct mutex switch_lock; /* Serialize flow installation */ 566 u32 used_entries; 567 u16 *entry2pcifunc; 568 u16 mode; 569 u16 start_entry; 570}; 571 572struct rep_evtq_ent { 573 struct list_head node; 574 struct rep_event event; 575}; 576 577struct rvu { 578 void __iomem *afreg_base; 579 void __iomem *pfreg_base; 580 struct pci_dev *pdev; 581 struct device *dev; 582 struct rvu_hwinfo *hw; 583 struct rvu_pfvf *pf; 584 struct rvu_pfvf *hwvf; 585 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 586 struct mutex alias_lock; /* Serialize bar2 alias access */ 587 int vfs; /* Number of VFs attached to RVU */ 588 u16 vf_devid; /* VF devices id */ 589 bool def_rule_cntr_en; 590 int nix_blkaddr[MAX_NIX_BLKS]; 591 592 /* Mbox */ 593 struct mbox_wq_info afpf_wq_info; 594 struct mbox_wq_info afvf_wq_info; 595 596 /* PF FLR */ 597 struct rvu_work *flr_wrk; 598 struct workqueue_struct *flr_wq; 599 struct mutex flr_lock; /* Serialize FLRs */ 600 601 /* MSI-X */ 602 u16 num_vec; 603 char *irq_name; 604 bool *irq_allocated; 605 dma_addr_t msix_base_iova; 606 u64 msixtr_base_phy; /* Register reset value */ 607 608 /* CGX */ 609#define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 610 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 611 u8 cgx_mapped_pfs; 612 u8 cgx_cnt_max; /* CGX port count max */ 613 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 614 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 615 * every cgx lmac port 616 */ 617 unsigned long pf_notify_bmap; /* Flags for PF notification */ 618 void **cgx_idmap; /* cgx id to cgx data map table */ 619 struct work_struct cgx_evh_work; 620 struct workqueue_struct *cgx_evh_wq; 621 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 622 struct list_head cgx_evq_head; /* cgx event queue head */ 623 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 624 625 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 626 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 627 628 /* Firmware data */ 629 struct rvu_fwdata *fwdata; 630 void *kpu_fwdata; 631 size_t kpu_fwdata_sz; 632 void __iomem *kpu_prfl_addr; 633 634 /* NPC KPU data */ 635 struct npc_kpu_profile_adapter kpu; 636 637 struct ptp *ptp; 638 639 int mcs_blk_cnt; 640 int cpt_pf_num; 641 642#ifdef CONFIG_DEBUG_FS 643 struct rvu_debugfs rvu_dbg; 644#endif 645 struct rvu_devlink *rvu_dl; 646 647 /* RVU switch implementation over NPC with DMAC rules */ 648 struct rvu_switch rswitch; 649 650 struct work_struct mcs_intr_work; 651 struct workqueue_struct *mcs_intr_wq; 652 struct list_head mcs_intrq_head; 653 /* mcs interrupt queue lock */ 654 spinlock_t mcs_intrq_lock; 655 /* CPT interrupt lock */ 656 spinlock_t cpt_intr_lock; 657 658 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ 659 u16 rep_pcifunc; 660 bool altaf_ready; 661 int rep_cnt; 662 u16 *rep2pfvf_map; 663 u8 rep_mode; 664 struct work_struct rep_evt_work; 665 struct workqueue_struct *rep_evt_wq; 666 struct list_head rep_evtq_head; 667 /* Representor event lock */ 668 spinlock_t rep_evtq_lock; 669 670 struct ng_rvu *ng_rvu; 671}; 672 673static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 674{ 675 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 676} 677 678static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 679{ 680 return readq(rvu->afreg_base + ((block << 28) | offset)); 681} 682 683static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 684{ 685 writeq(val, rvu->pfreg_base + offset); 686} 687 688static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 689{ 690 return readq(rvu->pfreg_base + offset); 691} 692 693static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 694{ 695 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 696 * write operation. 697 */ 698 rvu_write64(rvu, block, offset, val); 699 rvu_read64(rvu, block, offset); 700 /* Barrier to ensure read completes before accessing LF registers */ 701 mb(); 702} 703 704/* Silicon revisions */ 705static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 706{ 707 struct pci_dev *pdev = rvu->pdev; 708 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 709 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 710 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 711 (pdev->revision == 0x14)); 712} 713 714static inline bool is_rvu_96xx_A0(struct rvu *rvu) 715{ 716 struct pci_dev *pdev = rvu->pdev; 717 718 return (pdev->revision == 0x00); 719} 720 721static inline bool is_rvu_96xx_B0(struct rvu *rvu) 722{ 723 struct pci_dev *pdev = rvu->pdev; 724 725 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 726} 727 728static inline bool is_rvu_95xx_A0(struct rvu *rvu) 729{ 730 struct pci_dev *pdev = rvu->pdev; 731 732 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 733} 734 735/* REVID for PCIe devices. 736 * Bits 0..1: minor pass, bit 3..2: major pass 737 * bits 7..4: midr id 738 */ 739#define PCI_REVISION_ID_96XX 0x00 740#define PCI_REVISION_ID_95XX 0x10 741#define PCI_REVISION_ID_95XXN 0x20 742#define PCI_REVISION_ID_98XX 0x30 743#define PCI_REVISION_ID_95XXMM 0x40 744#define PCI_REVISION_ID_95XXO 0xE0 745 746static inline bool is_rvu_otx2(struct rvu *rvu) 747{ 748 struct pci_dev *pdev = rvu->pdev; 749 750 u8 midr = pdev->revision & 0xF0; 751 752 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 753 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 754 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 755} 756 757static inline bool is_cnf10ka_a0(struct rvu *rvu) 758{ 759 struct pci_dev *pdev = rvu->pdev; 760 761 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A && 762 (pdev->revision & 0x0F) == 0x0) 763 return true; 764 return false; 765} 766 767static inline bool is_cn10ka_a0(struct rvu *rvu) 768{ 769 struct pci_dev *pdev = rvu->pdev; 770 771 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 772 (pdev->revision & 0x0F) == 0x0) 773 return true; 774 return false; 775} 776 777static inline bool is_cn10ka_a1(struct rvu *rvu) 778{ 779 struct pci_dev *pdev = rvu->pdev; 780 781 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 782 (pdev->revision & 0x0F) == 0x1) 783 return true; 784 return false; 785} 786 787static inline bool is_cn10kb(struct rvu *rvu) 788{ 789 struct pci_dev *pdev = rvu->pdev; 790 791 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B) 792 return true; 793 return false; 794} 795 796static inline bool is_cgx_mapped_to_nix(unsigned short id, u8 cgx_id) 797{ 798 /* On CNF10KA and CNF10KB silicons only two CGX blocks are connected 799 * to NIX. 800 */ 801 if (id == PCI_SUBSYS_DEVID_CNF10K_A || id == PCI_SUBSYS_DEVID_CNF10K_B) 802 return cgx_id <= 1; 803 804 return !(cgx_id && !(id == PCI_SUBSYS_DEVID_96XX || 805 id == PCI_SUBSYS_DEVID_98XX || 806 id == PCI_SUBSYS_DEVID_CN10K_A || 807 id == PCI_SUBSYS_DEVID_CN10K_B)); 808} 809 810static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 811{ 812 u64 npc_const3; 813 814 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 815 if (!(npc_const3 & BIT_ULL(62))) 816 return false; 817 818 return true; 819} 820 821static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 822 u8 lmacid, u8 chan) 823{ 824 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 825 u16 cgx_chans = nix_const & 0xFFULL; 826 struct rvu_hwinfo *hw = rvu->hw; 827 828 if (!hw->cap.programmable_chans) 829 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 830 831 return rvu->hw->cgx_chan_base + 832 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 833} 834 835static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 836 u8 chan) 837{ 838 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 839 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 840 struct rvu_hwinfo *hw = rvu->hw; 841 842 if (!hw->cap.programmable_chans) 843 return NIX_CHAN_LBK_CHX(lbkid, chan); 844 845 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 846} 847 848static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 849{ 850 struct rvu_hwinfo *hw = rvu->hw; 851 852 if (!hw->cap.programmable_chans) 853 return NIX_CHAN_SDP_CHX(chan); 854 855 return hw->sdp_chan_base + chan; 856} 857 858static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 859{ 860 return rvu->hw->cpt_chan_base + chan; 861} 862 863static inline bool is_rvu_supports_nix1(struct rvu *rvu) 864{ 865 struct pci_dev *pdev = rvu->pdev; 866 867 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 868 return true; 869 870 return false; 871} 872 873/* Function Prototypes 874 * RVU 875 */ 876#define RVU_LBK_VF_DEVID 0xA0F8 877static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc) 878{ 879 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) && 880 (rvu->vf_devid == RVU_LBK_VF_DEVID)); 881} 882 883static inline bool is_vf(u16 pcifunc) 884{ 885 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 886} 887 888/* check if PF_FUNC is AF */ 889static inline bool is_pffunc_af(u16 pcifunc) 890{ 891 return !pcifunc; 892} 893 894static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 895{ 896 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 897 (rvu->fwdata->version == RVU_FWDATA_VERSION); 898} 899 900int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 901void rvu_free_bitmap(struct rsrc_bmap *rsrc); 902int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 903void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 904bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 905int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 906int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 907void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start); 908bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 909u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 910struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 911void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 912bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 913bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 914int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 915int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 916int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 917int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 918int rvu_get_num_lbk_chans(void); 919int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset); 920int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 921 u16 global_slot, u16 *slot_in_block); 922 923/* RVU HW reg validation */ 924enum regmap_block { 925 TXSCHQ_HWREGMAP = 0, 926 MAX_HWREGMAP, 927}; 928 929bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 930 931/* NPA/NIX AQ APIs */ 932int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 933 int qsize, int inst_size, int res_size); 934void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 935 936/* SDP APIs */ 937int rvu_sdp_init(struct rvu *rvu); 938bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc); 939bool is_sdp_pf(struct rvu *rvu, u16 pcifunc); 940bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); 941 942static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc) 943{ 944 if (rvu->rep_pcifunc && rvu->rep_pcifunc == pcifunc) 945 return true; 946 947 return false; 948} 949 950static inline int rvu_get_pf(struct pci_dev *pdev, u16 pcifunc) 951{ 952 if (is_cn20k(pdev)) 953 return (pcifunc >> RVU_CN20K_PFVF_PF_SHIFT) & 954 RVU_CN20K_PFVF_PF_MASK; 955 else 956 return (pcifunc >> RVU_OTX2_PFVF_PF_SHIFT) & 957 RVU_OTX2_PFVF_PF_MASK; 958} 959 960/* CGX APIs */ 961static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 962{ 963 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 964 !is_sdp_pf(rvu, rvu_make_pcifunc(rvu->pdev, pf, 0)); 965} 966 967static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 968{ 969 *cgx_id = (map >> 4) & 0xF; 970 *lmac_id = (map & 0xF); 971} 972 973static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 974{ 975 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 976 is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))); 977} 978 979#define M(_name, _id, fn_name, req, rsp) \ 980int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 981MBOX_MESSAGES 982#undef M 983 984/* Mbox APIs */ 985void rvu_queue_work(struct mbox_wq_info *mw, int first, 986 int mdevs, u64 intr); 987 988int rvu_cgx_init(struct rvu *rvu); 989int rvu_cgx_exit(struct rvu *rvu); 990void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 991int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 992void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 993int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 994int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 995 int rxtxflag, u64 *stat); 996void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 997 998/* NPA APIs */ 999int rvu_npa_init(struct rvu *rvu); 1000void rvu_npa_freemem(struct rvu *rvu); 1001void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 1002int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 1003 struct npa_aq_enq_rsp *rsp); 1004 1005/* NIX APIs */ 1006bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 1007int rvu_nix_init(struct rvu *rvu); 1008int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 1009 int blkaddr, u32 cfg); 1010void rvu_nix_freemem(struct rvu *rvu); 1011int rvu_get_nixlf_count(struct rvu *rvu); 1012void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 1013int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 1014int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 1015 struct nix_mce_list *mce_list, 1016 int mce_idx, int mcam_index, bool add); 1017void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 1018 struct nix_mce_list **mce_list, int *mce_idx); 1019struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 1020int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 1021void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 1022int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 1023 struct nix_hw **nix_hw, int *blkaddr); 1024int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 1025 u16 rq_idx, u16 match_id); 1026int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 1027 struct nix_cn10k_aq_enq_req *aq_req, 1028 struct nix_cn10k_aq_enq_rsp *aq_rsp, 1029 u16 pcifunc, u8 ctype, u32 qidx); 1030int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 1031int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 1032u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 1033u32 convert_bytes_to_dwrr_mtu(u32 bytes); 1034void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 1035 struct nix_txsch *txsch, bool enable); 1036void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc); 1037int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, 1038 u32 mcast_grp_idx); 1039int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc, 1040 u32 mcast_grp_idx, u16 mcam_index); 1041void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); 1042int rvu_alloc_cint_qint_mem(struct rvu *rvu, struct rvu_pfvf *pfvf, 1043 int blkaddr, int nixlf); 1044void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr); 1045int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req, 1046 struct nix_aq_enq_rsp *rsp); 1047 1048/* NPC APIs */ 1049void rvu_npc_freemem(struct rvu *rvu); 1050int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 1051void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 1052int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 1053void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 1054 int nixlf, u64 chan, u8 *mac_addr); 1055void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 1056 int nixlf, u64 chan, u8 chan_cnt); 1057void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1058 bool enable); 1059void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 1060 int nixlf, u64 chan); 1061void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1062 u64 chan); 1063void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1064 bool enable); 1065 1066void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 1067 int nixlf, int type, bool enable); 1068void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1069bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 1070void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1071void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1072void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1073void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 1074 int group, int alg_idx, int mcam_index); 1075void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 1076 struct rvu_npc_mcam_rule *rule); 1077void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 1078 struct rvu_npc_mcam_rule *rule, 1079 struct npc_install_flow_rsp *rsp); 1080void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 1081 int blkaddr, int *alloc_cnt, 1082 int *enable_cnt); 1083void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 1084 int blkaddr, int *alloc_cnt, 1085 int *enable_cnt); 1086void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf); 1087 1088bool is_npc_intf_tx(u8 intf); 1089bool is_npc_intf_rx(u8 intf); 1090bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 1091int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 1092int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 1093const char *npc_get_field_name(u8 hdr); 1094int npc_get_bank(struct npc_mcam *mcam, int index); 1095void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 1096void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 1097void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1098 int blkaddr, int index, bool enable); 1099u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1100 int blkaddr, int index); 1101void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1102 int blkaddr, int index, u64 cfg); 1103void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1104 int blkaddr, u16 src, struct mcam_entry *entry, 1105 u8 *intf, u8 *ena); 1106int npc_config_cntr_default_entries(struct rvu *rvu, bool enable); 1107bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 1108bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 1109u32 rvu_cgx_get_fifolen(struct rvu *rvu); 1110void *rvu_first_cgx_pdata(struct rvu *rvu); 1111int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 1112int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 1113int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); 1114int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 1115 u16 pfc_en); 1116int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 1117void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 1118u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 1119void cgx_start_linkup(struct rvu *rvu); 1120int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 1121 int type); 1122bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 1123 int index); 1124int rvu_npc_init(struct rvu *rvu); 1125int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1126 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1127 u64 bcast_mcast_val, u64 bcast_mcast_mask); 1128void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 1129bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 1130int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr); 1131void npc_mcam_rsrcs_deinit(struct rvu *rvu); 1132 1133/* CPT APIs */ 1134int rvu_cpt_register_interrupts(struct rvu *rvu); 1135void rvu_cpt_unregister_interrupts(struct rvu *rvu); 1136int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 1137 int slot); 1138int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 1139int rvu_cpt_init(struct rvu *rvu); 1140 1141#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 1142#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 1143 1144/* CN10K RVU */ 1145int rvu_set_channels_base(struct rvu *rvu); 1146void rvu_program_channels(struct rvu *rvu); 1147 1148/* CN10K NIX */ 1149void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 1150 1151/* CN10K RVU - LMT*/ 1152void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 1153void rvu_apr_block_cn10k_init(struct rvu *rvu); 1154 1155#ifdef CONFIG_DEBUG_FS 1156void rvu_dbg_init(struct rvu *rvu); 1157void rvu_dbg_exit(struct rvu *rvu); 1158#else 1159static inline void rvu_dbg_init(struct rvu *rvu) {} 1160static inline void rvu_dbg_exit(struct rvu *rvu) {} 1161#endif 1162 1163int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 1164 1165/* RVU Switch */ 1166void rvu_switch_enable(struct rvu *rvu); 1167void rvu_switch_disable(struct rvu *rvu); 1168void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1169void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena); 1170 1171int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 1172 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 1173 u8 shift_dir); 1174int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 1175 1176/* CN10K MCS */ 1177int rvu_mcs_init(struct rvu *rvu); 1178int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 1179void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 1180void rvu_mcs_exit(struct rvu *rvu); 1181 1182/* Representor APIs */ 1183int rvu_rep_pf_init(struct rvu *rvu); 1184int rvu_rep_install_mcam_rules(struct rvu *rvu); 1185void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1186int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable); 1187#endif /* RVU_H */
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