npc.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Marvell RVU Admin Function driver
  3 *
  4 * Copyright (C) 2018 Marvell.
  5 *
  6 */
  7
  8#ifndef NPC_H
  9#define NPC_H
 10
 11#define NPC_KEX_CHAN_MASK	0xFFFULL
 12
 13#define SET_KEX_LD(intf, lid, ltype, ld, cfg)	\
 14	rvu_write64(rvu, blkaddr,	\
 15		    NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
 16
 17#define SET_KEX_LDFLAGS(intf, ld, flags, cfg)	\
 18	rvu_write64(rvu, blkaddr,	\
 19		    NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
 20
 21enum NPC_LID_E {
 22	NPC_LID_LA = 0,
 23	NPC_LID_LB,
 24	NPC_LID_LC,
 25	NPC_LID_LD,
 26	NPC_LID_LE,
 27	NPC_LID_LF,
 28	NPC_LID_LG,
 29	NPC_LID_LH,
 30};
 31
 32#define NPC_LT_NA 0
 33
 34enum npc_kpu_la_ltype {
 35	NPC_LT_LA_8023 = 1,
 36	NPC_LT_LA_ETHER,
 37	NPC_LT_LA_IH_NIX_ETHER,
 38	NPC_LT_LA_HIGIG2_ETHER = 7,
 39	NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
 40	NPC_LT_LA_CUSTOM_L2_90B_ETHER,
 41	NPC_LT_LA_CPT_HDR,
 42	NPC_LT_LA_CUSTOM_L2_24B_ETHER,
 43	NPC_LT_LA_CUSTOM_PRE_L2_ETHER,
 44	NPC_LT_LA_CUSTOM0 = 0xE,
 45	NPC_LT_LA_CUSTOM1 = 0xF,
 46};
 47
 48enum npc_kpu_lb_ltype {
 49	NPC_LT_LB_ETAG = 1,
 50	NPC_LT_LB_CTAG,
 51	NPC_LT_LB_STAG_QINQ,
 52	NPC_LT_LB_BTAG,
 53	NPC_LT_LB_PPPOE,
 54	NPC_LT_LB_DSA,
 55	NPC_LT_LB_DSA_VLAN,
 56	NPC_LT_LB_EDSA,
 57	NPC_LT_LB_EDSA_VLAN,
 58	NPC_LT_LB_EXDSA,
 59	NPC_LT_LB_EXDSA_VLAN,
 60	NPC_LT_LB_FDSA,
 61	NPC_LT_LB_VLAN_EXDSA,
 62	NPC_LT_LB_CUSTOM0 = 0xE,
 63	NPC_LT_LB_CUSTOM1 = 0xF,
 64};
 65
 66/* Don't modify ltypes up to IP6_EXT, otherwise length and checksum of IP
 67 * headers may not be checked correctly. IPv4 ltypes and IPv6 ltypes must
 68 * differ only at bit 0 so mask 0xE can be used to detect extended headers.
 69 */
 70enum npc_kpu_lc_ltype {
 71	NPC_LT_LC_PTP = 1,
 72	NPC_LT_LC_IP,
 73	NPC_LT_LC_IP_OPT,
 74	NPC_LT_LC_IP6,
 75	NPC_LT_LC_IP6_EXT,
 76	NPC_LT_LC_ARP,
 77	NPC_LT_LC_RARP,
 78	NPC_LT_LC_MPLS,
 79	NPC_LT_LC_NSH,
 80	NPC_LT_LC_FCOE,
 81	NPC_LT_LC_NGIO,
 82	NPC_LT_LC_CUSTOM0 = 0xE,
 83	NPC_LT_LC_CUSTOM1 = 0xF,
 84};
 85
 86/* Don't modify Ltypes upto SCTP, otherwise it will
 87 * effect flow tag calculation and thus RSS.
 88 */
 89enum npc_kpu_ld_ltype {
 90	NPC_LT_LD_TCP = 1,
 91	NPC_LT_LD_UDP,
 92	NPC_LT_LD_SCTP = 4,
 93	NPC_LT_LD_ICMP6,
 94	NPC_LT_LD_CUSTOM0,
 95	NPC_LT_LD_CUSTOM1,
 96	NPC_LT_LD_IGMP = 8,
 97	NPC_LT_LD_AH,
 98	NPC_LT_LD_GRE,
 99	NPC_LT_LD_NVGRE,
100	NPC_LT_LD_NSH,
101	NPC_LT_LD_TU_MPLS_IN_NSH,
102	NPC_LT_LD_TU_MPLS_IN_IP,
103	NPC_LT_LD_ICMP,
104};
105
106enum npc_kpu_le_ltype {
107	NPC_LT_LE_VXLAN = 1,
108	NPC_LT_LE_GENEVE,
109	NPC_LT_LE_ESP,
110	NPC_LT_LE_GTPU = 4,
111	NPC_LT_LE_VXLANGPE,
112	NPC_LT_LE_GTPC,
113	NPC_LT_LE_NSH,
114	NPC_LT_LE_TU_MPLS_IN_GRE,
115	NPC_LT_LE_TU_NSH_IN_GRE,
116	NPC_LT_LE_TU_MPLS_IN_UDP,
117	NPC_LT_LE_CUSTOM0 = 0xE,
118	NPC_LT_LE_CUSTOM1 = 0xF,
119};
120
121enum npc_kpu_lf_ltype {
122	NPC_LT_LF_TU_ETHER = 1,
123	NPC_LT_LF_TU_PPP,
124	NPC_LT_LF_TU_MPLS_IN_VXLANGPE,
125	NPC_LT_LF_TU_NSH_IN_VXLANGPE,
126	NPC_LT_LF_TU_MPLS_IN_NSH,
127	NPC_LT_LF_TU_3RD_NSH,
128	NPC_LT_LF_CUSTOM0 = 0xE,
129	NPC_LT_LF_CUSTOM1 = 0xF,
130};
131
132enum npc_kpu_lg_ltype {
133	NPC_LT_LG_TU_IP = 1,
134	NPC_LT_LG_TU_IP6,
135	NPC_LT_LG_TU_ARP,
136	NPC_LT_LG_TU_ETHER_IN_NSH,
137	NPC_LT_LG_CUSTOM0 = 0xE,
138	NPC_LT_LG_CUSTOM1 = 0xF,
139};
140
141/* Don't modify Ltypes upto SCTP, otherwise it will
142 * effect flow tag calculation and thus RSS.
143 */
144enum npc_kpu_lh_ltype {
145	NPC_LT_LH_TU_TCP = 1,
146	NPC_LT_LH_TU_UDP,
147	NPC_LT_LH_TU_SCTP = 4,
148	NPC_LT_LH_TU_ICMP6,
149	NPC_LT_LH_CUSTOM0,
150	NPC_LT_LH_CUSTOM1,
151	NPC_LT_LH_TU_IGMP = 8,
152	NPC_LT_LH_TU_ESP,
153	NPC_LT_LH_TU_AH,
154	NPC_LT_LH_TU_ICMP = 0xF,
155};
156
157/* NPC port kind defines how the incoming or outgoing packets
158 * are processed. NPC accepts packets from up to 64 pkinds.
159 * Software assigns pkind for each incoming port such as CGX
160 * Ethernet interfaces, LBK interfaces, etc.
161 */
162#define NPC_UNRESERVED_PKIND_COUNT NPC_RX_CPT_HDR_PTP_PKIND
163
164enum npc_pkind_type {
165	NPC_RX_LBK_PKIND = 0ULL,
166	NPC_RX_CPT_HDR_PTP_PKIND = 54ULL,
167	NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
168	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
169	NPC_RX_CHLEN24B_PKIND = 57ULL,
170	NPC_RX_CPT_HDR_PKIND,
171	NPC_RX_CHLEN90B_PKIND,
172	NPC_TX_HIGIG_PKIND,
173	NPC_RX_HIGIG_PKIND,
174	NPC_RX_EDSA_PKIND,
175	NPC_TX_DEF_PKIND,	/* NIX-TX PKIND */
176};
177
178enum npc_interface_type {
179	NPC_INTF_MODE_DEF,
180};
181
182/* list of known and supported fields in packet header and
183 * fields present in key structure.
184 */
185enum key_fields {
186	NPC_DMAC,
187	NPC_SMAC,
188	NPC_ETYPE,
189	NPC_VLAN_ETYPE_CTAG, /* 0x8100 */
190	NPC_VLAN_ETYPE_STAG, /* 0x88A8 */
191	NPC_OUTER_VID,
192	NPC_INNER_VID,
193	NPC_TOS,
194	NPC_IPFRAG_IPV4,
195	NPC_SIP_IPV4,
196	NPC_DIP_IPV4,
197	NPC_IPFRAG_IPV6,
198	NPC_SIP_IPV6,
199	NPC_DIP_IPV6,
200	NPC_IPPROTO_TCP,
201	NPC_IPPROTO_UDP,
202	NPC_IPPROTO_SCTP,
203	NPC_IPPROTO_AH,
204	NPC_IPPROTO_ESP,
205	NPC_IPPROTO_ICMP,
206	NPC_IPPROTO_ICMP6,
207	NPC_SPORT_TCP,
208	NPC_DPORT_TCP,
209	NPC_SPORT_UDP,
210	NPC_DPORT_UDP,
211	NPC_SPORT_SCTP,
212	NPC_DPORT_SCTP,
213	NPC_IPSEC_SPI,
214	NPC_MPLS1_LBTCBOS,
215	NPC_MPLS1_TTL,
216	NPC_MPLS2_LBTCBOS,
217	NPC_MPLS2_TTL,
218	NPC_MPLS3_LBTCBOS,
219	NPC_MPLS3_TTL,
220	NPC_MPLS4_LBTCBOS,
221	NPC_MPLS4_TTL,
222	NPC_TYPE_ICMP,
223	NPC_CODE_ICMP,
224	NPC_TCP_FLAGS,
225	NPC_HEADER_FIELDS_MAX,
226	NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */
227	NPC_PF_FUNC, /* Valid when Tx */
228	NPC_ERRLEV,
229	NPC_ERRCODE,
230	NPC_LXMB,
231	NPC_EXACT_RESULT,
232	NPC_LA,
233	NPC_LB,
234	NPC_LC,
235	NPC_LD,
236	NPC_LE,
237	NPC_LF,
238	NPC_LG,
239	NPC_LH,
240	/* Ethertype for untagged frame */
241	NPC_ETYPE_ETHER,
242	/* Ethertype for single tagged frame */
243	NPC_ETYPE_TAG1,
244	/* Ethertype for double tagged frame */
245	NPC_ETYPE_TAG2,
246	/* outer vlan tci for single tagged frame */
247	NPC_VLAN_TAG1,
248	/* outer vlan tci for double tagged frame */
249	NPC_VLAN_TAG2,
250	/* inner vlan tci for double tagged frame */
251	NPC_VLAN_TAG3,
252	/* other header fields programmed to extract but not of our interest */
253	NPC_UNKNOWN,
254	NPC_KEY_FIELDS_MAX,
255};
256
257struct npc_kpu_profile_cam {
258	u8 state;
259	u8 state_mask;
260	u16 dp0;
261	u16 dp0_mask;
262	u16 dp1;
263	u16 dp1_mask;
264	u16 dp2;
265	u16 dp2_mask;
266} __packed;
267
268struct npc_kpu_profile_action {
269	u8 errlev;
270	u8 errcode;
271	u8 dp0_offset;
272	u8 dp1_offset;
273	u8 dp2_offset;
274	u8 bypass_count;
275	u8 parse_done;
276	u8 next_state;
277	u8 ptr_advance;
278	u8 cap_ena;
279	u8 lid;
280	u8 ltype;
281	u8 flags;
282	u8 offset;
283	u8 mask;
284	u8 right;
285	u8 shift;
286} __packed;
287
288struct npc_kpu_profile {
289	int cam_entries;
290	int action_entries;
291	struct npc_kpu_profile_cam *cam;
292	struct npc_kpu_profile_action *action;
293};
294
295/* NPC KPU register formats */
296struct npc_kpu_cam {
297#if defined(__BIG_ENDIAN_BITFIELD)
298	u64 rsvd_63_56     : 8;
299	u64 state          : 8;
300	u64 dp2_data       : 16;
301	u64 dp1_data       : 16;
302	u64 dp0_data       : 16;
303#else
304	u64 dp0_data       : 16;
305	u64 dp1_data       : 16;
306	u64 dp2_data       : 16;
307	u64 state          : 8;
308	u64 rsvd_63_56     : 8;
309#endif
310};
311
312struct npc_kpu_action0 {
313#if defined(__BIG_ENDIAN_BITFIELD)
314	u64 rsvd_63_57     : 7;
315	u64 byp_count      : 3;
316	u64 capture_ena    : 1;
317	u64 parse_done     : 1;
318	u64 next_state     : 8;
319	u64 rsvd_43        : 1;
320	u64 capture_lid    : 3;
321	u64 capture_ltype  : 4;
322	u64 capture_flags  : 8;
323	u64 ptr_advance    : 8;
324	u64 var_len_offset : 8;
325	u64 var_len_mask   : 8;
326	u64 var_len_right  : 1;
327	u64 var_len_shift  : 3;
328#else
329	u64 var_len_shift  : 3;
330	u64 var_len_right  : 1;
331	u64 var_len_mask   : 8;
332	u64 var_len_offset : 8;
333	u64 ptr_advance    : 8;
334	u64 capture_flags  : 8;
335	u64 capture_ltype  : 4;
336	u64 capture_lid    : 3;
337	u64 rsvd_43        : 1;
338	u64 next_state     : 8;
339	u64 parse_done     : 1;
340	u64 capture_ena    : 1;
341	u64 byp_count      : 3;
342	u64 rsvd_63_57     : 7;
343#endif
344};
345
346struct npc_kpu_action1 {
347#if defined(__BIG_ENDIAN_BITFIELD)
348	u64 rsvd_63_36     : 28;
349	u64 errlev         : 4;
350	u64 errcode        : 8;
351	u64 dp2_offset     : 8;
352	u64 dp1_offset     : 8;
353	u64 dp0_offset     : 8;
354#else
355	u64 dp0_offset     : 8;
356	u64 dp1_offset     : 8;
357	u64 dp2_offset     : 8;
358	u64 errcode        : 8;
359	u64 errlev         : 4;
360	u64 rsvd_63_36     : 28;
361#endif
362};
363
364struct npc_kpu_pkind_cpi_def {
365#if defined(__BIG_ENDIAN_BITFIELD)
366	u64 ena            : 1;
367	u64 rsvd_62_59     : 4;
368	u64 lid            : 3;
369	u64 ltype_match    : 4;
370	u64 ltype_mask     : 4;
371	u64 flags_match    : 8;
372	u64 flags_mask     : 8;
373	u64 add_offset     : 8;
374	u64 add_mask       : 8;
375	u64 rsvd_15        : 1;
376	u64 add_shift      : 3;
377	u64 rsvd_11_10     : 2;
378	u64 cpi_base       : 10;
379#else
380	u64 cpi_base       : 10;
381	u64 rsvd_11_10     : 2;
382	u64 add_shift      : 3;
383	u64 rsvd_15        : 1;
384	u64 add_mask       : 8;
385	u64 add_offset     : 8;
386	u64 flags_mask     : 8;
387	u64 flags_match    : 8;
388	u64 ltype_mask     : 4;
389	u64 ltype_match    : 4;
390	u64 lid            : 3;
391	u64 rsvd_62_59     : 4;
392	u64 ena            : 1;
393#endif
394};
395
396struct nix_rx_action {
397#if defined(__BIG_ENDIAN_BITFIELD)
398	u64	rsvd_63_61	:3;
399	u64	flow_key_alg	:5;
400	u64	match_id	:16;
401	u64	index		:20;
402	u64	pf_func		:16;
403	u64	op		:4;
404#else
405	u64	op		:4;
406	u64	pf_func		:16;
407	u64	index		:20;
408	u64	match_id	:16;
409	u64	flow_key_alg	:5;
410	u64	rsvd_63_61	:3;
411#endif
412};
413
414/* NPC_AF_INTFX_KEX_CFG field masks */
415#define NPC_EXACT_NIBBLE_START		40
416#define NPC_EXACT_NIBBLE_END		43
417#define NPC_EXACT_NIBBLE		GENMASK_ULL(43, 40)
418
419/* NPC_EXACT_KEX_S nibble definitions for each field */
420#define NPC_EXACT_NIBBLE_HIT		BIT_ULL(40)
421#define NPC_EXACT_NIBBLE_OPC		BIT_ULL(40)
422#define NPC_EXACT_NIBBLE_WAY		BIT_ULL(40)
423#define NPC_EXACT_NIBBLE_INDEX		GENMASK_ULL(43, 41)
424
425#define NPC_EXACT_RESULT_HIT		BIT_ULL(0)
426#define NPC_EXACT_RESULT_OPC		GENMASK_ULL(2, 1)
427#define NPC_EXACT_RESULT_WAY		GENMASK_ULL(4, 3)
428#define NPC_EXACT_RESULT_IDX		GENMASK_ULL(15, 5)
429
430/* NPC_AF_INTFX_KEX_CFG field masks */
431#define NPC_PARSE_NIBBLE		GENMASK_ULL(30, 0)
432
433/* NPC_PARSE_KEX_S nibble definitions for each field */
434#define NPC_PARSE_NIBBLE_CHAN		GENMASK_ULL(2, 0)
435#define NPC_PARSE_NIBBLE_ERRLEV		BIT_ULL(3)
436#define NPC_PARSE_NIBBLE_ERRCODE	GENMASK_ULL(5, 4)
437#define NPC_PARSE_NIBBLE_L2L3_BCAST	BIT_ULL(6)
438#define NPC_PARSE_NIBBLE_LA_FLAGS	GENMASK_ULL(8, 7)
439#define NPC_PARSE_NIBBLE_LA_LTYPE	BIT_ULL(9)
440#define NPC_PARSE_NIBBLE_LB_FLAGS	GENMASK_ULL(11, 10)
441#define NPC_PARSE_NIBBLE_LB_LTYPE	BIT_ULL(12)
442#define NPC_PARSE_NIBBLE_LC_FLAGS	GENMASK_ULL(14, 13)
443#define NPC_PARSE_NIBBLE_LC_LTYPE	BIT_ULL(15)
444#define NPC_PARSE_NIBBLE_LD_FLAGS	GENMASK_ULL(17, 16)
445#define NPC_PARSE_NIBBLE_LD_LTYPE	BIT_ULL(18)
446#define NPC_PARSE_NIBBLE_LE_FLAGS	GENMASK_ULL(20, 19)
447#define NPC_PARSE_NIBBLE_LE_LTYPE	BIT_ULL(21)
448#define NPC_PARSE_NIBBLE_LF_FLAGS	GENMASK_ULL(23, 22)
449#define NPC_PARSE_NIBBLE_LF_LTYPE	BIT_ULL(24)
450#define NPC_PARSE_NIBBLE_LG_FLAGS	GENMASK_ULL(26, 25)
451#define NPC_PARSE_NIBBLE_LG_LTYPE	BIT_ULL(27)
452#define NPC_PARSE_NIBBLE_LH_FLAGS	GENMASK_ULL(29, 28)
453#define NPC_PARSE_NIBBLE_LH_LTYPE	BIT_ULL(30)
454
455struct nix_tx_action {
456#if defined(__BIG_ENDIAN_BITFIELD)
457	u64	rsvd_63_48	:16;
458	u64	match_id	:16;
459	u64	index		:20;
460	u64	rsvd_11_8	:8;
461	u64	op		:4;
462#else
463	u64	op		:4;
464	u64	rsvd_11_8	:8;
465	u64	index		:20;
466	u64	match_id	:16;
467	u64	rsvd_63_48	:16;
468#endif
469};
470
471/* NIX Receive Vtag Action Structure */
472#define RX_VTAG0_VALID_BIT		BIT_ULL(15)
473#define RX_VTAG0_TYPE_MASK		GENMASK_ULL(14, 12)
474#define RX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
475#define RX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
476#define RX_VTAG1_VALID_BIT		BIT_ULL(47)
477#define RX_VTAG1_TYPE_MASK		GENMASK_ULL(46, 44)
478#define RX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
479#define RX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
480
481/* NIX Transmit Vtag Action Structure */
482#define TX_VTAG0_DEF_MASK		GENMASK_ULL(25, 16)
483#define TX_VTAG0_OP_MASK		GENMASK_ULL(13, 12)
484#define TX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
485#define TX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
486#define TX_VTAG1_DEF_MASK		GENMASK_ULL(57, 48)
487#define TX_VTAG1_OP_MASK		GENMASK_ULL(45, 44)
488#define TX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
489#define TX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
490
491/* NPC MCAM reserved entry index per nixlf */
492#define NIXLF_UCAST_ENTRY	0
493#define NIXLF_BCAST_ENTRY	1
494#define NIXLF_ALLMULTI_ENTRY	2
495#define NIXLF_PROMISC_ENTRY	3
496
497struct npc_coalesced_kpu_prfl {
498#define NPC_SIGN	0x00666f727063706e
499#define NPC_PRFL_NAME   "npc_prfls_array"
500#define NPC_NAME_LEN	32
501	__le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */
502	u8 name[NPC_NAME_LEN]; /* KPU Profile name */
503	u64 version; /* KPU firmware/profile version */
504	u8 num_prfl; /* No of NPC profiles. */
505	u16 prfl_sz[];
506};
507
508struct npc_mcam_kex {
509	/* MKEX Profle Header */
510	u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
511	u8 name[MKEX_NAME_LEN];   /* MKEX Profile name */
512	u64 cpu_model;   /* Format as profiled by CPU hardware */
513	u64 kpu_version; /* KPU firmware/profile version */
514	u64 reserved; /* Reserved for extension */
515
516	/* MKEX Profle Data */
517	u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
518	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
519	u64 kex_ld_flags[NPC_MAX_LD];
520	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
521	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
522	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
523	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
524} __packed;
525
526struct npc_kpu_fwdata {
527	int	entries;
528	/* What follows is:
529	 * struct npc_kpu_profile_cam[entries];
530	 * struct npc_kpu_profile_action[entries];
531	 */
532	u8	data[];
533} __packed;
534
535struct npc_lt_def {
536	u8	ltype_mask;
537	u8	ltype_match;
538	u8	lid;
539} __packed;
540
541struct npc_lt_def_ipsec {
542	u8	ltype_mask;
543	u8	ltype_match;
544	u8	lid;
545	u8	spi_offset;
546	u8	spi_nz;
547} __packed;
548
549struct npc_lt_def_apad {
550	u8	ltype_mask;
551	u8	ltype_match;
552	u8	lid;
553	u8	valid;
554} __packed;
555
556struct npc_lt_def_color {
557	u8	ltype_mask;
558	u8	ltype_match;
559	u8	lid;
560	u8	noffset;
561	u8	offset;
562} __packed;
563
564struct npc_lt_def_et {
565	u8	ltype_mask;
566	u8	ltype_match;
567	u8	lid;
568	u8	valid;
569	u8	offset;
570} __packed;
571
572struct npc_lt_def_cfg {
573	struct npc_lt_def	rx_ol2;
574	struct npc_lt_def	rx_oip4;
575	struct npc_lt_def	rx_iip4;
576	struct npc_lt_def	rx_oip6;
577	struct npc_lt_def	rx_iip6;
578	struct npc_lt_def	rx_otcp;
579	struct npc_lt_def	rx_itcp;
580	struct npc_lt_def	rx_oudp;
581	struct npc_lt_def	rx_iudp;
582	struct npc_lt_def	rx_osctp;
583	struct npc_lt_def	rx_isctp;
584	struct npc_lt_def_ipsec	rx_ipsec[2];
585	struct npc_lt_def	pck_ol2;
586	struct npc_lt_def	pck_oip4;
587	struct npc_lt_def	pck_oip6;
588	struct npc_lt_def	pck_iip4;
589	struct npc_lt_def_apad	rx_apad0;
590	struct npc_lt_def_apad	rx_apad1;
591	struct npc_lt_def_color	ovlan;
592	struct npc_lt_def_color	ivlan;
593	struct npc_lt_def_color	rx_gen0_color;
594	struct npc_lt_def_color	rx_gen1_color;
595	struct npc_lt_def_et	rx_et[2];
596} __packed;
597
598/* Loadable KPU profile firmware data */
599struct npc_kpu_profile_fwdata {
600#define KPU_SIGN	0x00666f727075706b
601#define KPU_NAME_LEN	32
602/** Maximum number of custom KPU entries supported by the built-in profile. */
603#define KPU_MAX_CST_ENT	6
604	/* KPU Profle Header */
605	__le64	signature; /* "kpuprof\0" (8 bytes/ASCII characters) */
606	u8	name[KPU_NAME_LEN]; /* KPU Profile name */
607	__le64	version; /* KPU profile version */
608	u8	kpus;
609	u8	reserved[7];
610
611	/* Default MKEX profile to be used with this KPU profile. May be
612	 * overridden with mkex_profile module parameter. Format is same as for
613	 * the MKEX profile to streamline processing.
614	 */
615	struct npc_mcam_kex	mkex;
616	/* LTYPE values for specific HW offloaded protocols. */
617	struct npc_lt_def_cfg	lt_def;
618	/* Dynamically sized data:
619	 *  Custom KPU CAM and ACTION configuration entries.
620	 * struct npc_kpu_fwdata kpu[kpus];
621	 */
622	u8	data[];
623} __packed;
624
625struct rvu_npc_mcam_rule {
626	struct flow_msg packet;
627	struct flow_msg mask;
628	u8 intf;
629	union {
630		struct nix_tx_action tx_action;
631		struct nix_rx_action rx_action;
632	};
633	u64 vtag_action;
634	struct list_head list;
635	u64 features;
636	u16 owner;
637	u16 entry;
638	u16 cntr;
639	bool has_cntr;
640	u8 default_rule;
641	bool enable;
642	bool vfvlan_cfg;
643	u16 chan;
644	u16 chan_mask;
645	u8 lxmb;
646};
647
648#endif /* NPC_H */