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mbox.h
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linux-6.19.14/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8#ifndef MBOX_H 9#define MBOX_H 10 11#include <linux/etherdevice.h> 12#include <linux/sizes.h> 13#include <linux/ethtool.h> 14 15#include "rvu_struct.h" 16#include "common.h" 17#include "cn20k/struct.h" 18 19#define MBOX_SIZE SZ_64K 20 21#define MBOX_DOWN_MSG 1 22#define MBOX_UP_MSG 2 23 24/* AF/PF: PF initiated, PF/VF VF initiated */ 25#define MBOX_DOWN_RX_START 0 26#define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 27#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 28#define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 29/* AF/PF: AF initiated, PF/VF PF initiated */ 30#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 31#define MBOX_UP_RX_SIZE SZ_1K 32#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 33#define MBOX_UP_TX_SIZE SZ_1K 34 35#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 36# error "incorrect mailbox area sizes" 37#endif 38 39#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 40 41#define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 42 43#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 44 45/* Mailbox directions */ 46#define MBOX_DIR_AFPF 0 /* AF replies to PF */ 47#define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 48#define MBOX_DIR_PFVF 2 /* PF replies to VF */ 49#define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 50#define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 51#define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 52#define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 53#define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 54 55enum { 56 TYPE_AFVF, 57 TYPE_AFPF, 58}; 59 60struct otx2_mbox_dev { 61 void *mbase; /* This dev's mbox region */ 62 void *hwbase; 63 spinlock_t mbox_lock; 64 u16 msg_size; /* Total msg size to be sent */ 65 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 66 u16 num_msgs; /* No of msgs sent or waiting for response */ 67 u16 msgs_acked; /* No of msgs for which response is received */ 68}; 69 70struct otx2_mbox { 71 struct pci_dev *pdev; 72 void *hwbase; /* Mbox region advertised by HW */ 73 void *reg_base;/* CSR base for this dev */ 74 u64 trigger; /* Trigger mbox notification */ 75 u16 tr_shift; /* Mbox trigger shift */ 76 u64 rx_start; /* Offset of Rx region in mbox memory */ 77 u64 tx_start; /* Offset of Tx region in mbox memory */ 78 u16 rx_size; /* Size of Rx region */ 79 u16 tx_size; /* Size of Tx region */ 80 u16 ndevs; /* The number of peers */ 81 struct otx2_mbox_dev *dev; 82}; 83 84/* Header which precedes all mbox messages */ 85struct mbox_hdr { 86 u64 msg_size; /* Total msgs size embedded */ 87 u16 num_msgs; /* No of msgs embedded */ 88 u16 opt_msg; 89 u8 sig; 90}; 91 92/* Header which precedes every msg and is also part of it */ 93struct mbox_msghdr { 94 u16 pcifunc; /* Who's sending this msg */ 95 u16 id; /* Mbox message ID */ 96#define OTX2_MBOX_REQ_SIG (0xdead) 97#define OTX2_MBOX_RSP_SIG (0xbeef) 98 u16 sig; /* Signature, for validating corrupted msgs */ 99#define OTX2_MBOX_VERSION (0x000a) 100 u16 ver; /* Version of msg's structure for this ID */ 101 u16 next_msgoff; /* Offset of next msg within mailbox region */ 102 int rc; /* Msg process'ed response code */ 103}; 104 105void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 106void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 107void otx2_mbox_destroy(struct otx2_mbox *mbox); 108int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 109 struct pci_dev *pdev, void __force *reg_base, 110 int direction, int ndevs); 111 112int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 113 struct pci_dev *pdev, void __force *reg_base, 114 int direction, int ndevs, unsigned long *bmap); 115void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 116void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid); 117int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 118int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 119struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 120 int size, int size_rsp); 121struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 122 struct mbox_msghdr *msg); 123int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 124int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 125 u16 pcifunc, u16 id); 126bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 127const char *otx2_mbox_id2name(u16 id); 128static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 129 int devid, int size) 130{ 131 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 132} 133 134bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid); 135 136/* Mailbox message types */ 137#define MBOX_MSG_MASK 0xFFFF 138#define MBOX_MSG_INVALID 0xFFFE 139#define MBOX_MSG_MAX 0xFFFF 140 141#define MBOX_MESSAGES \ 142/* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 143M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 144M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 145M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 146M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 147M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 148M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 149M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 150M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 151M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \ 152M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 153 msg_rsp) \ 154M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 155M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 156M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ 157M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \ 158M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \ 159/* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 160M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 161M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 162M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 163M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 164 cgx_mac_addr_set_or_get) \ 165M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 166 cgx_mac_addr_set_or_get) \ 167M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 168M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 169M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 170M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 171M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 172M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 173M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 174M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 175M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 176M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 177 cgx_pause_frm_cfg) \ 178M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 179M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 180M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 181 cgx_mac_addr_add_rsp) \ 182M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 183 msg_rsp) \ 184M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 185 cgx_max_dmac_entries_get_rsp) \ 186M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 187M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 188 cgx_set_link_mode_rsp) \ 189M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 190M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \ 191M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 192 cgx_features_info_msg) \ 193M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 194M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 195 msg_rsp) \ 196M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 197 cgx_mac_addr_update_rsp) \ 198M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 199 cgx_pfc_rsp) \ 200/* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 201M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 202 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 203M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 204M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 205M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 206M(NPA_CN20K_AQ_ENQ, 0x404, npa_cn20k_aq_enq, npa_cn20k_aq_enq_req, \ 207 npa_cn20k_aq_enq_rsp) \ 208/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 209/* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 210/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 211M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 212 msg_rsp) \ 213M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 214M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 215 cpt_rd_wr_reg_msg) \ 216M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 217 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 218M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 219M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 220 msg_rsp) \ 221M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 222M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 223M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 224 cpt_flt_eng_info_rsp) \ 225/* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 226M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 227M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 228/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 229M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 230 npc_mcam_alloc_entry_rsp) \ 231M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 232 npc_mcam_free_entry_req, msg_rsp) \ 233M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 234 npc_mcam_write_entry_req, msg_rsp) \ 235M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 236 npc_mcam_ena_dis_entry_req, msg_rsp) \ 237M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 238 npc_mcam_ena_dis_entry_req, msg_rsp) \ 239M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 240 npc_mcam_shift_entry_rsp) \ 241M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 242 npc_mcam_alloc_counter_req, \ 243 npc_mcam_alloc_counter_rsp) \ 244M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 245 npc_mcam_oper_counter_req, msg_rsp) \ 246M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 247 npc_mcam_unmap_counter_req, msg_rsp) \ 248M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 249 npc_mcam_oper_counter_req, msg_rsp) \ 250M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 251 npc_mcam_oper_counter_req, \ 252 npc_mcam_oper_counter_rsp) \ 253M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 254 npc_mcam_alloc_and_write_entry_req, \ 255 npc_mcam_alloc_and_write_entry_rsp) \ 256M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 257 msg_req, npc_get_kex_cfg_rsp) \ 258M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 259 npc_install_flow_req, npc_install_flow_rsp) \ 260M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 261 npc_delete_flow_req, npc_delete_flow_rsp) \ 262M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 263 npc_mcam_read_entry_req, \ 264 npc_mcam_read_entry_rsp) \ 265M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 266 npc_set_pkind, msg_rsp) \ 267M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 268 msg_req, npc_mcam_read_base_rule_rsp) \ 269M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 270 npc_mcam_get_stats_req, \ 271 npc_mcam_get_stats_rsp) \ 272M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 273 npc_get_field_hash_info_req, \ 274 npc_get_field_hash_info_rsp) \ 275M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 276 npc_get_field_status_req, \ 277 npc_get_field_status_rsp) \ 278/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 279M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 280 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 281M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 282M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 283M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 284 hwctx_disable_req, msg_rsp) \ 285M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 286 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 287M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 288M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 289 nix_txschq_config) \ 290M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 291M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 292 nix_vtag_config_rsp) \ 293M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 294 nix_rss_flowkey_cfg, \ 295 nix_rss_flowkey_cfg_rsp) \ 296M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 297M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 298M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 299M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 300M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 301M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 302 nix_mark_format_cfg, \ 303 nix_mark_format_cfg_rsp) \ 304M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 305M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 306 nix_lso_format_cfg, \ 307 nix_lso_format_cfg_rsp) \ 308M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 309M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 310M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 311 nix_bp_cfg_rsp) \ 312M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 313M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 314M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 315 nix_inline_ipsec_cfg, msg_rsp) \ 316M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 317 nix_inline_ipsec_lf_cfg, msg_rsp) \ 318M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 319 nix_cn10k_aq_enq_rsp) \ 320M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 321M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 322 nix_bandprof_alloc_rsp) \ 323M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 324 msg_rsp) \ 325M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 326 nix_bandprof_get_hwinfo_rsp) \ 327M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \ 328 nix_bp_cfg_rsp) \ 329M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ 330 msg_rsp) \ 331M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 332 msg_req, nix_inline_ipsec_cfg) \ 333M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \ 334 nix_mcast_grp_create_rsp) \ 335M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \ 336 msg_rsp) \ 337M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \ 338 nix_mcast_grp_update_req, \ 339 nix_mcast_grp_update_rsp) \ 340M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \ 341M(NIX_CN20K_AQ_ENQ, 0x802f, nix_cn20k_aq_enq, nix_cn20k_aq_enq_req, \ 342 nix_cn20k_aq_enq_rsp) \ 343/* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 344M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 345 mcs_alloc_rsrc_rsp) \ 346M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 347M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 348 msg_rsp) \ 349M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 350 msg_rsp) \ 351M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 352 msg_rsp) \ 353M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 354 msg_rsp) \ 355M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 356 msg_rsp) \ 357M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 358 msg_rsp) \ 359M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 360 msg_rsp) \ 361M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 362 msg_rsp) \ 363M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 364 msg_rsp) \ 365M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 366M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 367 mcs_flowid_stats) \ 368M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 369 mcs_secy_stats) \ 370M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 371M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 372M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 373 mcs_port_stats) \ 374M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 375M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 376M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 377M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 378 msg_rsp) \ 379M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 380 mcs_alloc_ctrl_pkt_rule_req, \ 381 mcs_alloc_ctrl_pkt_rule_rsp) \ 382M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 383 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 384M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 385 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 386M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 387M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 388M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 389 mcs_port_cfg_get_rsp) \ 390M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 391 mcs_custom_tag_cfg_get_req, \ 392 mcs_custom_tag_cfg_get_rsp) 393 394/* Messages initiated by AF (range 0xC00 - 0xEFF) */ 395#define MBOX_UP_CGX_MESSAGES \ 396M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 397 398#define MBOX_UP_CPT_MESSAGES \ 399M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 400 401#define MBOX_UP_MCS_MESSAGES \ 402M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 403 404#define MBOX_UP_REP_MESSAGES \ 405M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \ 406 407enum { 408#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 409MBOX_MESSAGES 410MBOX_UP_CGX_MESSAGES 411MBOX_UP_CPT_MESSAGES 412MBOX_UP_MCS_MESSAGES 413MBOX_UP_REP_MESSAGES 414#undef M 415}; 416 417/* Mailbox message formats */ 418 419#define RVU_DEFAULT_PF_FUNC 0xFFFF 420 421/* Generic request msg used for those mbox messages which 422 * don't send any data in the request. 423 */ 424struct msg_req { 425 struct mbox_msghdr hdr; 426}; 427 428/* Generic response msg used an ack or response for those mbox 429 * messages which don't have a specific rsp msg format. 430 */ 431struct msg_rsp { 432 struct mbox_msghdr hdr; 433}; 434 435/* RVU mailbox error codes 436 * Range 256 - 300. 437 */ 438enum rvu_af_status { 439 RVU_INVALID_VF_ID = -256, 440}; 441 442struct ready_msg_rsp { 443 struct mbox_msghdr hdr; 444 u16 sclk_freq; /* SCLK frequency (in MHz) */ 445 u16 rclk_freq; /* RCLK frequency (in MHz) */ 446}; 447 448/* Structure for requesting resource provisioning. 449 * 'modify' flag to be used when either requesting more 450 * or to detach partial of a certain resource type. 451 * Rest of the fields specify how many of what type to 452 * be attached. 453 * To request LFs from two blocks of same type this mailbox 454 * can be sent twice as below: 455 * struct rsrc_attach *attach; 456 * .. Allocate memory for message .. 457 * attach->cptlfs = 3; <3 LFs from CPT0> 458 * .. Send message .. 459 * .. Allocate memory for message .. 460 * attach->modify = 1; 461 * attach->cpt_blkaddr = BLKADDR_CPT1; 462 * attach->cptlfs = 2; <2 LFs from CPT1> 463 * .. Send message .. 464 */ 465struct rsrc_attach { 466 struct mbox_msghdr hdr; 467 u8 modify:1; 468 u8 npalf:1; 469 u8 nixlf:1; 470 u16 sso; 471 u16 ssow; 472 u16 timlfs; 473 u16 cptlfs; 474 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 475}; 476 477/* Structure for relinquishing resources. 478 * 'partial' flag to be used when relinquishing all resources 479 * but only of a certain type. If not set, all resources of all 480 * types provisioned to the RVU function will be detached. 481 */ 482struct rsrc_detach { 483 struct mbox_msghdr hdr; 484 u8 partial:1; 485 u8 npalf:1; 486 u8 nixlf:1; 487 u8 sso:1; 488 u8 ssow:1; 489 u8 timlfs:1; 490 u8 cptlfs:1; 491}; 492 493/* Number of resources available to the caller. 494 * In reply to MBOX_MSG_FREE_RSRC_CNT. 495 */ 496struct free_rsrcs_rsp { 497 struct mbox_msghdr hdr; 498 u16 schq[NIX_TXSCH_LVL_CNT]; 499 u16 sso; 500 u16 tim; 501 u16 ssow; 502 u16 cpt; 503 u8 npa; 504 u8 nix; 505 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 506 u8 nix1; 507 u8 cpt1; 508 u8 ree0; 509 u8 ree1; 510}; 511 512#define MSIX_VECTOR_INVALID 0xFFFF 513#define MAX_RVU_BLKLF_CNT 256 514 515struct msix_offset_rsp { 516 struct mbox_msghdr hdr; 517 u16 npa_msixoff; 518 u16 nix_msixoff; 519 u16 sso; 520 u16 ssow; 521 u16 timlfs; 522 u16 cptlfs; 523 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 524 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 525 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 526 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 527 u16 cpt1_lfs; 528 u16 ree0_lfs; 529 u16 ree1_lfs; 530 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 531 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 532 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 533}; 534 535struct get_hw_cap_rsp { 536 struct mbox_msghdr hdr; 537 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 538 u8 nix_shaping; /* Is shaping and coloring supported */ 539 u8 npc_hash_extract; /* Is hash extract supported */ 540#define HW_CAP_MACSEC BIT_ULL(1) 541 u64 hw_caps; 542}; 543 544/* CGX mbox message formats */ 545 546struct cgx_stats_rsp { 547 struct mbox_msghdr hdr; 548#define CGX_RX_STATS_COUNT 9 549#define CGX_TX_STATS_COUNT 18 550 u64 rx_stats[CGX_RX_STATS_COUNT]; 551 u64 tx_stats[CGX_TX_STATS_COUNT]; 552}; 553 554struct cgx_fec_stats_rsp { 555 struct mbox_msghdr hdr; 556 u64 fec_corr_blks; 557 u64 fec_uncorr_blks; 558}; 559/* Structure for requesting the operation for 560 * setting/getting mac address in the CGX interface 561 */ 562struct cgx_mac_addr_set_or_get { 563 struct mbox_msghdr hdr; 564 u8 mac_addr[ETH_ALEN]; 565 u32 index; 566}; 567 568/* Structure for requesting the operation to 569 * add DMAC filter entry into CGX interface 570 */ 571struct cgx_mac_addr_add_req { 572 struct mbox_msghdr hdr; 573 u8 mac_addr[ETH_ALEN]; 574}; 575 576/* Structure for response against the operation to 577 * add DMAC filter entry into CGX interface 578 */ 579struct cgx_mac_addr_add_rsp { 580 struct mbox_msghdr hdr; 581 u32 index; 582}; 583 584/* Structure for requesting the operation to 585 * delete DMAC filter entry from CGX interface 586 */ 587struct cgx_mac_addr_del_req { 588 struct mbox_msghdr hdr; 589 u32 index; 590}; 591 592/* Structure for response against the operation to 593 * get maximum supported DMAC filter entries 594 */ 595struct cgx_max_dmac_entries_get_rsp { 596 struct mbox_msghdr hdr; 597 u32 max_dmac_filters; 598}; 599 600struct cgx_link_user_info { 601 uint64_t link_up:1; 602 uint64_t full_duplex:1; 603 uint64_t lmac_type_id:4; 604 uint64_t speed:20; /* speed in Mbps */ 605 uint64_t an:1; /* AN supported or not */ 606 uint64_t fec:2; /* FEC type if enabled else 0 */ 607#define LMACTYPE_STR_LEN 16 608 char lmac_type[LMACTYPE_STR_LEN]; 609}; 610 611struct cgx_link_info_msg { 612 struct mbox_msghdr hdr; 613 struct cgx_link_user_info link_info; 614}; 615 616struct cgx_pause_frm_cfg { 617 struct mbox_msghdr hdr; 618 u8 set; 619 /* set = 1 if the request is to config pause frames */ 620 /* set = 0 if the request is to fetch pause frames config */ 621 u8 rx_pause; 622 u8 tx_pause; 623}; 624 625enum fec_type { 626 OTX2_FEC_NONE, 627 OTX2_FEC_BASER, 628 OTX2_FEC_RS, 629 OTX2_FEC_STATS_CNT = 2, 630 OTX2_FEC_OFF, 631}; 632 633struct fec_mode { 634 struct mbox_msghdr hdr; 635 int fec; 636}; 637 638struct sfp_eeprom_s { 639#define SFP_EEPROM_SIZE 256 640 u16 sff_id; 641 u8 buf[SFP_EEPROM_SIZE]; 642 u64 reserved; 643}; 644 645struct phy_s { 646 struct { 647 u64 can_change_mod_type:1; 648 u64 mod_type:1; 649 u64 has_fec_stats:1; 650 } misc; 651 struct fec_stats_s { 652 u32 rsfec_corr_cws; 653 u32 rsfec_uncorr_cws; 654 u32 brfec_corr_blks; 655 u32 brfec_uncorr_blks; 656 } fec_stats; 657}; 658 659struct cgx_lmac_fwdata_s { 660 u16 rw_valid; 661 u64 supported_fec; 662 u64 supported_an; 663 u64 supported_link_modes; 664 /* only applicable if AN is supported */ 665 u64 advertised_fec; 666 u64 advertised_link_modes_own:1; /* CGX_CMD_OWN */ 667 u64 advertised_link_modes:63; 668 /* Only applicable if SFP/QSFP slot is present */ 669 struct sfp_eeprom_s sfp_eeprom; 670 struct phy_s phy; 671 u32 lmac_type; 672 u32 portm_idx; 673 u64 mgmt_port:1; 674 u64 advertised_an:1; 675 u64 port; 676#define LMAC_FWDATA_RESERVED_MEM 1018 677 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 678}; 679 680struct cgx_fw_data { 681 struct mbox_msghdr hdr; 682 struct cgx_lmac_fwdata_s fwdata; 683}; 684 685struct cgx_set_link_mode_args { 686 u32 speed; 687 u8 duplex; 688 u8 an; 689 u8 mode_baseidx; 690 u8 multimode; 691 u64 mode; 692 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 693}; 694 695struct cgx_set_link_mode_req { 696 struct mbox_msghdr hdr; 697 struct cgx_set_link_mode_args args; 698}; 699 700struct cgx_set_link_mode_rsp { 701 struct mbox_msghdr hdr; 702 int status; 703}; 704 705struct cgx_mac_addr_reset_req { 706 struct mbox_msghdr hdr; 707 u32 index; 708}; 709 710struct cgx_mac_addr_update_req { 711 struct mbox_msghdr hdr; 712 u8 mac_addr[ETH_ALEN]; 713 u32 index; 714}; 715 716struct cgx_mac_addr_update_rsp { 717 struct mbox_msghdr hdr; 718 u32 index; 719}; 720 721#define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 722#define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 723 /* flow control from physical link higig2 messages */ 724#define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 725#define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 726#define RVU_MAC_VERSION BIT_ULL(4) 727#define RVU_MAC_CGX BIT_ULL(5) 728#define RVU_MAC_RPM BIT_ULL(6) 729 730struct cgx_features_info_msg { 731 struct mbox_msghdr hdr; 732 u64 lmac_features; 733}; 734 735struct rpm_stats_rsp { 736 struct mbox_msghdr hdr; 737#define RPM_RX_STATS_COUNT 43 738#define RPM_TX_STATS_COUNT 34 739 u64 rx_stats[RPM_RX_STATS_COUNT]; 740 u64 tx_stats[RPM_TX_STATS_COUNT]; 741}; 742 743struct cgx_pfc_cfg { 744 struct mbox_msghdr hdr; 745 u8 rx_pause; 746 u8 tx_pause; 747 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 748}; 749 750struct cgx_pfc_rsp { 751 struct mbox_msghdr hdr; 752 u8 rx_pause; 753 u8 tx_pause; 754}; 755 756 /* NPA mbox message formats */ 757 758struct npc_set_pkind { 759 struct mbox_msghdr hdr; 760#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 761#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 762 u64 mode; 763#define PKIND_TX BIT_ULL(0) 764#define PKIND_RX BIT_ULL(1) 765 u8 dir; 766 u8 pkind; /* valid only in case custom flag */ 767 u8 var_len_off; /* Offset of custom header length field. 768 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 769 */ 770 u8 var_len_off_mask; /* Mask for length with in offset */ 771 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 772}; 773 774/* NPA mbox message formats */ 775 776/* NPA mailbox error codes 777 * Range 301 - 400. 778 */ 779enum npa_af_status { 780 NPA_AF_ERR_PARAM = -301, 781 NPA_AF_ERR_AQ_FULL = -302, 782 NPA_AF_ERR_AQ_ENQUEUE = -303, 783 NPA_AF_ERR_AF_LF_INVALID = -304, 784 NPA_AF_ERR_AF_LF_ALLOC = -305, 785 NPA_AF_ERR_LF_RESET = -306, 786}; 787 788/* For NPA LF context alloc and init */ 789struct npa_lf_alloc_req { 790 struct mbox_msghdr hdr; 791 int node; 792 int aura_sz; /* No of auras */ 793 u32 nr_pools; /* No of pools */ 794 u64 way_mask; 795}; 796 797struct npa_lf_alloc_rsp { 798 struct mbox_msghdr hdr; 799 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 800 u32 stack_pg_bytes; /* Size of stack page */ 801 u16 qints; /* NPA_AF_CONST::QINTS */ 802 u8 cache_lines; /*BATCH ALLOC DMA */ 803}; 804 805/* NPA AQ enqueue msg */ 806struct npa_aq_enq_req { 807 struct mbox_msghdr hdr; 808 u32 aura_id; 809 u8 ctype; 810 u8 op; 811 union { 812 /* Valid when op == WRITE/INIT and ctype == AURA. 813 * LF fills the pool_id in aura.pool_addr. AF will translate 814 * the pool_id to pool context pointer. 815 */ 816 struct npa_aura_s aura; 817 /* Valid when op == WRITE/INIT and ctype == POOL */ 818 struct npa_pool_s pool; 819 }; 820 /* Mask data when op == WRITE (1=write, 0=don't write) */ 821 union { 822 /* Valid when op == WRITE and ctype == AURA */ 823 struct npa_aura_s aura_mask; 824 /* Valid when op == WRITE and ctype == POOL */ 825 struct npa_pool_s pool_mask; 826 }; 827}; 828 829struct npa_aq_enq_rsp { 830 struct mbox_msghdr hdr; 831 union { 832 /* Valid when op == READ and ctype == AURA */ 833 struct npa_aura_s aura; 834 /* Valid when op == READ and ctype == POOL */ 835 struct npa_pool_s pool; 836 }; 837}; 838 839struct npa_cn20k_aq_enq_req { 840 struct mbox_msghdr hdr; 841 u32 aura_id; 842 u8 ctype; 843 u8 op; 844 union { 845 /* Valid when op == WRITE/INIT and ctype == AURA. 846 * LF fills the pool_id in aura.pool_addr. AF will translate 847 * the pool_id to pool context pointer. 848 */ 849 struct npa_cn20k_aura_s aura; 850 /* Valid when op == WRITE/INIT and ctype == POOL */ 851 struct npa_cn20k_pool_s pool; 852 }; 853 /* Mask data when op == WRITE (1=write, 0=don't write) */ 854 union { 855 /* Valid when op == WRITE and ctype == AURA */ 856 struct npa_cn20k_aura_s aura_mask; 857 /* Valid when op == WRITE and ctype == POOL */ 858 struct npa_cn20k_pool_s pool_mask; 859 }; 860}; 861 862struct npa_cn20k_aq_enq_rsp { 863 struct mbox_msghdr hdr; 864 union { 865 /* Valid when op == READ and ctype == AURA */ 866 struct npa_cn20k_aura_s aura; 867 /* Valid when op == READ and ctype == POOL */ 868 struct npa_cn20k_pool_s pool; 869 }; 870}; 871 872/* Disable all contexts of type 'ctype' */ 873struct hwctx_disable_req { 874 struct mbox_msghdr hdr; 875 u8 ctype; 876}; 877 878/* NIX mbox message formats */ 879 880/* NIX mailbox error codes 881 * Range 401 - 500. 882 */ 883enum nix_af_status { 884 NIX_AF_ERR_PARAM = -401, 885 NIX_AF_ERR_AQ_FULL = -402, 886 NIX_AF_ERR_AQ_ENQUEUE = -403, 887 NIX_AF_ERR_AF_LF_INVALID = -404, 888 NIX_AF_ERR_AF_LF_ALLOC = -405, 889 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 890 NIX_AF_ERR_TLX_INVALID = -407, 891 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 892 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 893 NIX_AF_ERR_FRS_INVALID = -410, 894 NIX_AF_ERR_RX_LINK_INVALID = -411, 895 NIX_AF_INVAL_TXSCHQ_CFG = -412, 896 NIX_AF_SMQ_FLUSH_FAILED = -413, 897 NIX_AF_ERR_LF_RESET = -414, 898 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 899 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 900 NIX_AF_ERR_MARK_CFG_FAIL = -417, 901 NIX_AF_ERR_LSO_CFG_FAIL = -418, 902 NIX_AF_INVAL_NPA_PF_FUNC = -419, 903 NIX_AF_INVAL_SSO_PF_FUNC = -420, 904 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 905 NIX_AF_ERR_RX_VTAG_INUSE = -422, 906 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 907 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 908 NIX_AF_ERR_INVALID_NIXBLK = -425, 909 NIX_AF_ERR_INVALID_BANDPROF = -426, 910 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 911 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 912 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 913 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 914 NIX_AF_ERR_LINK_CREDITS = -431, 915 NIX_AF_ERR_INVALID_BPID = -434, 916 NIX_AF_ERR_INVALID_BPID_REQ = -435, 917 NIX_AF_ERR_INVALID_MCAST_GRP = -436, 918 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437, 919 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438, 920}; 921 922/* For NIX RX vtag action */ 923enum nix_rx_vtag0_type { 924 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 925 NIX_AF_LFX_RX_VTAG_TYPE1, 926 NIX_AF_LFX_RX_VTAG_TYPE2, 927 NIX_AF_LFX_RX_VTAG_TYPE3, 928 NIX_AF_LFX_RX_VTAG_TYPE4, 929 NIX_AF_LFX_RX_VTAG_TYPE5, 930 NIX_AF_LFX_RX_VTAG_TYPE6, 931 NIX_AF_LFX_RX_VTAG_TYPE7, 932}; 933 934/* For NIX LF context alloc and init */ 935struct nix_lf_alloc_req { 936 struct mbox_msghdr hdr; 937 int node; 938 u32 rq_cnt; /* No of receive queues */ 939 u32 sq_cnt; /* No of send queues */ 940 u32 cq_cnt; /* No of completion queues */ 941 u8 xqe_sz; 942 u16 rss_sz; 943 u8 rss_grps; 944 u16 npa_func; 945 u16 sso_func; 946 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 947 u64 way_mask; 948#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 949#define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 950 u64 flags; 951}; 952 953struct nix_lf_alloc_rsp { 954 struct mbox_msghdr hdr; 955 u16 sqb_size; 956 u16 rx_chan_base; 957 u16 tx_chan_base; 958 u8 rx_chan_cnt; /* total number of RX channels */ 959 u8 tx_chan_cnt; /* total number of TX channels */ 960 u8 lso_tsov4_idx; 961 u8 lso_tsov6_idx; 962 u8 mac_addr[ETH_ALEN]; 963 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 964 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 965 u16 cints; /* NIX_AF_CONST2::CINTS */ 966 u16 qints; /* NIX_AF_CONST2::QINTS */ 967 u8 cgx_links; /* No. of CGX links present in HW */ 968 u8 lbk_links; /* No. of LBK links present in HW */ 969 u8 sdp_links; /* No. of SDP links present in HW */ 970 u8 tx_link; /* Transmit channel link number */ 971}; 972 973struct nix_lf_free_req { 974 struct mbox_msghdr hdr; 975#define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 976#define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 977 u64 flags; 978}; 979 980/* CN20K NIX AQ enqueue msg */ 981struct nix_cn20k_aq_enq_req { 982 struct mbox_msghdr hdr; 983 u32 qidx; 984 u8 ctype; 985 u8 op; 986 union { 987 struct nix_cn20k_rq_ctx_s rq; 988 struct nix_cn20k_sq_ctx_s sq; 989 struct nix_cn20k_cq_ctx_s cq; 990 struct nix_rsse_s rss; 991 struct nix_rx_mce_s mce; 992 struct nix_bandprof_s prof; 993 }; 994 union { 995 struct nix_cn20k_rq_ctx_s rq_mask; 996 struct nix_cn20k_sq_ctx_s sq_mask; 997 struct nix_cn20k_cq_ctx_s cq_mask; 998 struct nix_rsse_s rss_mask; 999 struct nix_rx_mce_s mce_mask; 1000 struct nix_bandprof_s prof_mask; 1001 }; 1002}; 1003 1004struct nix_cn20k_aq_enq_rsp { 1005 struct mbox_msghdr hdr; 1006 union { 1007 struct nix_cn20k_rq_ctx_s rq; 1008 struct nix_cn20k_sq_ctx_s sq; 1009 struct nix_cn20k_cq_ctx_s cq; 1010 struct nix_rsse_s rss; 1011 struct nix_rx_mce_s mce; 1012 struct nix_bandprof_s prof; 1013 }; 1014}; 1015 1016/* CN10K NIX AQ enqueue msg */ 1017struct nix_cn10k_aq_enq_req { 1018 struct mbox_msghdr hdr; 1019 u32 qidx; 1020 u8 ctype; 1021 u8 op; 1022 union { 1023 struct nix_cn10k_rq_ctx_s rq; 1024 struct nix_cn10k_sq_ctx_s sq; 1025 struct nix_cq_ctx_s cq; 1026 struct nix_rsse_s rss; 1027 struct nix_rx_mce_s mce; 1028 struct nix_bandprof_s prof; 1029 }; 1030 union { 1031 struct nix_cn10k_rq_ctx_s rq_mask; 1032 struct nix_cn10k_sq_ctx_s sq_mask; 1033 struct nix_cq_ctx_s cq_mask; 1034 struct nix_rsse_s rss_mask; 1035 struct nix_rx_mce_s mce_mask; 1036 struct nix_bandprof_s prof_mask; 1037 }; 1038}; 1039 1040struct nix_cn10k_aq_enq_rsp { 1041 struct mbox_msghdr hdr; 1042 union { 1043 struct nix_cn10k_rq_ctx_s rq; 1044 struct nix_cn10k_sq_ctx_s sq; 1045 struct nix_cq_ctx_s cq; 1046 struct nix_rsse_s rss; 1047 struct nix_rx_mce_s mce; 1048 struct nix_bandprof_s prof; 1049 }; 1050}; 1051 1052/* NIX AQ enqueue msg */ 1053struct nix_aq_enq_req { 1054 struct mbox_msghdr hdr; 1055 u32 qidx; 1056 u8 ctype; 1057 u8 op; 1058 union { 1059 struct nix_rq_ctx_s rq; 1060 struct nix_sq_ctx_s sq; 1061 struct nix_cq_ctx_s cq; 1062 struct nix_rsse_s rss; 1063 struct nix_rx_mce_s mce; 1064 struct nix_bandprof_s prof; 1065 }; 1066 union { 1067 struct nix_rq_ctx_s rq_mask; 1068 struct nix_sq_ctx_s sq_mask; 1069 struct nix_cq_ctx_s cq_mask; 1070 struct nix_rsse_s rss_mask; 1071 struct nix_rx_mce_s mce_mask; 1072 struct nix_bandprof_s prof_mask; 1073 }; 1074}; 1075 1076struct nix_aq_enq_rsp { 1077 struct mbox_msghdr hdr; 1078 union { 1079 struct nix_rq_ctx_s rq; 1080 struct nix_sq_ctx_s sq; 1081 struct nix_cq_ctx_s cq; 1082 struct nix_rsse_s rss; 1083 struct nix_rx_mce_s mce; 1084 struct nix_bandprof_s prof; 1085 }; 1086}; 1087 1088/* Tx scheduler/shaper mailbox messages */ 1089 1090#define MAX_TXSCHQ_PER_FUNC 128 1091 1092struct nix_txsch_alloc_req { 1093 struct mbox_msghdr hdr; 1094 /* Scheduler queue count request at each level */ 1095 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 1096 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 1097}; 1098 1099struct nix_txsch_alloc_rsp { 1100 struct mbox_msghdr hdr; 1101 /* Scheduler queue count allocated at each level */ 1102 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 1103 u16 schq[NIX_TXSCH_LVL_CNT]; 1104 /* Scheduler queue list allocated at each level */ 1105 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1106 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 1107 u8 aggr_level; /* Traffic aggregation scheduler level */ 1108 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 1109 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 1110}; 1111 1112struct nix_txsch_free_req { 1113 struct mbox_msghdr hdr; 1114#define TXSCHQ_FREE_ALL BIT_ULL(0) 1115 u16 flags; 1116 /* Scheduler queue level to be freed */ 1117 u16 schq_lvl; 1118 /* List of scheduler queues to be freed */ 1119 u16 schq; 1120}; 1121 1122struct nix_txschq_config { 1123 struct mbox_msghdr hdr; 1124 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1125 u8 read; 1126#define TXSCHQ_IDX_SHIFT 16 1127#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1128#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1129 u8 num_regs; 1130#define MAX_REGS_PER_MBOX_MSG 20 1131 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1132 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1133 /* All 0's => overwrite with new value */ 1134 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1135}; 1136 1137struct nix_vtag_config { 1138 struct mbox_msghdr hdr; 1139 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1140 u8 vtag_size; 1141 /* cfg_type is '0' for tx vlan cfg 1142 * cfg_type is '1' for rx vlan cfg 1143 */ 1144 u8 cfg_type; 1145 union { 1146 /* valid when cfg_type is '0' */ 1147 struct { 1148 u64 vtag0; 1149 u64 vtag1; 1150 1151 /* cfg_vtag0 & cfg_vtag1 fields are valid 1152 * when free_vtag0 & free_vtag1 are '0's. 1153 */ 1154 /* cfg_vtag0 = 1 to configure vtag0 */ 1155 u8 cfg_vtag0 :1; 1156 /* cfg_vtag1 = 1 to configure vtag1 */ 1157 u8 cfg_vtag1 :1; 1158 1159 /* vtag0_idx & vtag1_idx are only valid when 1160 * both cfg_vtag0 & cfg_vtag1 are '0's, 1161 * these fields are used along with free_vtag0 1162 * & free_vtag1 to free the nix lf's tx_vlan 1163 * configuration. 1164 * 1165 * Denotes the indices of tx_vtag def registers 1166 * that needs to be cleared and freed. 1167 */ 1168 int vtag0_idx; 1169 int vtag1_idx; 1170 1171 /* free_vtag0 & free_vtag1 fields are valid 1172 * when cfg_vtag0 & cfg_vtag1 are '0's. 1173 */ 1174 /* free_vtag0 = 1 clears vtag0 configuration 1175 * vtag0_idx denotes the index to be cleared. 1176 */ 1177 u8 free_vtag0 :1; 1178 /* free_vtag1 = 1 clears vtag1 configuration 1179 * vtag1_idx denotes the index to be cleared. 1180 */ 1181 u8 free_vtag1 :1; 1182 } tx; 1183 1184 /* valid when cfg_type is '1' */ 1185 struct { 1186 /* rx vtag type index, valid values are in 0..7 range */ 1187 u8 vtag_type; 1188 /* rx vtag strip */ 1189 u8 strip_vtag :1; 1190 /* rx vtag capture */ 1191 u8 capture_vtag :1; 1192 } rx; 1193 }; 1194}; 1195 1196struct nix_vtag_config_rsp { 1197 struct mbox_msghdr hdr; 1198 int vtag0_idx; 1199 int vtag1_idx; 1200 /* Indices of tx_vtag def registers used to configure 1201 * tx vtag0 & vtag1 headers, these indices are valid 1202 * when nix_vtag_config mbox requested for vtag0 and/ 1203 * or vtag1 configuration. 1204 */ 1205}; 1206 1207#define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1208 1209struct nix_rss_flowkey_cfg { 1210 struct mbox_msghdr hdr; 1211 int mcam_index; /* MCAM entry index to modify */ 1212#define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1213#define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1214#define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1215#define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1216#define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1217#define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1218#define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1219#define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1220#define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1221#define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1222#define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1223#define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1224#define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1225#define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1226#define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1227#define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1228#define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1229#define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1230#define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19) 1231#define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1232#define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1233#define NIX_FLOW_KEY_TYPE_AH BIT(22) 1234#define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1235#define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1236#define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1237#define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1238#define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1239 u32 flowkey_cfg; /* Flowkey types selected */ 1240 u8 group; /* RSS context or group */ 1241}; 1242 1243struct nix_rss_flowkey_cfg_rsp { 1244 struct mbox_msghdr hdr; 1245 u8 alg_idx; /* Selected algo index */ 1246}; 1247 1248struct nix_set_mac_addr { 1249 struct mbox_msghdr hdr; 1250 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1251}; 1252 1253struct nix_get_mac_addr_rsp { 1254 struct mbox_msghdr hdr; 1255 u8 mac_addr[ETH_ALEN]; 1256}; 1257 1258struct nix_mark_format_cfg { 1259 struct mbox_msghdr hdr; 1260 u8 offset; 1261 u8 y_mask; 1262 u8 y_val; 1263 u8 r_mask; 1264 u8 r_val; 1265}; 1266 1267struct nix_mark_format_cfg_rsp { 1268 struct mbox_msghdr hdr; 1269 u8 mark_format_idx; 1270}; 1271 1272struct nix_rx_mode { 1273 struct mbox_msghdr hdr; 1274#define NIX_RX_MODE_UCAST BIT(0) 1275#define NIX_RX_MODE_PROMISC BIT(1) 1276#define NIX_RX_MODE_ALLMULTI BIT(2) 1277#define NIX_RX_MODE_USE_MCE BIT(3) 1278 u16 mode; 1279}; 1280 1281struct nix_rx_cfg { 1282 struct mbox_msghdr hdr; 1283#define NIX_RX_OL3_VERIFY BIT(0) 1284#define NIX_RX_OL4_VERIFY BIT(1) 1285#define NIX_RX_DROP_RE BIT(2) 1286 u8 len_verify; /* Outer L3/L4 len check */ 1287#define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1288 u8 csum_verify; /* Outer L4 checksum verification */ 1289}; 1290 1291struct nix_frs_cfg { 1292 struct mbox_msghdr hdr; 1293 u8 update_smq; /* Update SMQ's min/max lens */ 1294 u8 update_minlen; /* Set minlen also */ 1295 u8 sdp_link; /* Set SDP RX link */ 1296 u16 maxlen; 1297 u16 minlen; 1298}; 1299 1300struct nix_lso_format_cfg { 1301 struct mbox_msghdr hdr; 1302 u64 field_mask; 1303#define NIX_LSO_FIELD_MAX 8 1304 u64 fields[NIX_LSO_FIELD_MAX]; 1305}; 1306 1307struct nix_lso_format_cfg_rsp { 1308 struct mbox_msghdr hdr; 1309 u8 lso_format_idx; 1310}; 1311 1312struct nix_bp_cfg_req { 1313 struct mbox_msghdr hdr; 1314 u16 chan_base; /* Starting channel number */ 1315 u8 chan_cnt; /* Number of channels */ 1316 u8 bpid_per_chan; 1317 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1318 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1319}; 1320 1321/* Maximum channels any single NIX interface can have */ 1322#define NIX_MAX_BPID_CHAN 256 1323struct nix_bp_cfg_rsp { 1324 struct mbox_msghdr hdr; 1325 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1326 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1327}; 1328 1329struct nix_mcast_grp_create_req { 1330 struct mbox_msghdr hdr; 1331#define NIX_MCAST_INGRESS 0 1332#define NIX_MCAST_EGRESS 1 1333 u8 dir; 1334 u8 reserved[11]; 1335 /* Reserving few bytes for future requirement */ 1336}; 1337 1338struct nix_mcast_grp_create_rsp { 1339 struct mbox_msghdr hdr; 1340 /* This mcast_grp_idx should be passed during MCAM 1341 * write entry for multicast. AF will identify the 1342 * corresponding multicast table index associated 1343 * with the group id and program the same to MCAM entry. 1344 * This group id is also needed during group delete 1345 * and update request. 1346 */ 1347 u32 mcast_grp_idx; 1348}; 1349 1350struct nix_mcast_grp_destroy_req { 1351 struct mbox_msghdr hdr; 1352 /* Group id returned by nix_mcast_grp_create_rsp */ 1353 u32 mcast_grp_idx; 1354 /* If AF is requesting for destroy, then set 1355 * it to '1'. Otherwise keep it to '0' 1356 */ 1357 u8 is_af; 1358}; 1359 1360struct nix_mcast_grp_update_req { 1361 struct mbox_msghdr hdr; 1362 /* Group id returned by nix_mcast_grp_create_rsp */ 1363 u32 mcast_grp_idx; 1364 /* Number of multicast/mirror entries requested */ 1365 u32 num_mce_entry; 1366#define NIX_MCE_ENTRY_MAX 64 1367#define NIX_RX_RQ 0 1368#define NIX_RX_RSS 1 1369 /* Receive queue or RSS index within pf_func */ 1370 u32 rq_rss_index[NIX_MCE_ENTRY_MAX]; 1371 /* pcifunc is required for both ingress and egress multicast */ 1372 u16 pcifunc[NIX_MCE_ENTRY_MAX]; 1373 /* channel is required for egress multicast */ 1374 u16 channel[NIX_MCE_ENTRY_MAX]; 1375#define NIX_MCAST_OP_ADD_ENTRY 0 1376#define NIX_MCAST_OP_DEL_ENTRY 1 1377 /* Destination type. 0:Receive queue, 1:RSS*/ 1378 u8 dest_type[NIX_MCE_ENTRY_MAX]; 1379 u8 op; 1380 /* If AF is requesting for update, then set 1381 * it to '1'. Otherwise keep it to '0' 1382 */ 1383 u8 is_af; 1384}; 1385 1386struct nix_mcast_grp_update_rsp { 1387 struct mbox_msghdr hdr; 1388 u32 mce_start_index; 1389}; 1390 1391/* Global NIX inline IPSec configuration */ 1392struct nix_inline_ipsec_cfg { 1393 struct mbox_msghdr hdr; 1394 u32 cpt_credit; 1395 struct { 1396 u8 egrp; 1397 u16 opcode; 1398 u16 param1; 1399 u16 param2; 1400 } gen_cfg; 1401 struct { 1402 u16 cpt_pf_func; 1403 u8 cpt_slot; 1404 } inst_qsel; 1405 u8 enable; 1406 u16 bpid; 1407 u32 credit_th; 1408}; 1409 1410/* Per NIX LF inline IPSec configuration */ 1411struct nix_inline_ipsec_lf_cfg { 1412 struct mbox_msghdr hdr; 1413 u64 sa_base_addr; 1414 struct { 1415 u32 tag_const; 1416 u16 lenm1_max; 1417 u8 sa_pow2_size; 1418 u8 tt; 1419 } ipsec_cfg0; 1420 struct { 1421 u32 sa_idx_max; 1422 u8 sa_idx_w; 1423 } ipsec_cfg1; 1424 u8 enable; 1425}; 1426 1427struct nix_hw_info { 1428 struct mbox_msghdr hdr; 1429 u16 rsvs16; 1430 u16 max_mtu; 1431 u16 min_mtu; 1432 u32 rpm_dwrr_mtu; 1433 u32 sdp_dwrr_mtu; 1434 u32 lbk_dwrr_mtu; 1435 u32 rsvd32[1]; 1436 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1437}; 1438 1439struct nix_bandprof_alloc_req { 1440 struct mbox_msghdr hdr; 1441 /* Count of profiles needed per layer */ 1442 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1443}; 1444 1445struct nix_bandprof_alloc_rsp { 1446 struct mbox_msghdr hdr; 1447 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1448 1449 /* There is no need to allocate morethan 1 bandwidth profile 1450 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1451 * profiles to 64 per PF_FUNC. 1452 */ 1453#define MAX_BANDPROF_PER_PFFUNC 64 1454 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1455}; 1456 1457struct nix_bandprof_free_req { 1458 struct mbox_msghdr hdr; 1459 u8 free_all; 1460 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1461 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1462}; 1463 1464struct nix_bandprof_get_hwinfo_rsp { 1465 struct mbox_msghdr hdr; 1466 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1467 u32 policer_timeunit; 1468}; 1469 1470struct nix_stats_req { 1471 struct mbox_msghdr hdr; 1472 u8 reset; 1473 u16 pcifunc; 1474 u64 rsvd; 1475}; 1476 1477struct nix_stats_rsp { 1478 struct mbox_msghdr hdr; 1479 u16 pcifunc; 1480 struct { 1481 u64 octs; 1482 u64 ucast; 1483 u64 bcast; 1484 u64 mcast; 1485 u64 drop; 1486 u64 drop_octs; 1487 u64 drop_mcast; 1488 u64 drop_bcast; 1489 u64 err; 1490 u64 rsvd[5]; 1491 } rx; 1492 struct { 1493 u64 ucast; 1494 u64 bcast; 1495 u64 mcast; 1496 u64 drop; 1497 u64 octs; 1498 } tx; 1499}; 1500 1501/* NPC mbox message structs */ 1502 1503#define NPC_MCAM_ENTRY_INVALID 0xFFFF 1504#define NPC_MCAM_INVALID_MAP 0xFFFF 1505 1506/* NPC mailbox error codes 1507 * Range 701 - 800. 1508 */ 1509enum npc_af_status { 1510 NPC_MCAM_INVALID_REQ = -701, 1511 NPC_MCAM_ALLOC_DENIED = -702, 1512 NPC_MCAM_ALLOC_FAILED = -703, 1513 NPC_MCAM_PERM_DENIED = -704, 1514 NPC_FLOW_INTF_INVALID = -707, 1515 NPC_FLOW_CHAN_INVALID = -708, 1516 NPC_FLOW_NO_NIXLF = -709, 1517 NPC_FLOW_NOT_SUPPORTED = -710, 1518 NPC_FLOW_VF_PERM_DENIED = -711, 1519 NPC_FLOW_VF_NOT_INIT = -712, 1520 NPC_FLOW_VF_OVERLAP = -713, 1521}; 1522 1523struct npc_mcam_alloc_entry_req { 1524 struct mbox_msghdr hdr; 1525#define NPC_MAX_NONCONTIG_ENTRIES 256 1526 u8 contig; /* Contiguous entries ? */ 1527#define NPC_MCAM_ANY_PRIO 0 1528#define NPC_MCAM_LOWER_PRIO 1 1529#define NPC_MCAM_HIGHER_PRIO 2 1530 u8 priority; /* Lower or higher w.r.t ref_entry */ 1531 u16 ref_entry; 1532 u16 count; /* Number of entries requested */ 1533}; 1534 1535struct npc_mcam_alloc_entry_rsp { 1536 struct mbox_msghdr hdr; 1537 u16 entry; /* Entry allocated or start index if contiguous. 1538 * Invalid incase of non-contiguous. 1539 */ 1540 u16 count; /* Number of entries allocated */ 1541 u16 free_count; /* Number of entries available */ 1542 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1543}; 1544 1545struct npc_mcam_free_entry_req { 1546 struct mbox_msghdr hdr; 1547 u16 entry; /* Entry index to be freed */ 1548 u8 all; /* If all entries allocated to this PFVF to be freed */ 1549}; 1550 1551struct mcam_entry { 1552#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1553 u64 kw[NPC_MAX_KWS_IN_KEY]; 1554 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1555 u64 action; 1556 u64 vtag_action; 1557}; 1558 1559struct npc_mcam_write_entry_req { 1560 struct mbox_msghdr hdr; 1561 struct mcam_entry entry_data; 1562 u16 entry; /* MCAM entry to write this match key */ 1563 u16 cntr; /* Counter for this MCAM entry */ 1564 u8 intf; /* Rx or Tx interface */ 1565 u8 enable_entry;/* Enable this MCAM entry ? */ 1566 u8 set_cntr; /* Set counter for this entry ? */ 1567}; 1568 1569/* Enable/Disable a given entry */ 1570struct npc_mcam_ena_dis_entry_req { 1571 struct mbox_msghdr hdr; 1572 u16 entry; 1573}; 1574 1575struct npc_mcam_shift_entry_req { 1576 struct mbox_msghdr hdr; 1577#define NPC_MCAM_MAX_SHIFTS 64 1578 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1579 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1580 u16 shift_count; /* Number of entries to shift */ 1581}; 1582 1583struct npc_mcam_shift_entry_rsp { 1584 struct mbox_msghdr hdr; 1585 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1586}; 1587 1588struct npc_mcam_alloc_counter_req { 1589 struct mbox_msghdr hdr; 1590 u8 contig; /* Contiguous counters ? */ 1591#define NPC_MAX_NONCONTIG_COUNTERS 64 1592 u16 count; /* Number of counters requested */ 1593}; 1594 1595struct npc_mcam_alloc_counter_rsp { 1596 struct mbox_msghdr hdr; 1597 u16 cntr; /* Counter allocated or start index if contiguous. 1598 * Invalid incase of non-contiguous. 1599 */ 1600 u16 count; /* Number of counters allocated */ 1601 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1602}; 1603 1604struct npc_mcam_oper_counter_req { 1605 struct mbox_msghdr hdr; 1606 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1607}; 1608 1609struct npc_mcam_oper_counter_rsp { 1610 struct mbox_msghdr hdr; 1611 u64 stat; /* valid only while fetching counter's stats */ 1612}; 1613 1614struct npc_mcam_unmap_counter_req { 1615 struct mbox_msghdr hdr; 1616 u16 cntr; 1617 u16 entry; /* Entry and counter to be unmapped */ 1618 u8 all; /* Unmap all entries using this counter ? */ 1619}; 1620 1621struct npc_mcam_alloc_and_write_entry_req { 1622 struct mbox_msghdr hdr; 1623 struct mcam_entry entry_data; 1624 u16 ref_entry; 1625 u8 priority; /* Lower or higher w.r.t ref_entry */ 1626 u8 intf; /* Rx or Tx interface */ 1627 u8 enable_entry;/* Enable this MCAM entry ? */ 1628 u8 alloc_cntr; /* Allocate counter and map ? */ 1629}; 1630 1631struct npc_mcam_alloc_and_write_entry_rsp { 1632 struct mbox_msghdr hdr; 1633 u16 entry; 1634 u16 cntr; 1635}; 1636 1637struct npc_get_kex_cfg_rsp { 1638 struct mbox_msghdr hdr; 1639 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1640 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1641#define NPC_MAX_INTF 2 1642#define NPC_MAX_LID 8 1643#define NPC_MAX_LT 16 1644#define NPC_MAX_LD 2 1645#define NPC_MAX_LFL 16 1646 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1647 u64 kex_ld_flags[NPC_MAX_LD]; 1648 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1649 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1650 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1651 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1652#define MKEX_NAME_LEN 128 1653 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1654}; 1655 1656struct ptp_get_cap_rsp { 1657 struct mbox_msghdr hdr; 1658#define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1659 u64 cap; 1660}; 1661 1662struct get_rep_cnt_rsp { 1663 struct mbox_msghdr hdr; 1664 u16 rep_cnt; 1665 u16 rep_pf_map[64]; 1666 u64 rsvd; 1667}; 1668 1669struct esw_cfg_req { 1670 struct mbox_msghdr hdr; 1671 u8 ena; 1672 u64 rsvd; 1673}; 1674 1675struct rep_evt_data { 1676 u8 port_state; 1677 u8 vf_state; 1678 u16 rx_mode; 1679 u16 rx_flags; 1680 u16 mtu; 1681 u8 mac[ETH_ALEN]; 1682 u64 rsvd[5]; 1683}; 1684 1685struct rep_event { 1686 struct mbox_msghdr hdr; 1687 u16 pcifunc; 1688#define RVU_EVENT_PORT_STATE BIT_ULL(0) 1689#define RVU_EVENT_PFVF_STATE BIT_ULL(1) 1690#define RVU_EVENT_MTU_CHANGE BIT_ULL(2) 1691#define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3) 1692#define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4) 1693 u16 event; 1694 struct rep_evt_data evt_data; 1695}; 1696 1697struct flow_msg { 1698 unsigned char dmac[6]; 1699 unsigned char smac[6]; 1700 __be16 etype; 1701 __be16 vlan_etype; 1702 __be16 vlan_tci; 1703 union { 1704 __be32 ip4src; 1705 __be32 ip6src[4]; 1706 }; 1707 union { 1708 __be32 ip4dst; 1709 __be32 ip6dst[4]; 1710 }; 1711 union { 1712 __be32 spi; 1713 }; 1714 1715 u8 tos; 1716 u8 ip_ver; 1717 u8 ip_proto; 1718 u8 tc; 1719 __be16 sport; 1720 __be16 dport; 1721 union { 1722 u8 ip_flag; 1723 u8 next_header; 1724 }; 1725 __be16 vlan_itci; 1726#define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12) 1727#define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9) 1728#define OTX2_FLOWER_MASK_MPLS_BOS BIT(8) 1729#define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0) 1730#define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8) 1731 u32 mpls_lse[4]; 1732 u8 icmp_type; 1733 u8 icmp_code; 1734 __be16 tcp_flags; 1735 u16 sq_id; 1736}; 1737 1738struct npc_install_flow_req { 1739 struct mbox_msghdr hdr; 1740 struct flow_msg packet; 1741 struct flow_msg mask; 1742 u64 features; 1743 u16 entry; 1744 u16 channel; 1745 u16 chan_mask; 1746 u8 intf; 1747 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1748 u8 default_rule; 1749 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1750 u16 vf; 1751 /* action */ 1752 u32 index; 1753 u16 match_id; 1754 u8 flow_key_alg; 1755 u8 op; 1756 /* vtag rx action */ 1757 u8 vtag0_type; 1758 u8 vtag0_valid; 1759 u8 vtag1_type; 1760 u8 vtag1_valid; 1761 /* vtag tx action */ 1762 u16 vtag0_def; 1763 u8 vtag0_op; 1764 u16 vtag1_def; 1765 u8 vtag1_op; 1766 /* old counter value */ 1767 u16 cntr_val; 1768}; 1769 1770struct npc_install_flow_rsp { 1771 struct mbox_msghdr hdr; 1772 int counter; /* negative if no counter else counter number */ 1773}; 1774 1775struct npc_delete_flow_req { 1776 struct mbox_msghdr hdr; 1777 u16 entry; 1778 u16 start;/*Disable range of entries */ 1779 u16 end; 1780 u8 all; /* PF + VFs */ 1781}; 1782 1783struct npc_delete_flow_rsp { 1784 struct mbox_msghdr hdr; 1785 u16 cntr_val; 1786}; 1787 1788struct npc_mcam_read_entry_req { 1789 struct mbox_msghdr hdr; 1790 u16 entry; /* MCAM entry to read */ 1791}; 1792 1793struct npc_mcam_read_entry_rsp { 1794 struct mbox_msghdr hdr; 1795 struct mcam_entry entry_data; 1796 u8 intf; 1797 u8 enable; 1798}; 1799 1800struct npc_mcam_read_base_rule_rsp { 1801 struct mbox_msghdr hdr; 1802 struct mcam_entry entry; 1803}; 1804 1805struct npc_mcam_get_stats_req { 1806 struct mbox_msghdr hdr; 1807 u16 entry; /* mcam entry */ 1808}; 1809 1810struct npc_mcam_get_stats_rsp { 1811 struct mbox_msghdr hdr; 1812 u64 stat; /* counter stats */ 1813 u8 stat_ena; /* enabled */ 1814}; 1815 1816struct npc_get_field_hash_info_req { 1817 struct mbox_msghdr hdr; 1818 u8 intf; 1819}; 1820 1821struct npc_get_field_hash_info_rsp { 1822 struct mbox_msghdr hdr; 1823 u64 secret_key[3]; 1824#define NPC_MAX_HASH 2 1825#define NPC_MAX_HASH_MASK 2 1826 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1827 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1828 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1829 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1830}; 1831 1832enum ptp_op { 1833 PTP_OP_ADJFINE = 0, 1834 PTP_OP_GET_CLOCK = 1, 1835 PTP_OP_GET_TSTMP = 2, 1836 PTP_OP_SET_THRESH = 3, 1837 PTP_OP_PPS_ON = 4, 1838 PTP_OP_ADJTIME = 5, 1839 PTP_OP_SET_CLOCK = 6, 1840}; 1841 1842struct ptp_req { 1843 struct mbox_msghdr hdr; 1844 u8 op; 1845 s64 scaled_ppm; 1846 u64 thresh; 1847 u64 period; 1848 int pps_on; 1849 s64 delta; 1850 u64 clk; 1851}; 1852 1853struct ptp_rsp { 1854 struct mbox_msghdr hdr; 1855 u64 clk; 1856 u64 tsc; 1857}; 1858 1859struct npc_get_field_status_req { 1860 struct mbox_msghdr hdr; 1861 u8 intf; 1862 u8 field; 1863}; 1864 1865struct npc_get_field_status_rsp { 1866 struct mbox_msghdr hdr; 1867 u8 enable; 1868}; 1869 1870struct set_vf_perm { 1871 struct mbox_msghdr hdr; 1872 u16 vf; 1873#define RESET_VF_PERM BIT_ULL(0) 1874#define VF_TRUSTED BIT_ULL(1) 1875 u64 flags; 1876}; 1877 1878struct lmtst_tbl_setup_req { 1879 struct mbox_msghdr hdr; 1880 u64 dis_sched_early_comp :1; 1881 u64 sch_ena :1; 1882 u64 dis_line_pref :1; 1883 u64 ssow_pf_func :13; 1884 u16 base_pcifunc; 1885 u8 use_local_lmt_region; 1886 u64 lmt_iova; 1887 u64 rsvd[4]; 1888}; 1889 1890struct ndc_sync_op { 1891 struct mbox_msghdr hdr; 1892 u8 nix_lf_tx_sync; 1893 u8 nix_lf_rx_sync; 1894 u8 npa_lf_sync; 1895}; 1896 1897/* CPT mailbox error codes 1898 * Range 901 - 1000. 1899 */ 1900enum cpt_af_status { 1901 CPT_AF_ERR_PARAM = -901, 1902 CPT_AF_ERR_GRP_INVALID = -902, 1903 CPT_AF_ERR_LF_INVALID = -903, 1904 CPT_AF_ERR_ACCESS_DENIED = -904, 1905 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1906 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1907 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1908 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1909}; 1910 1911/* CPT mbox message formats */ 1912struct cpt_rd_wr_reg_msg { 1913 struct mbox_msghdr hdr; 1914 u64 reg_offset; 1915 u64 *ret_val; 1916 u64 val; 1917 u8 is_write; 1918 int blkaddr; 1919}; 1920 1921struct cpt_lf_alloc_req_msg { 1922 struct mbox_msghdr hdr; 1923 u16 nix_pf_func; 1924 u16 sso_pf_func; 1925 u16 eng_grpmsk; 1926 u8 blkaddr; 1927 u8 ctx_ilen_valid : 1; 1928 u8 ctx_ilen : 7; 1929}; 1930 1931#define CPT_INLINE_INBOUND 0 1932#define CPT_INLINE_OUTBOUND 1 1933 1934/* Mailbox message request format for CPT IPsec 1935 * inline inbound and outbound configuration. 1936 */ 1937struct cpt_inline_ipsec_cfg_msg { 1938 struct mbox_msghdr hdr; 1939 u8 enable; 1940 u8 slot; 1941 u8 dir; 1942 u8 sso_pf_func_ovrd; 1943 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1944 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1945}; 1946 1947/* Mailbox message request and response format for CPT stats. */ 1948struct cpt_sts_req { 1949 struct mbox_msghdr hdr; 1950 u8 blkaddr; 1951}; 1952 1953struct cpt_sts_rsp { 1954 struct mbox_msghdr hdr; 1955 u64 inst_req_pc; 1956 u64 inst_lat_pc; 1957 u64 rd_req_pc; 1958 u64 rd_lat_pc; 1959 u64 rd_uc_pc; 1960 u64 active_cycles_pc; 1961 u64 ctx_mis_pc; 1962 u64 ctx_hit_pc; 1963 u64 ctx_aop_pc; 1964 u64 ctx_aop_lat_pc; 1965 u64 ctx_ifetch_pc; 1966 u64 ctx_ifetch_lat_pc; 1967 u64 ctx_ffetch_pc; 1968 u64 ctx_ffetch_lat_pc; 1969 u64 ctx_wback_pc; 1970 u64 ctx_wback_lat_pc; 1971 u64 ctx_psh_pc; 1972 u64 ctx_psh_lat_pc; 1973 u64 ctx_err; 1974 u64 ctx_enc_id; 1975 u64 ctx_flush_timer; 1976 u64 rxc_time; 1977 u64 rxc_time_cfg; 1978 u64 rxc_active_sts; 1979 u64 rxc_zombie_sts; 1980 u64 busy_sts_ae; 1981 u64 free_sts_ae; 1982 u64 busy_sts_se; 1983 u64 free_sts_se; 1984 u64 busy_sts_ie; 1985 u64 free_sts_ie; 1986 u64 exe_err_info; 1987 u64 cptclk_cnt; 1988 u64 diag; 1989 u64 rxc_dfrg; 1990 u64 x2p_link_cfg0; 1991 u64 x2p_link_cfg1; 1992}; 1993 1994/* Mailbox message request format to configure reassembly timeout. */ 1995struct cpt_rxc_time_cfg_req { 1996 struct mbox_msghdr hdr; 1997 int blkaddr; 1998 u32 step; 1999 u16 zombie_thres; 2000 u16 zombie_limit; 2001 u16 active_thres; 2002 u16 active_limit; 2003}; 2004 2005/* Mailbox message request format to request for CPT_INST_S lmtst. */ 2006struct cpt_inst_lmtst_req { 2007 struct mbox_msghdr hdr; 2008 u64 inst[8]; 2009 u64 rsvd; 2010}; 2011 2012/* Mailbox message format to request for CPT LF reset */ 2013struct cpt_lf_rst_req { 2014 struct mbox_msghdr hdr; 2015 u32 slot; 2016 u32 rsvd; 2017}; 2018 2019/* Mailbox message format to request for CPT faulted engines */ 2020struct cpt_flt_eng_info_req { 2021 struct mbox_msghdr hdr; 2022 int blkaddr; 2023 bool reset; 2024 u32 rsvd; 2025}; 2026 2027struct cpt_flt_eng_info_rsp { 2028 struct mbox_msghdr hdr; 2029#define CPT_AF_MAX_FLT_INT_VECS 3 2030 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 2031 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS]; 2032 u64 rsvd; 2033}; 2034 2035struct sdp_node_info { 2036 /* Node to which this PF belons to */ 2037 u8 node_id; 2038 u8 max_vfs; 2039 u8 num_pf_rings; 2040 u8 pf_srn; 2041#define SDP_MAX_VFS 128 2042 u8 vf_rings[SDP_MAX_VFS]; 2043}; 2044 2045struct sdp_chan_info_msg { 2046 struct mbox_msghdr hdr; 2047 struct sdp_node_info info; 2048}; 2049 2050struct sdp_get_chan_info_msg { 2051 struct mbox_msghdr hdr; 2052 u16 chan_base; 2053 u16 num_chan; 2054}; 2055 2056/* CGX mailbox error codes 2057 * Range 1101 - 1200. 2058 */ 2059enum cgx_af_status { 2060 LMAC_AF_ERR_INVALID_PARAM = -1101, 2061 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 2062 LMAC_AF_ERR_PERM_DENIED = -1103, 2063 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 2064 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 2065 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 2066 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 2067 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 2068 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 2069 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 2070}; 2071 2072enum mcs_direction { 2073 MCS_RX, 2074 MCS_TX, 2075}; 2076 2077enum mcs_rsrc_type { 2078 MCS_RSRC_TYPE_FLOWID, 2079 MCS_RSRC_TYPE_SECY, 2080 MCS_RSRC_TYPE_SC, 2081 MCS_RSRC_TYPE_SA, 2082}; 2083 2084struct mcs_alloc_rsrc_req { 2085 struct mbox_msghdr hdr; 2086 u8 rsrc_type; 2087 u8 rsrc_cnt; /* Resources count */ 2088 u8 mcs_id; /* MCS block ID */ 2089 u8 dir; /* Macsec ingress or egress side */ 2090 u8 all; /* Allocate all resource type one each */ 2091 u64 rsvd; 2092}; 2093 2094struct mcs_alloc_rsrc_rsp { 2095 struct mbox_msghdr hdr; 2096 u8 flow_ids[128]; /* Index of reserved entries */ 2097 u8 secy_ids[128]; 2098 u8 sc_ids[128]; 2099 u8 sa_ids[256]; 2100 u8 rsrc_type; 2101 u8 rsrc_cnt; /* No of entries reserved */ 2102 u8 mcs_id; 2103 u8 dir; 2104 u8 all; 2105 u8 rsvd[256]; /* reserved fields for future expansion */ 2106}; 2107 2108struct mcs_free_rsrc_req { 2109 struct mbox_msghdr hdr; 2110 u8 rsrc_id; /* Index of the entry to be freed */ 2111 u8 rsrc_type; 2112 u8 mcs_id; 2113 u8 dir; 2114 u8 all; /* Free all the cam resources */ 2115 u64 rsvd; 2116}; 2117 2118struct mcs_flowid_entry_write_req { 2119 struct mbox_msghdr hdr; 2120 u64 data[4]; 2121 u64 mask[4]; 2122 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 2123 u8 flow_id; 2124 u8 secy_id; /* secyid for which flowid is mapped */ 2125 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 2126 u8 ena; /* Enable tcam entry */ 2127 u8 ctrl_pkt; 2128 u8 mcs_id; 2129 u8 dir; 2130 u64 rsvd; 2131}; 2132 2133struct mcs_secy_plcy_write_req { 2134 struct mbox_msghdr hdr; 2135 u64 plcy; 2136 u8 secy_id; 2137 u8 mcs_id; 2138 u8 dir; 2139 u64 rsvd; 2140}; 2141 2142/* RX SC_CAM mapping */ 2143struct mcs_rx_sc_cam_write_req { 2144 struct mbox_msghdr hdr; 2145 u64 sci; /* SCI */ 2146 u64 secy_id; /* secy index mapped to SC */ 2147 u8 sc_id; /* SC CAM entry index */ 2148 u8 mcs_id; 2149 u64 rsvd; 2150}; 2151 2152struct mcs_sa_plcy_write_req { 2153 struct mbox_msghdr hdr; 2154 u64 plcy[2][9]; /* Support 2 SA policy */ 2155 u8 sa_index[2]; 2156 u8 sa_cnt; 2157 u8 mcs_id; 2158 u8 dir; 2159 u64 rsvd; 2160}; 2161 2162struct mcs_tx_sc_sa_map { 2163 struct mbox_msghdr hdr; 2164 u8 sa_index0; 2165 u8 sa_index1; 2166 u8 rekey_ena; 2167 u8 sa_index0_vld; 2168 u8 sa_index1_vld; 2169 u8 tx_sa_active; 2170 u64 sectag_sci; 2171 u8 sc_id; /* used as index for SA_MEM_MAP */ 2172 u8 mcs_id; 2173 u64 rsvd; 2174}; 2175 2176struct mcs_rx_sc_sa_map { 2177 struct mbox_msghdr hdr; 2178 u8 sa_index; 2179 u8 sa_in_use; 2180 u8 sc_id; 2181 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 2182 u8 mcs_id; 2183 u64 rsvd; 2184}; 2185 2186struct mcs_flowid_ena_dis_entry { 2187 struct mbox_msghdr hdr; 2188 u8 flow_id; 2189 u8 ena; 2190 u8 mcs_id; 2191 u8 dir; 2192 u64 rsvd; 2193}; 2194 2195struct mcs_pn_table_write_req { 2196 struct mbox_msghdr hdr; 2197 u64 next_pn; 2198 u8 pn_id; 2199 u8 mcs_id; 2200 u8 dir; 2201 u64 rsvd; 2202}; 2203 2204struct mcs_hw_info { 2205 struct mbox_msghdr hdr; 2206 u8 num_mcs_blks; /* Number of MCS blocks */ 2207 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 2208 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 2209 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 2210 u16 sa_entries; /* PN table entries = SA entries */ 2211 u64 rsvd[16]; 2212}; 2213 2214struct mcs_set_active_lmac { 2215 struct mbox_msghdr hdr; 2216 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 2217 u8 mcs_id; 2218 u16 chan_base; /* MCS channel base */ 2219 u64 rsvd; 2220}; 2221 2222struct mcs_set_lmac_mode { 2223 struct mbox_msghdr hdr; 2224 u8 mode; /* 1:Bypass 0:Operational */ 2225 u8 lmac_id; 2226 u8 mcs_id; 2227 u64 rsvd; 2228}; 2229 2230struct mcs_port_reset_req { 2231 struct mbox_msghdr hdr; 2232 u8 reset; 2233 u8 mcs_id; 2234 u8 port_id; 2235 u64 rsvd; 2236}; 2237 2238struct mcs_port_cfg_set_req { 2239 struct mbox_msghdr hdr; 2240 u8 cstm_tag_rel_mode_sel; 2241 u8 custom_hdr_enb; 2242 u8 fifo_skid; 2243 u8 port_mode; 2244 u8 port_id; 2245 u8 mcs_id; 2246 u64 rsvd; 2247}; 2248 2249struct mcs_port_cfg_get_req { 2250 struct mbox_msghdr hdr; 2251 u8 port_id; 2252 u8 mcs_id; 2253 u64 rsvd; 2254}; 2255 2256struct mcs_port_cfg_get_rsp { 2257 struct mbox_msghdr hdr; 2258 u8 cstm_tag_rel_mode_sel; 2259 u8 custom_hdr_enb; 2260 u8 fifo_skid; 2261 u8 port_mode; 2262 u8 port_id; 2263 u8 mcs_id; 2264 u64 rsvd; 2265}; 2266 2267struct mcs_custom_tag_cfg_get_req { 2268 struct mbox_msghdr hdr; 2269 u8 mcs_id; 2270 u8 dir; 2271 u64 rsvd; 2272}; 2273 2274struct mcs_custom_tag_cfg_get_rsp { 2275 struct mbox_msghdr hdr; 2276 u16 cstm_etype[8]; 2277 u8 cstm_indx[8]; 2278 u8 cstm_etype_en; 2279 u8 mcs_id; 2280 u8 dir; 2281 u64 rsvd; 2282}; 2283 2284/* MCS mailbox error codes 2285 * Range 1201 - 1300. 2286 */ 2287enum mcs_af_status { 2288 MCS_AF_ERR_INVALID_MCSID = -1201, 2289 MCS_AF_ERR_NOT_MAPPED = -1202, 2290}; 2291 2292struct mcs_set_pn_threshold { 2293 struct mbox_msghdr hdr; 2294 u64 threshold; 2295 u8 xpn; /* '1' for setting xpn threshold */ 2296 u8 mcs_id; 2297 u8 dir; 2298 u64 rsvd; 2299}; 2300 2301enum mcs_ctrl_pkt_rulew_type { 2302 MCS_CTRL_PKT_RULE_TYPE_ETH, 2303 MCS_CTRL_PKT_RULE_TYPE_DA, 2304 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2305 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2306 MCS_CTRL_PKT_RULE_TYPE_MAC, 2307}; 2308 2309struct mcs_alloc_ctrl_pkt_rule_req { 2310 struct mbox_msghdr hdr; 2311 u8 rule_type; 2312 u8 mcs_id; /* MCS block ID */ 2313 u8 dir; /* Macsec ingress or egress side */ 2314 u64 rsvd; 2315}; 2316 2317struct mcs_alloc_ctrl_pkt_rule_rsp { 2318 struct mbox_msghdr hdr; 2319 u8 rule_idx; 2320 u8 rule_type; 2321 u8 mcs_id; 2322 u8 dir; 2323 u64 rsvd; 2324}; 2325 2326struct mcs_free_ctrl_pkt_rule_req { 2327 struct mbox_msghdr hdr; 2328 u8 rule_idx; 2329 u8 rule_type; 2330 u8 mcs_id; 2331 u8 dir; 2332 u8 all; 2333 u64 rsvd; 2334}; 2335 2336struct mcs_ctrl_pkt_rule_write_req { 2337 struct mbox_msghdr hdr; 2338 u64 data0; 2339 u64 data1; 2340 u64 data2; 2341 u8 rule_idx; 2342 u8 rule_type; 2343 u8 mcs_id; 2344 u8 dir; 2345 u64 rsvd; 2346}; 2347 2348struct mcs_stats_req { 2349 struct mbox_msghdr hdr; 2350 u8 id; 2351 u8 mcs_id; 2352 u8 dir; 2353 u64 rsvd; 2354}; 2355 2356struct mcs_flowid_stats { 2357 struct mbox_msghdr hdr; 2358 u64 tcam_hit_cnt; 2359 u64 rsvd; 2360}; 2361 2362struct mcs_secy_stats { 2363 struct mbox_msghdr hdr; 2364 u64 ctl_pkt_bcast_cnt; 2365 u64 ctl_pkt_mcast_cnt; 2366 u64 ctl_pkt_ucast_cnt; 2367 u64 ctl_octet_cnt; 2368 u64 unctl_pkt_bcast_cnt; 2369 u64 unctl_pkt_mcast_cnt; 2370 u64 unctl_pkt_ucast_cnt; 2371 u64 unctl_octet_cnt; 2372 /* Valid only for RX */ 2373 u64 octet_decrypted_cnt; 2374 u64 octet_validated_cnt; 2375 u64 pkt_port_disabled_cnt; 2376 u64 pkt_badtag_cnt; 2377 u64 pkt_nosa_cnt; 2378 u64 pkt_nosaerror_cnt; 2379 u64 pkt_tagged_ctl_cnt; 2380 u64 pkt_untaged_cnt; 2381 u64 pkt_ctl_cnt; /* CN10K-B */ 2382 u64 pkt_notag_cnt; /* CNF10K-B */ 2383 /* Valid only for TX */ 2384 u64 octet_encrypted_cnt; 2385 u64 octet_protected_cnt; 2386 u64 pkt_noactivesa_cnt; 2387 u64 pkt_toolong_cnt; 2388 u64 pkt_untagged_cnt; 2389 u64 rsvd[4]; 2390}; 2391 2392struct mcs_port_stats { 2393 struct mbox_msghdr hdr; 2394 u64 tcam_miss_cnt; 2395 u64 parser_err_cnt; 2396 u64 preempt_err_cnt; /* CNF10K-B */ 2397 u64 sectag_insert_err_cnt; 2398 u64 rsvd[4]; 2399}; 2400 2401/* Only for CN10K-B */ 2402struct mcs_sa_stats { 2403 struct mbox_msghdr hdr; 2404 /* RX */ 2405 u64 pkt_invalid_cnt; 2406 u64 pkt_nosaerror_cnt; 2407 u64 pkt_notvalid_cnt; 2408 u64 pkt_ok_cnt; 2409 u64 pkt_nosa_cnt; 2410 /* TX */ 2411 u64 pkt_encrypt_cnt; 2412 u64 pkt_protected_cnt; 2413 u64 rsvd[4]; 2414}; 2415 2416struct mcs_sc_stats { 2417 struct mbox_msghdr hdr; 2418 /* RX */ 2419 u64 hit_cnt; 2420 u64 pkt_invalid_cnt; 2421 u64 pkt_late_cnt; 2422 u64 pkt_notvalid_cnt; 2423 u64 pkt_unchecked_cnt; 2424 u64 pkt_delay_cnt; /* CNF10K-B */ 2425 u64 pkt_ok_cnt; /* CNF10K-B */ 2426 u64 octet_decrypt_cnt; /* CN10K-B */ 2427 u64 octet_validate_cnt; /* CN10K-B */ 2428 /* TX */ 2429 u64 pkt_encrypt_cnt; 2430 u64 pkt_protected_cnt; 2431 u64 octet_encrypt_cnt; /* CN10K-B */ 2432 u64 octet_protected_cnt; /* CN10K-B */ 2433 u64 rsvd[4]; 2434}; 2435 2436struct mcs_clear_stats { 2437 struct mbox_msghdr hdr; 2438#define MCS_FLOWID_STATS 0 2439#define MCS_SECY_STATS 1 2440#define MCS_SC_STATS 2 2441#define MCS_SA_STATS 3 2442#define MCS_PORT_STATS 4 2443 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2444 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2445 u8 mcs_id; 2446 u8 dir; 2447 u8 all; /* All resources stats mapped to PF are cleared */ 2448}; 2449 2450struct mcs_intr_cfg { 2451 struct mbox_msghdr hdr; 2452#define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2453#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2454#define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2455#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2456#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2457#define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2458#define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2459#define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2460#define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2461#define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2462#define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2463#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2464#define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2465#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2466#define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2467#define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2468 u64 intr_mask; /* Interrupt enable mask */ 2469 u8 mcs_id; 2470 u8 lmac_id; 2471 u64 rsvd; 2472}; 2473 2474struct mcs_intr_info { 2475 struct mbox_msghdr hdr; 2476 u64 intr_mask; 2477 int sa_id; 2478 u8 mcs_id; 2479 u8 lmac_id; 2480 u64 rsvd; 2481}; 2482 2483#endif /* MBOX_H */
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